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Cmos Co1 Material PDF
Cmos Co1 Material PDF
Prepared by
Dr. Fazal Noorbasha
M.Tech., Ph.D., MISTE, MIAENG, SMIACSIT
Associate Professor
VLSI Systems Research Group (VSRG) Head
Department of ECE – KL University
E-Mail Id: fazalnoorbasha@kluniversity.in
2013-14
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 7
Definition of Output characteristics: It is a set of drain characteristic curves also called volt-
amper characteristics. The plots are Variation of Drain current (Id) with the drain-to-source
voltage (Vds) for a fixed value of gate-to-source voltage (Vgs). The conduction starts after
threshold voltage VT,n.
Definition of Transfer Characteristics: It gives the variation of the drain current (Id) with the
gate-to-source voltage (Vgs) for a fixed value of drain-to-source voltage (Vds).
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 8
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 9
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 10
Fig. 1.17 Output and Transfer Characteristics of p-channel depletion-type MOSFET.
Points to remember:
1. It is a depletion type pMOSFET
2. Substrate (B) is n-type
3. Source (S) and Drain (D) diffusions are p+ type
4. There is a channel between source and drain when NO Gate voltage i.e. Vg=0V
5. It conducts for negative as well as positive gate voltages.
6. Gate threshold voltage (VT,n) starts from the positive values.
7. Linear current will increase by increasing the gate voltage from the +Ve to -Ve gate
voltages.
Fig. 1.18 Structures, symbols and I/V characteristics of P- and N- channel MOSFETs of
enhancement and depletion types (A Summary report)
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 11
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 12
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 13
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 14
Fig.1.23 Cross-sectional view of an n-channel (nMOS) transistor,
(a) Operating in the linear region, [Conditions: VGS > VT & VDS = 0V]
(b) Operating at the edge of saturation, [Conditions: VGS > VT & VDS < VGS-VT]
(c) Operating beyond saturation. [Conditions: VGS > VT & VDS > VGS-VT]
Points to remember: After certain pinch-off point the transistor becomes stay in saturation
mode. Due to large increases of the VDS; If we increase gate voltage (i.e. VGS) the width of the
inverse channel will increase; Due to this ID current will increase means linear mode will rise.
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 15
1.9 nMOS Fabrication
Basic steps:
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 16
Fig. 1.25 Process flow for the fabrication of an n-type MOS transistor
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 17
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 18
Step-5: A heavy boron implant can be used to form the p+ source and drain regions of the p-
MOSFETs. A layer of photoresist can be used to block the regions where n-MOSFETs are to be
formed.
Note: In the both cases the separation between the source and drain diffusions – channel
length – is defined by the polysilicon gate mask alone, hence the self-aligned property.
Step – 6: A photo-mask is used to define the contact window opening followed by a wet or dry
oxide etch.
Step-7: A thin aluminum layer is evaporated or sputtered onto the wafer. A final masking and
etching step is used to pattern the interconnections.
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 21
Table 1.3 Comparisons between CMOS and Bipolar Technologies
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 22
Some more points to remember regarding IC technology:
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 23
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 24
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 25
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 26
Fig. 2.4 Czochralski Crystal growth
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 27
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 28
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 29
2.10 Positive and Negative Photoresist
There are two types of photoresist: positive and negative. For positive resists, the resist is
exposed with UV light wherever the underlying material is to be removed. In these resists,
exposure to the UV light changes the chemical structure of the resist so that it becomes more
soluble in the developer. The exposed resist is then washed away by the developer solution,
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 30
leaving windows of the bare underlying material. In other words, "whatever shows, goes." The
mask, therefore, contains an exact copy of the pattern which is to remain on the wafer.
Negative resists behave in just the opposite manner. Exposure to the UV light causes the
negative resist to become polymerized, and more difficult to dissolve. Therefore, the negative
resist remains on the surface wherever it is exposed, and the developer solution removes only
the unexposed portions. Masks used for negative photoresists, therefore, contain the inverse
(or photographic "negative") of the pattern to be transferred. The figure below shows the
pattern differences generated from the use of positive and negative resist.
Negative resists were popular in the early history of integrated circuit processing, but positive
resist gradually became more widely used since they offer better process controllability for
small geometry features. Positive resists are now the dominant type of resist used in VLSI
fabrication processes.
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 31
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 32
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 33
2.4.8 Metallization
The purpose of metallization is to interconnect the various components of the integrated circuit
(transistors, capacitors, etc.) to form the desired circuit. Metallization involves the deposition of
a metal (aluminum) over the entire surface of the silicon. The required interconnection pattern
is then selectively etched. The aluminum is deposited by heating it in vaccum until it vaporizes.
The vapors then contact the silicon surface and condense to form a solid aluminum layer.
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 34
All diffused resistors are slef-isolated by the reverse-biased pn junctions. One serious drawback for these
resistors is the fact that they are accompanied by a substantial parasitic junction capacitance, masking
them not very useful for high-frequency applications.
A more useful resistor can be fabricated using the polysilicon layer placed on top of the thick field oxide.
The thin layer provides a better provides a better surface area matching and hence more accurate
resistor ratios. Furthermore, the polyresistor is physically separated from the substrate and exhibits a
much lower parasitic capacitance.
Fig. 2.16 Cross sections of various types of resistors available from a typical n-well CMOS Process
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 35
is determined by gemetry and doping levels and with a large voltage coefficient. The fact that this
capacitor works only with reverse bias voltages makes it less useful.
The inter-poly and the MOS capacitors, the capacitance values can be contgrolled to within 1%.
Paractical capacitance values range from 0.5 pF to a few 10s of pF. The matching between similar-size
capacitors can be within 0.1%. This property is extremely useful for designing precision anolog CMOS
circuit.
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 36
Fig. 2.19 Exploded view of 14-lead version of the flat package
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S D
n+ n+
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 37