CONFIGURACION DE LA PLATAFORMA.

CIRCUITO VHDL
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-- Nombre: FUNCIÓN LÓGICA
-- Documento: JMPL
-- Fecha:6/06/2020
-- Proyecto:Nro_2
---------------------------------------------------
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity FUNCION_LOGICA is
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
F : out STD_LOGIC -- la ultima
línea no lleva ;
);
end FUNCION_LOGICA;

architecture Behavioral of
FUNCION_LOGICA is

begin
F<= (A and B and C) OR ( A and (not B))
OR (B and (not C)) ;

end Behavioral;
SIMULACION
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Simulacion is
--
end Simulacion;

architecture Behavioral of Simulacion

is

component FUNCION_LOGICA
Port (

A : in STD_LOGIC;
 B : in STD_LOGIC;
C : in STD_LOGIC;
F : out STD_LOGIC -- la ultima
lineano lleva ;
);
end component;

-- Señales de las entradas

signal A_s : STD_LOGIC:= '0';

signal B_s : STD_LOGIC:= '0';
signal C_s : STD_LOGIC:= '0';

-- Señales de salidas
signal F_s : STD_LOGIC;

begin

UO: FUNCION_LOGICA Port map (

A => A_s,
B => B_s,
C => C_s,

F => F_s
);

process begin
--- Estímulos de la simulación wait for
100 ns;

A_s <= '0';

B_s <= '0';
C_s <= '0';
wait for 100 ns;

A_s <= '0';

B_s <= '0';
C_s <= '1';
wait for 100 ns;

A_s <= '0';

B_s <= '1';
C_s <= '0';
wait for 100 ns;

A_s <= '0';

B_s <= '1';
C_s <= '1';
wait for 100 ns;

A_s <= '1';

B_s <= '0';
C_s <= '0';
wait for 100 ns;

A_s <= '1';

B_s <= '0';
C_s <= '1';
wait for 100 ns;

A_s <= '0';

B_s <= '1';
C_s <= '0';
wait for 100 ns;
A_s <= '1';
B_s <= '1';
C_s <= '0';
wait for 100 ns;

A_s <= '1';

B_s <= '1';
C_s <= '0';
wait for 100 ns;

A_s <= '1';

B_s <= '1';
C_s <= '1';
wait for 100 ns;

wait;
end process;
end Behavioral;