Assignment 7

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

entity counter is Port ( clk : in std_logic;

up : in std_logic_vector(1 downto 0);

C : out std_logic_vector(2 downto 0));

end ;

architecture behavioral of counter is

signal Cout : integer;

begin

process(up,clk)

begin

if (clk ‘event and clk=’1’) then

if (up = “00”) then

Cout <= Cout;

elsif (up = “01”) then

Cout <= Cout + 1;

elsif (up = “10”) then

Cout <= Cout + 2;

else

Cout <= Cout + 3;

end if;

end if ;

end process;

C <= CONV_STD_LOGIC_VECTOR(Cout,3);

end;
Assignment 7