International Conference on Computing, Control, Networking, Electronics and Embedded Systems Engineering, 2015

Encryption implementation based on symmetric algorithm

using a key rounds upto four rounds

Murtada.M.Abdelwahab
Electronic Engineering Department –Faculty of Engineering &Technology
University of Gezira -Sudan
E-mail:mortadamohammad@yahoo.com

Abstract: The proposed implementation in this paper
describes a new advance encryption architecture. The
implementation developed for the purpose of obtaining high
performance and achieving efficient utilization area of the
field programmable gate array (FPGA) resources.The
maximum clock frequency is 134.686 MHz and the number
of the uses slices is 394. The design consists of four
encryption stages based on xor operand.The design used a
single mixcolumn stage in order to reduce the chip area which
improves the throughput results. The design model is typically
developed by a hardware description language and
implemented on xilinix device class spartan3.
encryption standard DES and AES are based on the tradition
techniques[3].
II. METHODOLOGY
The VLSI design flow consists of six steps as shown in
Fig.1. Digital designers must follow these steps in order to
save time and obtained a high level of accuracy. These steps
examine the design flow for any device, whether it is an
ASIC, an FPGA, or a CPLD[4].The VHDL and the
implemented model design on FPGA are completely done on
Xilinx –project navigator,ISE 9.2i.

Key words: Encryption, Decryption ,FPGA, Algorithm,

symmetric.

I. INTRODUCTION
The needs for a new encryption methods is increasing
everyday .Digital designers on all over the world are
competing to invent an optimized encryption algorithm. Any
encryption algorithm can be evaluated in terms of the
computations that it contains or it might be evaluated
according to the amount of logic that it needs and how fast it
can be. Although that most of standard algorithms are usually
specified by 16 rounds of encryption, but many of the
published papers presented a minimized number of rounds of
AES algorithm.The proposed implementation combined the Fig. 1 . Design steps
basic properties that required for all algorithms: securely
The inputs/outputs scheme for the implementation are shown
algorithm and fast speed. The described implementation is a
in Fig.2.
four rounds of advanced encryption algorithm (AES) which
contains single mixcolumns stage. The design categorized as
symmetric algorithm, it is based on XOR operand. This
compact AES algorithm used a key length of 128 bit. The key
is used in the four rounds with a different transposition in
each round. FPGAs consist of logic blocks. A connection
block connects the wire segments around a logic block to its
inputs and outputs [1]. FPGAs are optimized because it offers
short time-to be in markets where digital designers can easily
modify when they need to make changes[2].Basically almost
all popular modern encryption algorithms such as data Fig. 2. Inputs/outputs Scheme

978-1-4673-7869-7/15/$31.00 ©2015 IEEE 27

The implementation consists of five inputs and two outputs.
The design divided into two blocks: Encryption and
decryption where each block consists of three levels as shown
in Fig.3.
- Add key:The key composed of 128 bit distributed to
16 byte. It is used randomly in four rounds of
encryption.
- Mixcolumns: This is a popular technique. it used to
mix up the bytes in each column which produce un
predictable algorithm.

The output computation cipher in each round of encryption is

summarized in Eq.2:

Ci = Ai Ki (2)

Eq.2 states that each byte of the output cipher Ci is resulted

by adding (exclusive or) a byte Ai of the input block data with
a byte of the input key Kj. This mathematical calculation is
Fig. 3. Software description repeated in each encryption round. The operation of
encryption is demonstrated in the following steps:
The model design of the proposed implementation created by
using VHDL code. It based on the XOR operand which used Step -1 : Data are taken in a bytes form:
to create four rounds of encryption. A key generator function
used to generate different round key for each round of
encryption or decryption. Both algorithms of encryption and
decryption are distinguished widely in the following A=
discussion.
Step-2 : The key function generates four rounds keys:
A. Encryption Algorithm
A general definition for encryption process can be mapped K0 K4 K6 K5
as shown in eq.1,the operation used the substitute technique. RoundKey-1= K9 K8 K2 K1
K3 K10 K11 K12
E = PĺC (1) K15 K14 K13 K11

Where E refers o the encryption function, P is an input

plaintext and C defines the substituted cipher. This algorithm K2 K3 K4 K5
is specified in Fig.4. The algorithm used symmetric key of 128 K14 K8 K0 K1
RoundKey-2 =
K7 K9 K11 K13
bits added in multiple rounds of encryption with a different
K15 K10 K12 K6
transposition for each round.
K3 K10 K11 K12
RoundKey-3 = K9 K8 K2 K1
K0 K4 K6 K5
K13 K14 K15 K11

K0 K14 K8 K1
RoundyKey-4 = K14 K8 K0 K1
K13 K9 K11 K7
K10 K15 K12 K6

Step -3 : Adding the first round key:

C1 = (Round key-1) A
Fig. 4. Encryption scheme Step-4: Adding the second round key:
This implementation consists of the following three steps: C2 =( Round key-2) C1
- SubBytes : The block of plaintext which consists of Step-5 : Adding the third round key:
128 bit is divided into 16 bytes. C3 = (Round key-3) C2

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Step-6 : Adding the last round key: each stage.The operation is continued to reach to the last step
where the plaintext result is founded.
C = (Round Key-4) C3
Step-7 : The final stage is mixcolomns stage in which a new III. RESULTS
arranging is performed for the output cipher bytes: Simulation is a basic method that digital designers use it to
verify the correctness of the outputs results for any VLSI
C2 C3 C0 C1 implementation. The following discussion explains the
obtained results of simulation which are done in order to
C6 C7 C4 C5 verify the correctness of both algorithms (encryption and
C= decryption).
C10 C11 C8 C9
A. Encryption results
C14 C15 C12 C13
The regarding data of simulation is shown in Fig .6. This
test aimed to verify the assurance and correctness of the
B. Decryption algorithm
encryption algorithm.
Since decryption is defined as a reverse mapping of
Selectkey = 1
encryption [5], this can be given in Eq.3:

D = CĺP (3)
Where D refers to the decryption function and P is the
plaintext. Decryption algorithm has similar steps as encryption
but in reverse path. This algorithm is specified as shown in
Fig.5. This algorithm consists of the following
transformations: Fig. 6. Encryption inputs

- Inverse SubBytes The output results of simulation are shown in Fig.7. The
- Reverse Add round key given results were verified and it founded correct and
- Reverse Mixcolumns compatible with the proposed algorithm.

As single mixcolumn stage used in the last step for encryption,

reverse mixcolumn stage is also required to achieved correct
decryption output.

Fig. 7. Encryption results

The result in a binary form which obtained by selfcheck file

are written as:
data_in
("101001011000001000111101101010110101011001110010
Fig. 5. Decryption algorithm
00111001100000000001001101010010101011011111111101
The output results can be written mathematically as shown in
111000110011101111101001010100").
Eq.4:
Pi = Ci Ki (4)
key1:
Where P is the output plaintext which consists of 128 bit and
("101001010101001000110000110111101111100101010111
it divided into 16 bytes. Similar to the previous encryption
11011111101101011010010101010010001100001101111011
method, decryption can be described in the same way
111001010101111101111110110101")
beginning with step-7 where reverse operation applied for

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CHECK_cipher_out decryption stage as shown in Fig.9. The results determined
("011111000110111001111100100001100010000100011100 that the implementation provides high level of correctness.
00001011111100101110110000111010110010100101011011
100010110010000010010101001110”) C. Utilization results
Table I figures the hardware utilization where the targeted
B. Decryption results devices is Spartan 3.The results demonstrate that the design
The experimental inputs values are given in Fig.8.This has an efficient results of using the logic resources of the
experiment is done for the purpose of checking the correctness FPGA. TableII provides the performance results when the
of decryption. design implemented on Spartan3 and vertex5.
(Selectkey=0)
TABLE I. Design summary
Target device Spartan3

Logic Used Available Utilization

utilization
Number of 394 33280 0%
Fig. 8. Decryption inputs Slice s
Number of 600 66560 0%
The output results of decryption are shown in Fig.9.The Slice Flip Flops
obtained results were correct and prove the ability of using Number of 4 574 66560 30%
this implementation in real applications. input LUTs
Number of 600 784 76%
bonded IOBs
Number of 1 8 12%
cloccks

TABLE II. Timing summary

Device Spartan3 Virtex5

Speed grade -5 -3

Fig. 9. Decryption results Minimum period 7.425 ns 2.430ns

The result can be written in a binary as shown in the following Maximum Frequency 134.686 MHz 411.557MHz
form:
cipher_in: Minimum input arrival 4.528ns 1.114ns
"0111110001101110011111001000011000100001000111000 time before clock
00010111111001011101100001110101100101001010110111 Maximum output 7.471ns 3.130ns
00010110010000010010101001110" required time after clock
Maximum combinational 9.750ns 3.393ns
key1:
path delay
("101001010101001000110000110111101111100101010111
11011111101101011010010101010010001100001101111011 IV. RELATED WORKS
111001010101111101111110110101")
CHECK_data_out: A lot of FPGA implementations are published in the field
("101001011000001000111101101010110101011001110010 of symmetric encryption. Table III reported some examples of
00111001100000000001001101010010101011011111111101 these algorithms for the purpose of comparing the achieved
111000110011101111101001010100"); results of the proposed implementation with similar AES and
DES implementations. The comparisons are concluded in the
For the purpose of verifying the simulation results, the form of area consumption and the performance speed. Wong
operation is done by using the output cipher from encryption et al [8] presents a single round design of DES algorithm that
stage which shown in Fig.7 as an input cipher for the provides throughput of 26.7 Mbps.

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