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Irf1324pbf 353A PDF
Irf1324pbf 353A PDF
IRF1324PbF
HEXFET® Power MOSFET
Applications D
VDSS 24V
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply RDS(on) typ. 1.2m:
l High Speed Power Switching max. 1.5m:
l Hard Switched and High Frequency Circuits G
ID (Silicon Limited) 353A c
Benefits S ID (Package Limited) 195A
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free S
D
G
TO-220AB
IRF1324PbF
G D S
Gate Drain Source
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09/24/09
IRF1324PbF
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 195A, VGS = 0V g
trr Reverse Recovery Time ––– 46 ––– TJ = 25°C VR = 20V,
ns
––– 71 ––– TJ = 125°C IF = 195A
Qrr Reverse Recovery Charge ––– 160 –––
nC
TJ = 25°C di/dt = 100A/µs g
––– 430 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 7.7 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calcuted continuous current based on maximum allowable junction
temperature Bond wire current limit is 195A. Note that current
Pulse width ≤ 400µs; duty cycle ≤ 2%.
limitation arising from heating of the device leds may occur with Coss eff. (TR) is a fixed capacitance that gives the same charging time
some lead mounting arrangements. as Coss while VDS is rising from 0 to 80% VDSS .
Repetitive rating; pulse width limited by max. junction Coss eff. (ER) is a fixed capacitance that gives the same energy as
temperature. Coss while VDS is rising from 0 to 80% VDSS.
Limited by TJmax, starting TJ = 25°C, L = 0.014mH Rθ is measured at TJ approximately 90°C
RG = 25Ω, IAS = 195A, VGS =10V. Part not recommended for use
above this value .
ISD ≤ 195A, di/dt ≤ 450 A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
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IRF1324PbF
10000 10000
VGS VGS
≤60µs PULSE WIDTH TOP 15V ≤60µs PULSE WIDTH TOP 15V
Tj = 25°C 10V Tj = 175°C 10V
1000 8.0V 8.0V
6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
4.5V
1000 4.5V
100 BOTTOM 4.0V BOTTOM 4.0V
10
100
1
4.0V
4.0V
0.1 10
0.1 1 10 100 0.1 1 10 100
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)
100
T J = 175°C 1.5
(Normalized)
T J = 25°C
10
1.0
1
VDS = 15V
≤60µs PULSE WIDTH
0.1 0.5
2 3 4 5 6 7 8 9 -60 -40 -20 0 20 40 60 80 100120140160180
100000 14.0
VGS = 0V, f = 1 MHZ
ID= 195A
C iss = C gs + C gd, C ds SHORTED
C rss = C gd 12.0 VDS= 19V
VGS, Gate-to-Source Voltage (V)
8.0
10000 Ciss
Coss 6.0
Crss 4.0
2.0
1000 0.0
1 10 100 0 50 100 150 200
VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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IRF1324PbF
1000 10000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
TJ = 175°C 1000
100µsec
100
1msec
100
T J = 25°C Limited by
package
10
10msec
10
Tc = 25°C
Tj = 175°C
VGS = 0V Single Pulse DC
1.0 1
0.0 0.5 1.0 1.5 1 10 100
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area
Forward Voltage
300 30
ID, Drain Current (A)
250
200 28
150
100 26
50
0 24
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180
ID
1.8
TOP 44A
1000
1.6 83A
BOTTOM 195A
1.4
800
1.2
Energy (µJ)
1.0 600
0.8
400
0.6
0.4
200
0.2
0.0 0
-5 0 5 10 15 20 25 30 25 50 75 100 125 150 175
Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRF1324PbF
1
Thermal Response ( Z thJC ) °C/W
D = 0.50
0.1 0.20
0.10
R1
R1
R2
R2
R3
R3
R4
R4
Ri (°C/W) τi (sec)
0.05 0.0125 0.000008
τJ τC
τJ τ
τ1 0.0822 0.000078
0.02 τ1
τ2 τ3 τ4
0.01 τ2 τ3 τ4 0.2019 0.001110
0.01
Ci= τi/Ri 0.2036 0.007197
Ci i/Ri
Notes:
SINGLE PULSE 1. Duty Factor D = t1/t2
( THERMAL RESPONSE ) 2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
1000
100
0.05
0.10
10
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IRF1324PbF
300
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
250 ID = 195A Notes on Repetitive Avalanche Curves , Figures 14, 15:
EAR , Avalanche Energy (mJ)
4.5
VGS(th) , Gate threshold Voltage (V)
4.0
3.5
3.0
ID = 250µA
2.5 ID = 1.0mA
ID = 1.0A
2.0
1.5
1.0
-75 -50 -25 0 25 50 75 100 125 150 175 200
T J , Temperature ( °C )
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IRF1324PbF
Driver Gate Drive
P.W.
D.U.T P.W.
Period D=
Period
+
VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
Recovery Body Diode Forward
-
+ Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD
Ripple ≤ 5% ISD
V(BR)DSS
15V
tp
L DRIVER
VDS
RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS
Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms
RD
VDS VDS
VGS
90%
D.U.T.
RG
+
- VDD
V10V
GS 10%
Pulse Width ≤ 1 µs VGS
Duty Factor ≤ 0.1 %
td(on) tr t d(off) tf
Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Current Regulator Id
Same Type as D.U.T. Vds
Vgs
50KΩ
12V .2µF
.3µF
+
V
D.U.T. - DS
Vgs(th)
VGS
3mA
IG ID
Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr
Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
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IRF1324PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/2009
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