CLAMPERS

Clamper introduces the d.c levels to an a.c

signal by using diode, resistor, capacitor

Fig Block diagram of damper

Clamping is the process of introducing a

D.C voltage level into an a.c signal. i.e., A
device which is used to do the clamping
process is called Clamper.
A clamped circuit has a minimum
requirement of three elements.

1. Diode (D), 2. Capacitor (C), and 3.

Resistor (R).

Normally, it needs a d.c battery also. In

addition to this the following points
regarding clamper circuit are worth
keeping in mind:

1. Both resistor and capacitor affects the

waveform.

2. Values of R and C should produce a

time constant τ = RC which is large
enough to ensure that capacitor remains
almost fully charged during the time
period of the signal.
3. In other words, time constant τ >> T/2
where T is the time period of the input
signal.

4. For all clamping circuits, voltage swing

of the input and output waveforms is the
same.

Anyhow, depending upon the output

waveform from the clamper whether the
positive d.c or negative d.c shift is
introduced in the output waveform, the
clampers are divided into the following
two types.

I. Positive damper, and

2. Negative damper.

POSITIVE CLAMPER
Positive damper is nothing but, this lifts
the D.C level of the signal than its original
D.0 level in positive direction. This is
shown in Fig.

The above circuit is used to add a positive

level to the a.c output voltage Vo. This is
constructed by using capacitor, diode and
resistor.
Operation : Operation is explained as
follows.

First consider negative half cycle of input

voltage (Vin) to the clamper. This makes the
diode 'D’ in forward biased condition.
Hence, the capacitor is initially charged
through diode ‘D' almost equal to peak
value of input voltage Vin with polarities
mentioned in the above Fig. (a). But this
charge is approximately 0.6 V less, this is
due to the diode drop (i. e. , threshold
voltage drop of silicon semiconducting
material).

From above discussion, voltage across

capacitor is Vc = Vin (peak) — 0.6

Due to this, capacitor reaches the change

upto Vin(peak) — 0.6 V.

Then after getting fully charged it may act

as d.c source along with input which is
shown in Fig. (b).

Vc = Vin (peak) — 0.6 V

Fig (b) During positive half cycle

At the end of negative peak input, the

diode turns to a reverse biased condition.
But capacitor remains in charging
condition of Vc and it acts as source with
polarities shown in Fig (b).

Now the capacitor starts to discharge

through load resistor RL with time
constant of τ = RLC. This time constant is
selected normally as very large value, hence
it starts to discharge slowly peak to peak.
Hence, the capacitor discharge voltage in
output is,

Vo = Vin + Vc But Vc = Vin (peak) — 0.6 V

Vo = Vin + V in (peak) — 0.6 V

[ Vo = 2 Vin — 0.6 V
The above output voltage is when Vin = Vin
(peak)

Then, if Vin = —Vin (peak) means, Vo = Vin

— Vin (peak) -0.6 V

Vo = — 0.6 V

From the above discussion, the output

voltage is nothing but the addition of Vin
+ d.c level of Vc. Hence, for increasing the
peak to peak value from — 0.6 V. Then,
output values variations are shown in Fig.
Output waveform (positive clamper)
Fig Ideal output waveform

From Fig, the positive side added output

voltage shows the positive clamping for
ideal drop condition and voltage drop
across diode is 0.6 V.

NEGATIVE CLAMPER

Negative damper is nothing but, this lifts

the D.C level of the signal than its original
signal D.C level in negative direction (or)
Lifting the D.C level of the signal than its
original signal in negative direction. This
is shown in Fig.

The above circuit is used to add a negative

level to the a.c output voltage Va.

This is constructed by using capacitor,

diode and resistor.

Operation: Operation is explained as

follows.

Here first consider the positive half cycle

of input voltage (Vin) to the clamper. This
makes the diode D in forward bias
condition. Hence, the capacitor is initially
charged through diode 'D' almost equal to
peak value of input voltage Vin with
polarities mentioned in following Fig (a).

But this charge is approximately 0.6 V less.

This is due to the voltage drop (i.e.,
threshold voltage drop of silicon
semiconducting material.)

Fig. (a) Initial during positive half cycle

From the above discussion, voltage across

capacitor 'C' is VC = Vin(peak) — 0.6 V Due
to this, capacitor reaches the charge upto
Vin(peak) — 0.6 V.

Then after getting fully charged capacitor

may act as d.c source along with input.
Then input goes to next stage, that is, it
cross over the positive peak. Then the diode
goes to reverse biased in next half cycle.

Fig (b) During negative half cycle

At the end of positive peak of the applied

input, the diode D starts to behave in a
reverse biased condition. But the capacitor
gets charged in the same direction and
hence it acts as a d.c source with 2 Vin
(peak) which is shown in Fig. (b).

Now the capacitor starts to discharge

through load resistor RL with the time
constant of τ = RL C. This time constant is
selected normally as very large value. Hence
it starts to discharge slowly peak to peak.

Hence, the capacitor discharge voltage in

the output is Vo = Vin—VC [i.e., Vo = Vin +
(— Vc)

But, Vc = Vin (peak) — 0.6 V

Vo = V in — V in (peak) + 0.6 V

Vo = 0.6 V

The above output is when Vin = + Vin

(peak)
But, if Vin = — Vin (peak) means,

Vo = — V in — (V in (peak) — 0.6 V)

Vo = — 2 V, (peak) + 0.6 V

Hence, the output shifts the level upto — 2

Vin (peak) + 0.6 V.

This is shown in following graph (a) and

ideal case waveform is shown in Fig. (b).
Fig. (a) Negative clamping output for
practical case
Fig. (b) Negative clamping for ideal case