MIPRO 2014, 26-30 May 2014, Opatija, Croatia
A Simulation and Modeling Environment for the
Analysis and Design of Charge Redistribution
DACs used in SAR ADCs
S. Brenna1 , A. Bonetti2 , A. Bonfanti 1 , A. L. Lacaita1
1 Dip. di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milano, Italy
2 ams International AG, Rapperswil, Switzerland
email: stefano.brenna@polimi.it, andrea.bonetti@ams.com
Abstract—The optimal design of SAR ADCs requires the
accurate estimate of nonlinearity and parasitic effects in the
feedback charge-redistribution DAC. Since the effects of both
mismatch and stray capacitances depend on the specific array
topology, complex calculations, custom modeling and heavy
simulations in common circuit design environments are often
required. This paper presents a novel MATLAB-based numerical
tool to assist the design of classic, split and with attenuation
capacitor binary weighted capacitive array topologies with an
even number of bits from 6 to 14. The tool allows to perform
both parametric and statistical simulations taking into account
capacitive mismatch and parasitic capacitances in order to
compute both differential- (DNL) and integral nonlinearity (INL).
SNDR and ENoB degradation due to static non-linear effects is
also estimated. An excellent agreement with the results obtained
by the available circuit simulators (e.g. Cadence Spectre) is shown
but featuring up to 104 shorter simulation time.
Index Terms—Analog-to-digital conversion, numerical simula-
tions, charge redistribution successive approximation registers.
I. I NTRODUCTION
N power-limited applications, such as portable instruments,
I wireless sensor networks or implantable biomedical sys-
tems, the use of ultra low-power analog-to-digital converters
(ADCs) extends the battery life and limits heating phenom-
ena. Due to their energy efficiency, successive approximation
register (SAR) converters represent the best choice when
moderate resolution and speed are required. The performance
requirements of such converters are represented by static
metrics, such as differential-non-linearity (DNL) and integral-
non-linearity (INL), and by dynamic metrics, such as signal-
to-noise-plus-distortion ratio (SNDR) and effective-number-
of-bits (ENoB). All of these parameters mainly depend on the
quality of the capacitive array, which implements the feedback
charge-redistribution (CR) digital-to-analog converter (DAC).
In the last decade, several novel CR-DAC topologies have
been proposed for the design of SAR ADCs with outstanding
efficiency [1], [2] and adopted in various integrated systems
demonstrating their suitability for general purpose applications
[3] [4]. The capacitive DAC plays a dominant role in degrading
the overall performance of a SAR ADC as long as it is affected
by mismatch and parasitic capacitances. Mismatch effects on
DNL and INL can be considered statistical and they are well
known for the most common array topologies [5]. Differently,
the parasitic capacitance contribution is deterministic and
strongly depends on the array architecture.
However, precise relationships that quantify the effects of
both capacitor mismatch and parasitic capacitances on static
74
and dynamic metrics still lacks. Thus, the designer has to size
the DAC unit capacitance handling complex equations to target
the desired requirements and quantify the converter nonlin-
earities running long transient simulations. Unfortunately, in
common circuit design and simulation environments, like Ca-
dence, such simulations are quite time-consuming and require
heavily post-processing of the raw data, limiting the design
time of the converter. Moreover, statistical simulations, like
MonteCarlo analyses, are quite impractical since they require a
large number of runs, at least 100, to achieve confident results.
This paper presents a MATLAB-based numerical tool to
assist the design of the capacitive DAC adopted in SAR
ADCs. The proposed tool implements the model of the three
most common DAC topologies, such as the Classic Binary
Weighted (CBW) [6], the Split Binary Weighted (SBW) [7]
and the Binary Weighted with Attenuation Capacitor (BWA)
[8] array, both single-ended and fully-differential, and allows
to choose the switching algorithm between the conventional
[6] and the monotonic scheme [9]. The numerical models
take into account all possible mismatch and parasitic effects,
giving the possibility to estimate by means of both statistical
and parametric simulations the converter DNL, INL, SNDR,
ENoB and power consumption.
The paper is organized as follows. In Section II, a brief
overview of the array topologies is given, resuming the effects
of mismatch and parasitic capacitances on both DNL and
INL. Section III describes how the different array models are
implemented and simulated with the proposed tool. Section IV
shows the most significant results, which are in agreement with
Cadence Spectre analyses but achieved with a considerable
time saving. Finally, conclusions are drawn in Section V.
II. C ONVERTER TOPOLOGIES
In a generic N-bit capacitive DAC, as the one shown in Fig.
1, each digital code is associated with a particular configura-
tion of the bottom switches that produces the corresponding
output voltage. In an equivalent SAR ADC implemented by
means of such a DAC in the feedback path, this voltage marks
an input transition level between two adjacent digital codes. It
derives that the conversion accuracy depends on the actual size
of each capacitive bank. As a consequence of the technologic
mismatch and parasitics, the capacitance of each block can
differ from its nominal value and can be in general expressed
as
2∑
i−1
i−1
Ci = 2 Cu + Cpar,i + δj i = 1, ..., N (1)
j=1
 Out
CMSB = 2(N-1)C
Out
Cpar
(N-1) (N-2)
2 Cu 2 Cu 4Cu 2Cu Cu Cu Cpar
DN DN-1 D3 D2 D1 (N-2) (N-2)
VREF,P 2 C 2C C C 2 C 2C C C
VREF,N DMSB,N DMSB,2 DMSB,2 DMSB,1 DN-1 D2 D1
VREF,P
Fig. 1: Schematic of a N-bit CBW array. VREF,N

Fig. 2: Schematic of a N -bit SBW array.

where Cpar,i is the parasitic capacitance related to ith ca-

pacitive block and δj is the mismatch equivalent capacitance Main-DAC Sub-DAC

affecting the unit capacitor. The effect of the parasitic capac- Cpar,main Catt
itances Cpar,i can be considered deterministic, depending on Cpar,sub
Out
layout inaccuracies, capacitor geometry and wirings. On the
contrary, the capacitor mismatch can be modeled as a Gaussian 2(m-1)Cu 2Cu Cu 2(l-1)Cu 2Cu Cu
distribution of the unit capacitor value with a mean equal to Dl+m Dl+2 Dl+1 Dl D2 D1
VREF,P
the nominal capacitance, Cu , and a standard deviation equal VREF,N
to [10] √
Cu kc cspec ·Cu Fig. 3: Schematic of a (m + l)-bit BWA array.
σC = √ = kc · , (2)
2A 2
kc , Cu , A and cspec being the Pelgrom mismatch coefficient,
This DAC topology features an improved switching ef-
the unit capacitance, the area and the specific capacitance,
ficiency [12] and also a reduced impact of the capacitors
respectively. In presence of mismatch or parasitics, the DAC
mismatch. In fact, the maximum standard deviation of DNL √
output voltage levels differ from their ideal values being not
and INL, which still occurs at the mid-code, is a factor 2
equally spaced and determining a nonlinearity in the ADC
lower than in the CBW array topology [7] being
input-output characteristic. Another important parasitic in the
charge-redistribution array is the stray capacitance connected N −1 σC
σDN L,SBW = 2 2 · (5)
to top-plate node of the array to a fixed voltage node, e.g. Cu
N −2 σC
Cpar in Fig. 1. This parasitic capacitance causes a gain error σIN L,SBW = 2 2 · . (6)
in the converter characteristic but in some ADC topologies [5] Cu
it can also affect the converter nonlinearity. These relations are referred to a single-ended√configuration
while a fully-differential topology is a further 2-factor less
A. Conventional Binary Weighted Array (CBW) sensitive to mismatch. Moreover, as in the CBW array, only
the parasitics connected between top- and bottom-plate nodes
The classic binary weighted array [6], depicted in Fig. 1, is of each array capacitor limit the converter nonlinearity.
the most common topology, its linearity being affected only
by the mismatch and parasitic capacitances connected between
the top- and the bottom-plate nodes of each capacitance block, C. Binary Weighted Array with Attenuation Capacitor (BWA)
Ci . The statistical DNL and INL depend on the technology A single-ended BWA array [13] is shown in Fig. 3. An
mismatch and vary with the output code. In a single-ended attenuation capacitor Catt divides the DAC into two binary
configuration, the maximum standard deviation of the DNL weighted arrays, main- and sub-DAC, of m and l capacitors,
occurs in correspondence of the converter mid-code, being [5], respectively. In this work, we’ll refer to the architecture shown
[7] N σC in Fig. 3, with the same number of bits in the main- and
σDN L,CBW = 2 2 · , (3) sub-DAC (i.e. m = l = N/2) and Catt = Cu , which has
Cu
been shown to be the most energy efficient [5] among all the
while the correspondent INL maximum standard deviation is
possible choices. For the same unit capacitance, this topology
σC
σIN L,CBW = 2 2 −1 ·
N
. (4) is more sensitive to capacitor mismatch with respect to CBW
Cu and SBW arrays because of the reduction of the overall DAC
In a fully-differential
√ configuration, these results have to be capacitance. In fact, the maximum σDN L and σIN L are
divided by a factor 2 [11]. 3N σC
In this array topology, the parasitic capacitance related to the σDN L,BW A = 2 4 · (7)
Cu
top-plate node, Cpar , causes a difference between two adjacent σC
σIN L,BW A = 2 4 −1 ·
3N
(8)
output voltage levels to be smaller than the nominal value. This Cu
turns into a gain error without affecting the converter linearity. N
which are a factor 2 4 larger than in the conventional topology.
As far as the parasitic effect, the linearity is degraded also by
B. Split Binary Weighted Array (SBW) the stray capacitance connected to the top-plate node of the
The split DAC topology [12] is shown in Fig. 2. It consists sub-DAC, Cpar,sub in Fig. 3, which determines a dependence
of a binary weighted array where the MSB capacitor imple- on the input code of the DAC output voltage, while the
ments a binary weighted sub-array that perfectly reflects the parasitic capacitance connected to the main-DAC, Cpar,main ,
structure of the remaining banks. only affects the converter gain [5].

75
 Fig. 4: Screenshot of the Graphic User Interface.
III. CSA MATLAB S IMULATION TOOL
The proposed simulation platform (CSAtool, Charge-
redistribution SAR ADC tool) is implemented in MATLAB
and allows to evaluate the linearity, either static and dynamic,
and the array power consumption of each array topology. Both
statistical and deterministic effects due to capacitor mismatch
and parasitics can be taken into account once evaluating the
ADC performance. The tool provides a graphic user interface
(GUI) which is shown in Fig. 4. A behavioral model is defined
for each array topology and for a number of bits from 6 to 14.
The model does not simply implement the known equations
that estimate the nonlinearity (maximum standard deviation
of DNL and INL) and the average power consumption of the
different topologies. It reproduces the behavior of a specific
circuit architecture, which is described by functional capacitive
blocks, including the effects of mismatch and parasitics (see
Fig. 5). The simulations can be performed with a high degree
of customization, giving the possibility to accurately evaluate
the impact of mismatch, through both single or multiple
statistical runs, and also of the parasitics of each specific
array capacitor, thus representing a suitable alternative to
Cadence MonteCarlo and post-layout simulations. This section
is devoted to the description of the different converter models
that are implemented in the proposed tool.
A. CBW model
In a generic SAR ADC, the analog-to-digital conversion is
effectively performed by comparing the input analog voltage
signal with subsequent voltage levels generated by the capac-
itive DAC. For a N-bit converter, the input signal is compared
with N successive DAC output levels. In a conventional binary
weighted topology, the DAC output voltage at each conversion
step can be written as
DACout,CBW = F SR · H
where FSR is the full scale range of the converter and H, as
shown in Fig. 5, is the scalar product
1
H= ×C̄×D̄′ (10)
Ctot + Cpar
where Ctot is the total capacitance of the array, Cpar the
parasitic capacitance shown in Fig. 1, C̄ the vector of the
array capacitances Ci (see (1)) and D̄ the vector of the digital
word updated at each conversion cycle,
[ ]
C̄ = C1 . . . CN (11)
[ ]
D̄ = D1 . . . DN (12)
The digital word D̄, which encodes the DAC output levels at
each conversion step, is determined by the adopted switching
algorithm. By means of (10), (11) and (12), it is possible to
compute the ADC conversion characteristic.
B. SBW model
The simple model described in the previous section can
be extended to the SBW architecture of Fig. 2. The MSB
capacitor is implemented as a sub-array and the switching
scheme differs from the conventional algorithm [12]. Thus,
the DAC output voltage can be expressed as
DACout,SBW = F SR · (HM SB + H1,M SB−1 ) , (13)
HM SB and H1,M SB−1 being coefficients related to the MSB
and the residual capacitance array, respectively,
1 ′
HM SB = × C̄M SB × D̄M SB (14)
Ctot + Cpar
1 ′
H1,M SB−1 = × C̄1,M SB−1 × D̄1,M SB−1 . (15)
Ctot + Cpar
Thus, the conversion voltage level is set by two different
N-bit words, D̄M SB and D̄1,M SB−1 , and two vectors of
capacitances, C̄M SB and C̄1,M SB−1 , related to the MSB sub-
(9) array and to the residual array, respectively.
76
 Input Mismatch
(Yes / No) Options
Parasitics
(Yes / No) Output
Oversampled
A/D
VREF,P , VREF,N Characteristic
Sinusoid
N runs
None

N
Parasitics Parasitics
Models

Y
module
A/D
Switching D1-2 N
transition levels ADC
Topology

+
algorithm
DACout
ideal
Nbit DAC
Complete
Basic Array H(code)
+

Array + Structure

+
Structure
Cu C DNL/INL
FFT
Y N (SNDR, ENOB)
Tech Parameters
kc, cspec None

Fig. 5: CSAtool block diagram.

C. BWA model i.e. kc and cspec . This simple modeling approach allows to
As for as the BWA topology concerns, two equal capacitive accurately take into account the effects of mismatch and
arrays must be considered: the main-DAC, which is connected stray capacitances, which affect the converter linearity. The
to the MSB switches, and the sub-DAC, related to the least tool allows to run both nominal and statistical simulations in
significant bits. Let us indicate as Ctot,main and Ctot,sub to order to accurately evaluate the DNL and INL taking into
the overall capacitance of the main-DAC and of the sub- account at the same time capacitor mismatch and parasitic
DAC, respectively, and as Cpar,main and Cpar,sub the parasitic effects. The tool also allows to estimate the degradation of
capacitance at the top-plate node of the corresponding DAC both SNDR and ENoB due the converter nonlinearity. These
(see Fig. 3). Due to the presence of the attenuation capacitor, two parameters are evaluated by feeding the real ADC with an
Catt , the sub-DAC contribution to the overall DAC output oversampled sinewave of variable amplitude and re-converting
voltage is reduced by an attenuation factor AR, the digital output signal to an analog waveform by means
of an ideal DAC. Hence, the signal-to-noise ratio and the
Catt
AR = , (16) effective number of bits are evaluated by performing a FFT
Ctot,main + Cpar,main + Catt on the DAC output. Both SNDR and ENoB can be estimated
Ctot,main being the total capacitance of the ideal main-DAC, while considering both deterministic parasitic effects and the
while Cpar,main is the parasitic capacitance connected to the contribute of statistical capacitor mismatch on multiple runs.
top-plate node of the main array. Thus, the DAC output in the Thus, CSAtool allows to obtain results accurate enough to be
BWA topology is evaluated as compared with post-layout and MonteCarlo simulations in Ca-
dence Virtuoso environment but with a large improvement in
DACout,BW A = F SR · (Hmain + AR·Hsub ) , (17) terms of simulation time. In this section, the simulation results
for the three converter topologies are shown and compared
where Hmain and Hsub are coefficients related to the main-
to both analytic expressions and Cadence results in terms of
and sub-DAC,
accuracy and simulation time. The presented results are related
1
Hmain = ′
× C̄main × D̄main (18) to converters featuring a 20-fF 2MiM unit capacitor with a
Ctot,main + Cpar,main + Catt specific capacitance of 1f F/µm and a Pelgrom coefficient
1 ′ of 1% · µm.
Hsub = × C̄sub × D̄sub . (19)
Ctot,sub + Cpar,sub + Catt
where C̄main , C̄sub , D̄main and D̄sub are the capacitance and A. Static metrics
digital output code vectors related to the main- and the sub- The estimate of parasitic contribution to static non-linearity
DAC, has been evaluated by means of the CSAtool and compared
[ ] with Cadence Virtuoso simulation results. A single-ended SAR
C̄main = C N +1 . . . CN (20)
[ 2
] ADC has been designed in Cadence Virtuoso adopting a
C̄sub = C1 . . . C N (21) VerilogA description for the logic circuit and the comparator,
[ 2
]
D̄main = D N +1 . . . DN (22) while the feedback DAC has been implemented with ideal
[ 2
] capacitors. Arbitrary parasitic capacitances have been added
D̄sub = D1 . . . D N . (23)
2 between the main capacitor top- and bottom-plate nodes in
order to estimate their effect on the converter nonlinearity.
IV. S IMULATION R ESULTS Hence, the input-output characteristic has been evaluated by
The CSAtool implements in MATLAB the three above- means of a transient simulation applying a full-scale ramp as
mentioned converter topologies by considering each array input signal. To reduce the simulation time, only the converter
capacitor as a composition of unit elements, Cu , each with input and output values have been saved. The strobe and the
its own variability that depends on technologic parameters, sampling periods have been chosen short enough to guarantee

77
 CBW
70
1.0 1.0
60 CBW

SNDR [dB]
0.5 0.5
DNL

INL
0.0 0.0 50
-0.5 -0.5
40 CSAtool
-1.0 -1.0 Cadence
30
SBW 20
1.0 1.0

0.5 0.5
70
DNL

INL

SNDR [dB]
0.0 0.0 60 SBW
-0.5 -0.5
50
-1.0 -1.0
40
CSAtool
BW A
30 Cadence
1.0 1.0

0.5 0.5
20
INL
DNL

0.0 0.0 70

SNDR [dB]
-0.5 -0.5
60 BWA
-1.0 -1.0
0 256 512 768 1024 0 256 512 768 1024
50
Code Code
40
Fig. 6: Comparison between DNL and INL estimated by Cadence simulations 30
CSAtool

Cadence
(black lines) and by CSAtool (red lines) for a given pattern of parasitic
20
capacitances and for each converter topology. -35 -30 -25 -20 -15 -10 -5 0

Input Amplitude [dB ]

FSR

CBW
Fig. 8: SNDR as function of the input signal amplitude for the three converter
0.06 0.03
topologies.
0.05
(DNL)

(INL)

0.04 0.02

0.03

0.02 0.01

0.01

0.00 0.00
B. Dynamic metrics
SBW
The dynamic metrics have been computed in the CSAtool
0.06 0.03

0.05 for the three single-ended converter topologies (with added

(DNL)

0.04 0.02
(INL)

0.03 parasitic capacitances) and compared to Cadence simulation

0.02 0.01

0.01 results. The Cadence test-bench is similar to the one described

0.00 0.00

BWA
in the previous section. The input signal is a sinewave at 1-
0.3 0.15 kHz frequency but featuring a variable amplitude, while the
0.12
sampling rate has been set to 30 kHz.
(DNL)

(INL)

0.2
0.09

0.1
0.06

0.03
0.0
0 256 512 768 1024
0.00
0 256 512
Code Code
Fig. 7: Standard deviation of DNL and INL as a function of the output code
for a CBW, SBW and BWA 10-bit converter.
at least 100 points per each conversion level, thus keeping
the systematic error on the DNL below 1%. Fig. 6 shows the
comparison between the DNL and INL characteristics obtained
by CSAtool and Cadence Spectre simulations for the three
converter topologies affected by parasitics extracted in Assura.
The error between the CSAtool and Cadence results is never
larger than 0.05 LSB, confirming the good accuracy of the
implemented converter models.
Fig. 7 shows the results obtained by the CSAtool once the
capacitor mismatch has been considered in terms of standard
deviation of DNL and INL. Since a MonteCarlo simulation
performed in the Cadence environment requires at least 100
runs to achieve confident results, thus being impractical, the
effect of capacitor mismatch has been compared to the analytic
expressions by using (3), (4), (5) and (8). Table I compares the
maximum values of DNL/INL standard deviation, i.e. σDN L
and σIN L , computed by the CSAtool running 100 simulations
and the estimates obtained by the analytic expressions. The
error between estimates and CSAtool results is always lower
than 0.005 LSB.
Fig. 8 shows the SNDR evaluated by means of Cadence
768 1024
Spectre simulations and CSAtool as function of the input
signal amplitude (referred to the full scale range) for the three
converter topologies. The maximum discrepancy between the
Cadence and CSAtool results is always lower than 0.45 dB.
However, it’s worth pointing out that the CSAtool allows to
easily compute the SNDR vs. input amplitude curve, while
the same simulations in Cadence takes a long time allowing
to compute only few points of the dynamic characteristic. This
can results in a not correct evaluation of the SNDR peak and
thus of the ENoB.
C. Power consumption
The models implemented in the CSAtool allow to evaluate
the array switching energy as function of the output code.
Fig. 9 shows the average switching energies as function of
the number of bits for the three considered single-ended arrays
evaluated by means of the analytic expressions [5],
[ ]
Eave,CBW ∼
2
= 0.66 · 2N Cu (VREF,P − VREF,N ) (24)
[ ]
Eave,SBW ∼
2
= 0.41 · 2N Cu (VREF,P − VREF,N ) (25)
[ ]
Eave,BW A ∼
2
= 1.25 · Cu (VREF,P − VREF,N ) . (26)
The average energy evaluated with the CSAtool for the same
arrays is also shown in Fig. 9 as symbols, showing a good
agreement with the theoretical estimates.

78
 TABLE III: M ONTE C ARLO SIMULATION TIMES FOR 100 RUNS
) ]
2

10k
REF,N

Analytic expressions
CBW
-V

CSA Tool
SBW
Resolution Static metrics Dynamic metrics
REF,P

1k 6 2.13s 160s
Switching Energy [C (V
u

BWA
8 6.491s 172s

100 10 25.25s 183s

12 100s 245s
14 425s 573s
10
6 8 10 12 14
N bits
DACs and ADCs is presented. A graphic user interface
Fig. 9: Average switching energy for the three converter topologies. Dashed MATLAB environment supports the implemented models that
lines refer to analytic equations, symbols refer to CSAtool results.
allow to simulate both technology mismatch and parasitic
effects on linearity. The proposed tool overwhelms the con-
TABLE I: E STIMATES OF σDN L,max AND σIN L,max
ventional simulation method based on transient analyses in
terms of computation time for a given accuracy and does
σDN L,max σIN L,max not require a fine calibration of simulation parameters (points
Topology CSAtool Equation CSAtool Equation per conversion step, strobe period, etc.). In particular, the
CBW 0.0502 0.0506 0.0249 0.0253 method is helpful every time a fast analysis and an accurate
SBW 0.0351 0.0358 0.0252 0.0253 sizing of commonly-used converter architectures is needed.
BWA 0.286 0.286 0.143 0.144 The proposed CSAtool can be downloaded with encrypted
scripts from ftp://ftp.elet.polimi.it/outgoing/Stefano.Brenna.

D. Simulation time R EFERENCES

Table II reports a comparison between the simulation times
needed to compute the static and dynamic metrics with the
CSAtool and Cadence environment. The simulation times refer
to a CBW converter with a number of bits from 6 to 14 and
to a single simulation run. All the simulations have been per-
formed with a 3-GHz Pentium Xeon featuring a 4-Gbyte main
memory. For the same accuracy (i.e. DNL lower than 1%),
the CSAtool features an improvement in terms of simulation
time up to about 104 . Finally, it’s worth pointing out that
the CSAtool allows to estimate the static nonlinearities and
the dynamics metrics in presence of statistical mismatch and
parasitic capacitance effect allowing to perform a MonteCarlo
simulation over a large number of runs. Table III shows the
simulation time for a MonteCarlo analysis of 100 runs. For a
14-bit converter, i.e. the worst case, the tool allows to compute
the static and dynamic metrics in less than 10 minutes, while
the same analysis cannot be performed in a reasonable amount
of time in Cadence Virtuoso envirmonment.
V. C ONCLUSIONS
In this work, a fast and accurate simulation tool for the
analysis and design of charge redistribution SAR capacitive
TABLE II: S INGLE SIMULATION TIME
Static metrics
Number of Bits CSAtool Cadence
6 0.064s 625s
8 0.087s 2.5·103
10 0.272s 104 s
12 1.005s 4·104 s
14 3.997s 1.6·105 s
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