© 2015 IJIRT | Volume 1 Issue 12 | ISSN: 2349-6002

POWER ANALYSIS IN VLSI DESIGNS

Vijit Mangla,Parshant Sharma,Sahil Kapoor
Electronics and Communication Engineering.
Dronacharya College of Engineering, Gurgaon.

Abstract: - With the advent of portable and high- Depending upon the component and function,
density microelectronic devices, the power different optimization approaches can be
dissipation of very large scale integrated (VLSI) adopted.With various levels of designs there comes a
circuits is becoming a critical concern. Accurate number of techniques to save the power in VLSI
power estimation during the design phase is designs. The following chart explain the power
required in order to meet the power. Space, power consumption rises as we move on from layout level to
consumption and speed are major design issues in system level.
VLSI circuit. The design component has conflicting
effect on overallperformance of circuits. An
optimization of power dissipation can be achieved
by compromising various components.Here we
present various techniques evolved to utilize the
power without the compromise in overall
efficiency.

Index Terms— Very Large Scale Inegration(VLSI)

 Introduction

The continuing decrease in feature size and the

corresponding increase in chip density and operating
frequency have made power consumption a major
concern in VLSI design. Mod-

ern microprocessors are indeed hot: the PowerPC chip

from Motorola consumes 8.5 Watts,the Pentium chip
from Intel consumes 16 Watts, and DEC's alpha chip
consumes 30 Watts. Fig 1: Power Optimization at different levels

In CMOS and BiCMOS technologies, the chip

components (gates, cells) draw power supply current
only during a logic transition (if we ignore the small
leakage current). Whilethis is considered an attractive
low-power feature of these technologies, it makes the
power-dissipation highly dependent on the switching
activity inside these circuits. Simply put, a more active
circuit will consume more power. This complicates the
power estimation problembecause the power becomes
a moving target - it is input pattern-dependent.
 TECHNIQUES OF POWER SAVING
 ALGORITHMIC LEVEL REDUCTION
Power consumption at algorithm level related to
properties of those particular algorithm techniques.
Soit should carefully select for lowering the power
consumption. For lowering the power, algorithm
should be such that it have minimum number of
switching requirements. That algorithm is more useful
which have minimum number of operation because it
will require less hardware. By increasing concurrency
we can increase efficiency of that device.

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 © 2015 IJIRT | Volume 1 Issue 12 | ISSN: 2349-6002
 ARCHITECTURE LEVEL REDUCTION
The basic building block at this level are registers,
busses multipliers, memories, state machine etc. Each
block perform high level function. at architectural
level it is important to power analysis because now a
days chips become complex & it is not easy to analyses
each and every gate. The architectural level is the
design entry point for the large majority of digital
designs and design decisions at this level can have
dramatic impact on the power budget design.
We all know that the power is a function of the
frequency also.
 GATE LEVEL REDUCTION
Local restructing: In this technique we modified the
group of gates based on different operation such as
Combine Gates, Decomposition of gate, Delete wire,
Add wire, Duplicate a gate etc.
Signal gating: By using the controller we can avoid
extra switching activity which directly impact on
power dissipation.
Clearly the number of gates is directly proportional to
the power consumed , the power consumption goes on
advancing as more number of gate are employed in the
chip.
IJIRT 102127 INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY
 USE OF CLOCK TECHNIQUES
For providing synchronization of the digital system
one or more reference clocks are used. Fully
synchronization is done by using common clock. By a
single clock all parts of digital system is clocked for
different operations. Clock tree used for globally
distribution the clock signal to all modules. There are
two types of clock schemes: Single driver clock
scheme and Distributed buffers clock scheme.
Dynamic power dissipation by switching of clock is
given by:
Pclk = V2dd.f.(CL +CD)……………(1)
Where CL is Total load capacitance on clock.
There are two problems in clock generation
conclusion
We have seen the power optimizations applicable
at various levels of abstraction, namely the circuit,
logic,
architecture and system level. This survey is not all-
inclusive; rather we have focused a few typical
optimizations at each level of abstraction. Further,
device level and layout-level optimizations to reduce
power have not been presented. Lowering power
dissipation at all abstraction levels is a focus of intense
academic and industrial research.
 REFERNCES
[1] K. Y. Chao and D. F. Wong. "Lowpower
[2] consideration in floor plan design. " in
Proceedings of the 1994 International
Workshop on Low Power Design, pages 45-
50, April 1994.
[3] http://www.ijcsi.org/papers/IJCSI-8-2-648-
653.pdf
[4] http://ijcta.com/documents/volumes/vol2issu
e1/ijcta2011020101.pdf
[5] J. Wang, S. Fang, W. Feng, “New Efficient
Designs for XORand XNOR Functions on the
Transistor Level”, IEEEJournal of Solid-
State Circuits, 29(7), 1994, 780–786.
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