WEEK 4: Computer Interconnection Structures, Bus Interconnection, PCI

Objectives:
At the end of the lesson the learner will be able to:
Define computer interconnection structures
Describe the bus interconnection
Know the 3 types of a bus structure
Define the PCI

COMPUTER INTERCONNECTION STRUCTURES

A computer consists of a set of components or modules of three basic types
(processor, memory, I/O) that communicate with each other. In effect, a computer is a
network of basic modules. Thus, there must be paths for connecting the modules. The
collection of paths connecting the various modules is called the interconnection
structure. The design of this structure will depend on the exchanges that must be made
among modules.
Figure below suggests the types of exchanges that are needed by indicating the major
forms of input and output for each module type.

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WEEK 4: Computer Interconnection Structures, Bus Interconnection, PCI

• Memory: Typically, a memory module will consist of N words of equal length. Each
word is assigned a unique numerical address (0, 1, . . . , N – 1). A word of data can be
read from or written into the memory.The nature of the operation is indicated by read
and write control signals. The location for the operation is specified by an address.

• I/O module: From an internal (to the computer system) point of view, I/O
is functionally similar to memory. There are two operations, read and write.
Further, an I/O module may control more than one external device. We can refer to
each of the interfaces to an external device as a port and give each a unique address
(e.g., 0, 1,…, M – 1). In addition, there are external data paths for the input and output
of data with an external device. Finally, an I/O module may be able to send interrupt
signals to the processor.

• Processor: The processor reads in instructions and data, writes out data
after processing, and uses control signals to control the overall operation of the
system. It also receives interrupt signals. The preceding list defines the data to be
exchanged. The interconnection structure must support the following types of
transfers:

• Memory to processor: The processor reads an instruction or a unit of data

from memory.
• Processor to memory: The processor writes a unit of data to memory.
• I/O to processor:The processor reads data from an I/O device via an I/O module.
• Processor to I/O: The processor sends data to the I/O device.
• I/O to or from memory: For these two cases, an I/O module is allowed to
exchange data directly with memory, without going through the processor,
using direct memory access (DMA).
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Though a number of interconnection structures have been tried. By far the most
common is the bus and various multiple-bus structures.

BUS INTERCONNECTION

 A bus is a communication pathway connecting two or more devices

 It is a shared transmission medium
 A bus consists of multiple pathways or lines
 A bus that connects major components (CPU,Memory,I/O) is calledSystem Bus.

BUS STRUCTURE
 Each line is assigned a particular meaning or function.
 The lines can be classified into 3 functional groups

1. Data line
2.Addressline
3.Control line

1. DATA LINE

 Provide a path for moving data between system modules.

 These lines, collectively, are called thedata bus
 Data bus may consist of from 32 to 100 separated line
 Each line can carry only one bit at a time
 Number of line in the bus determine the data rate and overall the system
performance

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WEEK 4: Computer Interconnection Structures, Bus Interconnection, PCI
2. ADDRESS LINE
 Used to designate the source or destination of the data on the data bus
 The width of the address bus determines the maximum possible memory
capacity of the system.
3. Control line

 Used to control the access to and the use of the data and address lines
 Since the data and the address line shared by all the components, there must be a
means of controlling their use
 Control signal transmit both commands and timing information between the
modules
 Typical control lines include
1. Memory write
2. Memory read
3. I/O write
4. I/O read
5. Clock
6. Reset
7. Bus request
8. Bus grant
9. Interrupt request
10. Interrupt ACK
11. Transfer ACK

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WEEK 4: Computer Interconnection Structures, Bus Interconnection, PCI
PCI
Stands for "Peripheral Component Interconnect." PCI is a hardware bus used for
adding internal components to a desktop computer. For example, a PCI card can be
inserted into a PCI slot on a motherboard, providing additional I/O ports on the back
of a computer.
The PCI architecture, also known as "conventional PCI," was designed by Intel and
introduced in 1992. Many desktop PCs from the early 1990s to the mid 2000s had room
for two to five PCI cards. Each card required an open slot on the motherboard and a
removable panel on the back of the system unit. Adding PCI cards was an easy way to
upgrade a computer, since you could add a better video card,
faster wired or wireless networking, or add new ports, like USB 2.0.
The original 32-bit, 33 MHz PCI standard supported data transfer rates of
133 megabytes per second. An upgraded 64-bit, 66 MHz standard was created a few
years later and allowed for much faster data transfer rates up to 533 MHz. In 1998,
IBM, HP, and Compaq introduced PCI-X (or "PCI eXtended"), which was backwards
compatible with PCI. The 133 MHz PCI-X interface supported data transfer rates up to
1064 MHz.
Both PCI and PCI-X were superseded by PCI Express, which was introduced in 2004.

These specifications represent the most common version of PCI used in normal PCs:

 33.33 MHz clock with synchronous transfers

 Peak transfer rate of 133 MB/s (133 megabytes per second) for 32-bit bus width
(33.33 MHz × 32 bits ÷ 8 bits/byte = 133 MB/s)
 32-bit bus width
 32- or 64-bit memory address space (4 gigabytes or 16 exabytes)
 32-bit I/O port space
 256-byte (per device) configuration space
 5-volt signaling

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 Reflected-wave switching
The PCI specification also provides options for 3.3 V signaling, 64-bit bus width, and
66 MHz clocking, but these are not commonly encountered outside of PCI-X support
on server motherboards.
The PCI bus arbiter performs bus arbitration among multiple masters on the PCI bus.
Any number of bus masters can reside on the PCI bus, as well as requests for the bus.
One pair of request and grant signals is dedicated to each bus master.
Card voltage and keying

A PCI-X Gigabit Ethernet expansion card with both 5 V and 3.3 V support
notches, side B toward the camera

Typical PCI cards have either one or two key notches, depending on their signaling
voltage. Cards requiring 3.3 volts have a notch 56.21 mm from the card backplate;
those requiring 5 volts have a notch 104.47 mm from the backplate. This allows cards
to be fitted only into slots with a voltage they support. "Universal cards" accepting
either voltage have both key notches.
Connector pinout
The PCI connector is defined as having 62 contacts on each side of the edge connector,
but two or four of them are replaced by key notches, so a card has 60 or 58 contacts on
each side. Side A refers to the 'solder side' and side B refers to the 'component side': if

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the card is held with the connector pointing down, a view of side A will have the
backplate on the right, whereas a view of side B will have the backplate on the left. The
pinout of B and A sides are as follows, looking down into the motherboard connector
(pins A1 and B1 are closest to backplate)

32-bit PCI connector pinout

Pin Side B Side A Comments

1 −12 V TRST#

2 TCK +12 V
JTAG port pins (optional)
3 Ground TMS

4 TDO TDI

5 +5 V +5 V

6 +5 V INTA#

7 INTB# INTC# Interrupt lines (open-drain)

8 INTD# +5 V

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Pulled low to indicate 7.5 or 25 W

9 PRSNT1# Reserved
power required

10 Reserved IOPWR +5 V or +3.3 V

Pulled low to indicate 7.5 or 15 W

11 PRSNT2# Reserved
power required

12 Ground Ground
Key notch for 3.3 V-capable cards
13 Ground Ground

14 Reserved 3.3 V aux Standby power (optional)

15 Ground RST# Bus reset

16 CLK IOPWR 33/66 MHz clock

17 Ground GNT# Bus grant from motherboard to card

18 REQ# Ground Bus request from card to motherboard

Power management event (optional)

19 IOPWR PME#
3.3 V, open drain, active low.

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20 AD[31] AD[30]

21 AD[29] +3.3 V

22 Ground AD[28]

23 AD[27] AD[26]

24 AD[25] Ground

25 +3.3 V AD[24]
Address/data bus (upper half)
26 C/BE[3]# IDSEL

27 AD[23] +3.3 V

28 Ground AD[22]

29 AD[21] AD[20]

30 AD[19] Ground

31 +3.3 V AD[18]

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32 AD[17] AD[16]

33 C/BE[2]# +3.3 V

34 Ground FRAME# Bus transfer in progress

35 IRDY# Ground Initiator ready

36 +3.3 V TRDY# Target ready

37 DEVSEL# Ground Target selected

38 PCIXCAP Ground STOP# PCI-X capable; Target requests halt

39 LOCK# +3.3 V Locked transaction

Parity error; SMBus clock or Snoop done

40 PERR# SMBCLK SDONE
(obsolete)

41 +3.3 V SMBDAT SBO# SMBus data or Snoop backoff (obsolete)

42 SERR# Ground System error

43 +3.3 V PAR Even parity over AD[31:00] and

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C/BE[3:0]#

44 C/BE[1]# AD[15]

45 AD[14] +3.3 V

46 Ground AD[13]
Address/data bus (higher half)
47 AD[12] AD[11]

48 AD[10] Ground

49 M66EN Ground AD[09]

50 Ground Ground
Key notch for 5 V-capable cards
51 Ground Ground

52 AD[08] C/BE[0]#

53 AD[07] +3.3 V Address/data bus (lower half)

54 +3.3 V AD[06]

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55 AD[05] AD[04]

56 AD[03] Ground

57 Ground AD[02]

58 AD[01] AD[00]

59 IOPWR IOPWR

For 64-bit extension; no connect for 32-

60 ACK64# REQ64#
bit devices.

61 +5 V +5 V

62 +5 V +5 V

64-bit PCI extends this by an additional 32 contacts on each side which provide
AD[63:32], C/BE[7:4]#, the PAR64 parity signal, and a number of power and ground
pins.

Legend

Ground pin Zero volt reference

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Power pin Supplies power to the PCI card

Output pin Driven by the PCI card, received by the motherboard

Initiator output Driven by the master/initiator, received by the target

I/O signal May be driven by initiator or target, depending on operation

Target output Driven by the target, received by the initiator/master

Input Driven by the motherboard, received by the PCI card

Open drain May be pulled low and/or sensed by multiple cards

Reserved Not presently used, do not connect

Most lines are connected to each slot in parallel. The exceptions are:

 Each slot has its own REQ# output to, and GNT# input from the motherboard
arbiter.
 Each slot has its own IDSEL line, usually connected to a specific AD line.
 TDO is daisy-chained to the following slot's TDI. Cards without JTAG support must
connect TDI to TDO so as not to break the chain.
 PRSNT1# and PRSNT2# for each slot have their own pull-up resistors on the
motherboard. The motherboard may (but does not have to) sense these pins to
determine the presence of PCI cards and their power requirements.
 REQ64# and ACK64# are individually pulled up on 32-bit only slots.
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 The interrupt lines INTA# through INTD# are connected to all slots in different
orders. (INTA# on one slot is INTB# on the next and INTC# on the one after that.)
Notes:

 IOPWR is +3.3 V or +5 V, depending on the backplane. The slots also have a ridge in
one of two places which prevents insertion of cards that do not have the
corresponding key notch, indicating support for that voltage standard. Universal
cards have both key notches and use IOPWR to determine their I/O signal levels.
 The PCI SIG strongly encourages 3.3 V PCI signaling, requiring support for it since
standard revision 2.3, but most PC motherboards use the 5 V variant. Thus, while
many currently available PCI cards support both, and have two key notches to
indicate that, there are still a large number of 5 V-only cards on the market.
 The M66EN pin is an additional ground on 5 V PCI buses found in most PC
motherboards. Cards and motherboards that do not support 66 MHz operation also
ground this pin. If all participants support 66 MHz operation, a pull-up resistor on
the motherboard raises this signal high and 66 MHz operation is enabled. The pin is
still connected to ground via coupling capacitors on each card to preserve
its AC shielding function.
 The PCIXCAP pin is an additional ground on conventional PCI buses and cards. If
all cards and the motherboard support the PCI-X protocol, a pull-up resistor on the
motherboard raises this signal high and PCI-X operation is enabled. The pin is still
connected to ground via coupling capacitors on each card to preserve its AC
shielding function.
 At least one of PRSNT1# and PRSNT2# must be grounded by the card. The
combination chosen indicates the total power requirements of the card (25 W, 15 W,
or 7.5 W).
 SBO# and SDONE are signals from a cache controller to the current target. They are
not initiator outputs, but are colored that way because they are target inputs.

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 PME# (19A) - Power management event (optional) which is supported in
PCI version 2.2 and higher. It is a 3.3 V, open drain, active low signal. PCI cards
may use this signal to send and receive PME via the PCI socket directly, which
eliminates the need for a special Wake-on-LAN cable.
Mixing of 32-bit and 64-bit PCI cards in different width slots

A semi-inserted PCI-X card in a 32 bit PCI slot, illustrating the necessity of the rightmost notch and the extra room on the motherboard in
order to remain backwards compatible

Most 32-bit PCI cards will function properly in 64-bit PCI-X slots, but the bus clock rate
will be limited to the clock frequency of the slowest card, an inherent limitation of
PCI's shared bus topology. For example, when a PCI 2.3, 66-MHz peripheral is
installed into a PCI-X bus capable of 133 MHz, the entire bus backplane will be limited
to 66 MHz. To get around this limitation, many motherboards have two or more
PCI/PCI-X buses, with one bus intended for use with high-speed PCI-X peripherals,
and the other bus intended for general-purpose peripherals.
Many 64-bit PCI-X cards are designed to work in 32-bit mode if inserted in shorter 32-
bit connectors, with some loss of performance. An example of this is the Adaptec 29160
64-bit SCSI interface card. However, some 64-bit PCI-X cards do not work in standard
32-bit PCI slots.[
Installing a 64-bit PCI-X card in a 32-bit slot will leave the 64-bit portion of the card
edge connector not connected and overhanging. This requires that there be no
motherboard components positioned so as to mechanically obstruct the overhanging
portion of the card edge connector.

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REFERENCES:

http://tutorialbyte.com/2016/01/28/interconnection-structures/

http://casem3.blogspot.com/2016/08/bus-interconnection.html

https://techterms.com/definition/pci

https://en.wikipedia.org/wiki/Conventional_PCI#PCI_bus_transactions

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