Pir Mehr Ali Shah

Arid Agriculture University, Rawalpindi

Office of the controller of Examinations
Final Exam / Spring 2020 (Paper Duration 48 hours)
To be filled by Teacher

Course No.: …………………CS-532………….Course Title: ….… Computer Architecture and Organization …………..
Total Marks: ……….………30…………………Date of Exam: ………... 2020-08-12............………………………………………
Degree: …………BSCS & BSIT…………………….... Semester: ……………6..………… Section: ……………A & B…….……….
Marks Converted
Q. No. 1 2 3 4 5 6 7 8 9 10 Obtained/Total Marks if
Marks Applicable
Marks ** **
Obtained Expression Expression
is faulty **/ is faulty **/
50 30
Total Marks in Words:
Name of the teacher who taught the course: Muhammad Abrar
Signature of teacher / Examiner:

To be filled by Student

Registration No.: ……………………………………………….……… Name: ……………….………………………………………..

Answer the following questions

Q.No.1. How cache Coherence problem effects parallel processing and what are solution to this
problem, Explain in detail with the help of diagram and example.
How CPU find out particular word from generated address in direct mapping approach. (05)
Q.No.2. Explain the design of Micro program control unit in detail with the help of diagrams and also
describe how it is different from hardwired control unit of CPU? (05)

Q.No.3. How instructions are executed in pipeline, consider five stages pipeline and execute with
the help of diagram. Also Define machine check exception.

Consider a pipeline having 4 phases with duration 50, 40, 85 and 75 ns. Given latch delay is 10 ns.
Calculate-

1. Pipeline cycle time

2. Non-pipeline execution time
3. Speed up ratio
4. Pipeline time for 1000 tasks
5. Sequential time for 1000 tasks (05)

Q.No.4. How structural and control hazards puts effect on pipeline and what are their solution.
Describe all types of hazard solutions in parallel programming. (05)

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Q.No.5. How superscalar architecture works? How instruction is executed on this architecture and what
are the performance benefits you achieve by using this architecture. (05)
Q.No.6. How many type of parallel processing organization defines them and explain Symmetric
multiprocessor (SMP) versus (NUMA) non uniform memory access architecture with the help of
diagram.
Also tell me the concept of multithreading and clustering in parallel processing. (05)

**THE END**

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