© Bob Anderson/Masterfile © 1996 PhotoDisc, Inc.

By Gary F. Derbenwick
and Alan F. Isaacson

F
erroelectric memories hold the promise for dramatic improvements in the speed, endurance, and power consumption of non-
volatile semiconductor memories. Embedded and stand-alone ferroelectric memory products challenge traditional nonvola-
tile memories and position ferroelectric memory to create a significant presence in the broader semiconductor markets.
Today’s Flash memories and EEPROMs offer nonvolatile data storage but are limited by slow programming times, high program-
ming voltages, and one million or fewer programming cycles. Therefore, alternative nonvolatile semiconductor memories with faster
programming times, lower programming voltages, and unlimited endurance are under development. These include ferroelectric
memories where the polarization state of a ferroelectric capacitor can be switched and sensed, thin-film magnetic memories where the

■ 20 8755-3996/01/$10.00 ©2001 IEEE CIRCUITS & DEVICES ■ JANUARY 2001

giant magneto-resistive effect or magnetic tunnel junctions can lems between the ferroelectric materials and conventional sili-
be used to store and sense nonvolatile data, and ovonic memo- con materials. Perhaps the most severe of these problems is the
ries where the resistance of a chalcogenide glass layer in series tendency of many ferroelectric materials to lose oxygen and
with a transistor can be switched and sensed. form a chemically reduced state during thermal annealing steps
Perhaps the oldest of these three alternative technologies is in the manufacturing process. This loss of oxygen from the
ferroelectric technology. Nonvolatile memories using ferroelec- ferroelectric layer oxidizes the silicon in the channel region of
tric capacitors were developed and patented in the 1950s, and the transistor and renders the device inoperable. Other materi-
ferroelectric technology has already demonstrated fast pro- als lost from the ferroelectric can also alter the properties of the
gramming times, fast read times, virtually unlimited endurance, silicon. Because of the large relative permittivity difference be-
and low programming voltages. Why, then, has it taken so long tween a typical ferroelectric material and silicon dioxide (of the
for ferroelectric memories to be developed and why is ferroelec- order of 300-1000 for typical ferroelectric materials as compared
tric memory technology now considered on the brink? to 3.95 for SiO2), even a very thin layer of SiO2 forming under the
ferroelectric material prevents the programming voltage from
Historical Perspective appearing across the ferroelectric dielectric, again rendering the
The earliest ferroelectric memories had data disturb problems. device inoperable.
Partial programming voltages appeared on deselected memory
cells and corrupted the logical state of deselected cells. Ander-
son solved this problem in 1957 by adding a switching access de- Plate Line
vice to each memory capacitor [1], thus fixing the so-called
“half-voltage deselect problem.” Figure 1 shows the ferroelec-
tric memory patented by Anderson.
For Anderson’s implementation, the reverse breakdown volt-
Word Line
age of the back-to-back access diodes in each memory cell must be
larger than the switching saturation voltage of the ferroelectric
capacitor. Today’s ferroelectric memory architectures are similar
to the Anderson architecture, except that modern MOS transis-
tors have replaced the diode access devices used by Anderson.
During the 1960s and early 1970s, efforts were made to com-
bine ferroelectric technology with conventional silicon semi-
Bit Line

conductor technology by using the ferroelectric material as the

gate insulator in a MOS transistor. In theory, the logical state of
a memory cell could be sensed by the modulation effect of the Data Out
ferroelectric polarization on the channel conductivity of the Sense Amp
transistor. Most of these efforts were abandoned by the
Reference
mid-1970s, largely because of materials incompatibility prob-
2. One-transistor, one-capacitor ferroelectric memory cell schematic.
The plate line can run either parallel or perpendicular to the word
+
V line in the memory array.
−1/2
Pulse
Source Top Electrode (Pt)
Ferroelectric Layer
Pulse Bottom Electrode (Pt)
Source
Barrier Layer
Pulse
Source

+1/2 +1/2 +1/2

Pulse Pulse Pulse

Source Source Source
1. Ferroelectric memory patented by Anderson [1]. Each memory cell
is schematically shown by the devices connected diagonally between
a horizontal pulse source line and a vertical pulse source line. The
memory cells consist of pairs of back-to-back diodes (represented by
the two triangle diode symbols with a rectangle in-between) in series
with ferroelectric capacitors (represented by the symbol with one
large and two small rectangles).
N+
p-well
Polysilicon Plug
3. Cross section of a compact ferroelectric memory cell. The ferro-
electric capacitor is fabricated above the pass transistor. A barrier
material is required between the polysilicon plug and the bottom
electrode of the ferroelectric capacitor.

CIRCUITS & DEVICES ■ JANUARY 2001 21 ■

 In the 1980s, to overcome these problems, discrete ferroelec-
tric capacitors were fabricated between insulating layers that
were above and isolated from the silicon and underlying CMOS
transistors. Noble metals, such as platinum, were used for the
electrodes of the ferroelectric capacitor, and oxygen loss from
the ferroelectric material no longer affected the channel regions
of the CMOS transistors. PZT (lead-zirconium-titanate) was the
first practical ferroelectric material to emerge for use in these
capacitors. It is relatively easy to deposit and provides a large sig-
nal for detecting the logical state of a memory cell. Each mem-
ory cell consisted of a single access transistor connected in series
with a ferroelectric capacitor, as shown schematically in Fig. 2,
an architecture similar to that patented earlier by Anderson.
While many materials exhibit ferroelectric behavior, they differ
in polarization properties and chemical and temperature sensitivi-
ties. Around 1990 another ferroelectric material was discovered
that provides virtually unlimited endurance when standard plati-
num electrodes are used [2]. This material is SBT (strontium-bis-
muth-tantalate), a layered perovskite that forms a superlattice
structure. Previously it was not even agreed if SBT was ferroelectric
at all because the ferroelectric effect in bulk SBT can be very small.
However, in thin-film form, SBT is clearly ferroelectric and pro-
vides excellent nonvolatile memory properties.
In the 1990s it became clear that SBT required higher an-
nealing temperatures than PZT. A rapid thermal anneal above
approximately 700 °C is required to set the proper ferroelectric
crystal structure of SBT instead of a non-ferroelectric crystal
4. SEM cross section of a ferroelectric memory cell. Ferroelectric ca-
pacitors for two adjacent memory cells are depicted. The metal
straps from the pass transistors to the top electrodes of the ferroelec-
tric capacitors are clearly visible. Courtesy of Hyundai Electronics
Industrial Co., Ltd.
Permittivity
εr
Tc
Temperature
5. Relative permittivity of a ferroelectric dielectric versus temperature.
■ 22
What Is a Ferroelectric?
“Ferroelectric” is a misnomer because a ferroelectric gen-
erally contains no iron or ferrous material. It derives from the
term “ferromagnetic” because ferroelectric materials exhibit
electrostatic polarization behavior analogous to ferromag-
netic polarization behavior. Ferroelectric behavior results
when there is more than one stable state for a charged ion in
the unit cell of the lattice structure. Shifting the positions of
the charged ions by applying an external electric field results
in an electrostatic polarization. The state of polarization or
changing state of polarization can be sensed in semiconductor
circuits by a number of techniques. This creates the nonvola-
tile memory effect of ferroelectric memories.
structure that forms at lower temperature. In contrast, pro-
cesses exist to form PZT capacitors at temperatures as low as 450
°C. The lower processing temperatures of PZT are advantageous
because compact memory cells can be fabricated with the ferro-
electric capacitors physically above the pass transistors by using
existing semiconductor processes and materials, as shown in
Fig. 3. Today, this can give PZT an economic advantage when
compared to SBT. Development efforts are in progress to find
materials and processes compatible with SBT that allow these
types of compact memory cells to be made. To date, most ferro-
electric memories have used larger memory cells where the
ferroelectric capacitor is formed above the field oxide adjacent to
the pass transistor and connected to the pass transistor by a
metal strap, as shown in Fig. 4.
Most recently, efforts have been directed at both lowering the
annealing temperatures for SBT and improving the nonvolatile
properties of PZT. For the latter, it has been discovered that the
use of nonplatinum electrodes, such as LSCO (lanthanum-
strontium-cobalt-oxide), can allow the endurance of PZT to ap-
proach that of SBT and the thickness of the PZT to scale below
100 nm, allowing PZT to have lower programming voltages.
In the 1990s, it was also discovered that perovskite ferroelec-
tric materials, such as PZT and SBT, were sensitive to hydrogen
exposure. Because insulators in semiconductor processes are of-
ten deposited in hydrogen-rich atmospheres, ferroelectric capaci-
tors should be encapsulated within a hydrogen barrier, such as
silicon nitride. Since silicon nitride itself is often deposited in the
presence of ammonia, additional barriers may also be required.
Many prototype ferroelectric PZT and SBT memories have
been developed [3-6] and the major processing issues have been
solved, so ferroelectric memories are now on the brink of enter-
ing the market. Because ferroelectric memory processes are
similar to those used for high-density stacked DRAMs that incor-
porate high dielectric constant insulators for the DRAM storage
capacitors, rapid increases in density and yield may be attained
for ferroelectric memories by leveraging off the DRAM learning
curve. Today, at least ten major semiconductor companies are
actively developing ferroelectric memories, so a critical mass ef-
CIRCUITS & DEVICES ■ JANUARY 2001
fort is being applied to bring both embedded and stand-alone ture Tc, the material undergoes a first-order phase transition to
ferroelectric memories to market. While both PZT and SBT the paraelectric phase. The relative permittivity becomes large at
ferroelectric technologies may coexist in the marketplace for the Curie temperature, and above the Curie temperature it typi-
some time, the ultimate choice probably will be determined by cally exhibits Curie-Weiss behavior given by
cost per bit, reliability, and nonvolatile memory properties.
εr = C ( T − Tc ), (1)
Basic Principles of Ferroelectrics
Ferroelectricity is the spontaneous alignment of electric dipoles where C is the Curie constant. Since the ferroelectric state does
by mutual interaction under the influence of an externally ap- not exist above the Curie temperature, it is important that the Cu-
plied electric field. Below a critical temperature called the Curie rie temperature for a ferroelectric material be high compared to
temperature, certain insulators exhibit ferroelectric behavior. the operating temperatures and accelerated testing temperatures,
The temperature dependence of the relative permittivity εr of a
typical ferroelectric material is shown in Fig. 5.
The term permittivity is used instead of dielectric constant be-
cause it is not constant for ferroelectric materials. Since the ca-
pacitance of a ferroelectric capacitor is directly proportional to the
permittivity of the ferroelectric material, the capacitance-temper- Bismuth Oxide
ature curves have the same basic shape as that shown in Fig. 5. As Layer
the ferroelectric material is heated through the Curie tempera-

O Perovskite
Layers

Bismuth Oxide
Layer

Perovskite
Layers

Bi

B
Cubic Perovskite
6. Perovskite crystal structure, ABO3. The two representations show O
the B cation in its two stable states. For PZT, A = Pb2+, B = Zr4+ or
Ti4+, and O = O2 . 7. Structure for a layered perovskite ferroelectric containing bismuth.

CIRCUITS & DEVICES ■ JANUARY 2001 23 ■

or well above 200 °C. While cations cause the lattice to
there is evidence that the
Curie temperature for a
A ferroelectric wafer fabrication process distort to tetragonal,
orthorhombic, or rhom-
thin-film ferroelectric ma- can be less expensive than a bohedral structures. The

conventional Flash memory or

terial may be different from tetragonal structure forms
that in its bulk state, this ef- as the cube stretches along
fect is not well documented.
The physical behavior of
EEPROM process that requires extra one side of the cube, form-
ing a longer axis (by defini-
one unit cell of a perovskite mask levels for the high voltage. tion, the c-axis), and
ferroelectric is depicted in shorter axes (by definition,
Fig. 6. The lattice structure the a-axes). An orthor-
is ABO3, where B is a cation located at the center of the unit cell, A hombic structure forms if the cube stretches along a face diago-
are relatively large cations located at the corners of the unit cell, nal. A rhombohedral structure forms if the cube stretches along a
and O are oxygen anions located at the face center positions. body diagonal. For both PZT and SBT, the cube stretches along
Above the Curie temperature, the perovskite structure has a cubic the c-axis. In a ferroelectric material, the polarization of the B cat-
symmetry and is paraelectric. Below the Curie temperature, the A ion occurs in the direction of the stretched axis.
Below the Curie temperature, the B ion in the center of the
unit cell has two stable equilibrium positions that cause the ferro-
electric effect. The positions of the B ions are controlled by the ap-
plication of an applied electric field to a capacitor containing the
ferroelectric material as the dielectric. If, by application of a volt-
age to the capacitor the positions of the B ions change, a switching
Bi-Double Layers

current flows between the plates of the capacitor because of the

change in position of the charge centroid in the ferroelectric.
Some typical perovskite ferroelectric materials are BaTiO3,
PbTiO 3 , PbZr 1-x Ti x O 3 (PZT), Pb 1-x La x Zr 1-y Ti y O 3 (PLZT),
PbMg1-xNbxO3 (PMN), SrBi2Ta2O9 (SBT), SrBi2Nb2O9 (SBN),
and SrBi2(Ta1-xNbx)2O9 (SBTN). The B cations are Ti, Zr, Mg, Ta,
and Nb. The latter three ferroelectric materials have the prop-
erty that they spontaneously layer themselves at the atomic
level, as shown in Figs. 7 and 8. A single atomic layer of Bi2O3
5nm forms, then two layers of ABO3 unit cells, and then another layer
of Bi2O3, and so forth.
A hysteresis curve of a ferroelectric capacitor is shown in Fig.
9, giving the response of the polarization P to an externally ap-
plied electric field E. The curve saturates at Ps when the maxi-
mum alignment of the polarization occurs. When the electric
8. TEM micrograph of the molecular structure of an SBT layer. field is removed after reaching Ps, the electronic polarization as-
Courtesy of Infineon Technologies. sociated with the linear capacitance component decreases to
zero, but spontaneous polarization remains. Then, often within
Polarization milliseconds, the polarization decays to the remnant polariza-
Ps tion Pr (sometimes referred to as “remanent” polarization). For
Pr much longer times, the polarization is observed to decay linearly
with the log of time for many orders of magnitude of time.
From Maxwell’s equations, the displacement charge density
−Vc Vc
D (in C/cm2) is related to the polarization and applied electric
Voltage
field by

−Pr
−Ps
9. Typical hysteresis curve for a ferroelectric material. The voltage
Vc is the coercive voltage, the polarization Ps is the spontaneous po-
larization, and the polarization Pr is the remnant polarization.
D = εo E + P, (2)
where εo is the permittivity of free space. For most ferroelectric
materials used in semiconductor devices, εoE < P so that D ~ P.
Therefore, the hysteresis curve shown in Fig. 9 is also approxi-
mately the displacement charge density versus electric field.

■ 24 CIRCUITS & DEVICES ■ JANUARY 2001

 The ferroelectric polarization can switch in less than one
nanosecond. The actual switching times are difficult to measure
because of the time constants of peripheral circuitry. Various
models have been presented to explain the time dependence of
the switching of ferroelectric materials. The switching dynam-
ics of ferroelectric devices are complex and depend on the orien-
tation of the grains in the poly-crystalline film; defects within
the grains, at grain boundaries, and at the electrodes; and the
pinning of ferroelectric domains.
A model for the switching current and switching time of
ferroelectric devices has been proposed by Ishibashi [7]. Larson
et al. have shown that there is a distribution of switching times
depending on the microstructure of the ferroelectric material,
Making Ferroelectrics
Figure 12 shows a typical ferroelectric process flow. First, the
underlying CMOS transistors and devices are fabricated. Then,
the ferroelectric process module is inserted. Finally, the metal
interconnect and final chip passivation are completed. With
PZT, it is also possible to insert the ferroelectric process module
after the metal interconnect steps but before the final chip
passivation [5]. Because the ferroelectric process module occurs
50
Non-Switching Current
40

Current (µA/µm2)
30 a
with measured switching times for certain microstructures of
20
PZT capacitors being of the order of a nanosecond or less [8].
10
Measured switching currents for a ferroelectric capacitor for b
an applied voltage pulse across an SBT capacitor are shown in 0
0 10 20 30 40 50
Fig. 10. The switching current is given by 10
Time (ns)
20 (a)
I( t) = CL dV dt + dQs dt,
35
Current (µA/µm2) 30 Switching Current
where CL is the linear capacitance and Qs is the switched charge 25
associated with the polarization change of the capacitor. Resis- 20
tive contributions are small for ferroelectric capacitors, so they 15 c
are not included in Eq. (3). The curve labeled “b” in Fig. 10 is the 10
measured current when the capacitor remains in the same po- 5
larization state condition. In this case, the first term in Eq. (3) 0
0 10 20 30 40 50
dominates. The curve labeled “a” is the measured current when −5
Time (ns)
the capacitor switches from the opposite polarization condition, (b)
and the second term in Eq. (3) dominates. The leading edges of
10. Ferroelectric switching current. The applied voltage pulse was 32
both curves track the rise time of the applied voltage pulse. The ns wide with a rise time of 5 ns. Measurements were made on a 25
area between the two curves represents the signal detected by m2 SBT capacitor with a 240 nm ferroelectric thickness. The curve
the sense amplifier and is shown as curve “c” in Fig. 10. The labeled “a” is the total measured current when the ferroelectric polar -
ization switches. The curve labeled “b” is the measured current when
switching time measured in Fig. 10 is not the actual switching the ferroelectric polarization does not switch and is the i = C(dV/dt)
time of the ferroelectric but is limited by the circuitry. current on the rising and trailing edges of the applied voltage pulse.
Switching currents for ferroelectric capacitors are relatively The difference between the two currents shown by the curve labeled
“c” is the switching current of the ferroelectric capacitor, the absence
large, unlike the relatively small detection currents from ferro- or presence of which is used to determine the logical state of the
magnetic memory cells. This provides plenty of signal for detec- memory cell.
tion of the logical state of the ferroelectric memory cells and
allows ferroelectric memories to be read without the necessity
20
for extensive error detection and correction.
Ferroelectric polarization is a strong function of voltage even
65 nm
for long switching times. Figure 11 shows saturated polariza-
2pr (µC/cm2)

180 nm
tion of a ferroelectric capacitor as a function of applied voltage
for two different ferroelectric thicknesses. Almost full polariza- 10
tion has occurred for an applied voltage of 2 V.
The programming voltage, ferroelectric film thickness, and
programming time are not independent parameters. For 200
nm films, voltages higher than 3 V may be required for complete 0
switching films for write times of the order of 20 ns. For 40 nm
films, voltages under 1.5 V may be sufficient for complete satura- 0 1 2 3 4 5
Amplitude (V)
tion for write times of the order of 10 ns. The switching time for
a given ferroelectric capacitor is also a function of the tempera- 11. Polarization saturation as a function of voltage. Data for SBT for
ture, with slower switching occurring at lower temperatures. two film thicknesses are shown.

CIRCUITS & DEVICES ■ JANUARY 2001 25 ■

relatively late in the fabrication process, the underlying CMOS
process is not significantly disturbed.
The ferroelectric module typically adds three photolitho-
graphic mask levels to the semiconductor fabrication process.
However, as compared to other types of conventional nonvolatile
semiconductor memory, the low programming voltages of ferro-
electric memory eliminate several mask levels required for these
other memories associated with charge pumps, high and low volt-
age – and p-wells, and high- and low-voltage CMOS transistors.
Therefore, a ferroelectric wafer fabrication process can be less ex-
pensive than a conventional Flash memory or EEPROM process
that requires extra mask levels for the high voltage.
In theory, a ferroelectric one-transistor, one-capacitor mem-
ory cell may consist of a single MOS transistor where the ferro-
electric capacitor is fabricated in the contact window of the drain
of the pass transistor. This would give a memory cell size com-
petitive with that of random-access (NOR architecture) Flash
memory. Today, the smallest ferroelectric memory cell is the
compact cell shown earlier in Fig. 3. This memory cell size is al-
most 50% larger than a NOR architecture Flash memory cell,
giving a chip size approximately 25% larger for today’s design
rules. However, the resulting increase in chip cost is offset by re-
duced test cost because the programming time of ferroelectric
memories is of the order of 50,000 times faster than that of Flash
memory. In the long term, ferroelectric memory can be cost
competitive with Flash memory. In the case where both Flash
memory and DRAMs are embedded in logic circuits, the cost of
ferroelectric memory to replace both can be significantly lower.
An ever-increasing percentage of area of conventional Flash
memory and EEPROM memory cells is consumed by silicon area
required to isolate the high programming voltages. Some pro-
jections show Flash memory cell scaling to be difficult at design
rules of 0.12 micron and smaller. Since ferroelectric memories
program at low voltage, such limitations are not known to exist
for ferroelectric memories.
Earlier in Fig. 4, the SEM cross section of a ferroelectric mem-
ory cell was shown for a ferroelectric memory cell where the ferro-
electric capacitor is fabricated above the field oxide adjacent to the
CMOS
Under Layers
Ferroelectric
Module
b Insulator
a d
Metallization
and Passivation
12. Typical ferroelectric process flow. “a” is the bit line; “b” is the pass transistor; “c” and “e” are
the top and bottom electrodes of the ferroelectric capacitor, respectively; and “d” is the ferroelec - voltages from appearing on deselected
tric material.
■ 26
What Do Ferroelectrics
Mean To The Consumer?
In a world that is becoming enamored with handheld and
wireless devices, ferroelectric nonvolatile memory may hold
the promise of becoming the future standard memory of
choice, provided that economical manufacturing challenges
can be met. Cellular phones, PDAs, palmtops, laptops, wire-
less web surfers, MP3 players, digital cameras, and smart
cards now proliferate with slow Flash memory and EEPROM
to store digital information. Fast programming, low-voltage
ferroelectric memories can mean lower power, longer bat-
tery life, and improved performance. Battery size and weight
can be reduced. The customer can speak longer, check mes-
sages and access stock quotes more frequently, listen to
more songs, and store pictures quicker, for example. Data
access is accelerated, which will continue to be tied to ulti-
mate user satisfaction.
pass transistor. For small-density embedded memory, such as
that used in low-density radio frequency identification (RFID)
tags or cards, where the silicon area occupied by the memory ar-
ray is less than 10% of the total chip area, these ferroelectric
memory cells can be used competitively. In Fig. 13, a photograph
of an RFID tag chip incorporating a 144-bit ferroelectric memory
is shown. Ferroelectric memories are particularly well suited for
read/write RFID tag applications because of their fast program-
ming times and low power.
Finally, the smallest and most cost competitive ferroelectric
memory may be realized by using a one-transistor ferroelectric
memory cell. These memory cells do not exist today but are under
development. There are two major challenges. First, a ferroelec-
tric material must be found that is compatible with silicon when
placed in close proximity with the silicon. A promising approach
is to develop a ferroelectric material that has a low permittivity so
that the formation of a thin oxide layer between the ferroelectric
material and the silicon channel of the
transistor is acceptable. Figure 14 shows
capacitance voltage curves for a capacitor
using a ferroelectric material with a rela-
tive permittivity of the order of 10 that is in
Ferroelectric direct contact with silicon. The shift in the
Capacitor two curves corresponds to the shift in the
turn-on voltage of a transistor if fabricated
similarly. The observed shift of over 2 V
c would be adequate to sense the logical
state of a memory cell. The second chal-
e
lenge for a one-transistor memory cell is to
design a memory array architecture that
does not require an additional pass transis-
tor in each memory cell to prevent disturb
memory cells.
CIRCUITS & DEVICES ■ JANUARY 2001
 Designing with Ferroelectrics For very rugged applications, such as RFID tags and space appli-
Ferroelectric chip design provides true random-access opera- cations, two one-transistor, one-capacitor memory cells may be
tion with the added advantages of virtually unlimited endurance used in tandem for each logical data bit. These memory cells are
and inherent nonvolatility. A schematic of a typical one-transis- programmed to opposite states to provide true and complement bit
tor, one-capacitor ferroelectric memory cell was shown previ- lines that are differentially sensed by a conventional sense ampli-
ously in Fig. 2. fier. This dual architecture provides a high level of margin.
It is helpful to compare this ferroelectric memory architec- Because ferroelectric memories operate at low voltages, care
ture to that of the popular dynamic random-access memory must be taken to assure that data do not get disturbed during
(DRAM). Whereas a DRAM signal is detected by sensing the pres- power-up, power-down, and brown-out conditions. There are no
ence or absence of charge stored on a capacitor, the ferroelectric charge pumps to turn off to prevent inadvertent programming.
signal is detected by sensing the presence or absence of switch- The nonvolatile data must also be protected for low power supply
ing current of the ferroelectric capacitor as the polarization state voltage and out-of-specification pulse widths and cycle times.
switches or remains the same when voltage is applied across the Additionally, the design should allow sufficient energy to be
ferroelectric capacitor. Leakage of the charge on DRAM storage stored on the chip to assure that the rewrite operation is com-
capacitors limits the data retention time, and extensive design pleted successfully even if the power is removed during the de-
provisions must be made to provide automatic rewrite cycles to structive read operation.
refresh the charge in each memory cell. In contrast to the vola-
tile DRAM, the polarization state of the nonvolatile ferroelectric
capacitor is unaltered if the power is removed. Refresh is not
necessary, and turning off the memory can conserve power
when it is not being read or written.
Memory-cell operation is similar to that of a DRAM except
for the plate line. As compared to a DRAM, the major difference
is that the plate line is decoded for the ferroelectric memory
cell instead of being directly connected to the silicon in the
memory array. First, the bit lines in the memory array are
precharged to a known voltage. Then the pass transistor for the
selected word line is turned on. A voltage pulse of approxi-
mately 10 ns is then applied to the plate line of the ferroelectric
capacitor. If the logical state of the ferroelectric capacitor is
such that the capacitor does not switch, the bit line charges at a
slow rate. However, if the logical state of the ferroelectric ca-
pacitor is such that the polarization switches, the bit line
charges more rapidly. Then the sense amplifier is powered and
the logical state of the sense amplifier is latched based on the
charging rate of the bit line. At the same time the sense ampli- 13. RFID tag chip containing 144-bit embedded ferroelectric mem-
fier is powered, power supply voltages are driven on the bit lines ory. The top portion of the chip contains the ferroelectric memory,
the middle portion contains the digital logic, and the lower portion
that automatically rewrite the ferroelectric capacitor in ap- contains the analog radio frequency circuitry.
proximately 10-20 ns to its initial logical state after the destruc-
tive read sense operation. 16.0
The chip operation is similar to that of other random-access 14.0
memories. Because of the fast programming time, there is no
Capacitance (pF)

12.0
need to poll the part to see if it is busy during a write cycle, as is
10.0
needed for Flash memory or EEPROM.
A ferroelectric memory with destructive read sensing oper- 8.0
ates in a synchronous timing mode. The rewrite cycle must be 6.0
completed to assure uncorrupted data in the memory. On the 4.0
falling edge of chip enable, address bits and input data are
2.0
stored on internal latches for the duration of the synchronous
read/write cycle. In contrast, nondestructive read memories,
−6.0 −4.0 −2.0 0.0 2.0 4.0 6.0
such as Flash memory and EEPROM, can operate in an asyn- Voltage (V)
chronous manner where valid data appear at the memory out-
put one read access time after a valid address is applied at any 14. Capacitance-voltage curves for a low permittivity ferroelectric
material in contact with silicon. The shift in the two curves is indica-
time, irrespective of the clock. System designers need to be tive of the threshold voltage shift that would be observed on a transis-
aware of this difference. tor fabricated similarly. Courtesy of Cova Technologies Incorporated.

CIRCUITS & DEVICES ■ JANUARY 2001 27 ■

 Reliability for Today’s Markets
Since larger-bit-capacity ferroelectric memories are just enter-
ing production, failure rates in production have not been exten-
sively characterized. However, the reliability of small
ferroelectric memories has been compared to the reliability of
small-density floating-gate EEPROM memories and found to be
comparable or better. Failure rates for low-density SBT embed-
ded ferroelectric memories have been characterized. Failure
rates for chips with 288-bit and 1120-bit SBT-embedded ferro-
electric memories are shown in Fig. 15 [9]. The failure rate for
both memories is observed to be under 100 FITs at 70 °C and is
also observed to be independent of the memory density. One FIT
is one device failure per 109 device operating hours. These are
competitive failure rates for the commercial market.
108
256 bit
107
1 K bit
106
105
Failure Rate (FIT)
Of concern for any memory technology is the failure rate for
freak single-bit cells, not just the failure rate for nominal mem-
ory cells. Such data are not yet available for ferroelectric memo-
ries since the memory densities have been small and production
volumes have been limited.
Endurance
High endurance is critical for one-transistor, one-capacitor
ferroelectric memory cells because a destructive read operation
is used. This means that a rewrite operation occurs for every
read and, unlike nondestructive read memory, the endurance
specification applies to read operations as well as write opera-
tions. Continuously reading a bit at a 100 ns cycle time for ten
years corresponds to approximately 3 × 1015 write cycles. While
this scenario is unlikely to occur during operation in a real sys-
tem, 3 × 1015 programming cycles for endurance is a good target
for ferroelectric memories that use destructive read sensing.
Figure 16 shows the endurance of an SBT capacitor with plat-
inum electrodes [10]. Figure 17 shows the endurance of a PZT
capacitor with LSCO electrodes. In both cases, there is no evi-
dence for any impending endurance failure. Since typical en-
durance characteristics display signal roll off over at least a few
orders of magnitude in programming cycles, it is anticipated
that endurance levels of greater than 5 × 1015 can be obtained for

ferroelectric memories.
104
Retention
103 Data in a ferroelectric memory is stored as a retained polarization
state that depolarizes gradually with time. The available switched
102 charge from a polarized ferroelectric capacitor is observed to decay
linearly with the logarithm of time if the decay rate is accelerated by
101 increasing the temperature to 150 °C or higher. Decay in polariza-
tion of an SBT ferroelectric capacitor fabricated with a double metal
27 °C process is shown in Fig. 18. Since a sense amplifier can sense less
100
than 50 mV, devices fabricated with this SBT process can provide
70 °C
10−1 greater than ten-year retention at the highest operating tempera-
2 2.5 3 3.5 tures. Decay in polarization for a PZT ferroelectric capacitor is
1000/T (1/K)
shown in Fig. 19. The “log time” functional dependence observed
15. Ferroelectric memory failure rates [9]. in both cases is similar to that observed for other common phe-
nomena, such as decay of trapped charge in silicon nitride nonvola-
tile memory devices and decay of radiation induced charge in
1.4 transistor gate insulators. The physical mechanisms behind reten-
1.2 tion loss in ferroelectric devices are not well understood.
Normalized Polarization

Retention limitations are believed to dominate the failure

1.0
rates shown earlier in Fig. 15. For the ferroelectric process used
0.8 for fabrication of the embedded memories tested in Fig. 15, re-
0.6 tention performance can be calculated from

0.4 RFIT = 10(17 .8 − 5424 / T ) , (4)

0.2

0
where RFIT is the FIT failure rate and T is the temperature in de-
100 105 1010 1015 grees Kelvin.
Endurance Cycles Ferroelectric capacitors may also exhibit a behavior known as
16. Endurance of an SBT ferroelectric capacitor with imprint. If a ferroelectric capacitor is programmed repeatedly to
platinum electrodes [10]. the same state, that state may become preferred or reinforced. If

■ 28 CIRCUITS & DEVICES ■ JANUARY 2001

the capacitor is then pro-
grammed to the opposite
state, the retention in the
opposite state may be
ferroelectric 1 K embedded
The reliability of small ferroelectric memories have also been
exposed to unbiased proton
memories has been compared to the bombardment (simulating

reliability of small-density floating-gate

poorer than for a capacitor the solar wind) in excess of
that has not been im- 1012 protons/cm2 with no
printed. The imprint effect
may be stronger at higher
EEPROM memories and found to be bit failures. These radia-
tion survival levels are ade-
temperatures. The physi- comparable or better. quate for extreme radiation
cal mechanisms for im- environments.
print are not well under-
stood, nor are there standard definitions for retention and im- The Promise of Ferroelectrics
print in the industry. Properly fabricated ferroelectric devices Nonvolatile ferroelectric semiconductor memories are just be-
show little imprint. ing introduced into the marketplace, both as embedded memory
The retention decay rate increases with higher temperature. in logic products and stand-alone memory. Ferroelectric mem-
The retention decay rate may also be observed to increase with
endurance cycling. Therefore, practical ferroelectric memories
must be guaranteed to have adequate retention under the worst 40
case endurance, high-temperature, and imprint conditions.
Care must be taken in defining a retention test for ferroelec- 30
tric memories since the destructive read operation causes the re-
tention to be set to time zero with every read operation. A test 20
sequence for retention is to cycle the devices with unipolar
Polarization (µC/cm2)

pulses to the same polarization state at the highest device tem- 10

perature. Then the devices are written to the opposite state. The
∆P
retention decay rate at high temperature is determined by mea- 0
suring a parameter related to the remaining switched charge in −∆P
the ferroelectric capacitor at a later time. This testing can be ac- −10
complished on a sample basis for a given product to assure reli-
ability. Certain design schemes allow this margin testing to be −20
accomplished on every bit of every memory prior to shipment to
−30
a customer. Use of margin testing can result in ferroelectric
memories with very high reliability levels.
−40
1 102 104 106 108 1010 1012
Space – the Ferroelectric Frontier Endurance Cycles
Ferroelectric capacitors are tolerant to many forms of radiation.
When combined with radiation-hardened CMOS technology, ra- 17. Endurance of a PZT ferroelectric capacitor with LSCO electrodes.
Courtesy of Radiant Technologies.
diation-resistant ferroelectric technology can provide high-speed
nonvolatile memories that are suitable for near- and deep-space 800
applications. It has been demonstrated that the ferroelectric pro- Measured
cess module does not degrade the radiation hardness of underly- Fitted
Extrapolated
ing CMOS circuitry. Ferroelectric memories can be used in space 600
Signal Margin (mV)

applications where the low radiation resistance, slow program-

ming times, limited endurance, and high power of other semicon-
ductor nonvolatile memories are unsuitable. 400
A number of investigations have shown ferroelectric capaci-
tors to be tolerant to total ionizing radiation doses greater than 1
Mrad (Si) without loss of data. The design margin of the ferro-
200
electric sense amplifier may allow the correct memory state to
161 mV
be sensed for doses up to 10 Mrad (Si) or more.
After 10 Years
Ferroelectric capacitors have been shown to be tolerant to 0
neutron doses of at least 1015 neutrons/cm2. Commercial ferro- 100 102 104
electric 1 K embedded memories have been subjected to unbi- Retention Time (hr)
ased single event upset (SEU) heavy ion exposure of an effective 18. Retention decay for SBT Ferroelectric capacitors. Courtesy of
dose up to 128 MeV-cm2/mg with no bit failures. Commercial Hyundai Electronics Industries Co., Ltd.

CIRCUITS & DEVICES ■ JANUARY 2001 29 ■


20
15
Polarization (µC/cm2)
10
5 semiconductor processes for all Inmos products. Since leaving
0
100 101 102 103 104
Retention Time (sec)
19. Retention decay for PZT ferroelectric capacitors with LSCO elec-
trodes. Room temperature data are shown. Courtesy of Radiant
Technologies.
ories feature very fast programming times; fast read times; virtu-
ally unlimited endurance; and low-voltage, low-power
operation. With a memory-cell size comparable to that of a
DRAM memory cell and a manufacturing process similar to that
of a stacked high-density DRAM, it can be expected that the
ferroelectric technology will leverage off DRAMs and leap frog to
higher memory densities. Cost analysis projects cost competi-
tiveness with Flash memory and EEPROM.
SBT ferroelectric memory technology has been shown to
have reliability levels comparable to or better than other repro-
grammable nonvolatile semiconductor memories. High levels
of radiation hardness make these memories suitable for near-
and deep-space applications. Many large semiconductor compa-
nies have substantial efforts to develop and introduce ferroelec-
tric memories into the market.
When one considers the recent phenomenal growth of con-
sumer-driven product markets, the volume business potential
for ferroelectric memory as a replacement for Flash memory or
EEPROM in handheld electronics can be staggering. That is why
some have referred to ferroelectrics as the “Holy Grail” of
reprogrammable semiconductor nonvolatile memory.
Acknowledgments
The authors thank Dave Kamp, Alan DeVilbiss, and Steve Philpy at
Celis Semiconductor for their help with this article. The authors
also thank Dr. Joe Evans of Radiant Technologies, Dr. Fred
Gnadinger of Cova Technologies, Dr. N.S. Kang of Hyundai, and
Dr. Carlos Mazuré of Infineon Technologies for providing figures
■ 30
used in this article. The data shown in Fig. 14 from Cova Technol-
ogies was developed under a program supported by the Ballistic
Missile Defense Organization under an SBIR grant administered
by the US Army Space and Missile Defense Command.
Gary Derbenwick is president and CEO of Celis Semiconductor
Corporation. After receiving his Ph.D. from Stanford University
in 1970, he joined Bell Laboratories where he worked on semicon-
ductor devices, processes and design. In 1974 he joined Sandia
National Laboratories where he developed radiation hardened
CMOS processes and nonvolatile memories. From 1980 through
1985 he worked for Inmos Corporation and was responsible for
Inmos, he co-founded two semiconductor companies, Simtek
Corporation and Celis Semiconductor Corporation, both of which
have a focus on nonvolatile memory products.
105
Alan Isaacson is vice president of sales and marketing and chair-
man of the board of Celis Semiconductor Corporation. With
over 20 years of experience in the semiconductor industry, he
has held numerous technical positions with Honeywell and
Kyocera America, contributed to the development of hundreds
of advanced package designs for semiconductor and radio fre-
quency applications, and has been a senior sales account execu-
tive representing IBM Corporation, Catalyst Semiconductor,
and others.
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