Inter Integrated Circuit Bus Protocol

(I2C)

by: Dr. Mitesh Limachia

Need of Serial Bus Protocol
• Peripheral devices in embedded systems =>
parallel address and data bus => lots of wiring and
requires more number of pins => additional decoding
logic required.

• To reduce the pins and wiring => cost => Serial bus
protocol => I2C (2-wire) & SPI (4-wire)

• Penalty => Slower communication.

 Various Serial Bus Protocols
• UART
• I2C- Embedded System Protocol
• SPI –Embedded System Protocol
• I2S- Audio/Sound Bus Protocol
• CAN
• USB etc..
• I2C bus => Philips, consumer products (TV)

• Originally intended for operation on one single

board (PCB)

• Today, variety of devices are available with

on-chip I2C interface. i.e. Microcontroller,
E2PROM, A/D converters etc.
I2C Bus Configuration Example
I2C Bus Terminology

Term Description

Transmitter Device which send data to bus

Receiver Device which receives data from bus
Master Device which initiates transfer, generate CLK signal to
permit data transfer and stop data transfer
Slave Device addressed by Master
Multi-Master More than one Master control bus at same time
Arbitration Procedure to allow one Master among Multi-Master,
whose winning message is not corrupted
I2C Bus Characteristics

• Two wires, SDA, SCL carry information between

devices connected on bus

• Every device hooked on the bus is identified by

unique address (7-bit slave address)

• Synchronous, Half-duplex serial communication

• Unique Start and Stop conditions

• Multi-Master Capability

• Bi-directional data transfer

• Acknowledgement after each transferred byte

Improves reliability of communication

• No chip enable (Slave Select Signal, SPI) is required.

Realization

LCD

MCU
DATA Transfer on the I2C Bus

• In normal data transfer, the data line (SDA) only

changes state when the clock (SCL) is low.

SDA

SCL
Data line stable; Change
Data valid of data
allowed
Start and Stop Conditions
A transition on the data line while the clock line is high is
defined as either a start or a stop condition.

Both start and stop conditions are generated by the bus

master

The bus is considered busy after a start condition, until a

stop condition occurs

SDA SDA

SCL SCL

Start Stop
Condition Condition
Addressing Scheme

• Every devices, hook up on bus=> own unique address.

• Master => 7-bit address => device which it want to access.

• After START condition, 7-bit address sent along with data

direction bit (R/W’)

• Always, first byte of data transfer.

First Byte in Data Transfer on the I2C Bus
MSB LSB

R / Wr

7 – Bit Slave Address ACK

By Slave
R/W’
0 – Slave written by Master
1 – Slave read by Master

ACK – Generated by the slave whose address has been output

‘ ‘ ‘ ‘
MASTER

SLAVE
 Acknowledge
• The acknowledge takes place after every byte. The
acknowledge bit allows the receiver to signal the
transmitter that the byte was successfully received and
another byte may be sent.
• The Acknowledge signal is defined as follows: the
transmitter releases the SDA line during the acknowledge
clock pulse so the receiver can pull the SDA line LOW and
it remains stable LOW during the HIGH period of this clock
pulse.
• When SDA remains HIGH during 9th clock pulse, this is
defined as the Not Acknowledge signal. The master can then
generate either a STOP condition to abort the transfer, or a
repeated START condition to start a new transfer.
Data Transfer on the I2C Bus
• Start Condition
• Slave address + R/W
– Slave acknowledges with ACK (9th SCK)
• All data bytes
– Each followed by ACK
• Stop Condition

SDA

ACK from ACK from

Slave Slave

SCL
Remember : Clock is produced by Master
Start Stop
Multi-Master Capability

• Two Master can begin transmitting on an idle bus at

the same time. Method deciding which master take
control of the bus and completes its transmission.

• Arbitration (SDA Line)

• Clock Synchronization (SCL Line)

Arbitration
• Multiple masters can be connected to the same I2C
bus and operate concurrently.

• It is possible that two masters start a transfer at the

same time. During the transfer, the masters
constantly monitor SDA and SCL. If one of Master
detects that SDA is low when it should actually be
high, it assumes that another master is active and
immediately stops its data transfer. This process is
called arbitration.
Arbitration Between Two Masters

• As the data line (SDA) is like a wired AND,

ZERO address bit overwrites a ONE address bit.
• During every bit, while SCL is high each master checks to see
SDA level matches with what it has sent.

22 of 40
 Contd.
• The master tries to send a HIGH, but detects that the SDA
level is LOW, the master knows that it has lost the arbitration
and will turn off its SDA output driver. The other master goes
on to complete its transaction.
• No information is lost during the arbitration process.
A master that loses the arbitration can generate clock
pulses until the end of the byte in which it loses the
arbitration and must restart its transaction when the bus is
idle.
• Two masters can actually complete an entire transaction
without error, as long as their data transmissions are
identical.
 Example-2
• Two or more masters may generate a START condition at the same time
• Arbitration is done on SDA while SCL is HIGH - Slaves are not involved

Master? loses arbitration

DATA1 “0”
0

“1”

DATA2
0

“0”
SDA
0

SCL
0
START “1” “0” “0” “1” “1” “0”

24
Clock Synchronization
• The I2C bus protocol has the clock
synchronization mechanism between the
slower and faster devices. There will be a
handshake mechanism between slower and
faster devices.
Clock Synchronization
• CLK Synchronization => Wired-AND function on SCL line.

• SCL line => held Low by Master with longest LOW period,
Master with shorter LOW periods enter HIGH wait-states
during time.
 Contd.
• In this way, a synchronized SCL clock is generated.
• LOW period of SCL is determined by the master with the
longest clock LOW period, and its HIGH period
determined by the one with the shortest clock HIGH
period.
• Assume the followings in sequence in context of I2C bus
protocol:
(i) Master1 & Master2 having a clock of 100 KHz and
50 KHz respectively.
(ii) Master1 & Master2 generates the START conditions
simultaneously on the bus.
(iii) Master1 wants to send first data byte (address + R/W)
0x65H on the I2C SDA line while Master2 wants to send first
data byte 0x95H.

• Answer followings:
(a) Which Master will send its first data byte successfully?
Discuss the same using arbitration procedure.
(b) What is the frequency of SCLK set by I2C interface?
Discuss the same using clock synchronization procedure.
 I2C Bus
Programming
using
STM32F103C8 Kit
 I2C Data Register (I2C_DR)

Bits 15:8 Reserved forced by hardware to 0.

Bits 7:0 DR[7:0] 8-bit data register. It holds byte to be transmitted or received .

Transmitter Byte transmission starts automatically when a byte is written in the DR register.
mode: A continuous transmit stream can be maintained if the next data is put in DR ,

Received byte is copied into DR (RxNE=1).

Receiver
A continuous transmit stream can be maintained if DR is read before the next data byte is
mode:
received (RxNE=1).
• I2C Control Register (I2C_CR1)
Bit 15 SWRST: 0: I2C Peripheral not under reset. 1: I2C Peripheral under reset state
Bit 13 ALERT: SMBus alert
Bit 12 PEC: Packet error checking.
Bit 11 POS: Acknowledge/PEC Position (for data reception)
Bit 10 ACK: Acknowledge enable. 0: No acknowledge returned
Bit 9 STOP: Stop generation
Bit 8 START: Start generation
Bit 7 NOSTRETCH: 0: Clock stretching enabled. 1: Clock stretching disabled
Bit 6 ENGC: General call enable.
Bit 5 ENPEC: PEC enable. 0: PEC calculation disabled. 1: PEC calculation enabled
Bit 4 ENARP: ARP enable.
Bit 3 SMBTYPE: SMBus type, 0: SMBus Device. 1: SMBus Host
Bit 1 SMBUS: SMBus mode, 0: I2C mode. 1: SMBus mode
Bit 0 PE: Peripheral enable. 0: Peripheral disable. 1: Peripheral enable.
 Contd.
• Bit 8 START: Start generation
Setting the START bit causes the I2C interface to generate a
Start condition and to switch to Master mode.
- In Master Mode:
0: No Start generation
1: Repeated start generation

• This bit is set and cleared by software and cleared by hardware

only when start condition is generated on the bus.
 I2C Status Register1 I2C_SR1

SMBALERT
Bit 15 SMBus alert
:
Bit 14 TIMEOUT: Timeout or Tlow error
Bit 12 PECERR: PEC Error in reception
Bit 11 OVR: Overrun/Underrun
Bit 10 AF: Acknowledge failure
Bit 9 ARLO: Arbitration lost (master mode)
Bit 8 BERR: Bus error
Bit 7 TxE: Data register empty (transmitters)
Bit 6 RxNE: Data register not empty (receivers)
Bit 4 STOPF: Stop detection (slave mode)
Bit 3 ADD10: 10-bit header sent (Master mode)
Bit 2 BTF: Byte transfer finished
Bit 1 ADDR: Address sent (master mode)/matched (slave mode)
Bit 0 SB: Start bit (Master mode)
 Contd.
• Bit 0 SB: Start bit (Master mode)
0: No Start condition 1: Start condition generated.
– Set by hardware when a Start condition generated.
– Cleared by software by reading the SR1 register followed by
writing the DR register.

• Bit 1 ADDR: Address sent (Master mode)

Address Matched(Slave)
0: Address mismatched or not received 1: Received address matched

• Set by hardware as soon as the received slave address matched with

the OAR registers
• This bit is cleared by software by reading SR1 register followed by
reading SR2.
 Contd.
• Bit 7 TxE: Data register empty (transmitters)
0: Data register not empty
1: Data register empty

– Set when DR is empty in transmission.

Next byte can be put in DR register.
-- TxE is not set during address phase.
– Cleared by software writing to the DR register
 I2C Status Register2 I2C_SR2

Packet error checking register -contains

Bits 15:8 PEC[7:0]
the internal PEC when ENPEC=1.
Bit 7 DUALF: Dual flag (Slave mode)
Bit 6 SMBHOST: SMBus host header (Slave mode)
SMBDEFAU SMBus device default address (Slave
Bit 5
LT: mode)
Bit 4 GENCALL: General call address (Slave mode)
Bit 2 TRA: Transmitter/receiver
Bit 1 BUSY: Bus busy
Master/slave. 0: Slave Mode. 1: Master
Bit 0 MSL:
Mode
 I2C Control Register 2 I2C_CR2

Bit 12 LAST: DMA last transfer.

Bit 11 DMAEN: DMA requests enable
Bit 10 ITBUFEN: Buffer interrupt enable
Bit 9 ITEVTEN: Event interrupt enable
Bit 8 ITERREN: Error interrupt enable
Bits 5:0 FREQ[5:0]: Peripheral clock frequency in MHz.
Bits 5:0 FREQ[5:0]: Peripheral clock frequency
The FREQ bits must be configured with the APB clock frequency value The minimum
allowed frequency is 2 MHz and cannot exceed 50 MHz
0b000010: 2 MHz

…...
0b110010: 50 MHz
 I2C Clock Control Register I2C_CCR

I2C master mode selection. 0: Standard Mode I2C.

Bit 15 F/S:
1: Fast Mode I2C
Bit 14 DUTY: Fast mode duty cycle.
Clock control register in Fast/Standard mode (Master
mode). Controls the SCL clock in master mode.
Bits 11:0 CCR[11:0]:
Standard mode:
Thigh = CCR * TPCLK1, Tlow = CCR * TPCLK1

In Sm mode, to generate a 100 kHz SCL frequency:

If FREQ = 08, TPCLK1 = 125 ns so CCR must be programmed
with 0x28 (0x28 <=> 40d x 125 ns = 5000 ns.)
 Operating Modes
Four operating modes are:
• Master Transmitter
• Master Receiver
• Slave Receiver
• Slave Transmitter
 Master Transmitter Mode

• Master sends the START condition on the bus by setting

START bit.
• The interface waits for the SB flag (Status register) to be set
and then cleared by writing the slave address in the DR
register.
• The interface waits for the ADDR flag to be set then cleared
by reading the SR1 followed by SR2 status register.
• Master writes the first data byte in the data register. It then
continues by writing the next data bytes in the data register
after every TxE.
• After the last byte is written to the DR register, the application
software must set the STOP bit to generate a STOP
condition.
Sample C-Code
Data=0xAA, 0x03

Address=0x38,
DAC
 Program Code

#include<stm32f10x.h>
char res;

void I2C_init()
{
RCC->APB1ENR |= (1<<21); I2C1 clock enable.
I2C1->CR2 = 0x0008; To set the clock frequency of
I2C1->CCR = 0x0028; SCL = 100 KHz

I2C1->CR1 = 0x0001; //enable I2C1 peripheral

}
void I2C_Start()
{
I2C1->CR1 |= 1<<8; // Set start bit
I2C1->CR1 |= 1<<10; //I2C ack set
while (!(I2C1->SR1 & 0x0001)); //Set when start cond. generated
}

void I2C_Addr (unsigned char adr)

{
I2C1->DR = adr | 0; // Address kept in Data register
while (!(I2C1->SR1 & 0x0002)); // ADDR bit is checked.
res = (I2C1->SR2); // Reading of SR2 to clear ADDR bit
}
void I2C_Write (unsigned char c)
{
I2C1->DR = 0XAA; // Data 0xAA
while (!(I2C1->SR1 & (1<<7))); // TxE bit Checked.
// Set when DR is empty
I2C1->DR=0x03; // Next data
while(!(I2C1->SR1&(1<<7)));// Set when DR is empty
}

void I2C_Stop (void)

{
I2C1->CR1 |= 0x0200; // Stop bit set
while (I2C1->SR2 & 0x0002); // Communication going on or not
}
int main ()
{
I2C_init ();
I2C_Start( );
I2C_Addr(0x70);
I2C_Write();
I2C_Stop( );
}
Verification of I2C Bus
Start ACK
Condition R/W =0
ACK
7 bit Slave
Stop
Address
Condition

Data = 0x41(A)