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04 - NuMicro WDT - Timer - RTC - UART PDF
04 - NuMicro WDT - Timer - RTC - UART PDF
04 - NuMicro WDT - Timer - RTC - UART PDF
NuMicro@nuvoton.com
1
Agenda
Four sets of 24-bit Timer with 8-bit prescale
A 18-bit Watch dog timer
Real time clock with calendar
Just for NUC100 series
Up to three fully programmable UART channels.
Support Auto Flow Control Function
Support Support IrDA SIR Function.
Support LIN break Function.
2
Timer Feature
Four sets of 24-bit up-counting timer
Five selections of clock source and a prescale for every
timer
Time out period = (Period of timer clock input) * (8-bit
Prescale + 1) * (24-bit TCMP)
Four operation modes.
one shot, periodic, toggle mode and auto-reload counting mode
3
Timer Operation Mode
Ex: TCMPR=100
Interrupt
Reset counter
Periodic 0 100
Toggle Output :
Reset counter TM0PB8 , TM1PB9
0 100
TM2PB10 , TM3PB11
Toggle
Overflow
4
NUC100 Series Timer Clock Source
TMRx_S.CLKSEL
TMRx_EN
22.1184M
1xx
Reserved
011 TMRx_CLK
HCLK
010
32K
001
12M
000
5
M051 Series Timer Clock Source
TMRx_S.CLKSEL
TMRx_EN
22.1184M
1xx
Reserved
011 TMRx_CLK
HCLK
010
Reserved
001
12M
000
6
NuMicroTM Family Timer Block Diagram
24-bit TDR[23:0]
Refresh every four
timer clocks
TCSR.CRST[26]
load
Reset counter TCSR.TDR_EN[16]
Clear bit
TCSR.CEN[30] Reset counter in
MODE=00/01/10
8-bit
TMRx_CLK 0 24-bit up-counter Timer Interrupt
Prescale SET
D Q TISR.TIF[0]
TMx 1
+
=
- CLR Q
Time out period = (Period of timer clock input) * (8-bit Prescale + 1) * (24-bit TCMP)
TMAX = (1 / 12 MHz) * (28) * (224-1) ≒357.9 sec.
TMIN = (1 / 12 MHz) * (1+1) * (2) ≒0.333 usec.
8-bit Prescale: 1~255, Setting 0 will disable prescale clock
24bit TCMP: 2~(224-1)
Timer clock input: 12Mhz
7
Timer Example
Timer sample code with driver
Open timer0 and install a callback function to count from 0 to
10.
Call timer delay
8
Timer Sample Code with Driver
/*----------------------------------------------------------------------------
MAIN function
----------------------------------------------------------------------------*/
volatile uint32_t u32Timer0Cnt = 20;
int32_t main (void)
{
uint32_t u32Timer0Cnt=0;
DrvSYS_SelectIPClockSource(E_SYS_TMR0_CLKSRC, 0);
DrvTIMER_Init();
/* Using TIMER0 PERIODIC_MODE , the interval is set 2 tick /sec */ 1 tick = 0.5 sec
DrvTIMER_Open(E_TMR0, 2, E_PERIODIC_MODE);
/* Install Callback function "call_back" and execute it when Interrupt happen twice time */
DrvTIMER_SetTimerEvent(E_TMR0, 2, (TIMER_CALLBACK)TMR0_Callback, 1);
/* Enable TIMER0 Interrupt */
DrvTIMER_EnableInt(E_TMR0);
/* Start counting */
2 ticks = 1 sec
DrvTIMER_Start(E_TMR0);
/*Waiting for 10 times timer callbacks */
while(u32Timer0Cnt < 10);
/* Delay 4 ticks*/
DrvTIMER_Delay(E_TMR0, 4); 4 ticks = 2 sec
/* Close TIMER0 */
DrvTIMER_Close(E_TMR0);
}
void TMR_Callback()
{
u32Timer0Cnt++;
} 9
Timer Sample Code(1/2)
/*----------------------------------------------------------------------------
MAIN function – five steps
----------------------------------------------------------------------------*/
int32_t main (void)
{
/* Step 1. Enable and Select Timer clock source */
//Select 22Mhz for Timer0 clock source
SYSCLK->CLKSEL1.TMR0_S = 4; 22MHz
//Enable Timer0 clock source
SYSCLK->APBCLK.TMR0_EN =1;
Periodic mode
/* Step 2. Select Operation mode */
//Select periodic mode for operation mode
TIMER0->TCSR.MODE=1;
/* Step 3. Select Time out period = (Period of timer clock input) * (8-bit Prescale + 1) * (24-bit
TCMP)*/
// (1/22118400)*(1+1)*(2765)= 250.02usec or 3999.71Hz
// Set Prescale [1~255]
TIMER0->TCSR.PRESCALE=1;
// Set TCMP [2~16777215]
~4KHz
TIMER0->TCMPR= 2765;
10
Timer Sample Code(2/2)
/* Step 4. Enable interrupt */
TIMER0->TCSR.IE = 1;
//Write 1 to clear for safety
TIMER0->TISR.TIF = 1;
//Enable Timer0 Interrupt
NVIC_EnableIRQ(TMR0_IRQn);
12
WDT Clock Source
WDG_S (CLKSEL1[1:0])
WD_CLK_EN(APBCLK[0]
10KHz
11
NUC100 Series
WDT_CLK
HCLK/2048 10
Reserved
01
Reserved
00
WDG_S (CLKSEL1[1:0])
WD_CLK_EN(APBCLK[0]
10KHz
11
WDT_CLK
M051 Series HCLK/2048 10
Reserved
01
Reserved 00
13
WDT Block Diagram
WDT can cause a WDT Interrupt or WDT Reset to CPU after a fixed delay period.
WDT also can wakeup CPU form Power-down mode
WTR(WDTCR[0])
Reset WDT
Counter WTIF Watchdog
18-bit WDT Counter (WTCR[3]) Interrupt
WTIE
0 .. 4 …... 15 16 17
(WTCR[6])
000
Delay
001
:
Time-
1024
Watchdog
: out Reset
WDT
110 select WTRE
111 clocks
WDT_CLK (WTCR[1])
WTRF
WTE (WTCR[2])
(WTCR[7]) WDTCR.
WTIS[10:8] Wakeup CPU from
Power-down mode
WTWKE
(WTCR[4])
WTWKF
(WTCR[5])
14
WDT Time Out Select
WTR Timeout Interval
Interrupt Watchdog Reset for Reset
WTIS
Timeout Timeout (WDT_CLK=10KHz)
24 WDT_CLK (24 + 1024)` WDT_CLK 1.6 ms ~ 104 ms
000
(16 WDT_CLK) (1040 WDT_CLK)
(26 + 1024) 6.4 ms ~ 108.8 ms
001 26 WDT_CLK
WDT_CLK
(28 + 1024) 25.6 ms ~ 128 ms
010 28 WDT_CLK
WDT_CLK
(210 + 1024) 102.4 ms ~ 204.8 ms
011 210 WDT_CLK
WDT_CLK
(212 + 1024) 409.6 ms ~ 512 ms
100 212 WDT_CLK
WDT_CLK
(214 + 1024) 1.6384 s ~ 1.7408 s
101 214 WDT_CLK
WDT_CLK
(216 + 1024) 6.5536 s ~ 6.656 s
110 216 WDT_CLK
WDT_CLK
(218 + 1024) 26.2144 s ~ 26.3168 s
111 218 WDT_CLK
WDT_CLK 15
WDT Example
WDT sample code with driver
Open WDT and then install callback function to clear WDT
counter
16
WDT Sample Code with Driver
/*----------------------------------------------------------------------------
MAIN function
----------------------------------------------------------------------------*/
int32_t main (void)
{
DrvSYS_SetIPClock(E_SYS_WDT_CLK,1); 10KHz
DrvSYS_SetIPClockSource(E_SYS_WDT_CLKSRC,0);//10KHz
UNLOCKREG();
DrvWDT_Open(E_WDT_LEVEL4); //Level4 212 WDT_CLK
DrvWDT_InstallISR((WDT_CALLBACK)WDT_Callback);
DrvWDT_Ioctl(E_WDT_IOC_ENABLE_INT, 0);
DrvWDT_Ioctl(E_WDT_IOC_START_TIMER, 0);
while(1);
}
void WDT_Callback()
{
UNLOCKREG();
DrvWDT_Ioctl(E_WDT_IOC_RESET_TIMER, 0);
DrvWDT_Close();
LOCKREG();
}
17
WDT Sample Code(1/2)
/*----------------------------------------------------------------------------
MAIN function – 5 steps
----------------------------------------------------------------------------*/
int32_t main (void)
{
UNLOCKREG();
/* Step 1. Enable and Select WDT clock source */
//Select 10Khz for WDT clock source
SYSCLK->CLKSEL1.WDG_S =3;
10KHz
//Enable WDT clock source
SYSCLK->APBCLK.WDG_EN =1;
19
NUC100 Series RTC Features
RTC counter
Time counter
Calendar counter
Day of week
Leap year
BCD format
TLR=0x00093043
CLR=0x00120229
A set of Alarm
Alarm and time tick interrupt
Wakeup function
32KHz compensation
20
RTC Block Diagram
Time Alarm Calendar Alarm
Register (TAR) Register (CAR) RIER.AIER
INIR RIIR.AIF Alarm
Compare
(0xA5EB1357) Operation Interrupt
TTR.TTR[2:0]
Frequency
Compensation
Register (FCR) 21
RTC Access
Register Offset R/W Description Reset Value AER[16]=0
RTC_BA = 0x4000_8000
INIR RTC_BA+0x000 R/W RTC Initiation Register(A5EB1357) 0x0000_0000 R/W
AER RTC_BA+0x004 R/W RTC Access Enable Register(A965) 0x0000_0000 R/W
FCR RTC_BA+0x008 R/W RTC Frequency Compensation 0x0000_0700 -
Register
TLR RTC_BA+0x00C R/W Time Loading Register 0x0000_0000 R
CLR RTC_BA+0x010 R/W Calendar Loading Register 0x0005_0101 R
TSSR RTC_BA+0x014 R/W Time Scale Selection Register 0x0000_0001 R/W
DWR RTC_BA+0x018 R/W Day of the Week Register 0x0000_0006 R
TAR RTC_BA+0x01C R/W Time Alarm Register 0x0000_0000 -
CAR RTC_BA+0x020 R/W Calendar Alarm Register 0x0000_0000 -
LIR RTC_BA+0x024 R Leap year Indicator Register 0x0000_0000 R
RIER RTC_BA+0x028 R/W RTC Interrupt Enable Register 0x0000_0000 R/W
RIIR RTC_BA+0x02C R/C RTC Interrupt Indicator Register 0x0000_0000 R/C
TTR RTC_BA+0x030 R/W RTC Time Tick Register 0x0000_0000 -
24
RTC Sample Code with Driver(1/2)
/*----------------------------------------------------------------------------
MAIN function
----------------------------------------------------------------------------*/
volatile int32_t g_bAlarm = FALSE;
int32_t main (void)
{
S_DRVRTC_TIME_DATA_T sInitTime;
S_DRVRTC_TIME_DATA_T sCurTime;
/* RTC Initialize */
DrvRTC_Init();
/* Time Setting */
sInitTime.u32Year = 2009;
sInitTime.u32cMonth = 1;
sInitTime.u32cDay = 19;
sInitTime.u32cHour = 13;
sInitTime.u32cMinute = 20;
sInitTime.u32cSecond = 0;
sInitTime.u32cDayOfWeek = DRVRTC_MONDAY;
sInitTime.u8cClockDisplay = DRVRTC_CLOCK_24;
while(DrvRTC_Open(&sInitTime) !=E_SUCCESS);
26
RTC Sample Code(1/3)
/*----------------------------------------------------------------------------
MAIN function – 4 steps
----------------------------------------------------------------------------*/
int32_t main (void)
{
UNLOCKREG();
/* Step 1. Enable and Select RTC clock source */
//Enable 32Khz for RTC clock source
SYSCLK->PWRCON.XTL32K_EN = 1;
//Enable RTC clock source
SYSCLK->APBCLK.RTC_EN =1;
29
UART Feature
Up to three fully programmable UART channels.
Programmable baud-rate generator.
Programmable serial-interface.
Entry FIFO for Tx/Rx data payloads.
(UART0/UART1/UART264/16/16 bytes)
Support auto flow control function (/CTS, /RTS) in
UART0 and UART1.
Support IrDA SIR Function.
Support LIN break Function.
30
UART Clock Source
CLKSEL1.UART_S[25:24]
APBCLK.UART0_EN[16]
22.1184M
11 UART0_CLK
10
÷ (UART_N+1)
PLL_Fout
01 CLKDIV.UART_N[11:8]
12M UART1_CLK
00
APBCLK.UART1_EN[17]
UART2_CLK
APBCLK.UART2_EN[18]
User can easy generate standard baud-rate via 22.1184Mhz clock source
31
UART Block Diagram
APB BUS
8
8
8
Status & control Status & control
Control and
TX_FIFO(64/16)* RX_FIFO(64/16)*
Status registers
5 ~ 8bits 1 ~ 2bits
Baud-rate generator
Mode DIV_X_EN DIV_X_ONE Divider X BRD Baud rate equation
Mode 0 Disable 0 B A UART_CLK / [16 * (A+2)]
Mode 1 Enable 0 B A UART_CLK / [(B+1) * (A+2)] , B must >= 8
Mode 2 Enable 1 B A UART_CLK / (A+2), A must >=3
33
UART Timing Setting(2/2)
System source = 22.1184MHz
Baud rate Mode0 Mode1 Mode2
921600 x A=0,B=11 A=22
A=1,B=15
460800 A=1 A=2,B=11 A=46
A=4,B=15
230400 A=4 A=6,B=11 A=94
A=10,B=15
115200 A=10 A=14,B=11 A=190
A=22,B=15
57600 A=22 A=30,B=11 A=382
A=62,B=8
A=46,B=11
38400 A=34 A=34,B=15 A=574
A=126,B=8
A=94,B=11
19200 A=70 A=70,B=15 A=1150
A=254,B=8
A=190,B=11
9600 A=142 A=142,B=15 A=2302
A=510,B=8
A=382,B=11
4800 A=286 A=286,B=15 A=4606
34
UART Auto Flow Control Function
Support auto flow control function (/CTS, /RTS) in UART0 and
UART1.
Wake up from /CTS pin
NUC100 TX
Parallel to Serial RX
Tx FIFO
/CTS
Flow Control /RTS
Chip 2
BUS
RX
Serial to Parallel TX
Rx FIFO
/RTS
Flow Control /CTS
NUC100
SOUT TX pin Emit Infra red ray
TX IR_SOUT
IrDA IR
UART
SIR Transceiver
SIN RX pin Detect Infra red ray
RX IR_SIN
BAUDOUT
IrDA_enable
TX_select
IRCR INT_TX
INV_RX
36
IrDA Mode(2/2)
START BIT STOP BIT
SOUT
1 0 0 1 0 1 1 1 0 0 1
(from uart TX)
Tx
Timing
IR_SOUT
(encoder output)
Rx
Timing
3/16 bit width
SIN 1 0 1 0 0 1 0 1 0 0 1
(To uart RX)
START BIT
STOP BIT
37
LIN Mode
Support LIN break field and break length setting.
Support break field interrupt at LIN Rx mode
Frame slot
Frame
Inter-
Response frame
space space
Header Response
38
UART sample code
UART setting
Baudrate:115200
Date length: 8 bits
Parity : Disable
Stop: 1 bit
39
UART Sample Code With Driver(1/3)
/*----------------------------------------------------------------------------
MAIN function
----------------------------------------------------------------------------*/
int32_t main (void)
{
STR_UART_T param;
/* GPIO initial */
DrvGPIO_InitFunction(E_FUNC_UART0);
40
UART Sample Code With Driver(2/3)
/*Open UART0*/
param.u32BaudRate = 115200;
param.u8cDataBits = DRVUART_DATABITS_8;
param.u8cStopBits = DRVUART_STOPBITS_1;
param.u8cParity = DRVUART_PARITY_NONE;
param.u8cRxTriggerLevel = DRVUART_FIFO_1BYTES;
DrvUART_Open(UART_PORT0, ¶m);
do
{
Send(‘U’);
Send(‘A’);
Send(‘R’);
Send(‘T’);
}while(GetChar()!=0x1B);
}
41
UART Sample Code With Driver(3/3)
/*---------------------------------------------------------------------------------------------------------*/
/* Routine to write and get a char */
/*---------------------------------------------------------------------------------------------------------*/
void Send(int ch)
{
while(UART0->FSR.TX_FULL == 1);
UART0->DATA = ch;
if(ch == '\n')
{
while(UART0->FSR.TX_FULL == 1);
UART0->DATA = '\r';
}
}
char GetChar()
{
while (1)
{
if(UART0->FSR.RX_EMPTY == 0 )
{
return (UART0->DATA);
}
}
}
42
UART Sample Code(1/2)
/*----------------------------------------------------------------------------
MAIN function – 4 steps
----------------------------------------------------------------------------*/
int32_t main (void)
{
43
UART Sample Code(2/2)
/* Step 3. Select Operation mode */
//Reset Tx and Rx FIFO
UART0->FCR.TFR =1;
UART0->FCR.RFR =1;
//Set Rx Trigger Level -1byte FIFO
UART0->FCR.RTS_TRI_LEVEL = 0;
//Disable parity
UART0->LCR.PBE = 0;
//8 data bits
UART0->LCR.WLS = 3;
//Enable 1 Stop bit
UART0->LCR.NSB = 0;
NUC1xx BSP
NUC1xx_BSP Driver Reference Guide
NuvotonPlatform_Keil
Sample
NUC1xx-LB_002
Smpl_WDT_TIMER_RTC. uvproj
Smpl_WDT_TIMER_RTC
45
WDT_TIMER_RTC Condition
WDT setting
Clock source: 10KHz
Time out level: level 5
WDT time out interval for interrupt = 1.6 s
WDT time out interval for Reset = 1.7 s
TIMER setting
Clock source: 12MHz
Operation mode: Periodic mode
Time out period = (1/12000000)*(255+1)*(2765) = 58.99 ms
RTC setting
Clock source: 32KHz
Current time setting: Date09/1/19, time13:20:00
Alarm time setting: Date09/1/19, time13:20:20
46
WDT_TIMER_RTC Result
47
Practice
Calendar
System setting
Clock : M0 and IP
GPIO
Normal/Idle/Power down mode
Interrupt
Software Reset
48
Q&A
Thank You
49