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Introduction To LVDS, PECL
Introduction To LVDS, PECL
Introduction To LVDS, PECL
HFAN-1.0
Rev 1; 4/08
Functional Diagrams
OUT+
OUT-
50Ω 50Ω
V CC-2.0V
PECL Termination
Figure 1. PECL output structure
VCC
VCC
VCC-1.3V
1kΩ 1kΩ
IN+
IN+
IN-
IN-
VCC
50Ω 50Ω
OUT+
OUT- 50Ω 50Ω
IN+
IN-
16mA
Table II lists the CML output and input specifications for the MAX3831/MAX3832.
Application Note HFAN-1.0 (Rev.1, 4/08) Maxim Integrated
Page 3 of 14
Table II. CML Input and Output Specifications (Load = 50Ω to VCC)
PARAMETER CONDITION MIN TYP MAX Units
Differential Output Voltage 640 800 1000 mVp-p
Output Common Mode Voltage VCC-0.2 V
Single-Ended Input Voltage Range VIS VCC – 0.6V VCC + 0.2V V
Differential Input Voltage Swing 400 1200 mVp-p
Note: Different Maxim products have different CML input sensitivities (i.e., MAX3875, MAX3876).
and ( R1 // R 2 ) =50Ω.
R2
(VCC − 2V ) = VCC
R1 + R 2
Solving for R1 and R2 yields the following
VCC
50 ⋅VCC
R1 = and R 2 = 25 ⋅ VCC R1 R1
(VCC − 2V )
PECL PECL
DRIVER RECEIVER
R2 R2
V CC V CC
R1 R2 R2 R1 R2 R2
R1 R1
R3 R3 R3 R3
(b)
(a)
LVDS LVDS
DRIVER RECEIVER
+3.3V
+3.3V
R1
50Ω
A R3 B
LVPECL 182Ω 182Ω
290 Ω
R2
LVPECL CML
MAX3875 DRIVER RECEIVER
R 2 ⋅ Vcc
V A = VCC − 2.0V =
R 2 + R1 //( R3 + 50Ω) Figure 15. DC-coupling between LVPECL and
(1) [Open circuit Thevenin equivalent voltage] CML (MAX3875)
Zin = R1 // R 2 //( R3 + 50Ω) = 50Ω
(2) [Thevenin equivalent resistance]
50
Gain = ≥ 0.042
( R3 + 50)
(4)
(Note: Assuming the LVPECL output minimum
differential swing is 1200mV, and the MAX3875
has a input sensitivity of 50mV, the gain should be
greater than 50mV/1200mV = 0.042.)
2.7kΩ 2.7kΩ 82 Ω 82 Ω
130Ω 130Ω
4.3kΩ 4.3kΩ
(b)
(a)
CML LVPECL
DRIVER 100Ω RECEIVER
VCC
+3.3V
R1
R1 R3
LVPECL A
R2
R2 LVPECL LVDS
LVDS DRIVER RECEIVER
B
R2
R3 50Ω R1 R3
Virtual (AC)
+3.3V
Ground
R 2 + R3
V A = VCC − 2V = VCC ⋅ (1)
R1 + R 2 + R3
Figure 18. AC-coupling between LVPECL and
R AC = R1 //( R 2 + ( R3 // 50Ω) =50Ω (2) LVDS
R3
Gain = (4)
( R 2 + R3)
+3.3V
+3.3V
R3
B LVPECL
R1 R3
R2
R2
LVDS LVPECL
DRIVER 124Ω RECEIVER LVDS A
R2 R1 124/2
R1 R3 Ω
Virtual (AC)
Ground
+3.3V
(a) LVDS to LVPECL interface (b) Single-ended equivalent circuit
Figure 19. DC-coupling between LVDS and LVPECL
LVDS LVPECL
DRIVER 100Ω RECEIVER
+3.3V +3.3V
82 Ω 82 Ω
2.7kΩ 2.7kΩ
5kΩ
CML LVDS
DRIVER RECEIVER
5kΩ
LVDS CML
DRIVER RECEIVER