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ED&Cs LAB#10 M.usama Saghar 2019-CPE-27
ED&Cs LAB#10 M.usama Saghar 2019-CPE-27
ED&Cs LAB#10 M.usama Saghar 2019-CPE-27
Experiment # 10
______________________
Course Instructor / Lab Engineer
Objective: To Design a Small Signal Voltage Divider Biased Common Emitter BJT Amplifier
Apparatus:
DC power supply, Oscilloscope, Function Generator, Multimeter, Breadboard, NPN transistor, Resistor
Circuit
Diagram: +VCC
R1 RC
Cou
Cin
RL
r
R2
RE
AC v
Theory:
Voltage divider biased common emitter amplifier is the most commonly used configuration; it provides both voltage and
current gains with stability versus changes in temperature
As voltage of base is 0.7V higher than voltage of Emitter for an NPN transistor
Base voltage can be approximately considered as voltage across resistor R2 (a safe approximation). This can be used
to calculate value of resistor R1
Stage voltage gain is calculated by taking into account unloaded voltage gain i.e. C /( e + E )and the loading effect on both
input and output sides:
Similarly, Stage current gain is calculated by taking into account unloaded current gain i.e. and loading effect on both input
and output sides:
Procedure:
Design values of resistors using the following given data:
VCC=+ 15V, VCE=VCC/2, IC= 10mA, β=100, VE=0.1VCC, rs=50Ω, RL=1kΩ
Compare measured and calculated stage voltage gain and calculate percentage error
Observations:
Conclusion/ Comments:
In this experiment I learnt to draw the Small Signal Voltage Divider Biased Common Emitter BJT Amplifier on
proteus and finding values.