Exam1: Q1) What Is The Control Register in 80386DX in Protected Model?

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Computer Architecture

exam1
Q1) What is the control register in 80386DX in protected model?

The solution
The protected model includes the four system-control registers, identified as
through CR3,
that the lower 5 bits of CR0 are system-control
flags. These bits make up what is known as the machine status word (MSW). The
most significant bit of CR0 and register CR2 and CR3 are used by the 80386DX
paging mechanism.
The machine status word bits of CR0 they contain information about 80386DX
protected mode configuration and status. The 4 bits labeled PE, MP, EM, and R
are control bits that define the protected mode system configuration. The fifth bit,
TS, is a status bit. These bit can be examined or modified through software.
PE = Protected-mode Enable.
PE = 0 is real mode by software.
PE = 1 is protected mode by software.
MP = Math Present.
MP = 1 is indicate that a numeric coprocessor is present in the microprocessor
system. The EM is 1
MP = 0 is indicate that a numeric coprocessor is not present in the microprocessor
system. The EM is 0

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Computer Architecture

EM = Emulate Math.
EM = 1 is the software emulate to perform numeric operation. The MP is 1
EM = 0 is the software emulate not to perform numeric operation. The MP is 0
R = Extension Type.
R = 1 is complement 80387 to 80386.
R = 0 is complement 80287 to 80286.
TS = Task Switch, automatically gets set (1) whenever the 80386DX switches
from on task to another it can be clear by software. In the other hand,
TS = 0 in the same task.
TS = 1 transfer in the other task.
PG = Paging
PG = 0 is not paging the address is physical address in memory.
PG = 1 is paging the address is paging address in memory.
CR1 = Reserved.
CR2 = Page Fault Linear Address.
CR3 = Page Directory Base Register (PDBR).

Q2) What is the hardware organization of the physical address space in


protected mode?

The solution
Hardware Organization of The Physical Address Space in Protected Mode:
The 4GB in protected mode in physical address space is divided in four banks 0,
1, 2, 3,

FFFFFFFFH
FFFFFFFFH
Computer Architecture

FFFFFFFFH
4GB
00000002 H
00000001 H
00000000 H
In protected mode the 32-bit address bus the 80386DX results in a 4GB byte
physical memory address space. Each word is 32-bit or 4-byte.
• The address of bank must be start of zero.
• Miss aline: address can be start in 2H , 3H, 4H, 5H must be 4-byte this address
take two cycle 2H, 3H in cycle one and 4H, 5H in cycle two, the type of address is
miss aline.
• a line: address can be start in 4H , 5H, 6H, 7H must be 4-byte this address take
one cycle, the type of address is aline

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