A B C D E

Compal Confidential
Fan Control
Model Name : EAL30 page 4 Intel Dothan CPU Thermal Sensor Clock Generator
File Name : LA-2691 ADI ADM1032AR ICS954226
uFCPGA-478 CPU page 4,5
1
page 4 page 12 1

H_A#(3..31) FSB H_D#(0..63)

400 / 533 Mhz

LCD Conn.
page 20
Intel Alviso GM(PM) Memory BUS(DDR) 200pin DDR-SO-DIMM X2
ATI M24/M22 BANK 0, 1, 2, 3 page 10,11

CRT Conn. Ver A23 16X PCI-E PCBGA 1257 2.5V DDR200/266/333
page 21
with 32/64/128MB
page 6,7,8,9
On Board VRAM
TV-OUT Conn. page 13,14,15,16,17,18
page 21
Port 2,3
USB conn
DMI x2 page 35

2
page 19 2
Port 4
PCI BUS USB conn
3.3V 33 MHz
x1 page 35
IDSEL:AD18 IDSEL:AD17 IDSEL:AD20 USB 2.0
(PIRQ[G..H]#,
GNT#3/4,
(PIRQB#,
GNT#1,
(PIRQA#,B#,C#,D#,
GNT#2, REQ#2)
Intel ICH6-M 3.3V 48MHz
REQ#3/4) REQ#1) mBGA-609
3.3V 24.576MHz AC-LINK
Mini PCI LAN
3.3V ATA-100
socket RTL8100CL TI Controller PCI7411 page 22,23,24
page 30 page 26 IDE
page 23,24
CDROM AC97 Codec MDC Conn
Conn. page ALC250 Ver.D page 31
25 page 31
RJ45/RJ11 5in1 CardReader
13 94
page 26
Conn. Slot 0 Slot page 25
SATA SATA to PATA AMP EAL30 Sub Board
page 24 page 26 88SA8040
3
page 25
TPA0232
page 32 LED/SW Board 3
LPC BUS 3.3V 33MHz
Conn
Audio Board LS-2462 page 36
ENE KB910 SMsC LPC47N217 Conn
Super I/O HDD Conn. T/P Board
RTC CKT. ENE KB910L LS-2691
page 34,34 page 33 page 32 Conn
page 24
LS-2461 page 36

Power On/Off CKT. Touch Pad Int.KBD PARALLEL FIR

WL-KSW Board
page 36 page 33 page 33
page 37

LS-2692
DC/DC Interface CKT. 1MB BIOS
page 35

4
page 38 4

Power Circuit DC/DC

page 38,39,40,41 Security Classification Compal Secret Data Compal Electronics, Inc.
42,43,44,45 2005/03/01 2006/03/01 Title
Issued Date Deciphered Date
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom EAL30 LA-2691 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星 薔|, 三月 03, 2005 Sheet 1 of 52
A B C D E
 A B C D E

1 1

Compal Confidential
2

Fortworth Alviso 2

EAL30 LA-2691 Schematic

uFC-PGA Dothan / 915 PM/GM/910GML
3
ATI M24/M24C/M22 Ver A23 with 64M/128M VRAM / ICH6-M 3

2005-03-01
REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom EAL30 LA-2691 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 三月 04, 2005 Sheet 1 of 52
A B C D E
 A

Symbol note:
Voltage Rails
:means digital ground.
Power Plane Description S0-S1 S3 S5
:means analog ground.
VIN Adapter power supply (19V) N/A N/A N/A
@ :means reserved.
B+ AC or battery power rail for power circuit N/A N/A N/A
+CPU_CORE Core voltage for CPU ON OFF OFF
+1.05VS 1.05V rail for Processor I/O ON OFF OFF Fortworth Alviso Comparison Table
+1.25VS 1.25V switched power rail for DDR Vtt ON OFF OFF
+VGA_CORE 1.2V/1.0V switched power rail for VGA core power ON OFF OFF Item * Descrite UMA Page
+1.2VS 1.2V for VGA PCIE power ON OFF OFF
+1.5VALW 1.5V always on power rail ON ON ON* VGA ATi M22P/24P UMA 15 ~ 18
+1.5VS 1.5V switched power rail ON OFF OFF
VRAM 128MB/64MB N/A 19 ~ 20
+1.8VS 1.8V switched power rail for VGA frame buffer ON OFF OFF
+2.5V 2.5V power rail for system DDR ON ON OFF
+3VALW 3.3V always on power rail ON ON ON*
+3V 3.3V switched power rail ON ON OFF
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
+12VALW 12V always on power rail ON ON ON*
RTCVCC RTC power ON ON ON*

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID Table for AD channel
Vcc 3.3V +/- 5%
1 Ra 10K +/- 5% 1

ICH6-M I2C / SMBUS ADDRESSING BID/PID Rb/Rc V AD_BID min V AD_BID typ V AD_BID max
DEVICE HEX ADDRESS 0 0 0 V 0 V 0.1 V
1 8.2K +/- 5% 1.412 V 1.486 V 1.560 V
DDR SO-DIMM 0 A0 1010000X
2 18K +/- 5% 2.015 V 2.121 V 2.227 V
DDR SO-DIMM 1 A2 1010001X
3 33K +/- 5% 2.406 V 2.533 V 2.659 V
CLOCK GENERATOR (EXT.) D2 1101001X
4 56K +/- 5% 2.660 V 2.800 V 2.940 V
5 NC 3.135 V 3.300 V 3.465 V
KB910 I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS
SM1 24C16 A 0H 1010000Xb
Board ID PCB Revision
SM1 SMART BATTERY 16H 0001011Xb
SM2 ADM0132 98H 1001100Xb * 0 0.1
CPU THERMAL MONITOR 1
2
SM2 ALC250 codec 00H 0000000Xb
3
4
External PCI Devices 5
DEVICE PCI Device ID IDSEL # REQ/GNT # PIRQ 6
7
1394 D0 AD20 2 A,B,C,D
LAN D1 AD17 3 F
CARD BUS D4 AD20 2 A,B,C,D
5IN1 D4 AD20 2 A,B,C,D
Mini-PCI D2 AD18 1 G,H

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 3 of 52
A
 A B C D E

+1.05VS

ITP_TDI R426 2 1 150_0402_5%

ITP_TDO R423 2 1 @ 54.9_0402_1%

H_CPURST# R424 2 1 @ 54.9_0402_1%

H_D#[0..63]
H_D#[0..63] 6
ITP_TMS R427 2 1 40.2_0402_1%
U7A
PRO_CHOT# R23 2 1 56_0402_5%
H_A#[3..31] H_A#3 P4 A19 H_D#0
6 H_A#[3..31]
H_A#4
H_A#5
U4
A3#
A4#
Dothan D0#
D1# A25 H_D#1
H_D#2
H_PW RGOOD R422 2 1 200_0402_5%
V3 A5# D2# A22
4 H_A#6 H_D#3 H_IERR# R418 56_0402_5% 4
R3 A6# D3# B21 2 1
H_A#7 V2 A24 H_D#4
H_A#8 A7# D4# H_D#5 +3VS
W1 A8# D5# B26
H_A#9 T4 A21 H_D#6
H_A#10 A9# D6# H_D#7
W2 A10# D7# B20
H_A#11 Y4 C20 H_D#8 ITP_DBRRESET# R415 2 1 @ 150_0402_5%
H_A#12 A11# D8# H_D#9
Y1 A12# D9# B24
H_A#13 U1 D24 H_D#10 ITP_TRST# R22 2 1 680_0402_5%
H_A#14 A13# D10# H_D#11
AA3 A14# D11# E24
H_A#15 Y3 C26 H_D#12 ITP_TCK R21 2 1 27.4_0402_1%
H_A#16 A15# D12# H_D#13
AA2 A16# D13# B23
H_A#17 AF4 E23 H_D#14 TEST1 R421 2 1 @ 1K_0402_5%
H_A#18 A17# D14# H_D#15
AC4 A18# D15# C25
H_A#19 AC7 H23 H_D#16 TEST2 R414 2 1 @ 1K_0402_5%
H_A#20 A19# D16# H_D#17
AC3 A20# D17# G25
H_A#21 AD3 L23 H_D#18
H_A#22 A21# D18# H_D#19
AE4 A22# D19# M26
H_A#23 AD2 H24 H_D#20
H_A#24 A23# D20# H_D#21
AB4 A24# D21# F25
H_A#25 AC6 ADDR GROUP DATA GROUP G24 H_D#22
H_A#26 A25# D22# H_D#23
AD5 J23
H_A#27 AE2
A26#
A27#
D23#
D24# M23 H_D#24 Reserve For Testability
H_A#28 AD6 J25 H_D#25
H_A#29 A28# D25# H_D#26
AF3 A29# D26# L26
H_A#30 AE1 N24 H_D#27 H_FERR# C44 1 2@ 100P_0402_50V8J
H_A#31 A30# D27# H_D#28
AF1 A31# D28# M25
H26 H_D#29 H_CPUSLP# C32 1 2@ 100P_0402_50V8J
H_REQ#[0..4] H_REQ#0 D29# H_D#30
6 H_REQ#[0..4] R2 REQ0# D30# N25
H_REQ#1 P3 K25 H_D#31 H_DPSLP# C46 1 2@ 100P_0402_50V8J
H_REQ#2 REQ1# D31# H_D#32
T2 REQ2# D32# Y26
H_REQ#3 P1 AA24 H_D#33 H_STPCLK# C41 1 2@ 100P_0402_50V8J
H_REQ#4 REQ3# D33# H_D#34
T1 REQ4# D34# T25
3 H_D#35 H_INIT# C34 3
D35# U23 1 2@ 100P_0402_50V8J
U3 V23 H_D#36
6 H_ADSTB#0 ADSTB0# D36#
AE5 R24 H_D#37 H_SMI# C33 1 2@ 100P_0402_50V8J
6 H_ADSTB#1 ADSTB1# D37#
R26 H_D#38
D38# H_D#39 H_IGNNE# C29
D39# R23 1 2@ 100P_0402_50V8J
A16 AA23 H_D#40
ITP_CLK0 D40# H_D#41 H_NMI C49
A15 ITP_CLK1 D41# U26 1 2@ 100P_0402_50V8J
V24 H_D#42
D42# H_D#43
14 CLK_CPU_BCLK B15 BCLK0 D43# U25
B14 HOST CLK V26 H_D#44
14 CLK_CPU_BCLK# BCLK1 D44#
Y23 H_D#45
D45# H_D#46
AA26

N2
D46#
D47# Y25
AB25
H_D#47
H_D#48
Thermal Sensor ADI ADM1032AR
6 H_ADS# ADS# D48#
L1 AC23 H_D#49 +3VS
6 H_BNR# BNR# D49#
J3 AB24 H_D#50
6 H_BPRI# BPRI# D50# H_D#51
6 H_BR0# N4 BR0# D51# AC20
L4 AC22 H_D#52
6 H_DEFER# DEFER# D52# H_D#53 W =15mil U31
6 H_DRDY# H2 DRDY# D53# AC25
K3 AD23 H_D#54 2 1 8
6 H_HIT# HIT# D54# VDD SCLK EC_SMC_2 36,39

1
K4 CONTROL GROUP AE22 H_D#55 C457 R18 @ 1
6 H_HITM# HITM# D55#
H_IERR# A4 AF23 H_D#56 THERMDA 2 7
IERR# D56# D+ SDATA EC_SMD_2 36,39

10K_0402_5%
0.1U_0402_16V4Z
J2 AD24 H_D#57
6 H_LOCK# LOCK# D57# 1
H_CPURST# B11 AF20 H_D#58 C20 THERMDC 3 6
6 H_CPURST# RESET# D58# H_D#59 2 D- ALERT#
AE21

2
D59# H_D#60 2200P_0402_25V7K
D60# AD21 4 THERM# GND 5
H_RS#[0..2] H_RS#0 H1 AF25 H_D#61
6 H_RS#[0..2] RS0# D61#
H_RS#1 K1 AF22 H_D#62
H_RS#2 RS1# D62# H_D#63 ADM1032AR_SOP8
L2 RS2# D63# AF26
6 H_TRDY# M3 TRDY#
Address:1001_100X

DINV0# D25 H_DINV#0 6

2 2
DINV1# J26 H_DINV#1 6
C8 T24
B8
A9
BPM0#
BPM1#
DINV2#
DINV3# AD20
H_DINV#2
H_DINV#3
6
6 Fan Control circuit
BPM2# +5VS
C9 BPM3#
DSTBN0# C23 H_DSTBN#0 6
ITP_DBRRESET# A7 K24
DBR# DSTBN1# H_DSTBN#1 6
6 H_DBSY# M2 DBSY# DSTBN2# W25 H_DSTBN#2 6
24 H_DPSLP# B7 DPSLP# DSTBN3# AE24 H_DSTBN#3 6 1

1
G1 C22 PU5B C43
24 H_DPRSTP# DPRSTP# DSTBP0# H_DSTBP#0 6

1
C19 L24 5 LM358A_SO8 C D7
6 H_DPWR# DPWR# DSTBP1# H_DSTBP#1 6 39 EN_DFAN1 +
A10 PRDY# MISC DSTBP2# W24 H_DSTBP#2 6 0 7 FAN1_ON 1 2 2 Q3 10U_0805_10V4Z
R47 100_0402_5% B 2
FMMT619_SOT23 1SS355_SOD323
B10 PREQ# DSTBP3# AE25 H_DSTBP#3 6 1 2 6 -
PRO_CHOT# B17 R45 P@ 1 E

2
PROCHOT# 10K_0402_5%
H_PW RGOOD E4 C64
24 H_PWRGOOD PWRGOOD

1
H_CPUSLP# A6 0.1U_0402_16V4Z
6,24 H_CPUSLP# SLP# 2
ITP_TCK A13 D8
ITP_TDI TCK
C12 TDI A20M# C2 H_A20M# 24 1 2 1N4148_SOD80
ITP_TDO A12 D3 R46 8.2K_0402_5%
TDO FERR# H_FERR# 24
TEST1 C5 A3 JP7
H_IGNNE# 24

2
TEST2 TEST1 IGNNE# FAN1_VOUT
F23 TEST2 INIT# B5 H_INIT# 24 1
ITP_TMS C11 D1
TMS LINT0 H_INTR 24 2
ITP_TRST# B13 D4
TRST# LINT1 H_NMI 24 3
LEGACY CPU +3VS 1 2
THERMAL R362 10K_0402_5% ACES_85205-0300
THERMDA B18 C6
THERMDC THERMDA DIODE STPCLK# H_STPCLK# 24
A18 THERMDC SMI# B4 H_SMI# 24 39 FANSPEED1 1
C17 1 @
6,24 H_THERMTRIP# THERMTRIP# @ C448
C444 1000P_0402_50V7K
TYCO_1612365-1_Dothan 1000P_0402_50V7K 2
1 2 1

Close to Fan Conn.

THERMDA & THERMDC Trace / Space = 10 / 10 mil

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INTEL Dothan(1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 4 of 52
A B C D E
 A B C D E

+CPU_CORE

+CPU_CORE
U7B U7C
330U_D_2VM
R83 1 2 @ 54.9_0402_1% VCCSENSE AE7 A2 1 1 1 F20 T26
R82 @ 54.9_0402_1% VSSSENSE VCCSENSE VSS VCC VSS
1 2 AF6 VSSSENSE VSS A5 F22 VCC VSS U2
A8 + C475 + C474 + C473 G5 U6
VSS @ VCC VSS
VSS A11 G21 VCC VSS U22
F26 VCCA0 VSS A14 H6 VCC VSS U24
+VCCA 2 2 2
B1 VCCA1 VSS A17 H22 VCC VSS V1
N1 A20 330U_D_2VM 330U_D_2VM J5 V4
VCCA2 VSS VCC VSS
1 AC26 VCCA3 VSS A23 J21 VCC VSS V5 1
VSS A26 K22 VCC VSS V21
1.8V FOR DOTHAN-A +1.05VS P23 VCCQ0 VSS B3
+CPU_CORE
U5 VCC VSS V25
W4 VCCQ1 VSS B6 V6 VCC VSS W3
+1.8VS 1 2 VSS B9 V22 VCC VSS W6
R301 @ 0_1206_5% B12 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M W5 W22
D10 VCCP
Dothan VSS
VSS B16 1 1
C36
1
C38
1 1
C40
1 1 W21
VCC
VCC
VSS
VSS W23
D12 B19 Y6 W26
D14
VCCP
VCCP
VSS
VSS B22
C35 C37 C39 C47
Y22
VCC
VCC
Dothan VSS
VSS Y2
1.5V FOR DOTHAN-B D16 VCCP VSS B25
2 2 2 2 2 2 2
AA5 VCC VSS Y5
E11 VCCP VSS C1 AA7 VCC VSS Y21
1 2 E13 C4 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AA9 Y24

POWER, GROUNG, RESERVED SIGNALS AND NC

+1.5VS R302 0_1206_5% VCCP VSS VCC VSS
E15 VCCP VSS C7 AA11 VCC VSS AA1
F10 VCCP VSS C10 AA13 VCC VSS AA4
F12 C13 +CPU_CORE AA15 AA6
VCCP VSS VCC VSS
F14 VCCP VSS C15 AA17 VCC VSS AA8
1 1 F16 C18 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AA19 AA10
VCCP VSS VCC VSS
K6 VCCP VSS C21 1 1 1 1 1 1 1 AA21 VCC VSS AA12
L5 C24 C65 C53 C71 AB6 AA14
C30 C24 VCCP VSS VCC VSS
L21 VCCP VSS D2 AB8 VCC VSS AA16
2 2 C52 C48 C66 C72
M6 VCCP VSS D5 AB10 VCC VSS AA18
0.01U_0402_16V7K 10U_0805_6.3V6M 2 2 2 2 2 2 2
M22 VCCP VSS D7 AB12 VCC VSS AA20
N5 D9 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AB14 AA22
VCCP VSS VCC VSS
N21 VCCP VSS D11 AB16 VCC POWER, GROUND VSS AA25
P6 VCCP VSS D13 AB18 VCC VSS AB3
P22 D15 +CPU_CORE AB20 AB5
VCCP VSS VCC VSS
R5 VCCP VSS D17 AB22 VCC VSS AB7
R21 D19 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AC9 AB9
VCCP VSS VCC VSS
T6 VCCP VSS D21 1 1 1 1 1 1 1 AC11 VCC VSS AB11
T22 D23 C74 C76 C543 AC13 AB13
VCCP VSS VCC VSS
U21 VCCP VSS D26 AC15 VCC VSS AB15
E3 C73 C75 C544 C542 AC17 AB17
2 VSS 2 2 2 2 2 2 2 VCC VSS 2
VSS E6 AC19 VCC VSS AB19
D6 E8 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AD8 AB21
+CPU_CORE VCC VSS VCC VSS
D8 VCC VSS E10 AD10 VCC VSS AB23
D18 VCC VSS E12 AD12 VCC VSS AB26
D20 E14 +CPU_CORE AD14 AC2
VCC VSS VCC VSS
D22 VCC VSS E16 AD16 VCC VSS AC5
E5 E18 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AD18 AC8
VCC VSS VCC VSS
E7 VCC VSS E20 1 1 1 1 1 1 1 AE9 VCC VSS AC10
E9 E22 C540 C564 C586 AE11 AC12
VCC VSS VCC VSS
E17 VCC VSS E25 AE13 VCC VSS AC14
E19 F1 C541 C539 C570 C563 AE15 AC16
VCC VSS 2 2 2 2 2 2 2 VCC VSS
E21 VCC VSS F4 AE17 VCC VSS AC18
F6 F5 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AE19 AC21
VCC VSS VCC VSS
F8 VCC VSS F7 AF8 VCC VSS AC24
F18 VCC VSS F9 AF10 VCC VSS AD1
F11 +CPU_CORE AF12 AD4
VSS VCC VSS
VSS F13 AF14 VCC VSS AD7
50 PSI# E1 F15 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AF16 AD9
PSI# VSS VCC VSS
VSS F17 1 1 1 1 1 1 1 AF18 VCC VSS AD11
+1.05VS 50 CPU_VID0 E2 F19 C585 C611 C609 AD13
VID0 VSS VSS
50 CPU_VID1 F2 VID1 VSS F21 VSS AD15
50 CPU_VID2 F3 F24 C569 C612 C610 C608 AD17
VID2 VSS VSS
1

2 2 2 2 2 2 2
50 CPU_VID3 G3 VID3 VSS G2 VSS AD19
R62 50 CPU_VID4 G4 G6 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AD22
1K_0402_1% VID4 VSS VSS
50 CPU_VID5 H4 VID5 VSS G22 M4 VSS VSS AD25
VSS G23 M5 VSS VSS AE3
G26 M21 AE6
2

GTL_REF0 VSS VSS VSS

1 2 AD26 GTLREF VSS H3 M24 VSS VSS AE8
R59 2K_0402_1% H5 Vcc-core C,uF ESR, mohm ESL,nH N3 AE10
VSS VSS VSS
VSS H21 Decoupling N6 VSS VSS AE12
14 CPU_BSEL0 C16 BSEL0 VSS H25 N22 VSS VSS AE14
3
14 CPU_BSEL1 C14 BSEL1 VSS J1 SPCAP,Polymer 3X330uF 9m ohm/3 3.5nH/4 N23 VSS VSS AE16 3

VSS J4 N26 VSS VSS AE18

COMP0 P25 J6 MLCC 0805 X5R 35X10uF 5m ohm/35 0.6nH/35 P2 AE20
COMP1 COMP0 VSS VSS VSS
P26 COMP1 VSS J22 P5 VSS VSS AE23
COMP2 AB2 J24 P21 AE26
COMP3 COMP2 VSS VSS VSS
AB1 COMP3 VSS K2 P24 VSS VSS AF2
VSS K5 R1 VSS VSS AF5
VSS K21 R4 VSS VSS AF9
VSS K23 R6 VSS VSS AF11
B2 RSVD VSS K26 R22 VSS VSS AF13
C3 RSVD VSS L3 R25 VSS VSS AF15
E26 L6 +1.05VS T3 AF17
RSVD VSS VSS VSS
AF7 RSVD VSS L22 T5 VSS VSS AF19
AC1 L25 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T21 AF21
RSVD VSS VSS VSS
VSS M1 1 T23 VSS VSS AF24
1 1 1 1 1 1 1 1 1 1
+
TYCO_1612365-1_Dothan C104 C520 C519 C518 C517 C554 C575 C591 C560 C584 C602 TYCO_1612365-1_Dothan
2 2 2 2 2 2 2 2 2 2 2

150U_D2_6.3VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

R44 1 2 27.4_0402_1% COMP0

R42 1 2 54.9_0402_1% COMP1

R81 1 2 27.4_0402_1% COMP2

R80 1 2 54.9_0402_1% COMP3

4 4

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils
COMP1, COMP3 layout : Space 25mils Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/03/01 Deciphered Date 2005/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INTEL Dothan(2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 5 of 52
A B C D E
 5 4 3 2 1

H_RS#[0..2] +1.5VS
H_RS#[0..2] 4
H_A#[3..31]
4 H_A#[3..31] CLK_DREF_SSC R158 1 2 PM@ 0_0402_5%
H_REQ#[0..4] H_D#[0..63]
4 H_REQ#[0..4] H_D#[0..63] 4
CLK_DREF_SSC# R157 1 2 PM@ 0_0402_5%
U44A
U44B
H_A#3 G9 E4 H_D#0
D
H_A#4 C9
HA3#
HA4#
Alviso HD0#
HD1# E1 H_D#1
25 DMI_ITX_MRX_N0
DMI_ITX_MRX_N0 AA31 DMIRXN0 CFG0 G16 CFG0
D

H_A#5 E9 F4 H_D#2 DMI_ITX_MRX_N1 AB35 H13 MCH_CLKSEL1

HA5# HD2# 25 DMI_ITX_MRX_N1 DMIRXN1 CFG1 MCH_CLKSEL1 14
H_A#6 B7 H7 H_D#3 DMI_ITX_MRX_N2 AC31 G14 MCH_CLKSEL0
HA6# HD3# 25 DMI_ITX_MRX_N2 DMIRXN2 CFG2 MCH_CLKSEL0 14
H_A#7 A10 E2 H_D#4 DMI_ITX_MRX_N3 AD35 F16
HA7# HD4# 25 DMI_ITX_MRX_N3 DMIRXN3 CFG3
H_A#8 F9 F1 H_D#5 F15
H_A#9 HA8# HD5# H_D#6 DMI_ITX_MRX_P0 CFG4 CFG5
D8 HA9# HD6# E3 25 DMI_ITX_MRX_P0 Y31 DMIRXP0 CFG5 G15
H_A#10 B10 D3 H_D#7 DMI_ITX_MRX_P1 AA35 E16 CFG6 +1.05VS
HA10# HD7# 25 DMI_ITX_MRX_P1 DMIRXP1 CFG6
H_A#11 E10 K7 H_D#8 DMI_ITX_MRX_P2 AB31 D17 CFG7
HA11# HD8# 25 DMI_ITX_MRX_P2 DMIRXP2 CFG7
H_A#12 G10 F2 H_D#9 DMI_ITX_MRX_P3 AC35 J16
HA12# HD9# 25 DMI_ITX_MRX_P3 DMIRXP3 CFG8
H_A#13 D9 J7 H_D#10 D15 CFG9 CFG0 R121 1 2 10K_0402_5%
H_A#14 HA13# HD10# H_D#11 DMI_MTX_IRX_N0 CFG9
E11 HA14# HD11# J8 25 DMI_MTX_IRX_N0 AA33 DMITXN0 CFG10 E15
H_A#15 F10 H6 H_D#12 DMI_MTX_IRX_N1 AB37 D14
25 DMI_MTX_IRX_N1

DMI
H_A#16 HA15# HD12# H_D#13 DMI_MTX_IRX_N2 DMITXN1 CFG11 CFG12 CFG5 R115 1
G11 HA16# HD13# F3 25 DMI_MTX_IRX_N2 AC33 DMITXN2 CFG12 E14 2 @ 1K_0402_5%
H_A#17 G13 K8 H_D#14 DMI_MTX_IRX_N3 AD37 H12 CFG13
HA17# HD14# 25 DMI_MTX_IRX_N3 DMITXN3 CFG13
H_A#18 C10 H5 H_D#15 C14
H_A#19 HA18# HD15# H_D#16 DMI_MTX_IRX_P0 CFG14

CFG/RSVD
C11 HA19# HD16# H1 25 DMI_MTX_IRX_P0 Y33 DMITXP0 CFG15 H15
H_A#20 D11 H2 H_D#17 DMI_MTX_IRX_P1 AA37 J15 CFG16 CFG6 R117 1 2 @ 1K_0402_5%
HA20# HD17# 25 DMI_MTX_IRX_P1 DMITXP1 CFG16
H_A#21 C12 K5 H_D#18 DMI_MTX_IRX_P2 AB33 H14
HA21# HD18# 25 DMI_MTX_IRX_P2 DMITXP2 CFG17
H_A#22 B13 K6 H_D#19 DMI_MTX_IRX_P3 AC37 G22 CFG18 CFG7 R122 1 2 @ 1K_0402_5%
HA22# HD19# 25 DMI_MTX_IRX_P3 DMITXP3 CFG18
H_A#23 A12 J4 H_D#20 G23 CFG19
H_A#24 HA23# HD20# H_D#21 CFG19 CFG9 R113 1
F12 HA24# HD21# G3 CFG20 D23 2 @ 1K_0402_5%
H_A#25 G12 H3 H_D#22 AM33 G25
HA25# HD22# 11 DDRA_CLK1 SM_CK0 RSVD21
H_A#26 E12 J1 H_D#23 AL1 G24 CFG12 R114 1 2 @ 1K_0402_5%
HA26# HD23# 11 DDRA_CLK2 SM_CK1 RSVD22
H_A#27 C13 L5 H_D#24 AE11 J17
H_A#28 HA27# HD24# H_D#25 SM_CK2 RSVD23 CFG13 R107 1
B11 HA28# HD25# K4 12 DDRB_CLK1 AJ34 SM_CK3 RSVD24 A31 2 @ 1K_0402_5%
H_A#29 D13 J5 H_D#26 AF6 A30
HA29# HD26# 12 DDRB_CLK2 SM_CK4 RSVD25
H_A#30 A13 P7 H_D#27 AC10 D26 CFG16 R116 1 2 @ 1K_0402_5%
H_A#31 HA30# HD27# H_D#28 SM_CK5 RSVD26
F13 HA31# HD28# L7 RSVD27 D25
J3 H_D#29 AN33 CFG[17:3]: internal pull-up
HD29# 11 DDRA_CLK1# SM_CK0#

DDR MUXING
A11 P5 H_D#30 AK1
HOST

HPCREQ# HD30# 11 DDRA_CLK2# SM_CK1# +2.5VS

H_REQ#0 A7 L3 H_D#31 AE10
C H_REQ#1 HREQ#0 HD31# H_D#32 SM_CK2# C
D7 HREQ#1 HD32# U7 12 DDRB_CLK1# AJ33 SM_CK3#
H_REQ#2 B8 V6 H_D#33 AF5
HREQ#2 HD33# 12 DDRB_CLK2# SM_CK4#
H_REQ#3 C7 R6 H_D#34 AD10 CFG18 R140 1 2 @ 1K_0402_5%
H_REQ#4 HREQ#3 HD34# H_D#35 SM_CK5#
A8 HREQ#4 HD35# R5
B9 P3 H_D#36 DDRA_CKE0 AP21 CFG19 R137 1 2 @ 1K_0402_5%
4 H_ADSTB#0 HADSTB#0 HD36# 11 DDRA_CKE0 SM_CKE0
E13 T8 H_D#37 DDRA_CKE1 AM21
4 H_ADSTB#1 HADSTB#1 HD37# 11 DDRA_CKE1 SM_CKE1
R7 H_D#38 DDRB_CKE0 AH21 CFG[19:18]: internal pull-down
HD38# 12 DDRB_CKE0 SM_CKE2
AB1 R8 H_D#39 DDRB_CKE1 AK21
14 CLK_MCH_BCLK# HCLKN HD39# 12 DDRB_CKE1 SM_CKE3
AB2 U8 H_D#40 J23
14 CLK_MCH_BCLK HCLKP HD40# BM_BUSY# PM_BMBUSY# 25
R4 H_D#41 DDRA_SCS#0 AN16 J21 EXT_TS#0
HD41# 11 DDRA_SCS#0 SM_CS0# EXT_TS0#
G4 T4 H_D#42 DDRA_SCS#1 AM14 H22 EXT_TS#1
4 H_DSTBN#0 HDSTBN#0 HD42# 11 DDRA_SCS#1 SM_CS1# EXT_TS1#
K1 T5 H_D#43 DDRB_SCS#0 AH15 F5 H_THERMTRIP#
4 H_DSTBN#1 HDSTBN#1 HD43# 12 DDRB_SCS#0 SM_CS2# THRMTRIP# H_THERMTRIP# 4,24
R3 R1 H_D#44 DDRB_SCS#1 AG16 AD30
4 H_DSTBN#2 HDSTBN#2 HD44# 12 DDRB_SCS#1 SM_CS3# PWROK VGATE 14,25,50
V3 T3 H_D#45 AE29

CLK PM
4 H_DSTBN#3 HDSTBN#3 HD45# RSTIN# PLT_RST# 15,23,25,27,28,31,35,39
G5 V8 H_D#46 R135 1 2 @ 40.2_0402_1% M_OCDCOMP0 AF22
4 H_DSTBP#0 HDSTBP#0 HD46# H_D#47 R120 1 M_OCDCOMP1 SM_OCDCOMP0
4 H_DSTBP#1 K2 HDSTBP#1 HD47# U6 2 @ 40.2_0402_1% AF16 SM_OCDCOMP1
R2 W6 H_D#48 AP14 A24 CLK_DREF_96M#
4 H_DSTBP#2 HDSTBP#2 HD48# SM_ODT0 DREF_CLKN CLK_DREF_96M# 14
W4 U3 H_D#49 AL15 A23 CLK_DREF_96M
4 H_DSTBP#3 HDSTBP#3 HD49# SM_ODT1 DREF_CLKP CLK_DREF_96M 14
H8 V5 H_D#50 Intel new update AM11 D37 CLK_DREF_SSC
4 H_DINV#0 HDINV#0 HD50# SM_ODT2 DREF_SSCLKP CLK_DREF_SSC 14
K3 W8 H_D#51 AN10 C37 CLK_DREF_SSC#
4 H_DINV#1 HDINV#1 HD51# SM_ODT3 DREF_SSCLKN CLK_DREF_SSC# 14
T7 W7 H_D#52
4 H_DINV#2 HDINV#2 HD52# H_D#53 R106 1 M_RCOMPN
4 H_DINV#3 U5 HDINV#3 HD53# U2 +2.5V 2 80.6_0402_1% AK10 SMRCOMPN
U1 H_D#54 R105 1 2 80.6_0402_1% M_RCOMPP AK11 AP37 +2.5VS
HD54# H_D#55 SMVREF SMRCOMPP NC1
HD55# Y5 AF37 SMVREF0 NC2 AN37
H10 Y2 H_D#56 AD1 AP36 EXT_TS#0 R134 1 2 10K_0402_5%
4 H_CPURST# HCPURST# HD56# SMVREF1 NC3
V4 H_D#57 M_XSLEW AE27 AP2
HD57# H_D#58 SMXSLEWIN NC4 EXT_TS#1 R139 1
4 H_ADS# F8 HADS# HD58# Y7 AE28 SMXSLEWOUT NC5 AP1 2 10K_0402_5%
B5 W1 H_D#59 M_YSELW AF9 AN1
4 H_TRDY# HTRDY# HD59# H_D#60 SMYSLEWIN NC6
4 H_DPWR# G6 HDPWR# HD60# W3 AF10 SMYSLEWOUT NC7 B1
F7 Y3 H_D#61 A2
4 H_DRDY# HDRDY# HD61# H_D#62 NC8
4 H_DEFER# E6 HDEFER# HD62# Y6 NC9 B37 Refer to sheet 6 for FSB
H_D#63

NC
B B
F6 HEDRDY# HD63# W2
+1.05VS NC10 A36 CFG[2:0] frequency select
4 H_HITM# D6 HHITM# NC11 A37
D4 J11 H_VREF Low = DMI x 2
4 H_HIT# HHIT# HVREF H_XRCOMP R4732 24.9_0402_1%
B3 C1 1 (10mil:20mil) CFG5 High = DMI x 4
4
4
H_LOCK#
H_BR0# E7
HLOCK#
HBREQ0#
HXRCOMP
HXSCOMP C2 H_XSCOMP
H_YRCOMP
R4741
R4802
2 54.9_0402_1%
24.9_0402_1%
915PM@ ALVISO_BGA1257 *
4 H_BNR# A5 HBNR# HYRCOMP T1 1 Low = DDR-II
D5 L1 H_YSCOMP R4841 2 54.9_0402_1% CFG6 High = DDR-I
4
4
H_BPRI#
H_DBSY# C6
HBPRI#
HDBSY#
HYSCOMP
HXSWING D1 H_XSWING
H_YSWING +2.5V
*
4,24 H_CPUSLP# G8 HCPUSLP# HYSWING P1 Low = DT/Transportable CPU
H_RS#0 A4 CFG7 High = Mobile CPU
H_RS#1 C5
HRS0#
HRS1#
*

1
H_RS#2 B4 H_XRCOMP & H_YRCOMP Trace / Space = 10 / 20 mil CFG9 Low = Reverse Lane
HRS2# R466 High = Normal Operation
915PM@ ALVISO_BGA1257 1K_0402_1%
*
00 = Reserved
82915PM-C0 CFG[13:12] 01 = XOR Mode Enabled
2
0.1U_0402_16V4Z SMVREF 10 = All Z Mode Enabled
(R3:SA009150180) 11 = Normal Operation (Default)
(R1:SA009150160) R475
1

C236
1 1 *
CFG16
C691 Low = Disabled
+1.05VS +1.05VS +1.05VS 1K_0402_1% 0.1U_0402_16V4Z (FSB Dynamic High = Enabled
2 2
ODT) *
2
1

R108 R470 R467

CFG18
Low = 1.05V (Default)
100_0603_1% 221_0603_1% 221_0603_1% (VCC Select) High = 1.5V *
(5mil:15mil) (12mil:10mil) CFG19
2

Low = 1.05V (Default)

H_VREF H_XSWING H_YSWING (12mil:10mil) (VTT Select) High = 1.2V *
A A
1

1 1 1
C148 R111 C686 R462 C694
R483
0.1U_0402_16V4Z 200_0603_1% 0.1U_0402_16V4Z 100_0603_1% 0.1U_0402_16V4Z 100_0603_1%
2 2 2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INTEL Alviso HOST(1/5)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 6 of 52
5 4 3 2 1
 5 4 3 2 1

PCIE_MTX_C_GRX_N[0..15]
15 PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
15 PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
15 PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
15 PCIE_GTX_C_MRX_P[0..15]

U44G
+2.5VS R142 1 2 @ 3K_0402_1% H24 D36 PEG_COMP 1 2 +1.5VS
R143 1 SDVOCTRL_DATA EXP_COMPI
2 @ 3K_0402_1% H25 SDVOCTRL_CLK EXP_ICOMPO D34 R156 24.9_0402_1%
AB29

MISC
D 14 CLK_MCH_3GPLL# GCLKN D
AC29 E30 PCIE_GTX_C_MRX_N0
14 CLK_MCH_3GPLL GCLKP EXP_RXN0/SDVO_TVCLKIN#
F34 PCIE_GTX_C_MRX_N1
EXP_RXN1/SDVO_INT# PCIE_GTX_C_MRX_N2
EXP_RXN2/SDVO_FLDSTALL# G30
GMCH_TV_COMPS A15 H34 PCIE_GTX_C_MRX_N3
GMCH_TV_LUMA TVDAC_A EXP_RXN3 PCIE_GTX_C_MRX_N4
22 GMCH_TV_LUMA C16 TVDAC_B EXP_RXN4 J30
GMCH_TV_CRMA A17 K34 PCIE_GTX_C_MRX_N5
22 GMCH_TV_CRMA TVDAC_C EXP_RXN5
2 1 TV_REFSET J18 L30 PCIE_GTX_C_MRX_N6
R125 4.99K_0402_1% TV_REFSET EXP_RXN6 PCIE_GTX_C_MRX_N7
2 1 B15 TV_IRTNA EXP_RXN7 M34
R527 0_0402_5% B16 N30 PCIE_GTX_C_MRX_N8
TV_IRTNB EXP_RXN8 PCIE_GTX_C_MRX_N9
B17 P34

TV
TV_IRTNC EXP_RXN9 PCIE_GTX_C_MRX_N10
EXP_RXN10 R30
T34 PCIE_GTX_C_MRX_N11
EXP_RXN11 PCIE_GTX_C_MRX_N12
EXP_RXN12 U30
V34 PCIE_GTX_C_MRX_N13
EXP_RXN13 PCIE_GTX_C_MRX_N14
EXP_RXN14 W30
GMCH_CRT_CLK E24 Y34 PCIE_GTX_C_MRX_N15
22 GMCH_CRT_CLK DDCCLK EXP_RXN15
GMCH_CRT_DATA E23
22 GMCH_CRT_DATA DDCDATA
E21 D30 PCIE_GTX_C_MRX_P0
22 GMCH_CRT_B BLUE EXP_RXP0/SDVO_TVCLKIN
2 1 D21 E34 PCIE_GTX_C_MRX_P1
R124 150_0402_1% BLUE# EXP_RXP1/SDVO_INT PCIE_GTX_C_MRX_P2
22 GMCH_CRT_G C20 GREEN EXP_RXP2/SDVO_FLDSTALL F30
2 1 B20 G34 PCIE_GTX_C_MRX_P3
R127 150_0402_1% GREEN# EXP_RXP3 PCIE_GTX_C_MRX_P4
22 GMCH_CRT_R A19 RED EXP_RXP4 H30
2 1 B19 J34 PCIE_GTX_C_MRX_P5
R119 150_0402_1% RED# EXP_RXP5 PCIE_GTX_C_MRX_P6
H21 K30

VGA
22 GMCH_CRT_VSYNC VSYNC EXP_RXP6
G21 L34 PCIE_GTX_C_MRX_P7
22 GMCH_CRT_HSYNC HSYNC EXP_RXP7

PCI - EXPRESS GRAPHICS

1 2 REFSET J20 REFSET EXP_RXP8 M30 PCIE_GTX_C_MRX_P8
R131 255_0402_1% N34 PCIE_GTX_C_MRX_P9
EXP_RXP9 PCIE_GTX_C_MRX_P10
EXP_RXP10 P30
R34 PCIE_GTX_C_MRX_P11
EXP_RXP11 PCIE_GTX_C_MRX_P12
EXP_RXP12 T30
U34 PCIE_GTX_C_MRX_P13
C EXP_RXP13 PCIE_GTX_C_MRX_P14 C
EXP_RXP14 V30
W34 PCIE_GTX_C_MRX_P15
EXP_RXP15
E25 LBKLT_CTL
LBKLT_EN F25 E32 PCIE_MTX_GRX_N0 C153 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N0
LCTLA_CLK LBKLT_EN EXP_TXN0/SDVOB_RED# PCIE_MTX_GRX_N1 C132 1 PCIE_MTX_C_GRX_N1
C23 LCTLA_CLK EXP_TXN1/SDVOB_GREEN# F36 2 PM@ 0.1U_0402_16V4Z
+2.5VS LCTLB_DATA C22 G32 PCIE_MTX_GRX_N2 C155 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N2
LDDC_CLK LCTLB_DATA EXP_TXN2/SDVOB_BLUE# PCIE_MTX_GRX_N3 C134 1 PCIE_MTX_C_GRX_N3
F23 LDDC_CLK EXP_TXN3/SDVOB_CLKN H36 2 PM@ 0.1U_0402_16V4Z
R130 1 2 4.7K_0402_5% GMCH_CRT_CLK LDDC_DATA F22 J32 PCIE_MTX_GRX_N4 C157 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N4
GMCH_ENVDD LDDC_DATA EXP_TXN4/SDVOC_RED# PCIE_MTX_GRX_N5 C136 1 PCIE_MTX_C_GRX_N5
21 GMCH_ENVDD F26 LVDD_EN EXP_TXN5/SDVOC_GREEN# K36 2 PM@ 0.1U_0402_16V4Z
R126 1 2 4.7K_0402_5% GMCH_CRT_DATA LIBG C33 L32 PCIE_MTX_GRX_N6 C159 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N6
LIBG EXP_TXN6/SDVOC_BLUE# PCIE_MTX_GRX_N7 C138 1 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N7
C31 LVBG EXP_TXN7/SDVOC_CLKN M36 2
R133 1 GM@ 2 2.2K_0402_5% LCTLB_DATA F28 N32 PCIE_MTX_GRX_N8 C161 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N8
LVREFH EXP_TXN8 PCIE_MTX_GRX_N9 C140 1 PCIE_MTX_C_GRX_N9
F27 LVREFL EXP_TXN9 P36 2 PM@ 0.1U_0402_16V4Z
R141 1 GM@ 2 2.2K_0402_5% LCTLA_CLK R32 PCIE_MTX_GRX_N10 C163 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N10
GMCH_TXCLK- EXP_TXN10 PCIE_MTX_GRX_N11 C142 1 PCIE_MTX_C_GRX_N11
21 GMCH_TXCLK- B30 LACLKN EXP_TXN11 T36 2 PM@ 0.1U_0402_16V4Z
GMCH_TXCLK+ PCIE_MTX_GRX_N12 C165 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N12
Intel Recommand 21 GMCH_TXCLK+ B29 LACLKP EXP_TXN12 U32 1

LVDS
GMCH_TZCLK- C25 V36 PCIE_MTX_GRX_N13 C144 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N13
21 GMCH_TZCLK- LBCLKN EXP_TXN13
R146 1 2 100K_0402_5% LBKLT_EN GMCH_TZCLK+ C24 W32 PCIE_MTX_GRX_N14 C167 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N14
21 GMCH_TZCLK+ LBCLKP EXP_TXN14
Y36 PCIE_MTX_GRX_N15 C146 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N15
R152 1 1.5K_0402_1% LIBG GMCH_TXOUT0- EXP_TXN15
2 21 GMCH_TXOUT0- B34 LADATAN0
GMCH_TXOUT1- B33
21 GMCH_TXOUT1- LADATAN1
R529 1 2 75_0402_1% GMCH_TV_COMPS GMCH_TXOUT2- B32 D32 PCIE_MTX_GRX_P0 C152 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P0
21 GMCH_TXOUT2- LADATAN2 EXP_TXP0/SDVOB_RED
E36 PCIE_MTX_GRX_P1 C131 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P1
GMCH_TV_LUMA EXP_TXP1/SDVOB_GREEN PCIE_MTX_GRX_P2
R531 1 2 150_0402_1%
EXP_TXP2/SDVOB_BLUE F32 C154 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P2
GMCH_TXOUT0+ A34 G36 PCIE_MTX_GRX_P3 C133 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P3
21 GMCH_TXOUT0+ LADATAP0 EXP_TXP3/SDVOB_CLKP
R532 1 2 150_0402_1% GMCH_TV_CRMA GMCH_TXOUT1+ A33 H32 PCIE_MTX_GRX_P4 C156 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P4
21 GMCH_TXOUT1+ LADATAP1 EXP_TXP4/SDVOC_RED
GMCH_TXOUT2+ B31 J36 PCIE_MTX_GRX_P5 C135 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P5
21 GMCH_TXOUT2+ LADATAP2 EXP_TXP5/SDVOC_GREEN
K32 PCIE_MTX_GRX_P6 C158 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P6
EXP_TXP6/SDVOC_BLUE PCIE_MTX_GRX_P7 C137 1 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P7
EXP_TXP7/SDVOC_CLKP L36 2
M32 PCIE_MTX_GRX_P8 C160 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P8
GMCH_TZOUT0- EXP_TXP8 PCIE_MTX_GRX_P9 C139 1 PCIE_MTX_C_GRX_P9
21 GMCH_TZOUT0- C29 LBDATAN0 EXP_TXP9 N36 2 PM@ 0.1U_0402_16V4Z
B GMCH_TZOUT1- D28 P32 PCIE_MTX_GRX_P10 C162 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P10 B
21 GMCH_TZOUT1- LBDATAN1 EXP_TXP10
GMCH_TZOUT2- C27 R36 PCIE_MTX_GRX_P11 C141 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P11
21 GMCH_TZOUT2- LBDATAN2 EXP_TXP11
T32 PCIE_MTX_GRX_P12 C164 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P12
EXP_TXP12 PCIE_MTX_GRX_P13 C143 1 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P13
EXP_TXP13 U36 2
V32 PCIE_MTX_GRX_P14 C166 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P14
GMCH_TZOUT0+ EXP_TXP14 PCIE_MTX_GRX_P15 C145 1 PCIE_MTX_C_GRX_P15
21 GMCH_TZOUT0+ C28 LBDATAP0 EXP_TXP15 W36 2 PM@ 0.1U_0402_16V4Z
GMCH_TZOUT1+ D27
21 GMCH_TZOUT1+ LBDATAP1
GMCH_TZOUT2+ C26
21 GMCH_TZOUT2+ LBDATAP2

915PM@ ALVISO_BGA1257
+2.5VS
+3VS
2

R155 R154
GM@ 4.7K_0402_5% GM@ 4.7K_0402_5%
2
G

+3VS +2.5VS
1

LDDC_CLK 3 1 GMCH_LCD_CLK
GMCH_LCD_CLK 21
S

Q10
GM@ 2N7002_SOT23
R144
GM@ 2.2K_0402_5%
2
G
2

+2.5VS
+3VS 1 3 LBKLT_EN
15,39 ENBKL
D

A A
2

Q8
R153 R150 GM@ BSS138_SOT23
GM@ 4.7K_0402_5% GM@ 4.7K_0402_5%
2
G
1

LDDC_DATA 3 1 GMCH_LCD_DATA
GMCH_LCD_DATA 21
S

Q9 Security Classification Compal Secret Data Compal Electronics, Inc.

GM@ 2N7002_SOT23 2005/03/01 2006/03/01 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INTEL Alviso PCI-E(2/5)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 7 of 52
5 4 3 2 1
 5 4 3 2 1

D D

DDRA_SDQ[0..63]
11 DDRA_SDQ[0..63]
DDRA_SDM[0..7]
11 DDRA_SDM[0..7]
DDRA_SDQS[0..7]
11 DDRA_SDQS[0..7]
DDRA_SMA[0..13] DDRB_SMA[0..13]
11 DDRA_SMA[0..13] 12 DDRB_SMA[0..13]

U44C U44D
AK15 AG35 DDRA_SDQ0 AJ15 AE31
11 DDRA_SBS0 SA_BS0# SADQ0 12 DDRB_SBS0 SB_BS0# SBDQ0
AK16 AH35 DDRA_SDQ1 AG17 AE32
11 DDRA_SBS1 SA_BS1# SADQ1 12 DDRB_SBS1 SB_BS1# SBDQ1
AL21 AL35 DDRA_SDQ2 AG21 AG32
SA_BS2# SADQ2 DDRA_SDQ3 SB_BS2# SBDQ2
SADQ3 AL37 SBDQ3 AG36
DDRA_SDM0 AJ37 AH36 DDRA_SDQ4 AF32 AE34
DDRA_SDM1 SA_DM0 SADQ4 DDRA_SDQ5 SB_DM0 SBDQ4
AP35 SA_DM1 SADQ5 AJ35 AK34 SB_DM1 SBDQ5 AE33
DDRA_SDM2 AL29 AK37 DDRA_SDQ6 AK27 AF31
DDRA_SDM3 SA_DM2 SADQ6 DDRA_SDQ7 SB_DM2 SBDQ6
AP24 SA_DM3 SADQ7 AL34 AK24 SB_DM3 SBDQ7 AF30
DDRA_SDM4 AP9 AM36 DDRA_SDQ8 AJ10 AH33
DDRA_SDM5 SA_DM4 SADQ8 DDRA_SDQ9 SB_DM4 SBDQ8
AP4 SA_DM5 SADQ9 AN35 AK5 SB_DM5 SBDQ9 AH32
DDRA_SDM6 AJ2 AP32 DDRA_SDQ10 AE7 AK31
DDRA_SDM7 SA_DM6 SADQ10 DDRA_SDQ11 SB_DM6 SBDQ10
AD3 SA_DM7 SADQ11 AM31 AB7 SB_DM7 SBDQ11 AG30
AM34 DDRA_SDQ12 AG34
DDRA_SDQS0 SADQ12 DDRA_SDQ13 SBDQ12
AK36 SA_DQS0 SADQ13 AM35 AF34 SB_DQS0 SBDQ13 AG33
DDRA_SDQS1 AP33 AL32 DDRA_SDQ14 AK32 AH31
DDRA_SDQS2 SA_DQS1 SADQ14 DDRA_SDQ15 SB_DQS1 SBDQ14
AN29 SA_DQS2 SADQ15 AM32 AJ28 SB_DQS2 SBDQ15 AJ31
C DDRA_SDQS3 DDRA_SDQ16 C
AP23 SA_DQS3 SADQ16 AN31 AK23 SB_DQS3 SBDQ16 AK30
DDRA_SDQS4 AM8 AP31 DDRA_SDQ17 AM10 AJ30
DDRA_SDQS5 SA_DQS4 SADQ17 DDRA_SDQ18 SB_DQS4 SBDQ17
AM4 SA_DQS5 SADQ18 AN28 AH6 SB_DQS5 SBDQ18 AH29
DDRA_SDQS6 AJ1 AP28 DDRA_SDQ19 AF8 AH28
DDRA_SDQS7 SA_DQS6 SADQ19 DDRA_SDQ20 SB_DQS6 SBDQ19
AE5 SA_DQS7 SADQ20 AL30 AB4 SB_DQS7 SBDQ20 AK29
AM30 DDRA_SDQ21 AH30
SADQ21 DDRA_SDQ22 SBDQ21
AK35 SA_DQS0# SADQ22 AM28 AF35 SB_DQS0# SBDQ22 AH27
AP34 AL28 DDRA_SDQ23 AK33 AG28

DDR SYSTEM MEMORY B

SA_DQS1# SADQ23 DDRA_SDQ24 SB_DQS1# SBDQ23
AN30 AP27 AK28 AF24
DDR MEMORY SYSTEM A

SA_DQS2# SADQ24 DDRA_SDQ25 SB_DQS2# SBDQ24

AN23 SA_DQS3# SADQ25 AM27 AJ23 SB_DQS3# SBDQ25 AG23
AN8 AM23 DDRA_SDQ26 AL10 AJ22
SA_DQS4# SADQ26 DDRA_SDQ27 SB_DQS4# SBDQ26
AM5 SA_DQS5# SADQ27 AM22 AH7 SB_DQS5# SBDQ27 AK22
AH1 AL23 DDRA_SDQ28 AF7 AH24
SA_DQS6# SADQ28 DDRA_SDQ29 SB_DQS6# SBDQ28
AE4 SA_DQS7# SADQ29 AM24 AB5 SB_DQS7# SBDQ29 AH23
AN22 DDRA_SDQ30 AG22
DDRA_SMA0 SADQ30 DDRA_SDQ31 DDRB_SMA0 SBDQ30
AL17 SA_MA0 SADQ31 AP22 AH17 SB_MA0 SBDQ31 AJ21
DDRA_SMA1 AP17 AM9 DDRA_SDQ32 DDRB_SMA1 AK17 AG10
DDRA_SMA2 SA_MA1 SADQ32 DDRA_SDQ33 DDRB_SMA2 SB_MA1 SBDQ32
AP18 SA_MA2 SADQ33 AL9 AH18 SB_MA2 SBDQ33 AG9
DDRA_SMA3 AM17 AL6 DDRA_SDQ34 DDRB_SMA3 AJ18 AG8
DDRA_SMA4 SA_MA3 SADQ34 DDRA_SDQ35 DDRB_SMA4 SB_MA3 SBDQ34
AN18 SA_MA4 SADQ35 AP7 AK18 SB_MA4 SBDQ35 AH8
DDRA_SMA5 AM18 AP11 DDRA_SDQ36 DDRB_SMA5 AJ19 AH11
DDRA_SMA6 SA_MA5 SADQ36 DDRA_SDQ37 DDRB_SMA6 SB_MA5 SBDQ36
AL19 SA_MA6 SADQ37 AP10 AK19 SB_MA6 SBDQ37 AH10
DDRA_SMA7 AP20 AL7 DDRA_SDQ38 DDRB_SMA7 AH19 AJ9
DDRA_SMA8 SA_MA7 SADQ38 DDRA_SDQ39 DDRB_SMA8 SB_MA7 SBDQ38
AM19 SA_MA8 SADQ39 AM7 AJ20 SB_MA8 SBDQ39 AK9
DDRA_SMA9 AL20 AN5 DDRA_SDQ40 DDRB_SMA9 AH20 AJ7
DDRA_SMA10 SA_MA9 SADQ40 DDRA_SDQ41 DDRB_SMA10 SB_MA9 SBDQ40
AM16 SA_MA10 SADQ41 AN6 AJ16 SB_MA10 SBDQ41 AK6
DDRA_SMA11 AN20 AN3 DDRA_SDQ42 DDRB_SMA11 AG18 AJ4
DDRA_SMA12 SA_MA11 SADQ42 DDRA_SDQ43 DDRB_SMA12 SB_MA11 SBDQ42
AM20 SA_MA12 SADQ43 AP3 AG20 SB_MA12 SBDQ43 AH5
DDRA_SMA13 AM15 AP6 DDRA_SDQ44 DDRB_SMA13 AG15 AK8
SA_MA13 SADQ44 DDRA_SDQ45 SB_MA13 SBDQ44
SADQ45 AM6 SBDQ45 AJ8
AN15 AL4 DDRA_SDQ46 AH14 AJ5
11 DDRA_SCAS# SA_CAS# SADQ46 12 DDRB_SCAS# SB_CAS# SBDQ46
B AP16 AM3 DDRA_SDQ47 AK14 AK4 B
11 DDRA_SRAS# SA_RAS# SADQ47 12 DDRB_SRAS# SB_RAS# SBDQ47
AF29 AK2 DDRA_SDQ48 AF15 AG5
SA_RCVENIN# SADQ48 DDRA_SDQ49 SB_RCVENIN# SBDQ48
AF28 SA_RCVENOUT# SADQ49 AK3 AF14 SB_RCVENOUT# SBDQ49 AG4
AP15 AG2 DDRA_SDQ50 AH16 AD8
11 DDRA_SWE# SA_WE# SADQ50 12 DDRB_SWE# SB_WE# SBDQ50
AG1 DDRA_SDQ51 AD9
SADQ51 DDRA_SDQ52 SBDQ51
SADQ52 AL3 SBDQ52 AH4
AM2 DDRA_SDQ53 AG6
SADQ53 DDRA_SDQ54 SBDQ53
SADQ54 AH3 SBDQ54 AE8
AG3 DDRA_SDQ55 AD7
SADQ55 DDRA_SDQ56 SBDQ55
SADQ56 AF3 SBDQ56 AC5
AE3 DDRA_SDQ57 AB8
SADQ57 DDRA_SDQ58 SBDQ57
SADQ58 AD6 SBDQ58 AB6
AC4 DDRA_SDQ59 AA8
SADQ59 DDRA_SDQ60 SBDQ59
SADQ60 AF2 SBDQ60 AC8
AF1 DDRA_SDQ61 AC7
SADQ61 DDRA_SDQ62 SBDQ61
SADQ62 AD4 SBDQ62 AA4
AD5 DDRA_SDQ63 AA5
SADQ63 SBDQ63

915PM@ ALVISO_BGA1257 915PM@ ALVISO_BGA1257

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INTEL Alviso DDR(3/5)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 8 of 52
5 4 3 2 1
 5 4 3 2 1

+1.05VS
4000mA
U44F C238
U44E 0.1U_0402_16V4Z C237 2.2U_0603_6.3V6K
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.05VS K13 AM37 V1.8_DDR_CAP1 2 1 0.1U_0402_16V4Z
VTT0 VCCSM0 V1.8_DDR_CAP2
+1.05VS T29 VCC0 VCCA_TVDACA0 F17 +3VS_DAC J13 VTT1 VCCSM1 AH37 2 1 1 1 1 1 1 1
R29 E17 810mA K12 AP29 V1.8_DDR_CAP5 2 1 C212 C126 C224
VCC1 VCCA_TVDACA1 VTT2 VCCSM2 C227
3900mA N29 VCC2 VCCA_TVDACB0 D18 W11 VTT3 VCCSM3 AD28 +2.5V
M29 C18 120mA V11 AD27 0.1U_0402_16V4Z C129 C214 C179
VCC3 VCCA_TVDACB1 VTT4 VCCSM4 2 2 2 2 2 2
D K29 VCC4 VCCA_TVDACC0 F18 U11 VTT5 VCCSM5 AC27 2200mA D
J29 E18 T11 AP26 22U_1206_16V4Z_V1
VCC5 VCCA_TVDACC1 VTT6 VCCSM6 2.2U_0603_6.3V6K 0.1U_0402_16V4Z
V28 R11 AN26
U28
T28
VCC6
VCC7
VCC8 POWER VCCA_TVBG
VSSA_TVBG
H18
G18
P11
N11
VTT7
VTT8
VTT9
POWER VCCSM7
VCCSM8
VCCSM9
AM26
AL26 +2.5V
2200mA
R28 VCC9 M11 VTT10 VCCSM10 AK26
P28 D19 L11 AJ26 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCC10 VCCD_TVDAC VTT11 VCCSM11
N28 VCC11 VCCDQ_TVDAC H17 24mA K11 VTT12 VCCSM12 AH26 1
M28 VCC12 W10 VTT13 VCCSM13 AG26 1 1 1 1 1 1 1 1
L28 B26 V10 AF26 + C128 C204 C222 C217
VCC13 VCCD_LVDS0 +1.5VS VTT14 VCCSM14
K28 VCC14 VCCD_LVDS1 B25 U10 VTT15 VCCSM15 AE26
J28 A25 60mA T10 AP25 C745 C168 C213 C180 C147
VCC15 VCCD_LVDS2 VTT16 VCCSM16 330U_D2E_2.5VM 2 2 2 2 2 2 2 2 2
H28 VCC16 R10 VTT17 VCCSM17 AN25
G28 VCC17 VCCA_LVDS A35 +2.5VS P10 VTT18 VCCSM18 AM25
V27 20mA N10 AL25 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCC18 VTT19 VCCSM19
U27 VCC19 VCCHV0 B22 M10 VTT20 VCCSM20 AK25
T27 VCC20 VCCHV1 B21 10mA K10 VTT21 VCCSM21 AJ25
R27 VCC21 VCCHV2 A21 J10 VTT22 VCCSM22 AH25
P27 VCC22 Y9 VTT23 VCCSM23 AG25
+2.5VS
N27 VCC23 VCCTX_LVDS0 B28 W9 VTT24 VCCSM24 AF25 VCCHV(Ball A21,B21,B22)
M27 VCC24 VCCTX_LVDS1 A28 60mA U9 VTT25 VCCSM25 AE25
L27 VCC25 VCCTX_LVDS2 A27 R9 VTT26 VCCSM26 AE24
K27 VCC26 P9 VTT27 VCCSM27 AE23
J27 VCC27 VCCA_SM0 AF20 +1.5VS_DDRDLL N9 VTT28 VCCSM28 AE22 1 1 1 1 1 1
H27 AP19 M9 AE21 C231 C232 C202 C206 C225 C223
VCC28 VCCA_SM1 VTT29 VCCSM29
K26 VCC29 VCCA_SM2 AF19 L9 VTT30 VCCSM30 AE20
H26 VCC30 VCCA_SM3 AF18 J9 VTT31 VCCSM31 AE19
2 0.1U_0402_16V4Z 2 0.01U_0402_16V7K 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z
K25 VCC31 N8 VTT32 VCCSM32 AE18
J25 VCC32 VCC3G0 AE37 +1.5VS_PEG M8 VTT33 VCCSM33 AE17
K24 VCC33 VCC3G1 W37 N7 VTT34 VCCSM34 AE16
K23 VCC34 VCC3G2 U37 M7 VTT35 VCCSM35 AE15
C
K22 VCC35 VCC3G3 R37 N6 VTT36 VCCSM36 AE14 VCCA_LVDS (Ball A35) VCCTX_LVDS(Ball A27,A28,B28) C
K21 VCC36 VCC3G4 N37 M6 VTT37 VCCSM37 AP13
W20 VCC37 VCC3G5 L37 A6 VTT38 VCCSM38 AN13
+2.5VS
U20 VCC38 VCC3G6 J37 1000mA N5 VTT39 VCCSM39 AM13 VCCA_CRTDAC(Ball F19,E19)
T20 C715 1 M5 AL13
VCC39 0.47U_0603_16V4Z VTT40 VCCSM40
K20 VCC40 N4 VTT41 VCCSM41 AK13
V19 VCC41 M4 VTT42 VCCSM42 AJ13
U19 VCC42 VCCA_3GPLL0 Y29 +1.5VS_3GPLL N3 VTT43 VCCSM43 AH13 1 1 1 1
2 C189 C194 C200 C205
K19 VCC43 VCCA_3GPLL1 Y28 M3 VTT44 VCCSM44 AG13
W18 VCC44 VCCA_3GPLL2 Y27 N2 VTT45 VCCSM45 AF13
V18 VCC45 M2 VTT46 VCCSM46 AE13
2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.022U_0402_16V7K
T18 VCC46 B2 VTT47 VCCSM47 AP12
K18 VCC47 VCCA_3GBG F37 15mA +2.5VS_3GBG V1 VTT48 VCCSM48 AN12
K17 VCC48 VSSA_3GBG G37 N1 VTT49 VCCSM49 AM12
1 M1 VTT50 VCCSM50 AL12
+1.5VS AC1 VCCD_HMPLL1 VCC_SYNC H20 +2.5VS G1 VTT51 VCCSM51 AK12 VCC_SYNC(Ball H20)
180mA AC2 VCCD_HMPLL2 70mA VCCSM52 AJ12
+1.5VS_DPLLA +1.5VS_DPLLA B23 F19 C682 AH12
+1.5VS_DPLLB VCCA_DPLLA VCCA_CRTDAC0 0.47U_0603_16V4Z 2 VCCSM53
+1.5VS_DPLLB
+1.5VS_HPLL
C35 VCCA_DPLLB VCCA_CRTDAC1 E19 VCCSM54 AG12
+1.5VS VCCD_TVDAC (Ball D19)
+1.5VS_HPLL AA1 VCCA_HPLL VSSA_CRTDAC G19 1 VCCSM55 AF12
+1.5VS_MPLL +1.5VS_MPLL AA2 AE12 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCCA_MPLL VCCSM56
VCCSM57 AD11
C693 AC11
915PM@
ALVISO_BGA1257 0.22U_0402_10V4Z 2 VCCSM58
VCCSM59 AB11 1 1 1 1 1 1
1 AB10 C127 C220 C218 C184 C185 C178 C181
VCCSM60 0.1U_0402_16V4Z C120
VCCSM61 AB9
VCCSM62 AP8 V1.8_DDR_CAP6 2 1 0.1U_0402_16V4Z
C688 AM1 V1.8_DDR_CAP4 2 1 4.7U_0805_10V4Z 2 2 2 2 2 2
0.22U_0402_10V4Z 2 VCCSM63
VCCSM64 AE1 V1.8_DDR_CAP3 2 1
C689 0.1U_0402_16V4Z 0.022U_0402_16V7K 0.022U_0402_16V7K
0.1U_0402_16V4Z
915PM@
ALVISO_BGA1257 VCCD_LVDS(Ball A25,B25,B26) VCCDQ_TVDAC (Ball H17)
B B

+1.05VS
950mA

1 1 1 1
+1.5VS_DPLLA L11 +1.5VS_DPLLB L14 +1.5VS_DDRDLL R129 +1.5VS_PEG R160 C130 C170 C198 C173
60mA 0_0603_5% 60mA 0_0603_5% 0_0603_5% 0_0805_5%
1 2 +1.5VS 1 2 +1.5VS 1 2 +1.5VS 1 2 +1.5VS 2 2.2U_0603_6.3V6K 2 2.2U_0603_6.3V6K 2 2.2U_0603_6.3V6K 2 2.2U_0603_6.3V6K
1
1 1 1 1 1 1 1 1 1
C208 C209 C235 C233 C190 C196 C243 C242 C244 + C234

2 22U_1206_16V4Z_V12 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V12 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V1 2 4.7U_0805_10V4Z 2 4.7U_0805_10V4Z 2 470U_D2_2.5VM

L38
VCCA_TVDAC
+3VS_DAC VCCA_TVBG (Ball H18)
CHB1608U301_0603
+1.5VS_HPLL L27 +1.5VS_MPLL L7 +1.5VS_3GPLL R145 L13 +2.5VS_3GBG 1 2
+3VS
60mA 0_0603_5% 60mA 0_0603_5% 0.5_0603_1% 0_0603_5% 1
1 2 +1.5VS 1 2 +1.5VS 1 2+3GPLL 1 2 +1.5VS 1 2 +2.5VS 1 1 1 1 1 1
R159 0_0603_5% C855 + C856 C857 C177 C188 C187 C195
1 1 1 1 1 1 1 150U_D2_6.3VM
C690 C692 C112 C114 C221
C226 C241 2 2 2 2 2 0.022U_0402_16V7K 2 2 0.022U_0402_16V7K
0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 22U_1206_16V4Z_V12 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V12 0.1U_0402_16V4Z 2 10U_1206_16V4Z 2 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V1 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A A

120mA

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INTEL Alviso POWER(4/5)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 9 of 52
5 4 3 2 1
 5 4 3 2 1

U44H
U44I U44J
+1.05VS L12 VTT_NCTF17 VCCSM_NCTF31 AB12 +2.5V
M12 VTT_NCTF16 VCCSM_NCTF30 AC12 Y1 VSS271 AL24 VSS267
N12 VTT_NCTF15 VCCSM_NCTF29 AD12 D2 VSS270 VSSALVDS B36 AN24 VSS266 VSS67 AC32
D P12 VTT_NCTF14 VCCSM_NCTF28 AB13 G2 VSS269 A26 VSS265 VSS66 AD32 D
R12 VTT_NCTF13 VCCSM_NCTF27 AC13 J2 VSS268 VSS195 AA11 E26 VSS264 VSS65 AJ32
T12 VTT_NCTF12 VCCSM_NCTF26 AD13 L2 VSS260 VSS194 AF11 G26 VSS263 VSS64 AN32
U12 VTT_NCTF11 VCCSM_NCTF25 AC14 P2 VSS259 VSS193 AG11 J26 VSS262 VSS63 D33
V12 VTT_NCTF10 VCCSM_NCTF24 AD14 T2 VSS258 VSS192 AJ11 B27 VSS261 VSS62 E33
W12 VTT_NCTF9 VCCSM_NCTF23 AC15 V2 VSS257 VSS191 AL11 E27 VSS129 VSS61 F33
L13 VTT_NCTF8 VCCSM_NCTF22 AD15 AD2 VSS256 VSS190 AN11 G27 VSS128 VSS60 G33
M13 VTT_NCTF7 VCCSM_NCTF21 AC16 AE2 VSS255 VSS189 B12 W27 VSS127 VSS59 H33
N13
P13
R13
T13
U13
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
AD16
AC17
AD17
AC18
AD18
AH2
AL2
AN2
A3
C3
VSS254
VSS253
VSS252
VSS251
VSS
VSS188
VSS187
VSS186
VSS185
D12
J12
A14
B14
F14
AA27
AB27
AF27
AG27
AJ27
VSS126
VSS125
VSS124
VSS123
VSS VSS58
VSS57
VSS56
VSS55
J33
K33
L33
M33
N33
VTT_NCTF2 VCCSM_NCTF16 VSS250 VSS184 VSS122 VSS54
V13 VTT_NCTF1 VCCSM_NCTF15 AC19 AA3 VSS249 VSS183 J14 AL27 VSS121 VSS53 P33
W13 VTT_NCTF0 VCCSM_NCTF14 AD19 AB3 VSS248 VSS182 K14 AN27 VSS120 VSS52 R33
VCCSM_NCTF13 AC20 AC3 VSS247 VSS181 AG14 E28 VSS119 VSS51 T33
VCCSM_NCTF12 AD20 AJ3 VSS246 VSS180 AJ14 W28 VSS118 VSS50 U33
Y12 VSS_NCTF68 VCCSM_NCTF11 AC21 C4 VSS245 VSS179 AL14 AA28 VSS117 VSS49 V33
AA12 VSS_NCTF67 VCCSM_NCTF10 AD21 H4 VSS244 VSS178 AN14 AB28 VSS116 VSS48 W33
Y13 VSS_NCTF66 VCCSM_NCTF9 AC22 L4 VSS243 VSS177 C15 AC28 VSS115 VSS47 AD33
AA13 VSS_NCTF65 VCCSM_NCTF8 AD22 P4 VSS242 VSS176 K15 A29 VSS114 VSS46 AF33
L14 VSS_NCTF64 VCCSM_NCTF7 AC23 U4 VSS241 VSS175 A16 D29 VSS113 VSS45 AL33
M14 VSS_NCTF63 VCCSM_NCTF6 AD23 Y4 VSS240 VSS174 D16 E29 VSS112 VSS44 C34
N14 VSS_NCTF62 VCCSM_NCTF5 AC24 AF4 VSS239 VSS173 H16 F29 VSS111 VSS43 AA34
P14 VSS_NCTF61 VCCSM_NCTF4 AD24 AN4 VSS238 VSS172 K16 G29 VSS110 VSS42 AB34
R14 VSS_NCTF60 VCCSM_NCTF3 AC25 E5 VSS237 VSS171 AL16 H29 VSS109 VSS41 AC34
T14 VSS_NCTF59 VCCSM_NCTF2 AD25 W5 VSS236 VSS170 C17 L29 VSS108 VSS40 AD34
U14 VSS_NCTF58 VCCSM_NCTF1 AC26 AL5 VSS235 VSS169 G17 P29 VSS107 VSS39 AH34
V14 VSS_NCTF57 VCCSM_NCTF0 AD26 AP5 VSS234 VSS168 AF17 U29 VSS106 VSS38 AN34
W14 VSS_NCTF56 B6 VSS233 VSS167 AJ17 V29 VSS105 VSS37 B35
Y14 VSS_NCTF55 VCC_NCTF78 L17 +1.05VS J6 VSS232 VSS166 AN17 W29 VSS104 VSS36 D35
AA14 VSS_NCTF54 VCC_NCTF77 M17 L6 VSS231 VSS165 A18 AA29 VSS103 VSS35 E35
C C
AB14 VSS_NCTF53 VCC_NCTF76 N17 P6 VSS230 VSS164 B18 AD29 VSS102 VSS34 F35
L15 VSS_NCTF52 VCC_NCTF75 P17 T6 VSS229 VSS163 U18 AG29 VSS101 VSS33 G35
M15 T17 AA6 AL18 AJ29 H35
NCTF

VSS_NCTF51 VCC_NCTF74 VSS228 VSS162 VSS100 VSS32

N15 VSS_NCTF50 VCC_NCTF73 U17 AC6 VSS227 VSS161 C19 AM29 VSS99 VSS31 J35
P15 VSS_NCTF49 VCC_NCTF72 V17 AE6 VSS226 VSS160 H19 C30 VSS98 VSS30 K35
R15 VSS_NCTF48 VCC_NCTF71 W17 AJ6 VSS225 VSS159 J19 Y30 VSS97 VSS29 L35
T15 VSS_NCTF47 VCC_NCTF70 L18 G7 VSS224 VSS158 T19 AA30 VSS96 VSS28 M35
U15 VSS_NCTF46 VCC_NCTF69 M18 V7 VSS223 VSS157 W19 AB30 VSS95 VSS27 N35
V15 VSS_NCTF45 VCC_NCTF68 N18 AA7 VSS222 VSS156 AG19 AC30 VSS94 VSS26 P35
W15 VSS_NCTF44 VCC_NCTF67 P18 AG7 VSS221 VSS155 AN19 AE30 VSS93 VSS25 R35
Y15 VSS_NCTF43 VCC_NCTF66 R18 AK7 VSS220 VSS154 A20 AP30 VSS92 VSS24 T35
AA15 VSS_NCTF42 VCC_NCTF65 Y18 AN7 VSS219 VSS153 D20 D31 VSS91 VSS23 U35
AB15 VSS_NCTF41 VCC_NCTF64 L19 C8 VSS218 VSS152 E20 E31 VSS90 VSS22 V35
L16 VSS_NCTF40 VCC_NCTF63 M19 E8 VSS217 VSS151 F20 F31 VSS89 VSS21 W35
M16 VSS_NCTF39 VCC_NCTF62 N19 L8 VSS216 VSS150 G20 G31 VSS88 VSS20 Y35
N16 VSS_NCTF38 VCC_NCTF61 P19 P8 VSS215 VSS149 V20 H31 VSS87 VSS19 AE35
P16 VSS_NCTF37 VCC_NCTF60 R19 Y8 VSS214 VSS148 AK20 J31 VSS86 VSS18 C36
R16 VSS_NCTF36 VCC_NCTF59 Y19 AL8 VSS213 VSS147 C21 K31 VSS85 VSS17 AA36
T16 VSS_NCTF35 VCC_NCTF58 L20 A9 VSS212 VSS146 F21 L31 VSS84 VSS16 AB36
U16 VSS_NCTF34 VCC_NCTF57 M20 H9 VSS211 VSS145 AF21 M31 VSS83 VSS15 AC36
V16 VSS_NCTF33 VCC_NCTF56 N20 K9 VSS210 VSS144 AN21 N31 VSS82 VSS14 AD36
W16 VSS_NCTF32 VCC_NCTF55 P20 T9 VSS209 VSS143 A22 P31 VSS81 VSS13 AE36
Y16 VSS_NCTF31 VCC_NCTF54 R20 V9 VSS208 VSS142 D22 R31 VSS80 VSS12 AF36
AA16 VSS_NCTF30 VCC_NCTF53 Y20 AA9 VSS207 VSS141 E22 T31 VSS79 VSS11 AJ36
AB16 VSS_NCTF29 VCC_NCTF52 L21 AC9 VSS206 VSS140 J22 U31 VSS78 VSS10 AL36
R17 VSS_NCTF28 VCC_NCTF51 M21 AE9 VSS205 VSS139 AH22 V31 VSS77 VSS9 AN36
Y17 VSS_NCTF27 VCC_NCTF50 N21 AH9 VSS204 VSS138 AL22 W31 VSS76 VSS8 E37
AA17 VSS_NCTF26 VCC_NCTF49 P21 AN9 VSS203 VSS137 H23 AD31 VSS75 VSS7 H37
AB17 VSS_NCTF25 VCC_NCTF48 T21 D10 VSS202 VSS136 AF23 AG31 VSS74 VSS6 K37
AA18 VSS_NCTF24 VCC_NCTF47 U21 L10 VSS201 VSS135 B24 AL31 VSS73 VSS5 M37
AB18 VSS_NCTF23 VCC_NCTF46 V21 Y10 VSS200 VSS134 D24 A32 VSS72 VSS4 P37
B AA19 W21 AA10 F24 C32 T37 B
VSS_NCTF22 VCC_NCTF45 VSS199 VSS133 VSS71 VSS3
AB19 VSS_NCTF21 VCC_NCTF44 L22 F11 VSS198 VSS132 J24 Y32 VSS70 VSS2 V37
AA20 VSS_NCTF20 VCC_NCTF43 M22 H11 VSS197 VSS131 AG24 AA32 VSS69 VSS1 Y37
AB20 VSS_NCTF19 VCC_NCTF42 N22 Y11 VSS196 VSS130 AJ24 AB32 VSS68 VSS0 AG37
R21 VSS_NCTF18 VCC_NCTF41 P22
Y21 VSS_NCTF17 VCC_NCTF40 R22
AA21 VSS_NCTF16 VCC_NCTF39 T22
AB21 U22 915PM@ ALVISO_BGA1257 915PM@ ALVISO_BGA1257
VSS_NCTF15 VCC_NCTF38
Y22 VSS_NCTF14 VCC_NCTF37 V22
AA22 VSS_NCTF13 VCC_NCTF36 W22
AB22 VSS_NCTF12 VCC_NCTF35 L23
Y23 VSS_NCTF11 VCC_NCTF34 M23
AA23 VSS_NCTF10 VCC_NCTF33 N23
AB23 VSS_NCTF9 VCC_NCTF32 P23
Y24 VSS_NCTF8 VCC_NCTF31 R23
AA24 VSS_NCTF7 VCC_NCTF30 T23
AB24 VSS_NCTF6 VCC_NCTF29 U23
Y25 VSS_NCTF5 VCC_NCTF28 V23
AA25 VSS_NCTF4 VCC_NCTF27 W23
AB25 VSS_NCTF3 VCC_NCTF26 L24
Y26 VSS_NCTF2 VCC_NCTF25 M24
AA26 VSS_NCTF1 VCC_NCTF24 N24
AB26 VSS_NCTF0 VCC_NCTF23 P24
VCC_NCTF22 R24
+1.05VS V25 VCC_NCTF10 VCC_NCTF21 T24
W25 VCC_NCTF9 VCC_NCTF20 U24
L26 VCC_NCTF8 VCC_NCTF19 V24
M26 VCC_NCTF7 VCC_NCTF18 W24
N26 VCC_NCTF6 VCC_NCTF17 L25
P26 VCC_NCTF5 VCC_NCTF16 M25
R26 VCC_NCTF4 VCC_NCTF15 N25
A T26 VCC_NCTF3 VCC_NCTF14 P25 A
U26 VCC_NCTF2 VCC_NCTF13 R25
V26 VCC_NCTF1 VCC_NCTF12 T25
W26 VCC_NCTF0 VCC_NCTF11 U25

915PM@ ALVISO_BGA1257
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INTEL Alviso POWER(5/5)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 10 of 52
5 4 3 2 1
 5 4 3 2 1

+2.5V +2.5V +DIMM_VREF +2.5V RP35 RP118

JP25 DDRA_SDQ0 4 1 DDRA_DQ0 DDRA_SDQ1 1 4 DDRA_DQ1
1 2 DDRA_SDQ4 3 2 DDRA_DQ4 DDRA_SDQ5 2 3 DDRA_DQ5
VREF VREF

1
3 4 R168 +1.25VS
DDRA_DQ1 VSS VSS DDRA_DQ0 10_0404_4P2R_5% 10_0404_4P2R_5%
5 DQ0 DQ4 6
DDRA_DQ5 7 8 DDRA_DQ4 RP34 RP115
DQ1 DQ5 DDRA_SDM0 DDRA_DM0 DDRA_SDQS0
D 9 VDD VDD 10 1K_0402_1% 4 1 1 4 DDRA_DQS0 D
DDRA_DQS0 11 12 DDRA_DM0 DDRA_SDQ6 3 2 DDRA_DQ6 DDRA_SDQ7 2 3 DDRA_DQ7

2
DDRA_DQ7 DQS0 DM0 DDRA_DQ6
13 DQ2 DQ6 14
15 16 10_0404_4P2R_5% 10_0404_4P2R_5%
VSS VSS RP87

1
DDRA_DQ3 17 18 DDRA_DQ2 1 R170 RP33 RP112
DDRA_DQ13 DQ3 DQ7 DDRA_DQ8 DDRA_SDQ2 DDRA_DQ2 DDRA_SDQ3
19 DQ8 DQ12 20 4 1 1 4 DDRA_DQ3 DDRA_SMA11 1 4
21 22 DDRA_SDQ8 3 2 DDRA_DQ8 DDRA_SDQ13 2 3 DDRA_DQ13 DDRA_SMA8 2 3
DDRA_DQ9 VDD VDD DDRA_DQ12 1K_0402_1%
23 DQ9 DQ13 24
DDRA_DQS1 DDRA_DM1 2 10_0404_4P2R_5% 10_0404_4P2R_5% 56_0404_4P2R_5%
25 26

2
DQS1 DM1 RP86
27 28 RP32 RP109
DDRA_DQ15 VSS VSS DDRA_DQ14 DDRA_SDQ12 DDRA_DQ12 DDRA_SDQ9
29 DQ10 DQ14 30 4 1 1 4 DDRA_DQ9 DDRA_SMA6 1 4
DDRA_DQ11 31 32 DDRA_DQ10 C250 DDRA_SDM1 3 2 DDRA_DM1 DDRA_SDQS1 2 3 DDRA_DQS1 DDRA_SMA4 2 3
DQ11 DQ15 0.1U_0402_16V4Z
33 VDD VDD 34
35 36 10_0404_4P2R_5% 10_0404_4P2R_5% 56_0404_4P2R_5%
6 DDRA_CLK1 CK0 VDD
37 38 RP31 RP106 RP84
6 DDRA_CLK1# CK0# VSS
39 40 DDRA_SDQ14 4 1 DDRA_DQ14 DDRA_SDQ15 1 4 DDRA_DQ15 DDRA_SMA2 1 4
VSS VSS DDRA_SDQ10 DDRA_DQ10 DDRA_SDQ11
3 2 2 3 DDRA_DQ11 DDRA_SMA0 2 3

DDRA_DQ16 41 42 DDRA_DQ17 10_0404_4P2R_5% 10_0404_4P2R_5% 56_0404_4P2R_5%

DDRA_DQ20 DQ16 DQ20 DDRA_DQ21 RP82
43 44 RP30 RP102
DQ17 DQ21 DDRA_SDQ17 DDRA_DQ17 DDRA_SDQ16
45 VDD VDD 46 4 1 1 4 DDRA_DQ16 DDRA_SBS1 1 4
DDRA_DQS2 47 48 DDRA_DM2 DDRA_SDQ21 3 2 DDRA_DQ21 DDRA_SDQ20 2 3 DDRA_DQ20 DDRA_SRAS# 2 3
DDRA_DQ18 DQS2 DM2 DDRA_DQ19
49 DQ18 DQ22 50
51 52 10_0404_4P2R_5% 10_0404_4P2R_5% 56_0404_4P2R_5%
DDRA_DQ22 VSS VSS DDRA_DQ23 RP80
53 54 RP29 RP99
DDRA_DQ25 DQ19 DQ23 DDRA_DQ24 DDRA_SDM2 DDRA_DM2 DDRA_SDQS2
55 DQ24 DQ28 56 4 1 1 4 DDRA_DQS2 DDRA_SCAS# 1 4
57 58 DDRA_SDQ19 3 2 DDRA_DQ19 DDRA_SDQ18 2 3 DDRA_DQ18 DDRA_SCS#1 2 3
DDRA_DQ29 VDD VDD DDRA_DQ28
59 DQ25 DQ29 60
DDRA_DQS3 61 62 DDRA_DM3 10_0404_4P2R_5% 10_0404_4P2R_5%
DQS3 DM3 56_0404_4P2R_5%
63 64 RP28 RP97
DDRA_DQ27 VSS VSS DDRA_DQ26 DDRA_SDQ23 DDRA_DQ23 DDRA_SDQ22
65 DQ26 DQ30 66 4 1 1 4 DDRA_DQ22 RP24
DDRA_DQ30 67 68 DDRA_DQ31 DDRA_SDQ24 3 2 DDRA_DQ24 DDRA_SDQ25 2 3 DDRA_DQ25 DDRA_SMA12 2 3
C DQ27 DQ31 DDRA_SMA9 C
69 VDD VDD 70 1 4
71 72 10_0404_4P2R_5% 10_0404_4P2R_5%
CB0 CB4 56_0404_4P2R_5%
73 74 RP27 RP94
CB1 CB5 DDRA_SDQ28 DDRA_DQ28 DDRA_SDQ29
75 VSS VSS 76 4 1 1 4 DDRA_DQ29 RP22
77 78 DDRA_SDM3 3 2 DDRA_DM3 DDRA_SDQS3 2 3 DDRA_DQS3 DDRA_SMA7 2 3
DQS8 DM8 DDRA_SMA5
79 CB2 CB6 80 1 4
81 82 10_0404_4P2R_5% 10_0404_4P2R_5%
VDD VDD 56_0404_4P2R_5%
83 84 RP26 RP91
CB3 CB7 DDRA_SDQ26 DDRA_DQ26 DDRA_SDQ27
85 DU DU/RESET# 86 4 1 1 4 DDRA_DQ27 RP20
87 88 DDRA_SDQ31 3 2 DDRA_DQ31 DDRA_SDQ30 2 3 DDRA_DQ30 DDRA_SMA3 2 3
VSS VSS DDRA_SMA1
89 CK2 VSS 90 1 4
91 92 10_0404_4P2R_5% 10_0404_4P2R_5%
CK2# VDD 56_0404_4P2R_5%
93 94 RP15 RP77
DDRA_CKE1 VDD VDD DDRA_CKE0 DDRA_SDQ37 DDRA_DQ37 DDRA_SDQ36
6 DDRA_CKE1 95 CKE1 CKE0 96 DDRA_CKE0 6 4 1 1 4 DDRA_DQ36 RP18
97 98 DDRA_SDQ32 3 2 DDRA_DQ32 DDRA_SDQ33 2 3 DDRA_DQ33 DDRA_SMA10 2 3
DDRA_SMA12 DU/A13 DU/BA2 DDRA_SMA11 DDRA_SBS0
99 A12 A11 100 1 4
DDRA_SMA9 101 102 DDRA_SMA8 10_0404_4P2R_5% 10_0404_4P2R_5%
A9 A8 56_0404_4P2R_5%
103 104 RP14 RP74
DDRA_SMA7 VSS VSS DDRA_SMA6 DDRA_SDM4 DDRA_DM4 DDRA_SDQS4
105 A7 A6 106 4 1 1 4 DDRA_DQS4 RP16
DDRA_SMA5 107 108 DDRA_SMA4 DDRA_SDQ39 3 2 DDRA_DQ39 DDRA_SDQ38 2 3 DDRA_DQ38 DDRA_SWE# 2 3
DDRA_SMA3 A5 A4 DDRA_SMA2 DDRA_SCS#0
109 A3 A2 110 1 4
DDRA_SMA1 111 112 DDRA_SMA0 10_0404_4P2R_5% 10_0404_4P2R_5%
A1 A0 56_0404_4P2R_5%
113 114 RP13 RP72
DDRA_SMA10 VDD VDD DDRA_SBS1 DDRA_SDQ34 DDRA_DQ34 DDRA_SDQ35
115 A10/AP BA1 116 DDRA_SBS1 8 4 1 1 4 DDRA_DQ35
DDRA_SBS0 117 118 DDRA_SRAS# DDRA_SDQ45 3 2 DDRA_DQ45 DDRA_SDQ41 2 3 DDRA_DQ41 DDRA_SMA13 1 2
8 DDRA_SBS0 BA0 RAS# DDRA_SRAS# 8
DDRA_SWE# 119 120 DDRA_SCAS# R112 56_0402_5%
8 DDRA_SWE# WE# CAS# DDRA_SCAS# 8
DDRA_SCS#0 121 122 DDRA_SCS#1 10_0404_4P2R_5% 10_0404_4P2R_5% DDRA_CKE1 1 2
6 DDRA_SCS#0 S0# S1# DDRA_SCS#1 6
DDRA_SMA13 123 124 RP12 RP69 R138 56_0402_5%
DU DU DDRA_SDQ40 DDRA_DQ40 DDRA_SDQ44
125 VSS VSS 126 4 1 1 4 DDRA_DQ44 DDRA_CKE0 1 2
DDRA_DQ36 127 128 DDRA_DQ37 DDRA_SDM5 3 2 DDRA_DM5 DDRA_SDQS5 2 3 DDRA_DQS5 R544 56_0402_5%
DDRA_DQ33 DQ32 DQ36 DDRA_DQ32
129 DQ33 DQ37 130
B 131 132 10_0404_4P2R_5% 10_0404_4P2R_5% B
DDRA_DQS4 VDD VDD DDRA_DM4
133 134 RP11 RP66
DDRA_DQ38 DQS4 DM4 DDRA_DQ39 DDRA_SDQ42 DDRA_DQ42 DDRA_SDQ46
135 DQ34 DQ38 136 4 1 1 4 DDRA_DQ46
137 138 DDRA_SDQ43 3 2 DDRA_DQ43 DDRA_SDQ47 2 3 DDRA_DQ47 DDRA_DQ[0..63]
DDRA_DQ35 VSS VSS DDRA_DQ34 DDRA_DQ[0..63] 12
139 DQ35 DQ39 140
DDRA_DQ41 141 142 DDRA_DQ45 10_0404_4P2R_5% 10_0404_4P2R_5% DDRA_DM[0..7]
DQ40 DQ44 DDRA_DM[0..7] 12
143 144 RP10 RP62
DDRA_DQ44 VDD VDD DDRA_DQ40 DDRA_SDQ49 DDRA_DQ49 DDRA_SDQ52 DDRA_DQS[0..7]
145 DQ41 DQ45 146 4 1 1 4 DDRA_DQ52 DDRA_DQS[0..7] 12
DDRA_DQS5 147 148 DDRA_DM5 DDRA_SDQ48 3 2 DDRA_DQ48 DDRA_SDQ53 2 3 DDRA_DQ53
DQS5 DM5
149 VSS VSS 150
DDRA_DQ46 151 152 DDRA_DQ42 10_0404_4P2R_5% 10_0404_4P2R_5%
DDRA_DQ47 DQ42 DQ46 DDRA_DQ43
153 154 RP9 RP60
DQ43 DQ47 DDRA_SDM6 DDRA_DM6 DDRA_SDQS6
155 VDD VDD 156 4 1 1 4 DDRA_DQS6
157 158 DDRA_SDQ55 3 2 DDRA_DQ55 DDRA_SDQ54 2 3 DDRA_DQ54
VDD CK1# DDRA_CLK2# 6
159 VSS CK1 160 DDRA_CLK2 6
161 162 10_0404_4P2R_5% 10_0404_4P2R_5% DDRA_SDQ[0..63]
DDRA_DQ52 VSS VSS DDRA_DQ49 8 DDRA_SDQ[0..63]
163 164 RP8 RP57
DDRA_DQ53 DQ48 DQ52 DDRA_DQ48 DDRA_SDQ51 DDRA_DQ51 DDRA_SDQ50 DDRA_SDM[0..7]
165 DQ49 DQ53 166 4 1 1 4 DDRA_DQ50 8 DDRA_SDM[0..7]
167 168 DDRA_SDQ61 3 2 DDRA_DQ61 DDRA_SDQ60 2 3 DDRA_DQ60
DDRA_DQS6 VDD VDD DDRA_DM6 DDRA_SDQS[0..7]
169 DQS6 DM6 170 8 DDRA_SDQS[0..7]
DDRA_DQ54 171 172 DDRA_DQ55 10_0404_4P2R_5% 10_0404_4P2R_5%
DQ50 DQ54 DDRA_SMA[0..13]
173 174 RP7 RP54 8 DDRA_SMA[0..13]
DDRA_DQ50 VSS VSS DDRA_DQ51 DDRA_SDQ58 DDRA_DQ58 DDRA_SDQ56
175 DQ51 DQ55 176 4 1 1 4 DDRA_DQ56
DDRA_DQ60 177 178 DDRA_DQ61 DDRA_SDM7 3 2 DDRA_DM7 DDRA_SDQS7 2 3 DDRA_DQS7
DQ56 DQ60
179 VDD VDD 180
DDRA_DQ56 181 182 DDRA_DQ58 10_0404_4P2R_5% 10_0404_4P2R_5%
DDRA_DQS7 DQ57 DQ61 DDRA_DM7
183 184 RP6 RP51
DQS7 DM7 DDRA_SDQ63 DDRA_DQ63 DDRA_SDQ57
185 VSS VSS 186 4 1 1 4 DDRA_DQ57
DDRA_DQ57 187 188 DDRA_DQ63 DDRA_SDQ59 3 2 DDRA_DQ59 DDRA_SDQ62 2 3 DDRA_DQ62
DDRA_DQ62 DQ58 DQ62 DDRA_DQ59
189 DQ59 DQ63 190
191 192 10_0404_4P2R_5% 10_0404_4P2R_5%
D_CK_SDATA VDD VDD
A 12,14 D_CK_SDATA 193 SDA SA0 194 A
D_CK_SCLK 195 196
12,14 D_CK_SCLK SCL SA1
+3VS 197 VDD_SPD SA2 198
199 VDD_ID DU 200

AMP_1565917-1
DIMM0 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR-SODIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 11 of 52
5 4 3 2 1
 5 4 3 2 1

+2.5V +2.5V +DIMM_VREF

JP12
1 VREF VREF 2
+1.25VS 3 4
DDRA_DQ1 VSS VSS DDRA_DQ0
5 DQ0 DQ4 6 1
DDRA_DQ[0..63] DDRA_DQ5 7 8 DDRA_DQ4 C263
11 DDRA_DQ[0..63] DQ1 DQ5
9 VDD VDD 10
RP117 56_0404_4P2R_5% DDRA_DM[0..7] DDRA_DQS0 11 12 DDRA_DM0 0.1U_0402_16V4Z
11 DDRA_DM[0..7] DQS0 DM0 2
DDRA_DQ0 1 4 4 1 DDRA_DQ1 DDRA_DQ7 13 14 DDRA_DQ6
DDRA_DQ4 DDRA_DQ5 DDRA_DQS[0..7] DQ2 DQ6
2 3 3 2 11 DDRA_DQS[0..7] 15 VSS VSS 16
DDRA_DQ3 17 18 DDRA_DQ2
56_0404_4P2R_5% RP116 DDRB_SMA[0..13] DDRA_DQ13 DQ3 DQ7 DDRA_DQ8
8 DDRB_SMA[0..13] 19 DQ8 DQ12 20
RP114 56_0404_4P2R_5% 21 22
D VDD VDD D
DDRA_DM0 1 4 4 1 DDRA_DQS0 DDRA_DQ9 23 24 DDRA_DQ12
DDRA_DQ6 DDRA_DQ7 DDRA_DQS1 DQ9 DQ13 DDRA_DM1
2 3 3 2 25 DQS1 DM1 26
27 VSS VSS 28
56_0404_4P2R_5% RP113 DDRA_DQ15 29 30 DDRA_DQ14
56_0404_4P2R_5% DDRA_DQ11 DQ10 DQ14 DDRA_DQ10
RP111 31 32
DDRA_DQ2 DDRA_DQ3 DQ11 DQ15
1 4 4 1 33 VDD VDD 34
DDRA_DQ8 2 3 3 2 DDRA_DQ13 35 36
6 DDRB_CLK1 CK0 VDD
6 DDRB_CLK1# 37 CK0# VSS 38
56_0404_4P2R_5% RP110 39 40
56_0404_4P2R_5% VSS VSS
RP108
DDRA_DQ12 1 4 4 1 DDRA_DQ9
DDRA_DM1 2 3 3 2 DDRA_DQS1 DDRA_DQ16 41 42 DDRA_DQ17
DDRA_DQ20 DQ16 DQ20 DDRA_DQ21
43 DQ17 DQ21 44
56_0404_4P2R_5% RP107 45 46
56_0404_4P2R_5% DDRA_DQS2 VDD VDD DDRA_DM2
RP105 47 48
DDRA_DQ14 DDRA_DQ15 DDRA_DQ18 DQS2 DM2 DDRA_DQ19
1 4 4 1 49 DQ18 DQ22 50
DDRA_DQ10 2 3 3 2 DDRA_DQ11 51 52
DDRA_DQ22 VSS VSS DDRA_DQ23
53 DQ19 DQ23 54
56_0404_4P2R_5% RP104 DDRA_DQ25 55 56 DDRA_DQ24
56_0404_4P2R_5% DQ24 DQ28
RP101 57 58
DDRA_DQ17 DDRA_DQ16 DDRA_DQ29 VDD VDD DDRA_DQ28
1 4 4 1 59 DQ25 DQ29 60
DDRA_DQ21 2 3 3 2 DDRA_DQ20 DDRA_DQS3 61 62 DDRA_DM3
DQS3 DM3
63 VSS VSS 64
56_0404_4P2R_5% RP103 DDRA_DQ27 65 66 DDRA_DQ26
56_0404_4P2R_5% DDRA_DQ30 DQ26 DQ30 DDRA_DQ31
RP98 67 68
DDRA_DM2 DDRA_DQS2 DQ27 DQ31
1 4 4 1 69 VDD VDD 70
DDRA_DQ19 2 3 3 2 DDRA_DQ18 71 72
CB0 CB4
73 CB1 CB5 74
56_0404_4P2R_5% RP100 75 76
56_0404_4P2R_5% VSS VSS
RP95 77 78
DDRA_DQ23 DDRA_DQ22 DQS8 DM8
1 4 4 1 79 CB2 CB6 80
C DDRA_DQ24 2 3 3 2 DDRA_DQ25 +1.25VS 81 82
C
VDD VDD
83 CB3 CB7 84
56_0404_4P2R_5% RP96 85 86
56_0404_4P2R_5% DU DU/RESET#
RP92 87 88
DDRA_DQ28 DDRA_DQ29 VSS VSS
1 4 4 1 89 CK2 VSS 90
DDRA_DM3 2 3 3 2 DDRA_DQS3 2 1 DDRB_SMA10 91 92
56_0402_5% R294 CK2# VDD
93 VDD VDD 94
56_0404_4P2R_5% RP93 2 1 DDRB_CKE1 DDRB_CKE1 95 96 DDRB_CKE0
56_0404_4P2R_5% 6 DDRB_CKE1 CKE1 CKE0 DDRB_CKE0 6
RP89 56_0402_5% R545 97 98
DDRA_DQ26 DDRA_DQ27 DDRB_CKE0 DDRB_SMA12 DU/A13 DU/BA2 DDRB_SMA11
1 4 4 1 2 1 99 A12 A11 100
DDRA_DQ31 2 3 3 2 DDRA_DQ30 56_0402_5% R136 DDRB_SMA9 101 102 DDRB_SMA8
A9 A8
103 VSS VSS 104
56_0404_4P2R_5% RP90 RP58 DDRB_SMA7 105 106 DDRB_SMA6
56_0404_4P2R_5% DDRA_DM6 DDRB_SMA5 A7 A6 DDRB_SMA4
RP25 4 1 107 108
DDRB_SMA11 DDRB_SMA12 DDRA_DQ55 DDRB_SMA3 A5 A4 DDRB_SMA2
1 4 4 1 3 2 109 A3 A2 110
DDRB_SMA8 2 3 3 2 DDRB_SMA9 DDRB_SMA1 111 112 DDRB_SMA0
56_0404_4P2R_5% A1 A0
113 VDD VDD 114
56_0404_4P2R_5% RP88 RP55 DDRB_SMA10 115 116 DDRB_SBS1
56_0404_4P2R_5% A10/AP BA1 DDRB_SBS1 8
RP23 4 1 DDRA_DQ51 DDRB_SBS0 117 118 DDRB_SRAS#
8 DDRB_SBS0 BA0 RAS# DDRB_SRAS# 8
DDRB_SMA6 1 4 4 1 DDRB_SMA7 3 2 DDRA_DQ61 DDRB_SWE# 119 120 DDRB_SCAS#
8 DDRB_SWE# WE# CAS# DDRB_SCAS# 8
DDRB_SMA4 2 3 3 2 DDRB_SMA5 DDRB_SCS#0 121 122 DDRB_SCS#1
6 DDRB_SCS#0 S0# S1# DDRB_SCS#1 6
56_0404_4P2R_5% DDRB_SMA13 123 124
56_0404_4P2R_5% RP85 DU DU
RP52 125 126
56_0404_4P2R_5% DDRA_DQ58 DDRA_DQ36 VSS VSS DDRA_DQ37
RP21 4 1 127 128
DDRB_SMA2 DDRB_SMA3 DDRA_DM7 DDRA_DQ33 DQ32 DQ36 DDRA_DQ32
1 4 4 1 3 2 129 DQ33 DQ37 130
DDRB_SMA0 2 3 3 2 DDRB_SMA1 131 132
56_0404_4P2R_5% DDRA_DQS4 VDD VDD DDRA_DM4
133 DQS4 DM4 134
56_0404_4P2R_5% RP83 RP49 DDRA_DQ38 135 136 DDRA_DQ39
56_0404_4P2R_5% DDRA_DQ63 DQ34 DQ38
RP19 4 1 137 138
DDRB_SBS1 DDRB_SBS0 DDRA_DQ59 DDRA_DQ35 VSS VSS DDRA_DQ34
1 4 4 1 3 2 139 DQ35 DQ39 140
DDRB_SRAS# 2 3 3 2 DDRB_SWE# DDRA_DQ41 141 142 DDRA_DQ45
B 56_0404_4P2R_5% DQ40 DQ44 B
143 VDD VDD 144
56_0404_4P2R_5% RP81 56_0404_4P2R_5% DDRA_DQ44 145 146 DDRA_DQ40
56_0404_4P2R_5% DDRA_DQS6 DDRA_DQS5 DQ41 DQ45 DDRA_DM5
RP17 4 1 147 148
DDRB_SCAS# DDRB_SCS#0 DDRA_DQ54 DQS5 DM5
1 4 4 1 3 2 149 VSS VSS 150
DDRB_SCS#1 2 3 3 2 DDRB_SMA13 DDRA_DQ46 151 152 DDRA_DQ42
RP59 DDRA_DQ47 DQ42 DQ46 DDRA_DQ43
153 DQ43 DQ47 154
56_0404_4P2R_5% RP79 56_0404_4P2R_5% 155 156
56_0404_4P2R_5% DDRA_DQ50 VDD VDD
RP76 4 1 157 158 DDRB_CLK2# 6
DDRA_DQ37 DDRA_DQ36 DDRA_DQ60 VDD CK1#
1 4 4 1 3 2 159 VSS CK1 160 DDRB_CLK2 6
DDRA_DQ32 2 3 3 2 DDRA_DQ33 161 162
RP56 DDRA_DQ52 VSS VSS DDRA_DQ49
163 DQ48 DQ52 164
56_0404_4P2R_5% RP78 56_0404_4P2R_5% DDRA_DQ53 165 166 DDRA_DQ48
56_0404_4P2R_5% DDRA_DQ56 DQ49 DQ53
RP73 4 1 167 168
DDRA_DM4 DDRA_DQS4 DDRA_DQS7 DDRA_DQS6 VDD VDD DDRA_DM6
1 4 4 1 3 2 169 DQS6 DM6 170
DDRA_DQ39 2 3 3 2 DDRA_DQ38 DDRA_DQ54 171 172 DDRA_DQ55
RP53 DQ50 DQ54
173 VSS VSS 174
56_0404_4P2R_5% RP75 56_0404_4P2R_5% DDRA_DQ50 175 176 DDRA_DQ51
56_0404_4P2R_5% DDRA_DQ57 DDRA_DQ60 DQ51 DQ55 DDRA_DQ61
RP70 4 1 177 178
DDRA_DQ34 DDRA_DQ35 DDRA_DQ62 DQ56 DQ60
1 4 4 1 3 2 179 VDD VDD 180
DDRA_DQ45 2 3 3 2 DDRA_DQ41 DDRA_DQ56 181 182 DDRA_DQ58
RP50 DDRA_DQS7 DQ57 DQ61 DDRA_DM7
183 DQS7 DM7 184
56_0404_4P2R_5% RP71 185 186
56_0404_4P2R_5% DDRA_DQ57 VSS VSS DDRA_DQ63
RP67 187 188
DDRA_DQ40 DDRA_DQ44 DDRA_DQ62 DQ58 DQ62 DDRA_DQ59
1 4 4 1 189 DQ59 DQ63 190
DDRA_DM5 2 3 3 2 DDRA_DQS5 191 192
D_CK_SDATA VDD VDD
11,14 D_CK_SDATA 193 SDA SA0 194 +3VS
56_0404_4P2R_5% RP68 D_CK_SCLK 195 196
56_0404_4P2R_5% 11,14 D_CK_SCLK SCL SA1
RP64 197 198
DDRA_DQ42 DDRA_DQ46 +3VS VDD_SPD SA2
1 4 4 1 199 VDD_ID DU 200
DDRA_DQ43 2 3 3 2 DDRA_DQ47

A 56_0404_4P2R_5% RP65 A
56_0404_4P2R_5% AMP_1565917-1
RP61
DDRA_DQ49 1 4 4 1 DDRA_DQ52
DDRA_DQ48 2 3 3 2 DDRA_DQ53

56_0404_4P2R_5% RP63

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR-SODIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 12 of 52
5 4 3 2 1
 A B C D E

Layout note :
Distribute as close as possible
to DDR-SODIMM.

1 1

+2.5V

1 1 1 1 1 1 1 1 1
C110 C119 C123 C216 C230 C248 C324 C680 C683
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2

+2.5V +2.5V

1 1 1 1 1 1
C705 C762 C783 C795 + +
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C684 C799
2 2 2 2 150U_D2_6.3VM 150U_D2_6.3VM
2 2

2
Layout note : 2
Place one cap close to every 2 pull up resistors termination to
+1.25V

+1.25VS

1 1 1 1 1 1 1 1
C737 C695 C697 C183 C191 C700 C703 C711
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2

+1.25VS

1 1 1 1 1 1 1 1
C717 C721 C724 C734 C741 C746 C203 C763
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2

3 +1.25VS 3

1 1 1 1 1 1 1 1
C767 C771 C780 C768 C798 C811 C816 C823
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2

+1.25VS

+1.25VS
1 1 1 1

1 1 1 1 1 1 1 1 C199 C685 C696 C698

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C701 C720 C723 C725 C731 C712 C744 C772 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2

+1.25VS

1 1 1 1 1 1 1 1
C782 C797 C808 C814 C818 C169 C174 C150
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR SODIMM Decoupling
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 13 of 52
A B C D E
 A B C D E F G H

change 0 ohm
L6
KC FBM-L11-201209-221LMAT_0805 40mil
+CLK_VDD1
Clock Generator
+CLK_VDD48 +CLK_VDDREF +3VS 1 2
FSC FSB FSA CPU SRC PCI 1
C117
1
C115
1 1 1 1 1 1

CLKSEL0 CLKSEL1 CLKSEL2 C118 C107 C116 C109 C105 C106

MHz MHz MHz 0.047U_0402_16V7K 2.2U_0603_6.3V6K 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K
2 2.2U_0603_6.3V6K 2 0.047U_0402_16V7K 2 2 2 2 2 2
1 0 1 100 100 33.3
1 1

0 0 1 133 100 33.3

0 1 1 166 100 33.3 +CLK_VCCA

+CLK_VDD1
1 2 +CLK_VDD1 change 0 ohm
40mil R88
U40 2.2_0402_5% L28 +CLK_VDD2
0 1 0 200 100 33.3 1 1
KC FBM-L11-201209-221LMAT_0805
+CLK_VDD2 40mil
21 VDDPCIEX_0 +3VS 1 2
28 37 C111 C108
VDDPCIEX_1 VDDA 2 2.2U_0603_6.3V6K 2 0.047U_0402_16V7K
34 VDDPCIEX_2 1 1 1
+3VS 38
GNDA
1 VDDPCI_0
7 C122 C124 C125
CLKSEL2 VDDPCI_1 STP_PCI# 2 2.2U_0603_6.3V6K 2 0.047U_0402_16V7K 2 0.047U_0402_16V7K
1 2 PCI/SRC_STOP# 55 PM_STP_PCI# 25
R499 10K_0402_5% +CLK_VDD1
54 STP_CPU#
CPU_STOP# PM_STP_CPU# 25,50
1 2 CLK_PCI0
R508 10K_0402_5% 42 VDDCPU
C716 Y6 1 2 +CLK_VDDREF 48 VDDREF
1 2 CLK_PCI2 33P_0402_50V8J 14.318MHZ_16PF_DSX840GA R100 1_0402_5% 15mil
R101 10K_0402_5% 1 2 41 CLK_CPU1 R479 1 2 33_0402_5% CLK_MCH_BCLK
CPUCLKT1 CLK_MCH_BCLK 6
1 2 +CLK_VDD48 11 VDD48
1 R99 2.2_0402_5% 15mil CPUCLKC1 40 CLK_CPU1# R472 1 2 33_0402_5% CLK_MCH_BCLK#
CLK_MCH_BCLK# 6
1 2 CLK_PCI1 CLK_MCH_BCLK 1 2
R502 10K_0402_5% C713 CLK_X1 50 R478 49.9_0402_1%
33P_0402_50V8J X1 CLK_MCH_BCLK# 1 2
2

1 2 CLK_X2 49 44 CLK_CPU0 R493 1 2 33_0402_5% CLK_CPU_BCLK R471 49.9_0402_1%

X2 CPUCLKT0 CLK_CPU_BCLK 4
CLK_ICH_48M R498 1 2 12_0402_5% CLK_CPU_BCLK 1 2
25 CLK_ICH_48M
43 CLK_CPU0# R489 1 2 33_0402_5% CLK_CPU_BCLK# R492 49.9_0402_1%
2 CPUCLKC0 CLK_CPU_BCLK# 4 2
CLK_SD_48M R497 1 5IN1@ 2 12_0402_5% CLKSEL2 12 CLK_CPU_BCLK# 1 2
31 CLK_SD_48M FS_A/USB_48MHz
R800 1 2 33_0402_5% CLKSEL0 53 R488 49.9_0402_1%
36 CLK_14M_CODEC REF1/FSLC/TEST_SEL
delete ITP clock
CLKSEL1 16 FSLB/TEST_MODE CPUCLKT2_ITP/PCIEXT6 36
delete ITP clock
CPUCLKC2_ITP/PCIEXC6 35
delete pci E clock for Lan
CLK_PCI_LAN 1 2 CLK_PCI5 5
29 CLK_PCI_LAN PCICLK5
R520 33_0402_5%
CLK_PCI_MINI 1 2 CLK_PCI4 4 33
34 CLK_PCI_MINI PCICLK4 PEREQ1#/PCIEXT5
R521 33_0402_5% CLK_PCIE_SATA 1 2
CLK_PCI_SIO 1 2 CLK_PCI3 3 32 R444 49.9_0402_1%
35 CLK_PCI_SIO PCICLK3 PEREQ2#/PCIEXC5
R522 33_0402_5% CLK_PCIE_SATA# 1 2
CLK_PCI_PCM 1 2 CLK_PCI2 56 R441 49.9_0402_1%
31 CLK_PCI_PCM PCICLK2/REQ_SEL
R515 33_0402_5% CLK_MCH_3GPLL 1
39 CLK_PCI_LPC
CLK_PCI_LPC 1 2 CLK_PCI1 9 SELPCIEX_LCDCLK#/PCICLK_F1
PCIEXT4 31
delete pci E clock for Lan R454
2
49.9_0402_1%
R501 33_0402_5% 30 CLK_MCH_3GPLL# 1 2
PCIEXC4 R446 49.9_0402_1%
CLK_PCIE_VGA 1 2
CLK_PCI_ICH 1 2 CLK_PCI0 8 26 CLK_SRC4 R443 1 2 33_0402_5% CLK_PCIE_SATA R464 49.9_0402_1%
23 CLK_PCI_ICH ITP_EN/PCICLK_F0 SATACLKT CLK_PCIE_SATA 24
R507 33_0402_5% CLK_PCIE_VGA# 1 2
D_CK_SCLK 46 27 CLK_SRC4# R440 1 2 33_0402_5% CLK_PCIE_SATA# R458 49.9_0402_1%
11,12 D_CK_SCLK SCLK SATACLKC CLK_PCIE_SATA# 24
CLK_PCIE_ICH 1 2
R477 49.9_0402_1%
D_CK_SDATA 47 24 CLK_SRC3 R453 1 2 33_0402_5% CLK_MCH_3GPLL CLK_PCIE_ICH# 1 2
11,12 D_CK_SDATA SDATA PCIEXT3 CLK_MCH_3GPLL 7
R469 49.9_0402_1%
25 CLK_SRC3# R445 1 2 33_0402_5% CLK_MCH_3GPLL# CLK_DREF_SSC 1 2
PCIEXC3 CLK_MCH_3GPLL# 7
1 2 CLKIREF 39 IREF
R487 49.9_0402_1%
R461 475_0402_1% 15mil CLK_DREF_SSC# 1 2
22 CLK_SRC2 R463 1 2 33_0402_5% CLK_PCIE_VGA R482 49.9_0402_1%
PCIEXT2 CLK_PCIE_VGA 15
3 CLK_DREF_96M 1 2 3
23 CLK_SRC2# R457 1 2 33_0402_5% CLK_PCIE_VGA# R496 49.9_0402_1%
+3VS PCIEXC2 CLK_PCIE_VGA# 15
CLK_DREF_96M# 1 2
R97 R491 49.9_0402_1%
4.7K_0402_5% 19 CLK_SRC1 R476 1 2 33_0402_5% CLK_PCIE_ICH
PCIEXT1 CLK_PCIE_ICH 25
2
G

1 2 +3VS
20 CLK_SRC1# R468 1 2 33_0402_5% CLK_PCIE_ICH#
PCIEXC1 CLK_PCIE_ICH# 25
1 3 D_CK_SCLK 13
25 CK_SCLK GND_0
D

Q5 29 17 CLK_SRC0 R486 1 2 33_0402_5% CLK_DREF_SSC

GND_1 LCDCLK_SS/PCIEX0T CLK_DREF_SSC 6
2N7002_SOT23
2 18 CLK_SRC0# R481 1 2 33_0402_5% CLK_DREF_SSC#
GND_2 LCDCLK_SS/PCIEX0C CLK_DREF_SSC# 6
45 GND_3
+3VS 14 CLK_DOT R495 1 2 33_0402_5% CLK_DREF_96M
DOTT_96MHz CLK_DREF_96M 6
R103 51 15 CLK_DOT# R490 1 2 33_0402_5% CLK_DREF_96M#
GND_4 DOTC_96MHz CLK_DREF_96M# 6
4.7K_0402_5%
2
G

1 2 +3VS 6 GND_5
1 3 D_CK_SDATA +3VS 1 2
25 CK_SDATA VGATE 6,25,50
R98 10K_0402_5%
D

2
Q7

G
2N7002_SOT23
10 VTT_POWERGD# 1 3
VTT_PWRGD#/PD

S
52 CLK_REF 1 2 CLK_14M_SIO Q6
+1.05VS +1.05VS REF0 CLK_14M_SIO 35
R500 12_0402_5% 2N7002_SOT23

ICS954226AGT_TSSOP56 1 2 CLK_ICH_14M
CLK_ICH_14M 25
2

R92 R91 R505 12_0402_5%

@ 1K_0402_5% @ 1K_0402_5%
4 4
R94 R85 R93 R95
4.7K_0402_5% 0_0402_5% 4.7K_0402_5% 0_0402_5%
1

CLKSEL0 1 2 1 2 CLKSEL1 1 2 1 2
MCH_CLKSEL0 6 MCH_CLKSEL1 6
1 2 2 1 CPU_BSEL0 5 1 2 2 1 CPU_BSEL1 5
R90 R86 R96 R89
@ 0_0402_5% 0_0402_5% @ 0_0402_5% 0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS1.0
SHEET NOR THE INFORMATION IT CONTAINS EAL30 LA-2691
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期四, 三月 03, 2005 Sheet 14 of 52
A B C D E F G H
 5 4 3 2 1

U6A
PCIE_MTX_C_GRX_P0 AH30 AJ5 VGA_GPIO0 1 2 +3VS General Straping (VGA Internal PD) 0:Disable, 1:Enable
PCIE_MTX_C_GRX_N0 PCIE_RX0P Part 1 of 5 GPIO0 VGA_GPIO1 R243 PM@ 10K_0402_5%
AG30 PCIE_RX0N GPIO1 AH5 1 2
PCIE_MTX_C_GRX_P1 AG29 AJ4 VGA_GPIO2 R244 1 @ 2 10K_0402_5% GPIO0 Full Transmitter Output Swing Power DEFAULT : 1
PCIE_MTX_C_GRX_N1 PCIE_RX1P GPIO2 VGA_GPIO3 R245 @ 10K_0402_5%
AF29 PCIE_RX1N GPIO3 AK4 1 2
PCIE_MTX_C_GRX_P2 AE29 AH4 VGA_GPIO4 R246 1 @ 2 10K_0402_5% GPIO1 Transmitter De-emphasis Enable DEFAULT : 0
PCIE_MTX_C_GRX_N2 PCIE_RX2P GPIO4 VGA_GPIO5 R247 @ 10K_0402_5%
AE30 PCIE_RX2N GPIO5 AF4 1 2
PCIE_MTX_C_GRX_P3 AD30 AJ3 VGA_GPIO6 R248 1 @ 2 10K_0402_5% GPIO(3:2) 00: PCI Express 1.0A mode DEFAULT : 00
PCIE_MTX_C_GRX_N3 PCIE_RX3P GPIO6 R249 @ 10K_0402_5%
AD29 PCIE_RX3N GPIO7 AK3 01: Kyrene-compatible mode
PCIE_MTX_C_GRX_P4 AC29 AH3
PCIE_MTX_C_GRX_N4 PCIE_RX4P GPIO8 10: PCI Express 1.0 mode
AB29 PCIE_RX4N GPIO9 AJ2
PCIE_MTX_C_GRX_P5 AB30 AH2 POWER_SEL(High 3.3V):VDDC=1.05V 11: PCI Express 1.0A mode and short-circuit internal
PCIE_MTX_C_GRX_N5 PCIE_RX5P GPIO10
AA30 PCIE_RX5N GPIO11 AH1 loopback mode (Rx connected directly to Tx of PHY)
7 PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_P6 AA29 AG3 (Low 0V ):VDDC=1.20V
PCIE_MTX_C_GRX_N6 PCIE_RX6P GPIO12
D Y29 PCIE_RX6N GPIO13 AG1 1 2 GPIO4 Transmitter Extra Current DEFAULT : 0 D
PCIE_MTX_C_GRX_P7 W29 AG2 R20 PM@ 10K_0402_5%
7 PCIE_GTX_C_MRX_P[0..15]
PCIE_MTX_C_GRX_N7 PCIE_RX7P GPIO14 POWER_SEL
PCI-E Lane Reversal Enable
W30 PCIE_RX7N GPIO_PWRCNTL AF3 POWER_SEL 47
PCIE_MTX_C_GRX_P8 V30 AF2
7 PCIE_MTX_C_GRX_N[0:15] PCIE_RX8P GPIO_MEMSSIN
PCIE_MTX_C_GRX_N8 V29 OSC_SPREAD GPIO5 Force chip to go to compliance state quickly DEFAULT : 0
PCIE_MTX_C_GRX_P9 PCIE_RX8N
U29 AE10

DVO / EXT TMDS / GPIO

7 PCIE_MTX_C_GRX_P[0:15]
PCIE_MTX_C_GRX_N9 PCIE_RX9P DVOMODE for test purposes
T29 PCIE_RX9N
PCIE_MTX_C_GRX_P10 T30 AH6 MEM_ID0 R250 1 2 @ 10K_0402_5% +3VS GPIO6 Reduced PLL bandwidth DEFAULT : 0
PCIE_MTX_C_GRX_N10 PCIE_RX10P DVPDATA_0 MEM_ID1 R251 1
R30 PCIE_RX10N DVPDATA_1 AJ6 2 @ 10K_0402_5%
PCIE_MTX_C_GRX_P11 R29 AK6 MEM_ID2 R252 1 2 @ 10K_0402_5%
PCIE_MTX_C_GRX_N11 PCIE_RX11P DVPDATA_2
P29 PCIE_RX11N DVPDATA_3 AH7
PCIE_MTX_C_GRX_P12 N29 AK7
PCIE_MTX_C_GRX_N12 PCIE_RX12P DVPDATA_4
N30 PCIE_RX12N DVPDATA_5 AJ7
PCIE_MTX_C_GRX_P13 M30 AH8
PCIE_MTX_C_GRX_N13 PCIE_RX13P DVPDATA_6
PCIE_MTX_C_GRX_P14
M29 PCIE_RX13N DVPDATA_7 AJ8 Vedio Memory Config. (VGA Internal PD) 1.8V only
L29 PCIE_RX14P DVPDATA_8 AH9
PCIE_MTX_C_GRX_N14 K29 AJ9 MEM_ID0 MEM_ID1 MEM_ID2 Size Vendor Chips
PCIE_MTX_C_GRX_P15 PCIE_RX14N DVPDATA_9
K30 PCIE_RX15P DVPDATA_10 AK9
PCIE_MTX_C_GRX_N15 J30 AH10 0 0 1 64MB 8Mx32 Samsung x2
PCIE_RX15N DVPDATA_11
DVPDATA_12 AE6
PCIE_GTX_C_MRX_P0 C666 PM@ 1 2 0.1U_0402_10V6K PCIE_GTX_MRX_P0 AF26 AG6 0 1 1 Default 128MB 8Mx32 Samsung x4
PCIE_GTX_C_MRX_N0 C665 PCIE_GTX_MRX_N0 PCIE_TX0P DVPDATA_13
1 2 PM@ 0.1U_0402_10V6K AE26 PCIE_TX0N DVPDATA_14 AF6
PCIE_GTX_C_MRX_P1 C644 PM@ 1 2 0.1U_0402_10V6K PCIE_GTX_MRX_P1 AC25 AE7 1 0 1 64MB 8Mx32 Hynix x2
PCIE_GTX_C_MRX_N1 C643 PCIE_GTX_MRX_N1 PCIE_TX1P DPVDATA_15
1 2 PM@ 0.1U_0402_10V6K AB25 AF7

PCI EXPRESS
PCIE_GTX_C_MRX_P2 C664 PM@ 1 PCIE_GTX_MRX_P2 PCIE_TX1N DVPDATA_16
2 0.1U_0402_10V6K AC27 PCIE_TX2P DVPDATA_17 AE8 R2531 PM@ 2 4.7K_0402_5% +3VS 1 1 1 128MB 8Mx32 Hynix x4
PCIE_GTX_C_MRX_N2 C663 1 2 PM@ 0.1U_0402_10V6K PCIE_GTX_MRX_N2 AB27 AG8
PCIE_GTX_C_MRX_P3 C642 PM@ 1 PCIE_GTX_MRX_P3 PCIE_TX2N DVPDATA_18 VGA_LCD_DATA 21
2 0.1U_0402_10V6K AC26 PCIE_TX3P DVPDATA_19 AF8 VGA_LCD_CLK 21 0 0 0 32MB 4Mx32 Samsung x2
PCIE_GTX_C_MRX_N3 C641 1 2 PM@ 0.1U_0402_10V6K PCIE_GTX_MRX_N3 AB26 AE9
PCIE_GTX_C_MRX_P4 C662 PM@ 1 PCIE_GTX_MRX_P4 PCIE_TX3N DVPDATA_20
2 0.1U_0402_10V6K Y25 PCIE_TX4P DVPDATA_21 AF9 R2541 PM@ 2 4.7K_0402_5% +3VS 0 1 0 64MB 4Mx32 Samsung x4
PCIE_GTX_C_MRX_N4 C661 1 2 PM@ 0.1U_0402_10V6K PCIE_GTX_MRX_N4 W25 AG10 R2551 2@ 10K_0402_5%
PCIE_GTX_C_MRX_P5 C640 PM@ 1 PCIE_GTX_MRX_P5 PCIE_TX4N DVPDATA_22
2 0.1U_0402_10V6K Y27 PCIE_TX5P DVPDATA_23 AF10 RESRRVED FOR M24 TEST 1 0 0 32MB 4Mx32 Hynix x2
PCIE_GTX_C_MRX_N5 C639 1 2 PM@ 0.1U_0402_10V6K PCIE_GTX_MRX_N5 W27
C PCIE_GTX_C_MRX_P6 C660 PM@ 1 PCIE_GTX_MRX_P6 PCIE_TX5N C
2 0.1U_0402_10V6K Y26 PCIE_TX6P DVPCNTL_0 AJ10 1 8 +3VS 1 1 0 64MB 4Mx32 Hynix x4
PCIE_GTX_C_MRX_N6 C659 1 2 PM@ 0.1U_0402_10V6K PCIE_GTX_MRX_N6 W26 AK10 2 7
PCIE_GTX_C_MRX_P7 C638 PM@ 1 PCIE_GTX_MRX_P7 PCIE_TX6N DVPCNTL_1
2 0.1U_0402_10V6K U25 PCIE_TX7P DVPCNTL_2 AJ11 3 6
PCIE_GTX_C_MRX_N7 C637 1 2 PM@ 0.1U_0402_10V6K PCIE_GTX_MRX_N7 T25 AH11 4 5
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
C658 PM@ 1 2 0.1U_0402_10V6K PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8
U27
PCIE_TX7N
PCIE_TX8P
DVPCNTL_3
+VREFG
RP36 10K_0804_8P4R_5% M22 Core speed MAX 300MHz
C657 1 2 PM@ 0.1U_0402_10V6K T27 AG4 PM@
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
C636 PM@ 1 2 0.1U_0402_10V6K PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N9
U26
PCIE_TX8N
PCIE_TX9P
VREFG
(15mils) M24 Core speed MAX 400MHz
C635 1 2 PM@ 0.1U_0402_10V6K T26 AH15
PCIE_TX9N TXOUT_L0N VGA_TXOUT0- 21
PCIE_GTX_C_MRX_P10 C656 PM@ 1 2 0.1U_0402_10V6K PCIE_GTX_MRX_P10 P25 AH16 Place +VREFG divider Res
PCIE_TX10P TXOUT_L0P VGA_TXOUT0+ 21
PCIE_GTX_C_MRX_N10 C655 1 2 PM@ 0.1U_0402_10V6K PCIE_GTX_MRX_N10 N25 AJ16
PCIE_GTX_C_MRX_P11 PCIE_GTX_MRX_P11 PCIE_TX10N TXOUT_L1N VGA_TXOUT1- 21 and decoupling Cap close
C634 PM@ 1 2 0.1U_0402_10V6K P27 AJ17
PCIE_TX11P TXOUT_L1P VGA_TXOUT1+ 21 to Ball AG4
PCIE_GTX_C_MRX_N11 C633 1 2 PM@ 0.1U_0402_10V6K PCIE_GTX_MRX_N11 N27 AJ18
PCIE_TX11N TXOUT_L2N VGA_TXOUT2- 21
PCIE_GTX_C_MRX_P12 C654 PM@ 1 2 0.1U_0402_10V6K PCIE_GTX_MRX_P12 P26 AK18
PCIE_TX12P TXOUT_L2P VGA_TXOUT2+ 21
PCIE_GTX_C_MRX_N12 C653 1 2 PM@ 0.1U_0402_10V6K PCIE_GTX_MRX_N12 N26 AJ20 1 R256 2
PCIE_GTX_C_MRX_P13 C646 PM@ 1 2 0.1U_0402_10V6K PCIE_GTX_MRX_P13 L25
PCIE_TX12N
PCIE_TX13P
TXOUT_L3N
TXOUT_L3P AJ21
+3VS
1K_0402_1% ATI suggest 100 ohm
PCIE_GTX_C_MRX_N13 C645 1 2 PM@ 0.1U_0402_10V6K PCIE_GTX_MRX_N13 K25 AK19
PCIE_GTX_C_MRX_P14 C652 PM@ 1 2 0.1U_0402_10V6K PCIE_GTX_MRX_P14 L27
PCIE_TX13N
PCIE_TX14P
TXCLK_LN
TXCLK_LP AJ19
VGA_TXCLK- 21
VGA_TXCLK+ 21
+VREFG
PM@
Current Value same as EAT10
PCIE_GTX_C_MRX_N14 C651 1 2 PM@ 0.1U_0402_10V6K PCIE_GTX_MRX_N14 K27 AG16
PCIE_TX14N TXOUT_U0N VGA_TZOUT0- 21

1
0.1U_0402_16V4Z
PCIE_GTX_C_MRX_P15 C632 PM@ 1 2 0.1U_0402_10V6K PCIE_GTX_MRX_P15 L26 AG17 1 R257

LVDS
PCIE_TX15P TXOUT_U0P VGA_TZOUT0+ 21

1K_0402_1%
PCIE_GTX_C_MRX_N15 C631 1 2 PM@ 0.1U_0402_10V6K PCIE_GTX_MRX_N15 K26 AF16 C360
PCIE_TX15N TXOUT_U1N VGA_TZOUT1- 21
AF17 PM@
+3VS TXOUT_U1P VGA_TZOUT1+ 21
CLK_PCIE_VGA AF27 AE18 PM@
14 CLK_PCIE_VGA PCIE_REFCLKP TXOUT_U2N VGA_TZOUT2- 21 2
CLK_PCIE_VGA# AE27 AE19
14 CLK_PCIE_VGA# VGA_TZOUT2+ 21

2
PCIE_REFCLKN TXOUT_U2P
TXOUT_U3N AF19
R258 1 PM@ 2 150_0402_1% AC23 AF20
PCIE_CALRP TXOUT_U3P
1

+1.2VS R259 1 PM@ 2 100_0402_1% AB24 AG19

PCIE_CALRN TXCLK_UN VGA_TZCLK- 21
PM@ R262 2 PM@ 1 10K_0402_1% AB23 AG20
PCIE_CALI TXCLK_UP VGA_TZCLK+ 21
R260 R261
100K_0402_5% 100K_0402_5% +3VS R263 1 2 10K_0402_5% AE25 AE12 ENVDD
PCIE_TESTIN DIGON ENVDD 21 +3VS
PM@ @ AG12 PM@
ENBKL 7,39 C361
2

R_PLTRST_VGA# BLON
AD25 PWRGD
B Q29 1 PM@ 2 AD24 AK13 R265 1 2 10K_0402_5% 2 1 B
PWRGD_MASK TX0M
1

D R264 1K_0402_5% PM@

TX0P AJ13 Spread spectrum

1
2 2N7002_SOT23 2 PM@ 1 AH21 AJ14
Q30 G PM@ R266 715_0402_1% R2SET TX1M 0.1U_0402_16V4ZL19
TX1P AJ15
1

R268 D VGA_TV_LUMA VGA_CRT_R

S 22 VGA_TV_LUMA AK21 AK15 1 PM@ 2 CHB1608U301_0603
3

VGA_TV_CRMA Y_G TX2M R267 150_0402_1%

25 PLTRST_VGA# 1 2 2 22 VGA_TV_CRMA AJ22 C_R_PR TX2P AK16 PM@
PM@ 0_0402_5% G 1 PM@ 2 VGA_COMPS AK22 AJ12 VGA_CRT_G 1 PM@ 2 PM@
COMP_B_PB TXCM C865
R269 75_0402_5% R270 150_0402_1% U22
TMDS

S AK12
3

2
DAC2

R272 TXCP VGA_CRT_B OSC_IN

AJ24 H2SYNC 1 PM@ 2 2 1 7 VDD REF 5
8,31,35,39 PLT_RST# 1 2 2N7002_SOT23 150_0402_1%2 PM@ 1 R273 VGA_TV_LUMA AK24 AE13 R271 150_0402_1%
@ 0_0402_5% PM@ VGA_TV_CRMA V2SYNC DDC2CLK 10U_0805_10V4Z PM@ 2 OSC_SPREAD
2 1 DDC2DATA AE14 1 XIN MODOUT 4 1
150_0402_1% PM@ R274 AG22 AF12 R275 22_0402_5%
DDC3CLK HPD1
AG23 DDC3DATA 8 XOUT NC 3 2 1
AK27 VGA_CRT_R R276 @ 10K_0402_5%
R VGA_CRT_R 22
2 1 AJ23 AJ27 VGA_CRT_G 2 6 2 1
CLK SS

SSIN G VGA_CRT_G 22 VSS PD#

10K_0402_5% R277 AH24 AJ26 VGA_CRT_B R278 @ 10K_0402_5%
VGA_CRT_B 22
THERM DAC1

R79 SSOUT B ASM3P1819N-SR_SO8

PM@ HSYNC AJ25 VGA_CRT_HSYNC 22
OSC_IN 1 2 XTALIN AH28 AK25 PM@
XTALIN VSYNC VGA_CRT_VSYNC 22
121_0603_1% AJ29 XTALOUT
PM@
RSET AH26 DAC_RSET R279 1 PM@ 2 499_0402_1%
1

2 PM@ 1 AH27 AG25

R71 R280 1K_0402_5% TESTEN DDC1DATA VGA_DDC_DATA 22 Y1 PM@
E8 TEST_YCLK DDC1CLK AF24 VGA_DDC_CLK 22
PM@ B6 AG24 4 3
71.5_0402_1% TEST_MCLK GPIO_AUXWIN R2812 GND OUT
AF25 PLLTEST 1 10K_0402_5%
AF11 PM@ If GPIO_AUXWIN not used, 1 2 1
2

DPLUS pulled it to GND. IN GND

2 1 AH25 STEREOSYNC DMINUS AE11 1
R282PM@ 10K_0402_5% 27MHz_16PF_6P27000126 C383
M24P_BGA708 M24@ C385 16P_0603_50V8J
16P_0603_50V8J 2 PM@
Voltage divider 2 PM@
Reduce Voltage from 3.3V to 1.2V
A Keep away from other signal at last 25mils A
+3VS 4.7K_0402_5% 2 PM@ 1 R805 VGA_DDC_DATA

+3VS 4.7K_0402_5% 2 PM@ 1 R806 VGA_DDC_CLK

Reserve for M26 test

+3VS
Security Classification Compal Secret Data Compal Electronics, Inc.
VGA_CRT_VSYNC
2 1 2005/03/01 2006/03/01 Title
R283 @ 10K_0402_5%
Issued Date Deciphered Date
M22P/24P PCIE,LVDS,GPIO,CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom EAL30 LA-2691 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期四, 三月 03, 2005 Sheet 15 of 52
5 4 3 2 1
 5 4 3 2 1

MDA[0..63] MDB[0..63] +1.8VS

MDA[0..63] 19 MDB[0..63] 20
MEMVMODE0 MEMVMODE1
DQSA[0..7] DQSB[0..7]
D DQSA[0..7] 19 DQSB[0..7] 20 D

DQMA#[0..7] DQMB#[0..7] Default R405

DQMA#[0..7] 19 DQMB#[0..7] 20 M22/24(1.8V VRAM) Pull-low Pull-high
MEMVMODE1 PM@ 1 2
MAA[0..13]
MAA[0..13] 19
MAB[0..13]
MAB[0..13] 20
Memory speed MAX200MHz 4.7K_0402_5%
M26(1.8V VRAM) NC NC R403
MEMVMODE0 PM@ 2 1
4.7K_0402_5%

U6B
MDA0 H28 E22 MAA0 U6C
MDA1 DQA0 Part 2 of 5 MAA0 MAA1 MDB0 MAB0
H29 DQA1 MAA1 B22 D7 DQB0 MAB0 N5
MDA2 J28 B23 MAA2 MDB1 F7 Part 3 of 5 M1 MAB1
MDA3 DQA2 MAA2 MAA3 MDB2 DQB1 MAB1 MAB2
J29 DQA3 MAA3 B24 E7 DQB2 MAB2 M3
MDA4 J26 C23 MAA4 MDB3 G6 L3 MAB3
MDA5 DQA4 MAA4 MAA5 MDB4 DQB3 MAB3 MAB4
H25 DQA5 MAA5 C22 G5 DQB4 MAB4 L2
MDA6 H26 F22 MAA6 MDB5 F5 M2 MAB5
MDA7 DQA6 MAA6 MAA7 MDB6 DQB5 MAB5 MAB6
G26 DQA7 MAA7 F21 E5 DQB6 MAB6 M5
MDA8 G30 C21 MAA8 MDB7 C4 P6 MAB7
MDA9 DQA8 MAA8 MAA9 MDB8 DQB7 MAB7 MAB8
D29 DQA9 MAA9 A24 B5 DQB8 MAB8 N3
MDA10 D28 C24 MAA10 MDB9 C5 K2 MAB9
MDA11 DQA10 MAA10 MAA11 MDB10 DQB9 MAB9 MAB10
E28 DQA11 MAA11 A25 A4 DQB10 MAB10 K3
MDA12 E29 E21 MAA12 MDB11 B4 J2 MAB11
MDA13 DQA12 MAA12 MAA13 MDB12 DQB11 MAB11 MAB12
G29 DQA13 MAA13 B20 C2 DQB12 MAB12 P5
MDA14 G28 C19 MDB13 D3 P3 MAB13
MDA15 DQA14 MAA14 MDB14 DQB13 MAB13
F28 DQA15 D1 DQB14 MAB14 P2
MDA16 G25 J25 DQMA#0 MDB15 D2
MDA17 DQA16 DQMA#0 DQMA#1 MDB16 DQB15 DQMB#0
F26 DQA17 DQMA#1 F29 G4 DQB16 DQMB#0 E6
MDA18 E26 E25 DQMA#2 MDB17 H6 B2 DQMB#1
C MDA19 DQA18 DQMA#2 DQMA#3 MDB18 DQB17 DQMB#1 DQMB#2 C
F25 DQA19 DQMA#3 A27 H5 DQB18 DQMB#2 J5
MDA20 E24 F15 DQMA#4 MDB19 J6 G3 DQMB#3
MDA21 DQA20 DQMA#4 DQMA#5 MDB20 DQB19 DQMB#3 DQMB#4
F23 DQA21 DQMA#5 C15 K5 DQB20 DQMB#4 W6
MDA22 E23 C11 DQMA#6 MDB21 K4 W2 DQMB#5
MDA23 DQA22 DQMA#6 DQMA#7 MDB22 DQB21 DQMB#5 DQMB#6
D22 DQA23 DQMA#7 E11 L6 DQB22 DQMB#6 AC6
MDA24 B29 MDB23 L5 AD2 DQMB#7
MDA25 DQA24 DQSA0 MDB24 DQB23 DQMB#7
C29 DQA25 QSA0 J27 G2 DQB24
MDA26 C25 F30 DQSA1 MDB25 F3 F6 DQSB0
MDA27 DQA26 QSA1 DQSA2 MDB26 DQB25 QSB0 DQSB1
C27 DQA27 QSA2 F24 H2 DQB26 QSB1 B3
MEMORY INTERFACE A

MDA28 B28 B27 DQSA3 MDB27 E2 K6 DQSB2

DQA28 QSA3 DQB27 QSB2

MEMORY INTERFACE B
MDA29 B25 E16 DQSA4 MDB28 F2 G1 DQSB3
MDA30 DQA29 QSA4 DQSA5 MDB29 DQB28 QSB3 DQSB4
C26 DQA30 QSA5 B16 J3 DQB29 QSB4 V5
MDA31 B26 B11 DQSA6 MDB30 F1 W1 DQSB5
MDA32 DQA31 QSA6 DQSA7 MDB31 DQB30 QSB5 DQSB6
F17 DQA32 QSA7 F10 H3 DQB31 QSB6 AC5
MDA33 E17 MDB32 U6 AD1 DQSB7
MDA34 DQA33 MRASA# MDB33 DQB32 QSB7
D16 DQA34 RASA# A19 MRASA# 19 U5 DQB33
MDA35 F16 MDB34 U3 R2 MRASB#
DQA35 DQB34 RASB# MRASB# 20
MDA36 E15 E18 MCASA# MDB35 V6
DQA36 CASA# MCASA# 19 DQB35
MDA37 F14 MDB36 W5 T5 MCASB#
DQA37 DQB36 CASB# MCASB# 20
MDA38 E14 E19 MWEA# MDB37 W4
DQA38 WEA# MWEA# 19 DQB37
MDA39 F13 MDB38 Y6 T6 MWEB#
DQA39 DQB38 WEB# MWEB# 20
MDA40 C17 E20 MCSA0# MDB39 Y5
DQA40 CSA0# MCSA0# 19 DQB39
MDA41 B18 MDB40 U2 R5 MCSB0#
DQA41 DQB40 CSB0# MCSB0# 20
MDA42 B17 F20 MDB41 V2
MDA43 DQA42 CSA1# MDB42 DQB41
B15 DQA43 V1 DQB42 CSB1# R6
MDA44 C13 B19 MCKEA MDB43 V3
DQA44 CKEA MCKEA 19 DQB43
MDA45 B14 MDB44 W3 R3 MCKEB
DQA45 DQB44 CKEB MCKEB 20
MDA46 C14 MDB45 Y2
MDA47 DQA46 MCLKA0 MDB46 DQB45 MCLKB0
C16 DQA47 CLKA0 B21 MCLKA0 19 Y3 DQB46 CLKB0 N1 MCLKB0 20
MDA48 A13 C20 MCLKA0# MDB47 AA2 N2 MCLKB0#
DQA48 CLKA0# MCLKA0# 19 DQB47 CLKB0# MCLKB0# 20
MDA49 A12 MDB48 AA6
B MDA50 DQA49 MCLKA1 MDB49 DQB48 MCLKB1 B
C12 DQA50 CLKA1 C18 MCLKA1 19 AA5 DQB49 CLKB1 T2 MCLKB1 20
MDA51 B12 A18 MCLKA1# MDB50 AB6 T3 MCLKB1#
DQA51 CLKA1# MCLKA1# 19 DQB50 CLKB1# MCLKB1# 20
MDA52 C10 MDB51 AB5
MDA53 DQA52 MDB52 DQB51
C9 DQA53 AD6 DQB52
MDA54 B9 MDB53 AD5 E3
MDA55 DQA54 +MVREFD (15mils) MDB54 DQB53 DIMB_0
B10 DQA55 MVREFD B7 AE5 DQB54 DIMB_1 AA3
MDA56 E13 MDB55 AE4
MDA57 DQA56 +MVREFS (15mils) MDB56 DQB55
E12 DQA57 MVREFS B8 AB2 DQB56
MDA58 E10 MDB57 AB3 AF5
MDA59 DQA58 MDB58 DQB57 ROMCS#
F12 DQA59 AC2 DQB58
MDA60 F11 D30 MDB59 AC3 C6 MEMVMODE0
MDA61 DQA60 DIMA_0 MDB60 DQB59 MEMVMODE_0 MEMVMODE1
E9 DQA61 DIMA_1 B13 AD3 DQB60 MEMVMODE_1 C7
MDA62 F9 MDB61 AE1 PM@
MDA63 DQA62 MDB62 DQB61 MEMTEST R409 1
F8 DQA63 AE2 DQB62 MEMTEST C8 2
MDB63 AE3 (15mil) 47_0402_1%
M24P_BGA708 +1.8VS +1.8VS DQB63
M24@ M24P_BGA708
M24@
1

PM@ PM@ R408 change to 240 ohm when use M26

R410 100_0402_1%
100_0402_1%
2

+MVREFS +MVREFD
(15mils) (15mils)
1

1 1
R404
PM@ C528 PM@ C500 PM@ 100_0402_1%
0.1U_0402_16V4Z PM@ R413 0.1U_0402_16V4Z
2 100_0402_1% 2
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
M22P/24P Memory Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS EAL30 LA-2691 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期四, 三月 03, 2005 Sheet 16 of 52
5 4 3 2 1
 5 4 3 2 1

+1.8VS +1.8VS +VGA_CORE +VGA_CORE

PM@ C838 C599 C598 U6D 7500mA C557 C558 C534
1 2 1 2PM@ PM@1 2
400mA T7 AC13 1 2PM@ 1 2PM@ 1 2 PM@
VDDR1_0 Part 4 of 5 VDDC_0
R4 VDDR1_1 VDDC_1 AD13
22U_1206_10V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K R1 AD15 22U_1206_10V4Z 22U_1206_10V4Z 1000P_0402_50V7K
PM@ C313 C362 C363 VDDR1_2 VDDC_2 C314 C312 C315 +VGA_CORE
ATi suggestion: N8 VDDR1_3 VDDC_3 AC15
1 2 1 2PM@ PM@1 2 N7 AC17 1 2PM@ 1 2PM@ 1 2 PM@
Using filter is acceptable (Default) M4
VDDR1_4 VDDC_4
P17
22U_1206_10V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K VDDR1_5 VDDC_5 22U_1206_10V4Z 22U_1206_10V4Z 1000P_0402_50V7K
Using liner regulator is optimal. (Reserve) L8 VDDR1_6 VDDC_6 P18
PM@ C834 C597 C508 K23 P19 C562 C566 C538 1 1
VDDR1_7 VDDC_7
1 2 1 2PM@ PM@1 2 K24 VDDR1_8 VDDC_8 U12 1 2PM@ 1 2PM@ 1 2 PM@
U24 +VDD_PNLIO2.5 N4 U13 C836 + + C456
D VDDR1_9 VDDC_9 D
22U_1206_10V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K J8 U14 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K 330U_D_2VM 470U_D2_2.5VM
PM@ C467 C502 C496 VDDR1_10 VDDC_10 C545 C550 C531 PM@ @
+3VS 1 VIN VOUT 5 J7 VDDR1_11 VDDC_11 U17
2 2
1 2 1 2PM@ PM@1 2 J4 VDDR1_12 VDDC_12 U18 1 2PM@ 1 2PM@ 1 2 PM@
4 PG J1 VDDR1_13 VDDC_13 U19
22U_1206_10V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K H10 V19 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K
C843 C601 C593 VDDR1_14 VDDC_14 C533 C536 C574
1 3 EN GND 2 PM@ H13 VDDR1_15 VDDC_15 V18
2 1 1 2PM@ PM@1 2 H15 V17 1 2PM@ 1 2PM@ 1 2 PM@
C317 H17
VDDR1_16
VDDR1_17
VDDC_16
VDDC_17 V14 Reserve
@ 470P_0402_50V7K @ MIC5205-2.8BM5_SOT23-5~D 10U_0805_10V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K T8 V13 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K
2 C847 C600 C604 VDDR1_18 VDDC_18 C521 C537
PM@ V4 VDDR1_19 VDDC_19 V12
2 1 1 2PM@ PM@1 2 V7 VDDR1_20 VDDC_20 N18 1 2PM@ 1 2PM@
SA052050010(MIC5205-2.8BM5), max:150mA V8 VDDR1_21 VDDC_21 N17
10U_0805_10V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K AA1 N14 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C848 C605 C613 VDDR1_22 VDDC_22 C532 C573
AA4 VDDR1_23 VDDC_23 W17
PM@ 2 1 1 2PM@ PM@1 2 AA7 W18 1 2PM@ 1 2PM@
VDDR1_24 VDDC_24

+
AA8 VDDR1_25 VDDC_25 W12
220U_D2_4VM_R12 0.1U_0402_16V4Z 1000P_0402_50V7K A3 W13 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C505 C497 VDDR1_26 VDDC_26 C590 C589
A9 VDDR1_27 VDDC_27 W14
1 2PM@ PM@1 2 A15 VDDR1_28 VDDC_28 N13 1 2PM@ 1 2PM@
+VDD_PNLIO2.5 A21 N19
0.1U_0402_16V4Z 1000P_0402_50V7K VDDR1_29 VDDC_29 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A28 VDDR1_30 VDDC_30 M19
C547 C555 B1 M18 C580 C588
R296 2 VDDR1_31 VDDC_31
+2.5VS 1 1 2PM@ PM@1 2 B30 VDDR1_32 VDDC_32 M12 1 2PM@ 1 2PM@
0.1U_0402_16V4Z

0_0603_5% D26 N12

PM@ 0.1U_0402_16V4Z 1000P_0402_50V7K VDDR1_33 VDDC_33 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 1 1 D23 VDDR1_34 VDDC_34 M13
C835 C837 C839 C592 C577 D20 M14 C579 C587
PM@ PM@ PM@ VDDR1_35 VDDC_35
1 2PM@ PM@1 2 D17 VDDR1_36 VDDC_36 P12 1 2PM@ 1 2PM@
10U_0805_10V4Z D14 P13
1 2 2 0.1U_0402_16V4Z 1000P_0402_50V7K VDDR1_37 VDDC_37 0.1U_0402_16V4Z 0.1U_0402_16V4Z
D11 VDDR1_38 VDDC_38 P14
0.1U_0402_16V4Z C507 C495 D8 M17 C556 C561
VDDR1_39 VDDC_39
1 2PM@ PM@1 2 D5 VDDR1_40 VDDC_40 W19 1 2PM@ 1 2PM@
C 0.1U_0402_16V4Z 0.1U_0402_16V4Z C
E27 VDDR1_41
1000P_0402_50V7K 1000P_0402_50V7K F4
C565 C490 VDDR1_42 500mA 0.1U_0402_16V4Z 10U_0805_10V4Z
G7 VDDR1_43 VDDC1_0 W16
+VDD_DAC2.5 1 2PM@ PM@1 2 G10 M15
VDDR1_44 VDDC1_1 1 1 1 1 2 2
G13 R19 C530 C553 C516 C529 C567 C522
R600 2 1000P_0402_50V7K 1000P_0402_50V7K VDDR1_45 VDDC1_2 PM@ PM@ PM@ PM@ PM@ PM@
1 G15 VDDR1_46 VDDC1_3 T12
0.1U_0402_16V4Z

0_0603_5% C552 C620 G19 0.1U_0402_16V4Z

PM@ VDDR1_47 2 2 2 2 1 1
1 1 1 2PM@ PM@1 2 G22 VDDR1_48
C841 C845 G27 P8 50mA 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z
PM@ PM@ 1000P_0402_50V7K 1000P_0402_50V7K VDDR1_49 VDD15_0
H22 VDDR1_50 VDD15_1 Y8
C619 C615 H19 AC11 0.1U_0402_16V4Z 0.1U_0402_16V4Z +1.5VS
2 2 VDDR1_51 VDD15_2
1 2PM@ PM@1 2 AD4 VDDR1_52 VDD15_3 AC20 1 1 1 1 2
0.1U_0402_16V4Z L23 H20 C535 C511 C606 C576 C842
1000P_0402_50V7K 1000P_0402_50V7K VDDR1_53 VDD15_4 PM@ PM@ PM@ PM@ PM@
VDD15_5 H11
M23 0.1U_0402_16V4Z 10U_0805_10V4Z
VDD15_6 2 2 2 2 1
VDD15_7 Y23

POWER
0.1U_0402_16V4Z

AD7
50mA 1000P_0402_50V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VDDR3_0 +3VS
+VDD_PNLIO2.5 200mA AE16 AD19 1 1 1 1 1 1 1 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z LVDDR_25_0 VDDR3_1 C501 C509 C525 C498 C568 C571 C572 C846
+1.8VS AE17 LVDDR_25_1 VDDR3_2 AD21
AF15 AC22 PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
60mA LVDDR_18_0 VDDR3_3 10U_0805_10V4Z
1 1 1 +1.8VS AE15 LVDDR_18_1 VDDR3_4 AC8
C486 C504 C527 2 2 2 2 2 2 2 1
VDDR3_5 AC21
AC19 1000P_0402_50V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
15mA AH19 VDDR3_6
2 2 2 +VDD_PLL2_1.8 LPVDD
PM@ PM@ PM@ AH13 TPVDD
VDDR4_0 AG7
0.1U_0402_16V4Z 0.1U_0402_16V4Z AF13 AD9 +1.2VS
+1.8VS TXVDDR_0 VDDR4_1
1 1 AF14 TXVDDR_1 VDDR4_2 AC9
+AVDD1.8 C487 C489 AC10 0.1U_0402_16V4Z 0.1U_0402_16V4Z
B PM@ PM@ VDDR4_3 B
VDDR4_4 AD10 1 1 1 1 2 1
+1.8VS 1 R601 2 400mA F18 C596 C614 C629 C647 C648
2 2 VDDRH0
0.1U_0402_16V4Z

0_0603_5% N6 PM@ PM@ PM@ PM@ PM@ C630 PM@

PM@ 0.1U_0402_16V4Z VDDRH1
AG26
1100mA 22U_1206_10V4Z
1 1 PCIE_VDDR_12_0 2 2 2 2 1 2
C840 C844 AK29
PM@ PM@ 120mA AF21 PCIE_VDDR_12_1 0.1U_0402_16V4Z 10U_0805_10V4Z
+VDD_DAC2.5 A2VDD_0 PCIE_VDDR_12_2 AJ30
0.1U_0402_16V4Z 5mA AE20 AG28 1000P_0402_50V7K
2 2 A2VDD_1 PCIE_VDDR_12_3
PCIE_VDDR_12_4 AG27
AF23 A2VDDQ

+AVDD1.8 70mA AH23 N24 0.1U_0402_16V4Z

AVDD PCIE_PVDD_12_0 100mA
PCIE_PVDD_12_1 N23 1 1 1 2
+VDD_PLL1.8 P23 C650 C92 C98
10mA PCIE_PVDD_12_2 PM@ PM@ PM@ PM@ C99
+1.8VS AE23 VDD1DI
+1.8VS 1 R29 2 AE22 10U_0805_10V4Z
VDD2DI 2 2 2 1
0.1U_0402_16V4Z

0_0603_5% U23
PM@ PCIE_PVDD_18_0 1000P_0402_50V7K 0.1U_0402_16V4Z
1 1 PCIE_PVDD_18_1 T23
C28 C31 +VDD_PLL2_1.8 30mA AK28 V23
PM@ PM@ PVDD PCIE_PVDD_18_2
PCIE_PVDD_18_3 W23
0.1U_0402_16V4Z +VDD_PLL1.8 10mA A7
2 2 MPVDD
M24P_BGA708 500mA (20 mil) +1.8VS
M24@ 0.1U_0402_16V4Z
1 1 1 2
C526 C548 C546 C559
PM@ PM@ PM@ PM@
0.1U_0402_16V4Z 22U_1206_10V4Z
+VDD_PLL2_1.8 2 2 2 1
0.1U_0402_16V4Z
+1.8VS 1 R841 2
2.2_0603_5%
A PM@ 2 2 0.1U_0402_16V4Z A
1 1 1
22U_1206_10V4Z C859 PM@ C864 C549 C622 C863
PM@ PM@ PM@ PM@
1 1
2 2 2

10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M22P/24PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 17 of 52
5 4 3 2 1
 5 4 3 2 1

U6E
A2 VSS_0 PCIE_VSS_0 K28
D A10 Part 5 of 5 L28 D
VSS_1 PCIE_VSS_1
A16 VSS_2 PCIE_VSS_2 M27
A22 VSS_3 PCIE_VSS_3 M26
A29 VSS_4 PCIE_VSS_4 M24
C1 VSS_5 PCIE_VSS_5 M25
C3 VSS_6 PCIE_VSS_6 M28
C28 VSS_7 PCIE_VSS_7 P28
C30 VSS_8 PCIE_VSS_8 N28
D27 VSS_9 PCIE_VSS_9 R25
D24 VSS_10 PCIE_VSS_10 R23
D21 VSS_11 PCIE_VSS_11 R24
D18 VSS_12 PCIE_VSS_12 R26
D15 VSS_13 PCIE_VSS_13 R27
D12 VSS_14 PCIE_VSS_14 R28
D10 VSS_15 PCIE_VSS_15 T28
D6 VSS_16 PCIE_VSS_16 T24
D4 VSS_17 PCIE_VSS_17 U28
F27 VSS_18 PCIE_VSS_18 V24
G9 VSS_19 PCIE_VSS_19 V26
G12 VSS_20 PCIE_VSS_20 V27
G16 VSS_21 PCIE_VSS_21 V25
G18 VSS_22 PCIE_VSS_22 V28
G21 VSS_23 PCIE_VSS_23 Y28
G24 VSS_24 PCIE_VSS_24 W24
H27 VSS_25 PCIE_VSS_25 W28
H23 VSS_26 PCIE_VSS_26 AA26
H21 VSS_27 PCIE_VSS_27 AA27
H18 VSS_28 PCIE_VSS_28 AA23
H16 VSS_29 PCIE_VSS_29 AA24

GND
H14 VSS_30 PCIE_VSS_30 AA25
H12 VSS_31 PCIE_VSS_31 AA28
H9 VSS_32 PCIE_VSS_32 AB28
C C
H8 VSS_33 PCIE_VSS_33 AC28
H4 VSS_34 PCIE_VSS_34 AD28
J23 VSS_35 PCIE_VSS_35 AD26
J24 VSS_36 PCIE_VSS_36 AD27
AD12 VSS_37 PCIE_VSS_37 AE28
AG5 VSS_38 PCIE_VSS_38 AF28
AG9 VSS_39 PCIE_VSS_39 AH29
AG11 VSS_40
R7 VSS_41
P4 VSS_42 NC_0 D9
M7 VSS_43 NC_1 D13
M8 VSS_44 NC_2 D19
L4 VSS_45 NC_3 D25
K1 VSS_46 NC_4 E4
K7 VSS_47 NC_5 T4
K8 VSS_48 NC_6 AB4
R8 VSS_49
T1 VSS_50
U4 VSS_51
U8 VSS_52 AVSSQ AD22
W7 VSS_53
W8 VSS_54
Y4 VSS_55 LVSSR_0 AF18
AB8 VSS_56 LVSSR_1 AH17
AB7 VSS_57 LVSSR_2 AG15
AB1 VSS_58 LVSSR_3 AG18
AC4 VSS_59
AC12 VSS_60
AC14 VSS_61 LPVSS AH18
AD16 VSS_62 TPVSS AH12
AC16 VSS_63
B AC18 AH14 B
VSS_64 TXVSSR_0
AD18 VSS_65 TXVSSR_1 AG13
AK2 VSS_66 TXVSSR_2 AG14
AJ1 VSS_67
M16 VSS_68 VSSRH0 F19
N16 VSS_69 VSSRH1 M6
N15 VSS_70
P15 VSS_71
P16 VSS_72 A2VSSN_0 AH20
R18 VSS_73 A2VSSN_1 AG21
R17 VSS_74
R16 VSS_75 A2VSSQ AF22
R15 VSS_76
R14 VSS_77 AVSSN AH22
R13 VSS_78
R12 VSS_79
T13 VSS_80 VSS1DI AE24
T14 VSS_81 VSS2DI AE21
T15 VSS_82
W15 VSS_83
V16 VSS_84
V15 VSS_85 PVSS AJ28
U15 VSS_86
U16 VSS_87
T19 VSS_88 MPVSS A6
T18 VSS_89
T17 VSS_90
T16 VSS_91
M24P_BGA708

A M24@ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M22P/24P GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 18 of 52
5 4 3 2 1
 5 4 3 2 1

DQMA#[0..7]
16 DQMA#[0..7]
MAA[0..13]
16 MAA[0..13]

G10

G10
D10
D11

H10

D10
D11

H10
B11

K10

B11

K10
F10

F10
J10

J10
MDA[0..63]

G5

G5
D4
D5
D6
D9

H5

D4
D5
D6
D9

H5
B4

E6
E9

K5

B4

E6
E9

K5
F5

F5
J5

J5
16 MDA[0..63] U8 U5
DQSA[0..7]

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
D 16 DQSA[0..7] D

MAA0 N5 B7 MDA9 MAA0 N5 B7 MDA39

MAA1 A0 DQ0 MDA10 MAA1 A0 DQ0 MDA38
N6 A1 DQ1 C6 N6 A1 DQ1 C6
MAA2 M6 B6 MDA12 MAA2 M6 B6 MDA37
MAA3 A2 DQ2 MDA11 MAA3 A2 DQ2 MDA36
N7 A3 DQ3 B5 N7 A3 DQ3 B5
MAA4 N8 C2 MDA15 MAA4 N8 C2 MDA35
MAA5 A4 DQ4 MDA8 MAA5 A4 DQ4 MDA34
M9 A5 DQ5 D3 M9 A5 DQ5 D3
MAA6 N9 D2 MDA13 MAA6 N9 D2 MDA33
MAA7 A6 DQ6 MDA14 MAA7 A6 DQ6 MDA32
N10 A7 DQ7 E2 N10 A7 DQ7 E2
MAA8 N11 K13 MDA22 MAA8 N11 K13 MDA51
MAA9 A8/AP DQ8 MDA23 MAA9 A8/AP DQ8 MDA49
M8 A9 DQ9 K12 M8 A9 DQ9 K12
+1.8VS MAA10 L6 J13 MDA21 +1.8VS MAA10 L6 J13 MDA50
MAA11 A10 DQ10 MDA20 MAA11 A10 DQ10 MDA48
M7 A11 DQ11 J12 M7 A11 DQ11 J12
MAA12 N4 G13 MDA18 MAA12 N4 G13 MDA54
BA0 DQ12 BA0 DQ12
1

1
1K_0402_1%

1K_0402_1%
MAA13 M5 G12 MDA17 MAA13 M5 G12 MDA55
R34 BA1 DQ13 MDA19 R28 BA1 DQ13 MDA53
DQ14 F13 DQ14 F13
PM@ DQMA#1 B3 F12 MDA16 PM@ DQMA#4 B3 F12 MDA52
DQMA#2 DM0 DQ15 MDA29 DQMA#6 DM0 DQ15 MDA44
H12 DM1 DQ16 F3 H12 DM1 DQ16 F3
DQMA#3 H3 F2 MDA26 DQMA#5 H3 F2 MDA46
2

2
(25mil) DQMA#0 DM2 DQ17 MDA30 (25mil) DQMA#7 DM2 DQ17 MDA43
B12 DM3 DQ18 G3 B12 DM3 DQ18 G3
0.1U_0402_16V4Z

0.1U_0402_16V4Z
G2 MDA31 G2 MDA45
DQ19 DQ19
1

1
1K_0402_1%

1K_0402_1%
1 DQSA1 B2 J3 MDA27 1 DQSA4 B2 J3 MDA42
R36 C51 DQSA2 DQS0 DQ20 MDA28 R25 C22 DQSA6 DQS0 DQ20 MDA47
H13 DQS1 DQ21 J2 H13 DQS1 DQ21 J2
PM@ DQSA3 H2 K2 MDA24 PM@ DQSA5 H2 K2 MDA41
PM@ DQSA0 DQS2 DQ22 MDA25 PM@ DQSA7 DQS2 DQ22 MDA40
B13 DQS3 DQ23 K3 B13 DQS3 DQ23 K3
2 MDA0 2 MDA63
E13 E13
2

2
VR_VREF_1 DQ24 MDA1 VR_VREF_2 DQ24 MDA61
N13 VREF DQ25 D13 N13 VREF DQ25 D13
M13 D12 MDA2 M13 D12 MDA62
MCL DQ26 MDA3 MCL DQ26 MDA58
L9 RFU1 DQ27 C13 L9 RFU1 DQ27 C13
C MDA5 MDA57 C
M10 RFU2 DQ28 B10 M10 RFU2 DQ28 B10
B9 MDA4 B9 MDA60
MRASA# DQ29 MDA6 MRASA# DQ29 MDA56
16 MRASA# M2 RAS# DQ30 C9 M2 RAS# DQ30 C9
MCASA# L2 B8 MDA7 MCASA# L2 B8 MDA59
16 MCASA# CAS# DQ31 CAS# DQ31
MWEA# L3 MWEA# L3
16 MWEA# WE# WE#
MCSA0# N2 MCSA0# N2
16 MCSA0# CS# CS#
VDDQ C3 VDDQ C3
MCKEA N12 C5 MCKEA N12 C5
16 MCKEA CKE VDDQ CKE VDDQ
VDDQ C7 VDDQ C7
16 MCLKA0 M11 CK VDDQ C8 16 MCLKA1 M11 CK VDDQ C8
16 MCLKA0# M12 CK# VDDQ C10 16 MCLKA1# M12 CK# VDDQ C10
C578 VDDQ C12 VDDQ C12
1 2 C4 NC VDDQ E3 1 2 C4 NC VDDQ E3
2 1 R428 @ 56_0402_1% C11 E12 2 1 R400 @ 56_0402_1% C11 E12
NC VDDQ NC VDDQ
1 2 H4 NC VDDQ F4 1 2 H4 NC VDDQ F4
470P_0402_50V7K R425 @ 56_0402_1% H11 F11 C485 R396 @ 56_0402_1% H11 F11
@ NC VDDQ 470P_0402_50V7K NC VDDQ
L12 NC VDDQ G4 L12 NC VDDQ G4
L13 NC VDDQ G11 @ L13 NC VDDQ G11
M3 NC VDDQ J4 M3 NC VDDQ J4
M4 J11 +1.8VS M4 J11 +1.8VS
NC VDDQ NC VDDQ
N3 NC VDDQ K4 N3 NC VDDQ K4
VDDQ K11 VDDQ K11
E7 VSS E7 VSS
E8 VSS VDD D7 E8 VSS VDD D7
E10 VSS VDD D8 E10 VSS VDD D8
K6 VSS VDD E4 K6 VSS VDD E4
K7 VSS VDD E11 K7 VSS VDD E11
K8 VSS VDD L4 K8 VSS VDD L4
K9 VSS VDD L7 K9 VSS VDD L7
L5 VSS VDD L8 L5 VSS VDD L8
L10 VSS VDD L11 L10 VSS VDD L11
B E5 E5 B
VSS VSS
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH

VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
K4D55323QF-GC33_FBGA144 K4D55323QF-GC33_FBGA144
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
@ @

+1.8VS
As close as possible to relatived pin +1.8VS

10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C621 C594 C581 C582 C583 C595 C607 C618 C617 C616 C603 C472 C491 C477 C478 C479 C480 C492 C499 C514 C513 C512
PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
VGA DDR CHANNEL A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom EAL30 LA-2691 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期四, 三月 03, 2005 Sheet 19 of 52
5 4 3 2 1
 5 4 3 2 1

DQSB[0..7]
16 DQSB[0..7]
MDB[0..63]
16 MDB[0..63]
DQMB#[0..7]

G10

G10
D10
D11

H10

D10
D11

H10
B11

K10

B11

K10
F10

F10
16 DQMB#[0..7]

J10

J10
G5

G5
D4
D5
D6
D9

H5

D4
D5
D6
D9

H5
B4

E6
E9

K5

B4

E6
E9

K5
F5

F5
J5

J5
MAB[0..13] U2 U1
16 MAB[0..13]

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
D D

MAB0 N5 B7 MDB7 MAB0 N5 B7 MDB38

MAB1 A0 DQ0 MDB4 MAB1 A0 DQ0 MDB39
N6 A1 DQ1 C6 N6 A1 DQ1 C6
MAB2 M6 B6 MDB6 MAB2 M6 B6 MDB37
MAB3 A2 DQ2 MDB5 MAB3 A2 DQ2 MDB36
N7 A3 DQ3 B5 N7 A3 DQ3 B5
MAB4 N8 C2 MDB0 MAB4 N8 C2 MDB34
MAB5 A4 DQ4 MDB1 MAB5 A4 DQ4 MDB35
M9 A5 DQ5 D3 M9 A5 DQ5 D3
MAB6 N9 D2 MDB2 MAB6 N9 D2 MDB33
MAB7 A6 DQ6 MDB3 MAB7 A6 DQ6 MDB32
N10 A7 DQ7 E2 N10 A7 DQ7 E2
MAB8 N11 K13 MDB24 MAB8 N11 K13 MDB63
MAB9 A8/AP DQ8 MDB26 MAB9 A8/AP DQ8 MDB62
M8 A9 DQ9 K12 M8 A9 DQ9 K12
+1.8VS MAB10 L6 J13 MDB29 +1.8VS MAB10 L6 J13 MDB60
MAB11 A10 DQ10 MDB31 MAB11 A10 DQ10 MDB61
M7 A11 DQ11 J12 M7 A11 DQ11 J12
MAB12 N4 G13 MDB30 MAB12 N4 G13 MDB56
BA0 DQ12 BA0 DQ12
1

1
1K_0402_1%

1K_0402_1%
MAB13 M5 G12 MDB28 MAB13 M5 G12 MDB58
R11 BA1 DQ13 MDB25 R12 BA1 DQ13 MDB59
DQ14 F13 DQ14 F13
DQMB#0 B3 F12 MDB27 NON32M@ DQMB#4 B3 F12 MDB57
NON32M@ DQMB#3 DM0 DQ15 MDB14 DQMB#7 DM0 DQ15 MDB47
H12 DM1 DQ16 F3 H12 DM1 DQ16 F3
NON32M@ DQMB#1 H3 F2 MDB15 NON32M@ DQMB#5 H3 F2 MDB45
2

2
(25mil) DQMB#2 DM2 DQ17 MDB13 (25mil) DQMB#6 DM2 DQ17 MDB46
B12 DM3 DQ18 G3 B12 DM3 DQ18 G3
0.1U_0402_16V4Z

0.1U_0402_16V4Z
G2 MDB12 G2 MDB44
DQ19 DQ19
1

1
1K_0402_1%

1K_0402_1%
1 DQSB0 B2 J3 MDB9 1 DQSB4 B2 J3 MDB40
R14 C9 DQSB3 DQS0 DQ20 MDB11 R13 C8 DQSB7 DQS0 DQ20 MDB43
H13 DQS1 DQ21 J2 H13 DQS1 DQ21 J2
DQSB1 H2 K2 MDB8 NON32M@ DQSB5 H2 K2 MDB41
NON32M@ DQSB2 DQS2 DQ22 MDB10 DQSB6 DQS2 DQ22 MDB42
B13 DQS3 DQ23 K3 B13 DQS3 DQ23 K3
2 MDB21 2 MDB52
E13 E13
2

2
VR_VREF_3 DQ24 MDB23 VR_VREF_4 DQ24 MDB54
N13 VREF DQ25 D13 N13 VREF DQ25 D13
M13 D12 MDB22 M13 D12 MDB55
MCL DQ26 MDB20 MCL DQ26 MDB53
L9 RFU1 DQ27 C13 L9 RFU1 DQ27 C13
M10 B10 MDB16 M10 B10 MDB51
C RFU2 DQ28 MDB18 RFU2 DQ28 MDB50 C
DQ29 B9 DQ29 B9
MRASB# M2 C9 MDB17 MRASB# M2 C9 MDB48
16 MRASB# RAS# DQ30 RAS# DQ30
MCASB# L2 B8 MDB19 MCASB# L2 B8 MDB49
16 MCASB# CAS# DQ31 CAS# DQ31
MWEB# L3 MWEB# L3
16 MWEB# WE# WE#
MCSB0# N2 MCSB0# N2
16 MCSB0# CS# CS#
VDDQ C3 VDDQ C3
MCKEB N12 C5 MCKEB N12 C5
16 MCKEB CKE VDDQ CKE VDDQ
VDDQ C7 VDDQ C7
16 MCLKB0 M11 CK VDDQ C8 16 MCLKB1 M11 CK VDDQ C8
16 MCLKB0# M12 CK# VDDQ C10 16 MCLKB1# M12 CK# VDDQ C10
VDDQ C12 VDDQ C12
1 2 C4 NC VDDQ E3 1 2 C4 NC VDDQ E3
2 1 R349 @ 56_0402_1% C11 E12 2 1 R351 @ 56_0402_1% C11 E12
NC VDDQ NC VDDQ
1 2 H4 NC VDDQ F4 1 2 H4 NC VDDQ F4
C415 R350 @ 56_0402_1% H11 F11 C412 R352 @ 56_0402_1% H11 F11
470P_0402_50V7K NC VDDQ 470P_0402_50V7K NC VDDQ
L12 NC VDDQ G4 L12 NC VDDQ G4
@ L13 NC VDDQ G11 @ L13 NC VDDQ G11
M3 J4 +1.8VS M3 J4 +1.8VS
NC VDDQ NC VDDQ
M4 NC VDDQ J11 M4 NC VDDQ J11
N3 NC VDDQ K4 N3 NC VDDQ K4
VDDQ K11 VDDQ K11
E7 VSS E7 VSS
E8 VSS VDD D7 E8 VSS VDD D7
E10 VSS VDD D8 E10 VSS VDD D8
K6 VSS VDD E4 K6 VSS VDD E4
K7 VSS VDD E11 K7 VSS VDD E11
K8 VSS VDD L4 K8 VSS VDD L4
K9 VSS VDD L7 K9 VSS VDD L7
L5 VSS VDD L8 L5 VSS VDD L8
L10 VSS VDD L11 L10 VSS VDD L11
E5 VSS E5 VSS
B
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH

VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
B

K4D55323QF-GC33_FBGA144 K4D55323QF-GC33_FBGA144
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
@ @

+1.8VS
As close as possible to relatived pin +1.8VS

10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C436 C422 C435 C428 C446 C454 C452 C442 C438 C433 C453 C427 C447 C432 C437 C429 C451 C450 C449 C434 C441 C417
NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@ NON32M@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA DDR CHANNEL B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Custom EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 20 of 52
5 4 3 2 1
 5 4 3 2 1

LCD CONN.
LCD POWER CIRCUIT Width: 40mils JP6
INVPWR_B+ 16 1
GM@ reserved for GMCH +3VS
39 DAC_BRIG
DAC_BRIG 17
16
17
1
2 2 DISPOFF#
INVPWR_B+
1 2 INVT_PWM 18 3 +LCDVDD_LCD 1 2
7 GMCH_ENVDD 39 INVT_PWM 18 3 +LCDVDD
R192 0_0402_5% 1 2 +3VS_LCD 19 4 R358 0_1206_5%
R19 0_0805_5% LCD_CLK 19 4 LCD_DATA
20 20 5 5
1 21 21 6 6
TZCLK- 22 7 TXCLK+
15 ENVDD 22 7
C18 TZCLK+ 23 8 TXCLK-
0.1U_0402_16V4Z 23 8
24 24 9 9
+3VALW 2 TZOUT1- TXOUT2+
D 25 25 10 10 D
TZOUT1+ 26 11 TXOUT2-
TZOUT2+ 26 11 TXOUT1-
27 27 12 12
TZOUT2- 28 13 TXOUT1+
28 13

5
1
U4 SN74AHCT1G125GW_SOT353-5 TZOUT0+ 29 14 TXOUT0-
TZOUT0- 29 14 TXOUT0+
30 15

OE#
P
30 15
2 A Y 4
2 ACES_87216-3002

G
C26

2
1U_0402_6.3V4Z
+LCDVDD 1 R24
100_0402_5%
1

1
R26 +3VS
300_0402_5%
1 2

3
D
Q2 2 2 Q1
2N7002_SOT23 G SI2301DS_SOT23
S 1
3

+LCDVDD

1
R27 C23
100K_0402_5% 2 0.047U_0402_16V7K
1 1
For ATI M24
1

C21 C19
4.7U_0805_10V4Z 0.1U_0402_16V4Z
R328 1 PM@ 2 0_0402_5% TXOUT0-
C 2 2 15 VGA_TXOUT0- C
R329 1 PM@ 2 0_0402_5% TXOUT0+
15 VGA_TXOUT0+
R326 1 PM@ 2 0_0402_5% TXOUT1-
15 VGA_TXOUT1-
R327 1 PM@ 2 0_0402_5% TXOUT1+
15 VGA_TXOUT1+
R325 1 PM@ 2 0_0402_5% TXOUT2-
15 VGA_TXOUT2-
R324 1 PM@ 2 0_0402_5% TXOUT2+
15 VGA_TXOUT2+
R323 1 PM@ 2 0_0402_5% TXCLK-
15 VGA_TXCLK-
R322 1 PM@ 2 0_0402_5% TXCLK+
15 VGA_TXCLK+
R370 1 PM@ 2 0_0402_5% TZOUT0-
15 VGA_TZOUT0-
R369 1 PM@ 2 0_0402_5% TZOUT0+
15 VGA_TZOUT0+
R365 1 PM@ 2 0_0402_5% TZOUT1-
15 VGA_TZOUT1-
R366 1 PM@ 2 0_0402_5% TZOUT1+
15 VGA_TZOUT1+
R368 1 PM@ 2 0_0402_5% TZOUT2-
15 VGA_TZOUT2-
R367 1 PM@ 2 0_0402_5% TZOUT2+
15 VGA_TZOUT2+
R364 1 PM@ 2 0_0402_5% TZCLK-
15 VGA_TZCLK-
R363 1 PM@ 2 0_0402_5% TZCLK+
15 VGA_TZCLK+

R335 1 PM@ 2 0_0402_5% LCD_DATA

15 VGA_LCD_DATA
R360 1 PM@ 2 0_0402_5% LCD_CLK
15 VGA_LCD_CLK

width = 60mil
INVPWR_B+

+3VS L4 FBM-L11-201209-121LMT_0805
1 2 B+
1

1 2
R10 1 1 L5 FBM-L11-201209-121LMT_0805 R343 1 GM@ 2 0_0402_5% TXOUT0-
7 GMCH_TXOUT0-
4.7K_0402_5% C14 R344 1 GM@ 2 0_0402_5% TXOUT0+
7 GMCH_TXOUT0+
B 0.1U_0603_25V7K C15 R341 1 GM@ 2 0_0402_5% TXOUT1- B
From EC 68P_0402_50V8K 7
7
GMCH_TXOUT1-
GMCH_TXOUT1+
R342 1 GM@ 2 0_0402_5% TXOUT1+
2

DISPOFF# 2 2 R340 GM@ 0_0402_5% TXOUT2-

39 BKOFF# 1 2 7 GMCH_TXOUT2- 1 2
D4 RB751V_SOD323 R339 1 GM@ 2 0_0402_5% TXOUT2+
7 GMCH_TXOUT2+
R338 1 GM@ 2 0_0402_5% TXCLK-
7 GMCH_TXCLK-
R337 1 GM@ 2 0_0402_5% TXCLK+
7 GMCH_TXCLK+
R382 1 GM@ 2 0_0402_5% TZOUT0-
7 GMCH_TZOUT0-
R381 1 GM@ 2 0_0402_5% TZOUT0+
7 GMCH_TZOUT0+
R377 1 GM@ 2 0_0402_5% TZOUT1-
7 GMCH_TZOUT1-
R378 1 GM@ 2 0_0402_5% TZOUT1+
7 GMCH_TZOUT1+
R380 1 GM@ 2 0_0402_5% TZOUT2-
7 GMCH_TZOUT2-
R379 1 GM@ 2 0_0402_5% TZOUT2+
7 GMCH_TZOUT2+
R376 1 GM@ 2 0_0402_5% TZCLK-
7 GMCH_TZCLK-
R375 1 GM@ 2 0_0402_5% TZCLK+
7 GMCH_TZCLK+

R359 1 GM@ 2 0_0402_5% LCD_DATA

7 GMCH_LCD_DATA
R371 1 GM@ 2 0_0402_5% LCD_CLK
7 GMCH_LCD_CLK

For GMCH

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 21 of 52
5 4 3 2 1
 A B C D E

D1 D2 +5VS +R_CRT_VCC +CRT_VCC

CRT Connector @ DAN217_SC59 @ DAN217_SC59

D23
W=40mils
W=40mils

1
2 1 F1

RB411D_SOT23 POLYSWITCH_1A
1
D3
@ DAN217_SC59 C1

3
0.1U_0402_16V4Z
2
1 +3VS 1

JP1
FOX_DZ11A91-L7

R4 1 2 PM@ 0_0402_5% CRT_R 1 2 CRT_R_L 6

15 VGA_CRT_R
1 2 L2 11
7 GMCH_CRT_R
R5 GM@ 0_0402_5% FCM2012C-800_0805 1
R1 1 2 PM@ 0_0402_5% CRT_G 1 2 CRT_G_L 7
15 VGA_CRT_G
1 2 L1 12
7 GMCH_CRT_G
R6 GM@ 0_0402_5% FCM2012C-800_0805 2
R2 1 2 PM@ 0_0402_5% CRT_B 1 2 CRT_B_L 8
15 VGA_CRT_B
1 2 L3 13
7 GMCH_CRT_B
R3 GM@ 0_0402_5% FCM2012C-800_0805 3

1
1 1 1 1 1 1 DDC_MD2 9
R8 R9 R7 C7 C6 C2 14
@ C3 @ C4 @ C5 4
8P_0402_50V8K 1 10
150_0402_1% 150_0402_1% 150_0402_1% 2 8P_0402_50V8K 2 8P_0402_50V8K 2 2 2 2 C390 15
2

2
8P_0402_50V8K 5
8P_0402_50V8K 8P_0402_50V8K
2
+CRT_VCC HSYNC_L 100P_0402_50V8J
1 2
L20 FCM1608C-121T_0603
1 2 2 1 DSUB_12
C396 0.1U_0402_16V4Z R316 10K_0402_5% 1 2 VSYNC_L
L21 FCM1608C-121T_0603 1

5
1
1 1

OE#
P
1 2 CRT_HSYNC 2 4 D_CRT_HSYNC C391
15 VGA_CRT_HSYNC A Y
R315 PM@ 0_0402_5% C392 C393 2

G
2 U27 10P_0402_50V8J 10P_0402_50V8J 68P_0402_50V8K DSUB_15 2
7 GMCH_CRT_HSYNC 1 2
R317 GM@ 39_0402_5% SN74AHCT1G125GW_SOT353-5 2 2
3
+CRT_VCC 1
C389
1 2 68P_0402_50V8K
C395 0.1U_0402_16V4Z 2

5
1
OE#
P
1 2 CRT_VSYNC 2 4 D_CRT_VSYNC
15 VGA_CRT_VSYNC A Y
R314 PM@ 0_0402_5%

G
1 2 U26
7 GMCH_CRT_VSYNC
R313 GM@ 39_0402_5% SN74AHCT1G125GW_SOT353-5

3
+CRT_VCC
R312 1 2 PM@ 0_0402_5% +3VS

R311 1 2 GM@ 0_0402_5% +2.5VS

1
R310 R303 GM@ 0_0402_5%
4.7K_0402_5% R309 2 1
GMCH_CRT_DATA 7

2
G
4.7K_0402_5% R803 PM@ 0_0402_5%
DSUB_12 1 3 1 2
VGA_DDC_DATA 15

S
Q31

2
BSS138_SOT23

G
R804 PM@ 0_0402_5%
3 DSUB_15 1 3 1 2 3
VGA_DDC_CLK 15

S
Q32
BSS138_SOT23 GM@ 0_0402_5%
TV-Out Connector D21 D20
2
R318
1 GMCH_CRT_CLK 7
@ DAN217_SC59 @ DAN217_SC59

1
15 VGA_TV_LUMA 1 2

3
R332 PM@ 0_0402_5% +3VS
1 2 L23 1 2
7 GMCH_TV_LUMA
R333 GM@ 0_0402_5% FBM-11-160808-121-T_0603

1 2 L22 1 2 JP3
15 VGA_TV_CRMA
R331 PM@ 0_0402_5% FBM-11-160808-121-T_0603 1 1. Y ground
LUMA_1 1
7 GMCH_TV_CRMA 1 2 2 2 GND 5 2. C ground
R330 GM@ 0_0402_5% 3 6 3. Y (luminance+sync)
CRMA_1 3 GND
4 4
4. C (crominance)
1

R321 R320

C402 C401 SUYIN_030336FR004T115ZU

100P_0402_50V8J 100P_0402_50V8J C398 C397
150_0402_1% 150_0402_1% 100P_0402_50V8J 100P_0402_50V8J
TV-OUT Conn.
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TV-OUT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 22 of 52
A B C D E
 A B C D

1 1

RP2
1 8 PCI_SERR#
+3VS
2 7 PCI_TRDY#
3 6 PCI_FRAME#
4 5 PCI_STOP# U36B
29,31,34 PCI_AD[0..31]
PCI_AD0 E2 L5 PCI_REQ#0 Internal Pull-up.
8.2K_0804_8P4R_5% PCI_AD1 AD[0] REQ[0]#
E5 AD[1] PCI GNT[0]# C1
PCI_AD2 C2 B5 PCI_REQ#1
PCI_REQ#1 34
Sample high destination is LPC.
PCI_AD3 AD[2] REQ[1]# PCI_GNT#1
F5 AD[3] GNT[1]# B6 PCI_GNT#1 34
PCI_AD4 F3 M5 PCI_REQ#2 PCI_GNT#5
AD[4] REQ[2]# PCI_REQ#2 31
RP46 PCI_AD5 E9 F1 PCI_GNT#2
AD[5] GNT[2]# PCI_GNT#2 31
1 8 PCI_PLOCK# PCI_AD6 F2 B8 PCI_REQ#3
+3VS AD[6] REQ[3]# PCI_REQ#3 29

1
2 7 PCI _IRDY# PCI_AD7 D6 C8 PCI_GNT#3
AD[7] GNT[3]# PCI_GNT#3 29
3 6 PCI_PERR# PCI_AD8 E6 F7 PCI_REQ#4 R38
PCI_DEVSEL# PCI_AD9 AD[8] REQ[4]#/GPI[40] @ 0_0402_5%
4 5 D3 AD[9] GNT[4]#/GPO[48] E7
PCI_AD10 A2 E8 PCI_REQ#5
8.2K_0804_8P4R_5% PCI_AD11 AD[10] REQ[5]#/GPI[1] PCI_GNT#5
D2 F6

2
PCI_AD12 AD[11] GNT[5]#/GPO[17] PCI_REQ#6
D5 AD[12] REQ[6]#/GPI[0] B7
2 PCI_AD13 2
H3 AD[13] GNT[6]#/GPO[16] D8
PCI_AD14 B4
RP45 PCI_AD15 AD[14] PCI_CBE#0
J5 AD[15] C/BE[0]# J6 PCI_CBE#0 29,31,34
1 8 PCI_PIRQD# PCI_AD16 K2 H6 PCI_CBE#1 PCI_CBE#1 29,31,34
+3VS AD[16] C/BE[1]#
2 7 PCI_PIRQB# PCI_AD17 K5 G4 PCI_CBE#2
AD[17] C/BE[2]# PCI_CBE#2 29,31,34
3 6 PCI_PIRQC# PCI_AD18 D4 G2 PCI_CBE#3
AD[18] C/BE[3]# PCI_CBE#3 29,31,34
4 5 PCI_PIRQA# PCI_AD19 L6
PCI_AD20 AD[19] PCI _IRDY#
G3 AD[20] IRDY# A3 PCI_IRDY# 29,31,34
8.2K_0804_8P4R_5% PCI_AD21 H4 E1 PCI_PAR
PCI_AD22 AD[21] PAR PCI_RST# PCI_PAR 29,31,34
H2 AD[22] PCIRST# R2 PCI_RST# 28,29,31,34,35,39
PCI_AD23 H5 C3 PCI_DEVSEL#
RP1 PCI_AD24 AD[23] DEVSEL# PCI_PERR# PCI_DEVSEL# 29,31,34
B3 AD[24] PERR# E3 PCI_PERR# 29,31,34
1 8 PCI_PIRQE# PCI_AD25 M6 C5 PCI_PLOCK#
+3VS AD[25] PLOCK#
2 7 PCI_PIRQF# PCI_AD26 B2 G5 PCI_SERR#
AD[26] SERR# PCI_SERR# 29,31,34
3 6 PCI_PIRQG# PCI_AD27 K6 J1 PCI_STOP#
AD[27] STOP# PCI_STOP# 29,31,34
4 5 PCI_REQ#6 PCI_AD28 K3 J2 PCI_TRDY#
AD[28] TRDY# PCI_TRDY# 29,31,34
PCI_AD29 A5
8.2K_0804_8P4R_5% PCI_AD30 AD[29]
L1 AD[30]
PCI_AD31 K4 AD[31] PLT_RST#
PLTRST# R5 PLT_RST# 6,15,25,27,28,31,35,39
RP47 G6 CLK_ICH_PCI CLK_PCI_ICH
PCICLK CLK_PCI_ICH 14
1 8 PCI_REQ#5 PCI_FRAME# J3 P6
+3VS 29,31,34 PCI_FRAME# FRAME# PME#
PCI_REQ#3
2 7
add PIRQF for PCI LAN

2
3 6 PCI_REQ#1 Interrupt I/F
4 5 PCI_REQ#4 PCI_PIRQA# N2 D9 PCI_PIRQE#
31 PCI_PIRQA# PIRQ[A]# PIRQ[E]#/GPI[2]
PCI_PIRQB# L2 C7 PCI_PIRQF# R43
31 PCI_PIRQB# PIRQ[B]# PIRQ[F]#/GPI[3] PCI_PIRQF# 29
8.2K_0804_8P4R_5% PCI_PIRQC# M1 C6 PCI_PIRQG# @ 10_0402_5%
31 PCI_PIRQC# PIRQ[C]# PIRQ[G]#GPI[4] PCI_PIRQG# 34
PCI_PIRQD# L3 M3 PCI_PIRQH#
31 PCI_PIRQD# PCI_PIRQH# 34

1
PIRQ[D]# PIRQ[H]#/GPI[5]

RP3 AC5
RESERVED 1
C67
SATA[1]RXN/RSVD[1] @ 10P_0402_50V8J
+3VS 1 8 AD5 SATA[1]RXP/RSVD[2]
3 PCI_REQ#0 3
2 7 AF4 SATA[1]TXN/RSVD[3]
PCI_REQ#2 2
3 6 AG4 SATA[1]TXP/RSVD[4]
4 5 PCI_PIRQH# AC9 SATA[3]RXN/RSVD[5]
AD9 SATA[3]RXP/RSVD[6]
8.2K_0804_8P4R_5% AF8 SATA[3]TXN/RSVD[7]
AG8 SATA[3]TXP/RSVD[8]
U3 TP[3]/RSVD[9]
ICH6_BGA609

ICH6-M
(R3:SA828010890)
(R1:SA8280108B0)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH6(1/4)_HUB,PCI,HOST
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 23 of 52
A B C D
 A B C D

C628
18P_0402_50V8J
2 1 ICH_RTCX1
+RTCVCC

10M_0402_5%
1 Y5 1

1
3 NC OUT 4
1

R438
R73 32.768KHZ_12.5P_1TJS125DJ2A073 2 1
NC IN U36A
1M_0402_1% C627 +1.05VS

2
18P_0402_50V8J Y1 P2 LPC_LAD0
LPC_AD0 35,39
2

RTCX1 LAD[0]/FWH[0]

RTC
2 1 ICH_RTCX2 Y2 N3 LPC_LAD1
RTCX2 LAD[1]/FWH[1] LPC_AD1 35,39
INTRUDER# N5 LPC_LAD2
LAD[2]/FWH[2] LPC_AD2 35,39
1 2 ICH_RTCRST# AA2 N4 LPC_LAD3 H_FERR# 1 2

LPC
+RTCVCC RTCRST# LAD[3]/FWH[3] LPC_AD3 35,39
R74 R435 56_0402_5%
20K_0402_5% INTRUDER# AA3 N6 H_DPRSTP# 1 2
INTVRMEN INTRUDER# LDRQ[0]# LPC_DRQ#1 R432 @ 56_0402_5%
AA5 INTVRMEN LDRQ[1]#/GPI[41] P4 LPC_DRQ#1 35
+3VS
LPC_FRAME#
close to RAM door J1
2 1
JOPEN D12
LFRAME#/FWH[4] P3 LPC_FRAME# 35,39 Intel Recommand
EE_CS
1

@ B12 R442 1 2 10K_0402_5% +3VS

R75 EE_SHCLK EC_GA20
D11 EE_DOUT A20GATE AF22 EC_GA20 39
C649 F13 AF23 H_A20M#
EE_DIN A20M# H_A20M# 4
10K_0402_5% 1U_0402_6.3V4Z

LAN
R437 1 2 @ 0_0402_5% H_CPUSLP#

CPU
1 2 F12 AE27 H_CPUSLP# 4,6
2

LAN_CLK CPUSLP#
B11 AE24 R431 1 2 0_0402_5% H_DPRSTP# H_DPRSTP# 4
PHDD_LED# LAN_RSTSYNC DPRSLP#/TP[4]
DPSLP#/TP[2] AD27 H_DPSLP# 4
E12 LANRXD[0]
E11 AF24 1 2 H_FERR# H_FERR# 4
LANRXD[1] FERR# R434 56_0402_5%
C13 LANRXD[2]
AG25 H_PW RGOOD H_PWRGOOD 4
CPUPWRGD/GPO[49] MAINPWON 43,44,46
C12 LANTXD[0]
C11 AG26 H_IGNNE# H_IGNNE# 4 R465
LANTXD[1] IGNNE#

1
C54 R33 E13 AE22 @ 330_0402_5% C
@ 10P_0402_50V8J @ 10_0402_5% LANTXD[2] INIT3_3V# H_INIT# Q36
INIT# AF27 H_INIT# 4 +1.05VS 1 2 2
2 H_INTR R460 B @ 2SC2411K_SC59 2
1 2 2 1 INTR AG24 H_INTR 4
10K_0402_5% E

3
AC97_BITCLK C10 1 2 +3VS
36 AC97_BITCLK ACZ_BIT_CLK

AC-97/AZALIA
36 AC97_SYNC 2 1 AC97_SYNC_R B9 AD23 KB_RST#
ACZ_SYNC RCIN# EC_KBRST# 39
R32 33_0402_5%
1 2 AC97_RST_R# A10 AF25 H_NMI H_NMI 4 +1.05VS 1 2 2 1 THRMTRIP#
36 AC97_RST# ACZ_RST# NMI
R30 33_0402_5% AG27 H_SMI# H_SMI# 4 R459 75_0402_1% R452
AC_SDIN0 SMI# 56_0402_5%
36 AC97_SDIN0 F11 ACZ_SDIN[0]
36 AC97_SDIN1 F10 AE26 H_STPCLK# H_STPCLK# 4
ACZ_SDIN[1] STPCLK# H_THERMTRIP#
B10 ACZ_SDIN[2] H_THERMTRIP# 4,6
AE23 THRMTRIP#
AC97_SDOUT_R THRMTRIP#
36 AC97_SDOUT 2 1 C9 ACZ_SDO
R35 33_0402_5%
AC16 IDE_DA0 IDE_DA0 28
PHDD_LED# DA[0] IDE_DA1
39 PHDD_LED# AC19 SATALED# DA[1] AB17 IDE_DA1 28
AC17 IDE_DA2 IDE_DA2 28
DA[2]

27 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 AE3 AD16 IDE_DCS1# IDE_DCS1# 28

SATA_DTX_C_IRX_P0 SATA[0]RXN DCS1# IDE_DCS3#
27 SATA_DTX_C_IRX_P0 AD3 SATA[0]RXP DCS3# AE17 IDE_DCS3# 28
SATA_ITX_DRX_N0 AG2
SATA_ITX_DRX_P0 SATA[0]TXN
27 SATA_ITX_C_DRX_N0 1 2 AF2 SATA[0]TXP IDE_DD[0..15] 28
0.01U_0402_16V7K C669 AD14 IDE_DD0
DD[0]

SATA
1 2 SATA2_RXN AD7 AF15 IDE_DD1
27 SATA_ITX_C_DRX_P0 SATA[2]RXN DD[1]

PIDE
0.01U_0402_16V7K C668 SATA2_RXP AC7 AF14 IDE_DD2
SATA[2]RXP DD[2] IDE_DD3
Place near ICH6 side. AF6
AG6
SATA[2]TXN DD[3] AD12
AE14 IDE_DD4
SATA[2]TXP DD[4] IDE_DD5
DD[5] AC11
CLK_PCIE_SATA# AC2 AD11 IDE_DD6
14 CLK_PCIE_SATA# CLK_PCIE_SATA AC1 SATA_CLKN DD[6] IDE_DD7
14 CLK_PCIE_SATA SATA_CLKP DD[7] AB11
AE13 IDE_DD8
DD[8] IDE_DD9
AG11 SATARBIAS# DD[9] AF13
R450 1 2 24.9_0402_1% SATARBIAS AF11 AB12 IDE_DD10
3 SATARBIAS DD[10] IDE_DD11 3
DD[11] AB13
AC13 IDE_DD12
DD[12] IDE_DD13
DD[13] AE15
R451 1 2 4.7K_0402_5% IDE_ DIORDY AG15 IDE_DD14
+3VS DD[14]
IDE_ DIORDY AF16 AD13 IDE_DD15
28 IDE_DIORDY IORDY DD[15]
IDE_IRQ AB16
28 IDE_IRQ IDEIRQ
R76 1 2 8.2K_0402_5% IDE_IRQ IDE_DDACK# AB15
28 IDE_DDACK# DDACK#
IDE_DIOW# AC14 AB14 IDE_DDREQ
28 IDE_DIOW# DIOW# DDREQ IDE_DDREQ 28
IDE_DIOR# AE16
28 IDE_DIOR# DIOR#
R834 1 2 1K_0402_5% SATA2_RXN
ICH6@ ICH6_BGA609
R835 1 2 1K_0402_5% SATA2_RXP

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH6(2/4)_CPU,AC97,IDE,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 24 of 52
A B C D
 A B C D E F G H

+3VALW

1 2 ICH_SMLINK0
R60 10K_0402_5% U36C
1 2 ICH_SMLINK1 EC_SWI# T2 H25
R54 10K_0402_5% 39 EC_SWI# RI# PERn[1]
PERp[1] H24
1 2 CK_SCLK GPI26 AF17 G27
R63 2.2K_0402_5% GPI27 SATA[0]GP/GPI[26] PETn[1]
AE18 SATA[1]GP/GPI[29] PETp[1] G26
1 2 CK_SDATA GPI28 AF18
1 R64 2.2K_0402_5% GPI29 SATA[2]GP/GPI[30] 1
AG18 SATA[3]GP/GPI[31] PERn[2] K25
1 2 LINKALERT# K24
R70 10K_0402_5% CK_SCLK PERp[2]
14 CK_SCLK Y4 SMBCLK PETn[2] J27

PCI-EXPRESS
1 2 EC_LID_OUT# CK_SDATA W5 J26
14 CK_SDATA SMBDATA PETp[2]
R49 @ 10K_0402_5% LINKALERT# Y5
EC_SWI# ICH_SMLINK0 LINKALERT#
1 2 W4 SMLINK[0] PERn[3] M25

GPIO
R55 10K_0402_5% ICH_SMLINK1 U6 M24
PM_BATLOW# MCH_SYNC# SMLINK[1] PERp[3]
1 2 AG21 MCH_SYNC# PETn[3] L27
R66 8.2K_0402_5% SB_SPKR F8 L26
WAKE# 36 SB_SPKR SPKR PETp[3]
1 2
R240 1K_0402_1% W3 P24
40 SUS_STAT# SUS_STAT#/LPCPD# PERn[4]
1 2 SYSRST# P23
R61 10K_0402_5% SYSRST# PERp[4] +3VALW
U2 SYS_RESET# PETn[4] N27
PETp[4] N26
PM_BMBUSY# AD19
+3VS 6 PM_BMBUSY# BM_BUSY#/GPI[6]
T25 DMI_MTX_IRX_N0 RP4
DMI[0]RXN DMI_MTX_IRX_N0 6
ICH_GPI7 AE19 T24 DMI_MTX_IRX_P0 USB_OC#5 4 5
GPI[7] DMI[0]RXP DMI_MTX_IRX_P0 6
1 2 ICH_GPI7 R439 1 2 0_0402_5% 39 EC_SMI# EC_SMI# R1 R27 DMI_ITX_MRX_N0 USB_OC#7 3 6
GPI[8] DMI[0]TXN DMI_ITX_MRX_N0 6
R455 10K_0402_5% R26 DMI_ITX_MRX_P0 USB_OC#6 2 7
DMI[0]TXP DMI_ITX_MRX_P0 6

DIRECT MEDIA INTERFACE

1 2 PM_CLKRUN# 1 2 @ W6 USB_OC#3 1 8
38,39,43 ACIN SMBALERT#/GPI[11]
R447 8.2K_0402_5% D25 RB751V_SOD323 V25 DMI_MTX_IRX_N1
DMI[1]RXN DMI_MTX_IRX_N1 6
1 2 ICH_VGATE +3VALW 2 1 EC_LID_OUT# M2 V24 DMI_MTX_IRX_P1 10K_0804_8P4R_5%
39 EC_LID_OUT# GPI[12] DMI[1]RXP DMI_MTX_IRX_P1 6
R448 10K_0402_5% 100K_0402_5% R218@ EC_SCI# R6 U27 DMI_ITX_MRX_N1
39 EC_SCI# GPI[13] DMI[1]TXN DMI_ITX_MRX_N1 6
1 2 MCH_SYNC# U26 DMI_ITX_MRX_P1 USB_OC#1 1 2
DMI[1]TXP DMI_ITX_MRX_P1 6
R449 10K_0402_5% PM_STP_PCI# AC21 R411 10K_0402_5%
14 PM_STP_PCI# STP_PCI#/GPO[18]
1 2 SERIRQ Y25 DMI_MTX_IRX_N2
DMI[2]RXN DMI_MTX_IRX_N2 6
R69 10K_0402_5% AB21 Y24 DMI_MTX_IRX_P2
40 SB_INT_FLASH_SEL# GPO[19] DMI[2]RXP DMI_MTX_IRX_P2 6
W27 DMI_ITX_MRX_N2
DMI[2]TXN DMI_ITX_MRX_N2 6
PM_STP_CPU# AD22 W26 DMI_ITX_MRX_P2
14,50 PM_STP_CPU# STP_CPU#/GPO[20] DMI[2]TXP DMI_ITX_MRX_P2 6
AB24 DMI_MTX_IRX_N3
DMI[3]RXN DMI_MTX_IRX_N3 6
1 2 SYS_PWROK AD20 AB23 DMI_MTX_IRX_P3
2 GPO[21] DMI[3]RXP DMI_MTX_IRX_P3 6 2
R77 10K_0402_5% PLTRST_VGA# AD21 AA27 DMI_ITX_MRX_N3
15 PLTRST_VGA# GPO[23] DMI[3]TXN DMI_ITX_MRX_N3 6
1 2 EC_RSMRST# AA26 DMI_ITX_MRX_P3
DMI[3]TXP DMI_ITX_MRX_P3 6
R65 10K_0402_5% V3
27 IDE_HDDRST# GPIO[24]
AD25 CLK_PCIE_ICH#
DMI_CLKN CLK_PCIE_ICH# 14
RP48 P5 AC25 CLK_PCIE_ICH
39 IDE_ODDRST# GPIO[25] DMI_CLKP CLK_PCIE_ICH 14
4 5 GPI29 R3
GPI28 EC_FLASH# GPIO[27]
3 6 40 EC_FLASH# T3 GPIO[28]
2 7 GPI27 29,34,35 PM_CLKRUN# PM_CLKRUN# AF19 F24
GPI26 CLKRUN#/GPIO[32] DMI_ZCOMP
1 8 AF20 GPIO[33]
AC18 F23 DMI_IRCOMP R39 1 2 24.9_0402_1% +1.5VS
100_1206_8P4R_5% GPIO[34] DMI_IRCOMP
WAKE# U5 C23 USB_OC#4
WAKE# OC[4]#/GPI[9] USB_OC#4 41
D23 USB_OC#5
PM_DPRSLPVR SERIRQ OC[5]#/GPI[10] USB_OC#6
1 2 31,35,39 SERIRQ AB20 SERIRQ OC[6]#/GPI[14] C25
R288 100K_0402_5% C24 USB_OC#7
EC_THERM# OC[7]#/GPI[15]
39 EC_THERM# AC20 THRM#
Intel new update C27 USB_OC#0
OC[0]# USB_OC#0 41
6,14,50 VGATE 2 1 ICH_VGATE AF21 VRMPWRGD OC[1]# B27 USB_OC#1
R456 0_0402_5% B26 USB_OC#2
OC[2]# USB_OC#2 41
CLK_14M_ICH E10 C26 USB_OC#3
CLK14 OC[3]#
CLK_48M_ICH USB20_N0

CLOCK
A27 CLK48 USBP[0]N C21 USB20_N0 41
D21 USB20_P0
USBP[0]P USB20_P0 41
V6 SUSCLK USBP[1]N A20
USBP[1]P B20
SLP_S3# T4 D19 USB20_N2
39 PM_SLP_S3# SLP_S3# USBP[2]N USB20_N2 41
SLP_S4# T5 C19 USB20_P2
SLP_S4# USBP[2]P USB20_P2 41

USB
SLP_S5# T6 A18
SLP_S5# USBP[3]N
USBP[3]P B18
SYS_PWROK AA1 E17 USB20_N4
38 SYS_PWROK PWROK USBP[4]N USB20_N4 41

POWER MGT
D17 USB20_P4
USBP[4]P USB20_P4 41
PM_DPRSLPVR AE20 B16
3 50 PM_DPRSLPVR DPRSLPVR/TP[1] USBP[5]N 3
USBP[5]P A16
PM_BATLOW# V2 C15
BATLOW#/TP[0] USBP[6]N
USBP[6]P D15
PBTN_OUT# U1 A14
39 PBTN_OUT# PWRBTN# USBP[7]N
USBP[7]P B14
PLT_RST# V5
6,15,23,27,28,31,35,39 PLT_RST# LAN_RST# USBRBIAS
USBRBIAS# A22 1 2
EC_RSMRST# Y3 B22 R31 21.5_0402_1%
39 EC_RSMRST# RSMRST# USBRBIAS
ICH6_BGA609

+3VALW C623
0.1U_0402_16V4Z
1 2
RTC Battery
14

U13B +RTCPWR
4 SLP_S4#
P

CLK_48M_ICH CLK_14M_ICH A BATT1 45@

6
14 CLK_ICH_48M 14 CLK_ICH_14M 39 PM_SLP_S5# O
B 5 SLP_S5# - + C679
1

2 1 1 2
1

R41 SN74LVC08APW_TSSOP14 0.1U_0402_16V4Z

1
R412 @ 10_0402_5%
@ 10_0402_5% ML1220T13RE
2
2

BAS40-04_SOT23
1
D26
1
C68 +RTCVCC

2
C506 @ 10P_0402_50V8J
4 @ 10P_0402_50V8J 2 4
2

+CHGRTC

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH6(3/4)_USB,PM,LAN,GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 25 of 52
A B C D E F G H
 5 4 3 2 1

+1.5VS
Near PIN F27(C155), +1.5VS C69
P27(C154), AB27(C157) U36E +RTCVCC 0.1U_0402_16V4Z U36D
1 2 E27 VSS[172] VSS[86] F4
+1.5VS AA22 VCC1_5[1] VCC1_5[98] F9 Y6 VSS[171] VSS[85] F22

220U_D2_4VM_R12

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 AA23 U17 0.1U_0402_16V4Z C77 Y27 F19
VCC1_5[2] VCC1_5[97] 0.1U_0402_16V4Z VSS[170] VSS[84]
2 2 2 AA24 VCC1_5[3] VCC1_5[96] U16 Y26 VSS[169] VSS[83] F17

C510
+ AA25 U14 1 2 Y23 E25
VCC1_5[4] VCC1_5[95] 2 2 VSS[168] VSS[82]

C95

C56

C81
AB25 U12 C672 W7 E19
VCC1_5[5] VCC1_5[94] C83 VSS[167] VSS[81]
AB26 VCC1_5[6] VCC1_5[93] U11 W25 VSS[166] VSS[80] E18
2 1 1 1 0.1U_0402_16V4Z
D AB27 VCC1_5[7] VCC1_5[92] T17 W24 VSS[165] VSS[79] E15 D
F25 T11 C6731 1
1 2 W23 E14
VCC1_5[8] VCC1_5[91] VSS[164] VSS[78]
F26 VCC1_5[9] VCC1_5[90] P17 W1 VSS[163] VSS[77] D7
F27 P11 0.1U_0402_16V4Z C90 V4 D22
VCC1_5[10] VCC1_5[89] 0.1U_0402_16V4Z VSS[162] VSS[76]
FOR SW DJ FUNCTION G22 M17 V27 D20

CORE
VCC1_5[11] VCC1_5[88] VSS[161] VSS[75]
G23 VCC1_5[12] VCC1_5[87] M11 1 2 V26 VSS[160] VSS[74] D18
G24 VCC1_5[13] VCC1_5[86] L17 V23 VSS[159] VSS[73] D14
G25 L16 C78 U25 D13
+5VCD +5VS +3VS VCC1_5[14] VCC1_5[85] 0.1U_0402_16V4Z VSS[158] VSS[72]
H21 VCC1_5[15] VCC1_5[84] L14 U24 VSS[157] VSS[71] D10
H22 VCC1_5[16] VCC1_5[83] L12 1 2 U23 VSS[156] VSS[70] D1
J21 VCC1_5[17] VCC1_5[82] L11 U15 VSS[155] VSS[69] C4
2

2 J22 VCC1_5[18] VCC1_5[81] AA21 C667 U13 VSS[154] VSS[68] C22

R815 R485 D27 K21 AA20 0.1U_0402_16V4Z T7 C20
VCC1_5[19] VCC1_5[80] VSS[153] VSS[67]
K22 VCC1_5[20] VCC1_5[79] AA19 1 2 T27 VSS[152] VSS[66] C18

PCIE
@ 1K_0402_5% 10_0402_5% RB751V_SOD323 L21 T26 C14
VCC1_5[21] C94 VSS[151] VSS[65]
L22 T23 B25
1

VCC1_5[22] 0.1U_0402_16V4Z +3VS 0.1U_0402_16V4Z VSS[150] VSS[64]

M21 VCC1_5[23] VCC3_3[21] AA10 T16 VSS[149] VSS[63] B24
ICH_V5REF_RUN M22 AG19 1 2 T15 B23
VCC1_5[24] VCC3_3[20] VSS[148] VSS[62]
2 2 2 N21 VCC1_5[25] VCC3_3[19] AG16 T14 VSS[147] VSS[61] B21
N22 AG13 2 2 C85 T13 B19
C687 C681 VCC1_5[26] VCC3_3[18] 0.1U_0402_16V4Z VSS[146] VSS[60]
N23 VCC1_5[27] VCC3_3[17] AD17 T12 VSS[145] VSS[59] B15
1U_0603_10V4Z C678 0.1U_0402_16V4Z N24 AC15 C677 Near PIN 1 2 T1 B13
1 1 1 VCC1_5[28] VCC3_3[16] VSS[144] VSS[58]
N25 AA17 R4 AG7

IDE
0.1U_0402_16V4Z P21
VCC1_5[29] VCC3_3[15]
AA15 C6761 1 AG13, AG16 C86 R25
VSS[143] VSS[57]
AG3
VCC1_5[30] VCC3_3[14] 0.1U_0402_16V4Z VSS[142] VSS[56]
P25 VCC1_5[31] VCC3_3[13] AA14 R24 VSS[141] VSS[55] AG22
P26 VCC1_5[32] VCC3_3[12] AA12 1 2 R23 VSS[140] VSS[54] AG20
P27 0.1U_0402_16V4Z R17 AG17
VCC1_5[33] C79 VSS[139] VSS[53]
R21 VCC1_5[34] R16 VSS[138] VSS[52] AG14
R22 P1 +3VS 0.1U_0402_16V4Z R15 AG12
VCC1_5[35] VCC3_3[11] VSS[137] VSS[51]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
T21 VCC1_5[36] VCC3_3[10] M7 2 2 2 1 2 R14 VSS[136] VSS[50] AG1
T22 VCC1_5[37] VCC3_3[9] L7 R13 VSS[135] VSS[49] AF7

C55

C96

C63
U21 L4 C524 R12 AF3
C VCC1_5[38] VCC3_3[8] 0.01U_0402_16V7K VSS[134] VSS[48] C
U22 VCC1_5[39] VCC3_3[7] J7 R11 VSS[133] VSS[47] AF26
1 1 1
V21 VCC1_5[40] VCC3_3[6] H7 1 2 P22 VSS[132] VSS[46] AF12

GROUND
PCI
V22 VCC1_5[41] VCC3_3[5] H1 P16 VSS[131] VSS[45] AF10
W21 VCC1_5[42] VCC3_3[4] E4 Near PIN A25 P15 VSS[130] VSS[44] AF1
W22 VCC1_5[43] VCC3_3[3] B1 Near PIN C93
P14 VSS[129] VSS[43] AE7
Y21 A6 P13 AE6
Y22
VCC1_5[44] VCC3_3[2] A2-A6, D1-H1 0.01U_0402_16V7K P12
VSS[128] VSS[42]
AE25
VCC1_5[45] VSS[127] VSS[41]
VCCSUS1_5[3] U7 +1.5VALW 1 2 N7 VSS[126] VSS[40] AE21
+1.5VS AA6 VCC1_5[46] VCCSUS1_5[2] R7 N17 VSS[125] VSS[39] AE2
AB4 VCC1_5[47] Near PIN AA19 N16 VSS[124] VSS[38] AE12

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AB5 VCC1_5[48] 2 2 2 N15 VSS[123] VSS[37] AE11

USB
2 AB6 VCC1_5[49] VCCSUS1_5[1] G19 N14 VSS[122] VSS[36] AE10

C58

C87
C84
AC4 VCC1_5[50] N13 VSS[121] VSS[35] AD6
Near PIN AG5 C674 AD4 G20 N12 AD24
0.1U_0402_16V4Z VCC1_5[51] VCC1_5[78] 1 1 1 VSS[120] VSS[34]
AE4 VCC1_5[52] VCC1_5[77] F20 N11 VSS[119] VSS[33] AD2
1
AE5 VCC1_5[53] VCC1_5[76] E24 N1 VSS[118] VSS[32] AD18

SATA
AF5 VCC1_5[54] VCC1_5[75] E23 M4 VSS[117] VSS[31] AD15

USB CORE
AG5 VCC1_5[55] VCC1_5[74] E22 M27 VSS[116] VSS[30] AD10
VCC1_5[73] E21 +3VALW M26 VSS[115] VSS[29] AD1
+1.5VS AA7 VCC1_5[56] VCC1_5[72] E20 M23 VSS[114] VSS[28] AC6
AA8 D27 C61 M16 AC3
VCC1_5[57] VCC1_5[71] 0.1U_0402_16V4Z VSS[113] VSS[27]
AA9 VCC1_5[58] VCC1_5[70] D26 M15 VSS[112] VSS[26] AC26
2 AB8 VCC1_5[59] VCC1_5[69] D25 1 2 M14 VSS[111] VSS[25] AC24
AC8 VCC1_5[60] VCC1_5[68] D24 +1.5VS M13 VSS[110] VSS[24] AC23
+5VALWP+3VALW C675 C89
Near PIN AG9 0.1U_0402_16V4Z
AD8 VCC1_5[61] +2.5VS 0.1U_0402_16V4Z
M12 VSS[109] VSS[23] AC22
AE8 VCC1_5[62] VCC1_5[67] G8 L25 VSS[108] VSS[22] AC12
1
AE9 VCC1_5[63] 1 2 L24 VSS[107] VSS[21] AC10
2

AF9 VCC1_5[64] VCC2_5[4] AB18 L23 VSS[106] VSS[20] AB9

R406 D24 AG9 PCI/IDE RBP P7 C91 L15 AB7
VCC1_5[65] VCC2_5[2] 0.1U_0402_16V4Z VSS[105] VSS[19]
L13 VSS[104] VSS[18] AB2

0.1U_0402_16V4Z
10_0402_5% RB751V_SOD323 ICH6_VCCPLL AC27 AA18 ICH_V5REF_RUN 2 1 2 K7 AB19
B VCCDMIPLL V5REF[2] VSS[103] VSS[17] B
+3VS E26 A8 K27 AB10
1

VCC3_3[1] V5REF[1] VSS[102] VSS[16]

C80
ICH_V5REF_SUS C523 K26 AB1
ICH_V5REF_SUS 0.1U_0402_16V4Z VSS[101] VSS[15]
2 2 +1.5VS AE1 VCCSATAPLL V5REF_SUS F21 K23 VSS[100] VSS[14] AA4
C515 1
2 +3VS AG10 VCC3_3[22] 1 2 K1 VSS[99] VSS[13] AA16
C60 Near PIN A25 +1.5VS J4 AA13
1U_0603_10V4Z 0.1U_0402_16V4Z VCCUSBPLL VSS[98] VSS[12]
1 1 C50 E26, E27
A13 VCCLAN3_3/VCCSUS3_3[1] VCCSUS3_3[20] A24 +3VALW Near PIN A24 J25 VSS[97] VSS[11] AA11
+3VS F14 VCCLAN3_3/VCCSUS3_3[2] J24 VSS[96] VSS[10] A9
0.1U_0402_16V4Z 1 G13 AB3 +RTCVCC J23 A7
VCCLAN3_3/VCCSUS3_3[3] VCCRTC VSS[95] VSS[9]
G14 VCCLAN3_3/VCCSUS3_3[4] Near PIN AB18 H27 VSS[94] VSS[8] A4
VCCLAN1_5/VCCSUS1_5[2] G11 H26 VSS[93] VSS[7] A26
+3VALW A11 VCCSUS3_3[1] VCCLAN1_5/VCCSUS1_5[1] G10 +1.5VS H23 VSS[92] VSS[6] A23
U4 VCCSUS3_3[2] G9 VSS[91] VSS[5] A21
V1 VCCSUS3_3[3] V_CPU_IO[3] AG23 G7 VSS[90] VSS[4] A19
+3VS
V7 VCCSUS3_3[4] V_CPU_IO[2] AD26 +1.05VS G21 VSS[89] VSS[3] A15
W2 AB22 C62 G12 A12
VCCSUS3_3[5] V_CPU_IO[1] 0.1U_0402_16V4Z VSS[88] VSS[2]
Y7 VCCSUS3_3[6] G1 VSS[87] VSS[1] A1

0.1U_0402_16V4Z
VCCSUS3_3[19] G16 2 1 2
+3VALW A17 VCCSUS3_3[7] VCCSUS3_3[18] G15 Near PIN AG23
C670

change 0 ohm B17 F16 ICH6_BGA609

VCCSUS3_3[8] VCCSUS3_3[17]
0.1U_0402_16V4Z

0.1U_0402_16V4Z

2 2 C17 VCCSUS3_3[9] VCCSUS3_3[16] F15

L26 R436 1 C671
F18 VCCSUS3_3[10] VCCSUS3_3[15] E16
C42

C45

CHB1608U301_0603 0.5_0603_1% G17 D16 0.1U_0402_16V4Z

VCCSUS3_3[11] VCCSUS3_3[14]
+1.5VS 1 2 ICH6_VCCDMIPLL1 2 ICH6_VCCPLL G18 VCCSUS3_3[12] VCCSUS3_3[13] C16 1 2
1 1

2 1 ICH6_BGA609 Near PIN AG10

C624
Near PIN A17
0.1U_0402_16V4Z 1 C625 2
0.01U_0402_16V7K
A A

Near PIN
AC27

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH6(4/4)_POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 26 of 52
5 4 3 2 1
 5 4 3 2 1

+3VS
+5VS +1.8VS
1 2 ATAIOSEL 1 2 T1
SATA Module
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R389 10K_0402_5% R393 10K_0402_5%
1 2 P IDE_HIORDY
Sets maximum transfer rate and UDMA mode
1 1 1 1 1 1 1 R420 4.7K_0402_5% 2 1 PIDE_HDREQ CNFG2 CNFG1 CNFG0 NOTE
C102 C97 C551 1 2 PIDE_HIOCS16# R417 5.6K_0402_5% INT PD INT PD
R419 10K_0402_5%
C100 C103 C25 C488 1 2 T0 2 1 PIDE_HINTRQ * Device Mode 100MB/s
2 2 2 2 2 2 2 R391 @ 10K_0402_5% R416 10K_0402_5%
0 0 0
1000P_0402_50V7K 1U_0603_10V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 1 2 T2 Device Mode 133MB/s
R394 @ 10K_0402_5%
0 0 1
1 2 T3 Device Mode 150MB/s
R398 10K_0402_5%
0 1 0
Pleace near HD CONN Pleace near U178
D 1 2 T6
1 0 0 Host Mode 100MB/s D
R401 10K_0402_5%
1 0 1 Host Mode 133MB/s
U35 1 1 0 Host Mode 150MB/s
C465 2 1 0.01U_0402_16V7K
PIDE_HDD0 SATA_DTX_IRX_P0 SATA_DTX_C_IRX_P0 24
62 HDD0 TXP 32 0 1 1 Reserved
PIDE_HDD1 64 31 SATA_DTX_IRX_N0 C466 2 1 0.01U_0402_16V7K
PIDE_HDD2 HDD1 TXM SATA_ITX_C_DRX_P0 SATA_DTX_C_IRX_N0 24
2 HDD2 SATA RXP 27 SATA_ITX_C_DRX_P0 24 1 1 1 Reserved
PIDE_HDD3 5 28 SATA_ITX_C_DRX_N0
PIDE_HDD4 HDD3 RXM SATA_ITX_C_DRX_N0 24
7 HDD4
PIDE_HDD5 11 17 SATA_RST#
PIDE_HDD6 HDD5 RST# T0
13 33
PIDE_HDD7 15
HDD6 T0
34 T1 P-ATA HDD Conn.

Config & Debug

PIDE_HDD8 HDD7 T1 T2
14 HDD8 T2 35
PIDE_HDD9 12 36 T3 SUYIN_200055FB044GX03ZX
PIDE_HDD10 HDD9 T3
10 HDD10 T4 37
PIDE_HDD11 6 38 T5 1 2 PIDE_HRESET# 1 2

Parallel ATA
PIDE_HDD12 HDD11 T5 T6 R397 10K_0402_5% PIDE_HDD7 1 2 PIDE_HDD8
3 HDD12 T6 39 3 3 4 4
PIDE_HDD13 1 40 PIDE_HDD6 5 6 PIDE_HDD9
PIDE_HDD14 HDD13 T7 PIDE_HDD5 5 6 PIDE_HDD10
63 HDD14 CNFG2 20 7 7 8 8
PIDE_HDD15 61 19 CNFG1 1 2 PIDE_HDD4 9 10 PIDE_HDD11
HDD15 CNFG1 R390 10K_0402_5% PIDE_HDD3 9 10 PIDE_HDD12
CNFG0 18 11 11 12 12
21 ATAIOSEL PIDE_HDD2 13 14 PIDE_HDD13
PIDE_HDA0 ATAIOSEL PIDE_HDD1 13 14 PIDE_HDD14
50 HDA0 15 15 16 16
PIDE_HDA1 51 22 IDE_XTLIN PIDE_HDD0 17 18 PIDE_HDD15
PIDE_HDA2 HDA1 XTLIN/OSC IDE_XTLOUT 17 18
49 HDA2 XTLOUT 23 19 19 20 20
PIDE_HCS0# 48 PIDE_HDREQ 21 22
PIDE_HCS1# HCS0# +3VS +3VS PIDE_HDIOW# 21 22
47 HCS1# 23 23 24 24
26 2 1 PIDE_HDIOR# 25 26
PIDE_HIOCS16# ISET R373 12.1K_0603_1% +1.8VS P IDE_HIORDY 25 26 SEC_CSEL R429 1
52 HIOCS16# VDDIO_0 44 27 27 28 28 2 470_0402_5%
PIDE_HINTRQ 53 4 PIDE_HDMACK# 29 30
C PIDE_HDMACK# HINTRQ VDDIO_1 PIDE_HINTRQ 29 30 R430 1 C
54 HDMACK# VDD_0 9 31 31 32 32 2 10K_0402_5%
P IDE_HIORDY 55 41 PIDE_HDA1 33 34 R433 1 2 10K_0402_5%
PIDE_HDIOR# HIORDY VDD_1 PIDE_HDA0 33 34 PIDE_HDA2
58 HDIOR# VDD_2 56 35 35 36 36
PIDE_HDIOW# 59 24 PIDE_HCS0# 37 38 PIDE_HCS1#
PIDE_HDREQ HDIOW# VAA1 0.1U_0402_16V4Z R78 37 38
60 HDMARQ VAA2 29 1 2 1 2 @ 10K_0402_5% 39 39 40 40
PIDE_HRESET# 1 2 PIDE_R_HRESET# L25 CHB1608U800_0603
R392 33_0402_5%
16
46
HRESET# Power 25
+5VS 41
43
41 42 42
44
+5VS
HPDIAG# VSS1 43 44
VSS2 30 1 1 1 1
8 C459 C461 JP8
GND_0 2.2U_0603_6.3V6K
45
43
UAO UART GND_1 42
57
UAI GND_2
1

2 2 2 2
C468 C460
88SA8040_TQFP64
R407 0.01U_0402_16V7K 1000P_0402_50V7K
10K_0402_5%
2

R384
+3VS 0_0603_5%
2

1 1 1 36,39 EC_IDERST
C27 C503 C493 +3VALW
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 +3VALW

1
Y3 +3VALW
IDE_XTLIN 1 2 IDE_XTLOUT C710 R832
1 2 0.1U_0402_16V4Z 10K_0402_5%
B @ 25MHZ_12PF_1BG25000CK1B B

14
1

R833 @ 0_0402_5% U13D

14
Place near connector side.

2
U13A 1 2 12

P
R374 A SATA_RST#
1 11

P
25 IDE_HDDRST# A O
@ 0_0402_5% 3 13
O B

G
PLT_RST# 2
6,15,23,25,28,31,35,39 PLT_RST#
2

7
SN74LVC08APW_TSSOP14

7
R372 @ 1M_0402_5%

1 1 SN74LVC08APW_TSSOP14

C470 C439
@ 12P_0402_50V8J @ 12P_0402_50V8J
2 2

+3VS
25MHz reference clock T[4:3] = 01
1

R840
0_0402_5%
X5
2

4 3 IDE_XTLIN
VDD OUT
C370 1U_0603_10V4Z
2 1
U25 1 2
C321 CONT VSS
GM@ 1
+1.8VS 1 5 1 2 OSC 25MHZ SG645PCG
VOUT BP GM@ C862
A A
2 0.1U_0402_16V4Z
GND 0.1U_0402_16V4Z 2
+3VS 3 VIN SHDN# 4 SUSP# 33,39,40,42,47,49
1
1U_0603_10V4Z C369 APL5301-18BC-TR_SOT23-5
GM@ GM@
2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
SATA/PATA-HDD, PATA ODD Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS EAL30 LA-2691 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期四, 三月 03, 2005 Sheet 27 of 52
5 4 3 2 1
 5 4 3 2 1

Reserve for SWDJ

Q58
@ AOS 3401_SOT23

+5VALW 3 1 +5VCD

PJ20

2
2 2 1 1 +5VS
@ JUMP_43X118
R816
D D
+5VALW 1 2
@ 240K_0402_5%

C851 R817 @ 10K_0402_5%

1 2 2 1

1
@ 1U_0603_10V4Z

2 CD_PLAY
CD_PLAY 39
Q59
@ DTC124EK_SC59

3
Placea caps. near CDROM Reserve for SWDJ
+5VCD
CONN.
+3VALW +5VCD
C852
1 1 1 1 2 1

1
G_PCI_RST#
C766 C769 C779 R818
C764 1U_0603_10V4Z 10U_1206_16V4Z @ 0.1U_0402_16V4Z @ 10K_0402_5%

14

1
1000P_0402_50V7K 2 2 2 2 U50A

OE#

2
0.1U_0402_16V4Z IDE_DCS3# 2 3 SW_SD_CS#3
24 IDE_DCS3# I O

G
C @ SN74LVC125APWLE_TSSOP14 C

7
R830 0_0402_5%
1 2
Reserve for SWDJ
CDROM CONN +5VCD
C149

1
2 1 CD_AGND G_PCI_RST#
CD_AGND 36
R819
@ 10K_0402_5%
10U_0805_10V4Z

4
U50B

OE#

2
JP13 IDE_DCS1# 5 6 SW_SD_CS#1
24 IDE_DCS1# I O
INT_CD_L 1 2 INT_CD_R
36 INT_CD_L INT_CD_R 36
3 4
5 6 IDE_DD8 1 2 @ SN74LVC125APWLE_TSSOP14
39 ODD_RST#
IDE_DD7 7 8 IDE_DD9 R102 @ 0_0603_5%
IDE_DD6 9 10 IDE_DD10
IDE_DD5 11 12 IDE_DD11
IDE_DD4 13 14 IDE_DD12
IDE_DD3 15 16 IDE_DD13 R831 0_0402_5%
IDE_DD2 17 18 IDE_DD14 1 2
IDE_DD1 19 20 IDE_DD15
IDE_DD0 21 22 IDE_DDREQ 24
23 24 IDE_DIOR# 24
24 IDE_DIOW# 25 26
B B
24 IDE_DIORDY 27 28 IDE_DDACK# 24
24 IDE_IRQ 29 30
PDIAG# 100K_0402_5%
24 IDE_DA1 31 32 1 R551 2 +5VCD
24 IDE_DA0 33 34 IDE_DA2 24
SW_SD_CS#1 35 36 SW_SD_CS#3
1 2 37 38 W=80mils
+5VCD
R553 100K_0402_5% 39 40
+5VCD Reserve for SWDJ
+5VCD 41 42
43 44 +3VALW
39 SHDD_LED#
45 46
SD_CSEL 47 48

1
49 50 1 2 +5VCD
2

51 52 R564 @ 100K_0402_5% R820

R557 ALLTOP_C12431-1-5001 @ 10K_0402_5%
470_0402_5%

2
G_PCI_RST#
1

1
IDE_DD[0..15] R821 @ 0_0402_5% D
24 IDE_DD[0..15] R_PCIRST# @ 2N7002_SOT23
1 2 2
23,29,31,34,35,39 PCI_RST# G Q60
S

3
6,15,23,25,27,31,35,39 PLT_RST# 1 2
R822 @ 0_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CDROM Connector & Direct CD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 28 of 52
5 4 3 2 1
 5 4 3 2 1

U28 +3V
23,31,34 PCI_AD[0..31]
PCI_AD[0..31] PCI_AD0
PCI_AD1
PCI_AD2
104
103
AD0
AD1
EEDO
AUX/EEDI
108
109
LAN_EEDO
LAN_EEDI
LAN_EECLK
1
R402
2 +3V
LAN_EECS
LAN_EECLK
1
U32
CS VCC 8
LAN RTL8100C(L)
102 AD2 EESK 111 2 SK NC 7 1
PCI_AD3 98 106 LAN_EECS 3.6K_0402_5% LAN_EEDI 3 6
PCI_AD4 AD3 EECS LAN_EEDO DI NC C494
97 AD4 4 DO GND 5
PCI_AD5 96 117 ACTIVITY# 0.1U_0402_16V4Z
PCI_AD6 AD5 LED0 LINK10_100# AT93C46-10SI-2.7_SO8 2
95 AD6 LED1 115
PCI_AD7 93 114
PCI_AD8 AD7 LED2
D
PCI_AD9
90
89
AD8 NC/LED3 113 H=1.98mm D

CLK_PCI_LAN PCI_AD10 AD9 LAN_TD+

87 AD10 TXD+/MDI0+ 1
PCI_AD11 86 2 LAN_TD- U30
AD11 TXD-/MDI0-
1

PCI_AD12 85 5 LAN_RD+
@ PCI_AD13 AD12 RXIN+/MDI1+ LAN_RD- LAN_RD+ RJ45_RX+
83 AD13 RXIN-/MDI1- 6 1 RD+ RX+ 16
R355 PCI_AD14 82 LAN_RD- 2 15 RJ45_RX-
10_0402_5% PCI_AD15 AD14 RD- RX-
79 AD15 NC/MDI2+ 14 3 CT CT 14
PCI_AD16 59 15 4 13
2

PCI_AD17 AD16 NC/MDI2- NC NC

1 58 AD17 NC/MDI3+ 18 5 NC NC 12
@ PCI_AD18 57 19 6 11
C416 PCI_AD19 AD18 NC/MDI3- LAN_TD+ CT CT RJ45_TX+
55 AD19 7 TD+ TX+ 10

1
15P_0402_50V8J PCI_AD20 53 121 LAN_X1 LAN_TD- 8 9 RJ45_TX-
2 PCI_AD21 AD20 X1 LAN_X2 R387 R388 TD- TX-
50 AD21 X2 122

1
PCI I/F
PCI_AD22 49 10mil 49.9_0402_1% 49.9_0402_1%
PCI_AD23 AD22 R356 1
47 AD23 LWAKE 105 2 1K_0402_5% +3VS R385 R386 LF-H80P_16P

1
PCI_AD24 43 23 LAN_ISOLATE# R357 1 2 15K_0402_5% 49.9_0402_1% 49.9_0402_1%

2
PCI_AD25 AD24 ISOLATE# LOAN_RTSET R361 1
42 AD25 RTSET 127 2 5.6K_0603_1%
PCI_AD26 40 72 10mil R354 R353

2
PCI_AD27 AD26 NC/SMBCLK 75_0402_1% 75_0402_1%
39 AD27 NC/SMBDATA 74
PCI_AD28 37

2
PCI_AD29 AD28
36 AD29 NC/M66EN 88 1 1 1
PCI_AD30 34
PCI_AD31 AD30 C469 C464 C463 RJ45_GND
33 AD31 NC/AVDDH 10
120 0.01U_0402_25V7Z 0.01U_0402_25V7Z 0.1U_0402_16V4Z
PCI_CBE#0 NC/HV 2 2 2
23,31,34 PCI_CBE#0 92 C/BE#0
PCI_CBE#1 77 11
23,31,34 PCI_CBE#1 C/BE#1 NC/HSDAC+
PCI_CBE#2 60 123
23,31,34 PCI_CBE#2 C/BE#2 NC/HG
PCI_CBE#3 44 124
23,31,34 PCI_CBE#3 C/BE#3 NC/LG2
126 +LAN_DVDD
PCI_AD17 NC/LV2
1 2 LAN_IDSEL 46 IDSEL
C
R383
23,31,34 PCI_PAR
100_0402_5%
76 PAR
LAN I/F +3V C

23,31,34 PCI_FRAME# 61 FRAME# NC/VSS 9

23,31,34 PCI_IRDY# 63 IRDY# NC/VSS 13
23,31,34 PCI_TRDY# 67 TRDY#

3
68 E
23,31,34 PCI_DEVSEL# DEVSEL#
69 22 CTRL25 2 Q34
23,31,34 PCI_STOP# STOP# NC/GND B
48 2SB1197K_SOT23 Q33
NC/GND C DTA114YKA_SOT23 JP4
70 62 40mil

E
23,31,34 PCI_PERR#

1
PERR# NC/GND
23,31,34 PCI_SERR# 75 SERR# NC/GND 73 +2.5V_LAN +3V 3 1 1 2 10mil 12 Amber LED+

47K
112 1 1 R336

C
NC/GND 300_0402_5%
23 PCI_REQ#3 30 REQ# NC/GND 118 11 Amber LED-

10K
29 C421 C423 16

B
23 PCI_GNT#3 GNT# SHLD4
10U_0805_10V4Z 0.1U_0402_16V4Z 8
2 2 PR4-
25 15

2
23 PCI_PIRQF# INTA# CTRL25 SHLD3
CTRL25 8 7 PR4+
34,39 ONBD_LAN_PME# 31 ACTIVITY#
PME# RJ45_RX-
RTT3/CRTL18 125 6 PR2-
23,28,31,34,35,39 PCI_RST# 27 RST#
VDD33 26 +3V 5 PR3-
CLK_PCI_LAN 28 41
14 CLK_PCI_LAN CLK VDD33
PM_CLKRUN# 65 56 4
25,34,35 PM_CLKRUN# CLKRUN# VDD33 PR3+
VDD33 71
84 RJ45_RX+ 3
VDD33 PR2+
VDD33 94
107 RJ45_TX- 2
VDD33 PR1-
4 GND/VSS SHLD2 14
17 RJ45_TX+ 1
GND/VSS PR1+
128 GND/VSS SHLD1 13
3 +LAN_AVDDL 1 2 +3V 10
AVDD33/AVDDL L24 0_0805_5% Green LED-
7 40mil

E
AVDD33/AVDDL
21 GND/VSSPST AVDD33/AVDDL 20 1 1 1 +3V 3 1 1 2 10mil 9 Green LED+

47K
B 38 16 C419 0.1U_0402_16V4Z C426 R334 B

C
GND/VSSPST NC/AVDDL

1
51 300_0402_5% AMP RJ45/RJ11 with LED
GND/VSSPST

10K
66 0.1U_0402_16V4Z C425 0.1U_0402_16V4Z

B
GND/VSSPST 2 2 2 Q35 R346 R345
Y4 81 32
LAN_X1 LAN_X2 GND/VSSPST VDD25/VDD18 DTA114YKA_SOT23 75_0402_1% 75_0402_1%
91 54

2
GND/VSSPST VDD25/VDD18
101 78

2
GND/VSSPST VDD25/VDD18 +LAN_DVDD LINK10_100#
25MHZ_20P_1BX25000CK1A 119 GND/VSSPST VDD25/VDD18 99 1 2 +2.5V_LAN
1 1 40mil R347 0_0805_5%
Power

1 1 1
C455 C445 35 24 0.1U_0402_16V4Z RJ45_GND 1 2 LANGND
27P_0402_50V8J 27P_0402_50V8J GND NC/VDD18 C482
2 2
52 GND NC/VDD18 45 20mil 1 1
80 64 C471 C4580.1U_0402_16V4Z C403
GND NC/VDD18 2 2 2 1000P_1206_2KV7K C404 C409
100 GND NC/VDD18 110
116 0.1U_0402_16V4Z 4.7U_0805_10V4Z
NC/VDD18 2 2
+3V
12 +2.5V_LAN_VDD 1 2 +2.5V_LAN 0.1U_0402_16V4Z
AVDD25/HSDAC- R348 0_0805_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
20mil 1 1
RTL8100C_QFP128 1 1 1 1 1 1 Termination plane should be closed
C424 C420
0.1U_0402_16V4Z 10U_0805_10V4Z C462 C440 C484 C481 C483 C418 to chassis ground and also depends
2 2 0.1U_0402_16V4Z on safety concern
2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8100CL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 29 of 52
5 4 3 2 1
 A B C D E

+S1_VCC +3VS

1 1

S1_A[0..25]
33 S1_A[0..25]
For Cardbus TI7411 & TI6411

M10
M12
H10
H11
H12

D19
A11

K12

K19
J12
M7

M9
S1_D[0..15]

H8
H9

N7
A5

K8
J8
33 S1_D[0..15]
U43A

VCCA
VCCA

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
S1_D10 D1
S1_D9 A_CAD31/A_D10
C1 A_CAD30/A_D9
S1_D1 D3 N1
A_CAD29/A_D1 DATA DATA_CB 33
S1_D8 C2 L6
A_CAD28/A_D8 CLOCK CLOCK_CB 33
S1_D0 B1 N2
A_CAD27/A_D0 LATCH LATCH_CB 33
S1_A0 B4
S1_A1 A_CAD26/A_A0
A4 A_CAD25/A_A1
S1_A2 E6
S1_A3 A_CAD24/A_A2
B5 A_CAD23/A_A3
S1_A4 C6 B15 +3VS
S1_A5 A_CAD22/A_A4 RSVD 1U_0603_10V4Z
B6 A_CAD21/A_A5 RSVD A16
S1_A6 G9 B16 0.1U_0402_16V4Z 0.1U_0402_16V4Z
S1_A25 A_CAD20/A_A6 RSVD
C7 A_CAD19/A_A25 RSVD A17 1 1 1 2 2
S1_A7 B7 C16
S1_A24 A_CAD18/A_A7 RSVD C708 C740 C707 C729 C722
A7 A_CAD17/A_A24 RSVD D17
S1_A17 A10 C19
S1_IOWR# A_CAD16/A_A17 RSVD 2 2 2 1 1
33 S1_IOWR# E11 A_CAD15/A_IOWR# RSVD D18
S1_A9 G11 E17 0.1U_0402_16V4Z 0.1U_0402_16V4Z
S1_IORD# A_CAD14/A_A9 RSVD
33 S1_IORD# C11 A_CAD13/A_IORD# RSVD E19
S1_A11 B11 G15
S1_OE# A_CAD12/A_A11 RSVD +3VS
33 S1_OE# C12 A_CAD11/A_OE# RSVD F18
S1_CE2# B12 H14
33 S1_CE2# A_CAD10/A_CE2# RSVD
S1_A10 A12 H15 0.1U_0402_16V4Z 0.1U_0402_16V4Z
S1_D15 A_CAD9/A_A10 RSVD
E12 A_CAD8/A_D15 RSVD G17 1 1 1 1 1
2 S1_D7 C757 2
C13 A_CAD7/A_D7 RSVD K17
S1_D13 F12 L13 C172 C754 C759 C714
S1_D6 A_CAD6/A_D13 RSVD 10U_0805_10V4Z
A13 A_CAD5/A_D6 RSVD K18
S1_D12 2 2 2 2 2
C14 A_CAD4/A_D12 RSVD L15
S1_D5 E13 L17 0.1U_0402_16V4Z 0.1U_0402_16V4Z
S1_D11 A_CAD3/A_D5 RSVD
A14 A_CAD2/A_D11 RSVD L18
S1_D4 B14 L19
S1_D3 A_CAD1/A_D4 RSVD
E14 A_CAD0/A_D3 RSVD M17
M14

S1_REG# C5
PCI 7411 RSVD
RSVD M15
N19
+S1_VCC
33 S1_REG# A_CC/BE3#/A_REG# RSVD
S1_A12 F9 N18
S1_A8 A_CC/BE2#/A_A12 RSVD
B10 A_CC/BE1#/A_A8 RSVD N15 1 1 1 1
S1_CE1# G12 M13
33 S1_CE1# A_CC/BE0#/A_CE1# RSVD
P18 C726 C728 C735 C736
S1_A13 RSVD 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
G10 A_CPAR/A_A13 RSVD P17 0.1U_0402_16V4Z
S1_A23 2 2 2 2
C8 A_CFRAME#/A_A23 RSVD P19
S1_A22 A8 F15
S1_A15 A_CTRDY#/A_A22 RSVD
B8 A_CIRDY#/A_A15 RSVD G18
S1_A20 A9 K14
S1_A21 A_CSTOP#/A_A20 RSVD
C9 A_CDEVSEL#/A_A21 RSVD M18
S1_A19 E10 K13
S1_A14 A_CBLOCK#/A_A19 RSVD
F10 A_CPERR#/A_A14 RSVD G19
S1_WAIT# B3 H17
33 S1_WAIT# A_CSERR#/A_WAIT# RSVD
S1_INPACK# E7 J13
33 S1_INPACK# A_CREQ#/A_INPACK# RSVD
S1_WE# B9 J17
33 S1_WE# A_CGNT#/A_WE# RSVD
S1_BVD1 B2 H19
33 S1_BVD1 A_CSTSCHG/A_BVD1(STSCHG/RI) RSVD
S1_WP C3 J19
33 S1_WP A_CCLKRUN#/A_WP(IOIS16) RSVD
S1_A16 2 1 A16_CLK E9 J18
R534 33_0402_5% A_CCLK/A_A16 RSVD
C4 A_CINT#/A_READY(IREQ) RSVD B18
S1_RDY# E18
33 S1_RDY# RSVD
3 S1_RST A6 J15 3
33 S1_RST A_CRST#/A_RESET RSVD
RSVD F14
S1_BVD2 A2 A18 4510_2 2 1
33 S1_BVD2 A_CAUDIO/A_BVD2(SPKR#) RSVD
H18 R542 1K_0402_5%
S1_CD1# RSVD (44+1)10@
33 S1_CD1# C15 A_CCD1#/A_CD1# RSVD B19
S1_CD2# E5 F17
33 S1_CD2# A_CCD2#/A_CD2# RSVD
S1_VS1 A3 C17
33 S1_VS1 A_CVS1/A_VS1# RSVD
S1_VS2 E8 N13 Reserve for TI PCI4510
33 S1_VS2 A_CVS2/A_VS2# RSVD
RSVD B17
S1_D14 B13 C18
S1_D2 A_CRSVD/A_D14 RSVD
D2 F19
S1_A18 C10
A_CRSVD/A_D2
A_CRSVD/A_A18
RSVD
RSVD
RSVD
N17
A15
PCI4510 =one Slot Cardbus + 1394
+3VS 2 1 E2 A_USB_EN# RSVD K15
R504 2 @ 10K_0402_5%
1 E1
R503 @ 10K_0402_5% B_USB_EN#
PCI1510 =one Slot Cardbus
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

7411@ PCI7411GHK_PBGA288
PCI6411 =one Slot Cardbus + 5 in 1
G7
G8
G13
H13
J9
J10
J11
K9
K10
K11
L8
L9
L10
L11
L12
M8

PCI7411 =one Slot Cardbus + 5 in 1 + 1394

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
PCI7411-1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom EAL30 LA-2691 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期四, 三月 03, 2005 Sheet 30 of 52
A B C D E
 A B C D E

+3VS
change 0 ohm
L10 +VDPLL_33
CHB1608U301_0603
1 2 0.01U_0402_16V7K 0.1U_0402_16V4Z C854 (44+1)10@
Place C854 near T18 and T19
1 1 1 1 1 1 2 FILTER1
C210 0.1U_0402_16V4Z
C211 C207 C219 C215
10U_0805_10V4Z C755 7411@
2 2 2 2 2
0.01U_0402_16V7K 0.1U_0402_16V4Z 1 2 Place C755 near T17 and T18
0.1U_0402_16V4Z

1 1

change 0 ohm
2 C704
+3VS +AVDD_7411 +3VS

1U_0603_10V4Z
CHB1608U301_0603
2 1 0.1U_0402_16V4Z 0.01U_0402_16V7K
L8 1 0.1U_0402_16V4Z 0.01U_0402_16V7K 1U_0603_10V4Z
1 1 1 1 1 1 1 1 1 2
C171
C197 C176 C201 C186 C175 C733 C151 C182 C719
2 2 2 2 2 2 2 2 2 1
0.1U_0402_16V4Z 0.01U_0402_16V7K 10U_0805_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K

W10
M19
R13
R14
V17

V19
T18

W3
H1
U43B

VCCP
VCCP
AVDD
AVDD
AVDD

VDPLL_33
VDPLL_15

VR_PORT
VR_PORT
U2 PCI_AD31
AD31 PCI_AD30
AD30 V1
MC_PWR_CTRL_0 F1 V2 PCI_AD29
32 MC_PWR_CTRL_0 MC_PWR_CTRL_0 AD29 PCI_AD[0..31]
1 2 F2 U3 PCI_AD28 PCI_AD[0..31] 23,29,34
R519 @ 0_0402_5% MC_PWR_CTRL_1 AD28 PCI_AD27 +3VS
AD27 W2
SDCD# E3 V3 PCI_AD26
32 SDCD# SD_CD# AD26
MSCD# F5 U4 PCI_AD25
32 MSCD# MS_CD# AD25

1
SMCD# F6 V4 PCI_AD24
32 SMCD# SM_CD# AD24
V5 PCI_AD23 R587
R284 1 5IN1@ 2 33_0402_5% AD23 PCI_AD22
32 MSCLK_SDCLK AD22 U5 120_0402_5%
R104 1 5IN1@ 2 33_0402_5%G5 R6 PCI_AD21 5IN1@
32 SMELWP# MS_CLK/SD_CLK/SM_EL_WP# AD21
MSBS_SDCMD_SMWE2 F3 P6 PCI_AD20
32 MSBS_SDCMD_SMWE2

2 2
MSDATA3_SDDAT3_SMD3 H5 MS_BS/SD_CMD/SM_WE# AD20 PCI_AD19
32 MSDATA3_SDDAT3_SMD3 MS_DATA3/SD_DAT3/SM_D3 AD19 W6
MSDATA2_SDDAT2_SMD2 G3 V6 PCI_AD18
2 32 MSDATA2_SDDAT2_SMD2 MS_DATA2/SD_DAT2/SM_D2 AD18 2
MSDATA1_SDDAT1_SMD1 G2 U6 PCI_AD17 D29
32 MSDATA1_SDDATA1_SMD1 MS_DATA1/SD_DAT1/SM_D1 AD17
MSDATA0_SDDAT0_SMD0 G1 R7 PCI_AD16 HT-110UYG-CT_YEL/GRN
32 MSDATA0_SDDAT0_SMD0 MS_SDIO(DATA0)/SD_DAT0/SM_D0 AD16
V9 PCI_AD15 5IN1@
R514 5IN1@ AD15 PCI_AD14
U9
32 SMRE# 1 2 33_0402_5% J5
AD14
R9 PCI_AD13 5IN1 LED

1
SMALE SD_CLK/SM_RE#/SC_GPIO1 AD13 PCI_AD12
32 SMALE J3 SD_CMD/SM_ALE/SC_GPIO2 AD12 N9
Side View

V-PORT-0603-220 M-V05_0603
SMD4 H3 V10 PCI_AD11
32 SMD4 SD_DAT0/SM_D4/SC_GPIO6 AD11

1
SMD5 J6 U10 PCI_AD10
32 SMD5 SD_DAT1/SM_D5/SC_GPIO5 AD10
SMD6 J1 R10 PCI_AD9
32 SMD6 SD_DAT2/SM_D6/SC_GPIO4 AD9

2
SMD7 J2 N10 PCI_AD8 D9
32 SMD7 SD_DAT3/SM_D7/SC_GPIO3 AD8
SDWP_SMCE# H7 V11 PCI_AD7 10K
32 SDWP_SMCE# SD_WP/SM_CE# AD7
U11 PCI_AD6 5IN1_LED 2
AD6 PCI_AD5
AD5 R11
SMCLE J7 W12 PCI_AD4 Q4
32 SMCLE SM_CLE/SC_GPIO0 AD4
SMRB# K1 V12 PCI_AD3 5IN1@ 47K
32 SMRB#

1
SM_PHYS_WP# SM_R/B AD3 PCI_AD2 DTC114YKA_SC59
32 SM_PHYS_WP# K2 U12

3
SM_PHYS_WP#/SC_FCB AD2 PCI_AD1
AD1 N11
W13 PCI_AD0
AD0
L2 RSVD
K5 @
RSVD
C322 K3 RSVD C/BE3# W4 PCI_CBE#3 23,29,34
R293 +3VS 2 1 K7 W7
RSVD C/BE2# PCI_CBE#2 23,29,34
2 1 2 1 CLK_SD_48M R109 10K_0402_5% L1 W9

@ 15P_0402_50V8J @ 10_0402_5%
L3
L5
RSVD
RSVD PCI7411 C/BE1#
C/BE0# W11
PCI_CBE#1
PCI_CBE#0
23,29,34
23,29,34
33 VCCD1# RSVD
PAR P9 PCI_PAR 23,29,34
1 2 P12 TEST0 FRAME# V7 PCI_FRAME# 23,29,34
R118 1K_0402_5% W17 R8
NC TRDY# PCI_TRDY# 23,29,34
Reserve for TI PCI4510 FILTER1 T19 U7
RSVD IRDY# PCI_IRDY# 23,29,34
1 2 STOP# W8 PCI_STOP# 23,29,34
1K_0402_5% R287(44+1)10@ N8
DEVSEL# PCI_DEVSEL# 23,29,34
CLK_SD_48M M1 W5 PCM_ID 2 1 PCI_AD20
3 14 CLK_SD_48M CLK_48 IDSEL R292 C323 3
V8 100_0402_5% R523
PERR# PCI_PERR# 23,29,34
R552 4.7K_0402_5%
EAL20 CONN 1 +3VS 1 2 R17 PHY_TEST_MA
SERR#
REQ#
U8
U1
PCI_SERR# 23,29,34
PCI_REQ#2 23
1
@
2 1
@
2
2

1394@ T2
GNT# PCI_GNT#2 23 10_0402_5% 15P_0402_50V8J
C750 1394@ 1394@
1U_0603_10V4Z 56.2_0603_1% 56.2_0603_1% R550 6.34K_0402_1% P5 CLK_PCI_PCM
2 PCICLK CLK_PCI_PCM 14
R539 R541 1 2 1394@ U18 R3 R512 2 1 0_0402_5%
R0 PCIRST# PCI_RST# 23,28,29,34,35,39
U19 T1 R513 2 1 @ 0_0402_5% PLT_RST# 6,15,23,25,27,28,35,39
1

FOX_UV31413-4R1-TR TPBIAS0 R1 GRST#

U15 TPBIAS0 RI_OUT#/PME# T3
TPA0+
4 4 TPA0-
V15 TPA0P
6 6 3 3 W15 TPA0N SUSPEND# R2 1 2 +3VS
5 5 TPB0+ R516 4.7K_0402_5%
2 2 TPB0-
V14 TPB0P PCM_SPK#
1 1 W14 TPB0N SPKROUT L7 PCM_SPK# 36
2 1 U17 TPBIAS1
2

1394@ JP20 1 2 C371 1394@ 1U_0603_10V4Z V18 N3 7411_PIRQA#

TPA1P MFUNC0 PCI_PIRQA# 23

2
1394@ R543 1394@ 1K_0402_5% W18 M5 7411_PIRQB#
TPA1N MFUNC1 PCI_PIRQB# 23
Connect To 56.2_0603_1% 56.2_0603_1% 1394@ 1 2 V16 P1 7411_PIRQC# R110
TPB1P MFUNC2 PCI_PIRQC# 23
R535 R536 R540 1394@ 1K_0402_5% W16 P2 33K_0603_1%
Shielding 1 2 M11
TPB1N MFUNC3
P3 7411_PIRQD#
SERIRQ 25,35,39
+AVDD_7411 PCI_PIRQD# 23
1

GND R123 1394@ 1K_0402_5% CPS MFUNC4 5IN1_LED

2 1 P15 N5 5IN1_LED 32

1
R128 1394@ 4.7K_0402_5% CNA MFUNC5
R19 XO MFUNC6 R1 2 1
1 R18 R517 @ 10K_0402_5%
XI
2

R12 PC0(TEST1) SCL M3 1 2

1394@ 1394@ U13 M2 1 R510 2 300_0402_5% 2 1 +3VS
5.11K_0603_1% PC1(TEST2) SDA
VSSPLL
VSSPLL

C730 V13 R518 300_0402_5% R509 10K_0402_5%

2 PC2(TEST3)
AGND
AGND
AGND

R533 220P_0402_50V7K H2
18P_0402_50V8J C761 VR_EN#
1

1394@ 7411@ PCI7411GHK_PBGA288

N12
U14
U16

P14
T17

X3 2
24.576MHz_16P_3XG-24576-43E1 1
R511 C706
1

4 0.1U_0402_16V4Z 4
1K_0402_5%
18P_0402_50V8J C758
2
1

1394@

Security Classification Compal Secret Data Compal Electronics, Inc.

2005/03/01 2006/03/01 Title
PCI1510 & PCI6411 UNMOUNT THOSE PARTS Issued Date Deciphered Date
PCI7411-2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom EAL30 LA-2691 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期四, 三月 03, 2005 Sheet 31 of 52
A B C D E
 5 4 3 2 1

D D

**
+VCC_5IN1 +3VS +3VS +3VS JP15
MSDATA0_SDDAT0_SMD0 34 11 MSDATA3_SDDAT3_SMD3
31 MSDATA0_SDDAT0_SMD0 SM-D0 / XD-D0 SD-DAT3
MSDATA1_SDDAT1_SMD1 33 12 MSDATA2_SDDAT2_SMD2
31 MSDATA1_SDDATA1_SMD1 SM-D1 / XD-D1 SD-DAT2
MSDATA2_SDDAT2_SMD2 32 6 MSDATA1_SDDAT1_SMD1 2.2K_0402_5%
31 MSDATA2_SDDAT2_SMD2 SM-D2 / XD-D2 SD-DAT1 R295
MSDATA3_SDDAT3_SMD3 31 5 IN 1 CONN SD-DAT0 7 MSDATA0_SDDAT0_SMD0 5IN1@
31 MSDATA3_SDDAT3_SMD3 SM-D3 / XD-D3
SMD4 21 5 SDWP_SMCE# 1 2
31 SMD4 SM-D4 / XD-D4 SD-WP-SW
1

2
SMD5 22 10 MSBS_SDCMD_SMWE2
31 SMD5 SM-D5 / XD-D5 SD-CMD
R285 R528 R555 R524 SMD6 23 8 MSCLK_SDCLK
31 SMD6 SM-D6 / XD-D6 SD_CLK MSCLK_SDCLK 31
2.2K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% SMD7 24 9 +VCC_5IN1
31 SMD7 SM-D7 / XD-D7 SD-VCC
5IN1@ @ @ @ 4
@ R298 0_0402_5% SM_WP-IN N/C SDCD#
35 42 SDCD# 31
2

1
SDCD# SM_PHYS_WPS# SM_WP-IN / XD_WP-IN SD-CD-SW
31 SM_PHYS_WP# 1 2 43 SM-WP-SW SD-CD-COM 41
MSBS_SDCMD_SMWE2 36
31 MSBS_SDCMD_SMWE2 #SM_-WE / XD_-WE
MSCD# SMALE 37 15 MSDATA0_SDDAT0_SMD0
31 SMALE #SM-ALE / XD-ALE MS-DATA0
14 MSDATA1_SDDAT1_SMD1
SMCD# MS-DATA1 MSDATA2_SDDAT2_SMD2
25 SM-LVD MS-DATA2 16
SMCD# 3 18 MSDATA3_SDDAT3_SMD3
31 SMCD# SM-CD-SW MS-DATA3
SMRB# +VCC_5IN1 29 19 MSCLK_SDCLK
SMRB# SM_-VCC / XD_-VCC MS-SCLK MSCD#
31 SMRB# 26 #SM_R/-B / XD_R/-B MS-INS 17 MSCD# 31
SMRE# 27 13 MSBS_SDCMD_SMWE2
31 SMRE# #SM_-RE / XD_-RE MS-BS
SDWP_SMCE# 28 20 +VCC_5IN1
31 SDWP_SMCE# #SM_-CE / XD_-CE MS-VCC
SMCD# 2 1 30
R836 @ 0_0402_5% R537 #SM_-CD
2 SM-CD-COM XD-VCC 40
SM_WP-IN 1 2 SM_PHYS_WPS# SMCLE 38 39 SMCD#
31 SMCLE SM-CLE / XD-CLE XD-CD
5IN1@ 0_0402_5% 1
GND
GND 44

TAITW_R007-010-N3 5IN1@
C C
+3VS +3VS
2
***

C316
R286 @
10K_0402_5% @ 0.1U_0402_16V4Z
1

U21
SM_PHYS_WPS# 1
SD/XD/MS/SM PWR SWITCH
P

B
Y 4SM_WP-IN
SMELWP# 2
31 SMELWP# A
G

@ TC7SH08FU_SSOP5
3

+3VS

R837 0_0402_5%
1 2
5IN1@ +VCC_5IN1
2

+VCC_5IN1

1
R526
10K_0402_5% R538
5IN1@ U41 470_0402_5%
1 8 5IN1@
1

GND OUT
2 7

1 2
B 5IN1@ IN OUT 0.1U_0402_16V4Z SMCD# B
3 IN OUT 6 D 2 1
MC_PWR_CTRL_1 1 R530 2 4 5 1 1 R838 @ 0_0402_5%
31 MC_PWR_CTRL_0 EN# FLG 4.7U_0805_10V4Z
C742 2 2 1 MC_PWR_CTRL_0
1

D
1U_0603_10V6K

0_0603_5% 1 G528_SO8 5IN1@ 1U_0603_10V4Z 5IN1@ G R839 5IN1@ 0_0402_5%

2 C743 5IN1@ C739 S Q57
31 5IN1_LED

3
G 5IN1@ 5IN1@ 2 2 2N7002_SOT23
2

Q37 S C718 5IN1@

3

R506 2N7002_SOT23 2
10K_0402_5%
5IN1@
@
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
5IN 1 CON
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 32 of 52
5 4 3 2 1
 5 4 3 2 1

Power Switch for PCMCIA

Power Switch for PCMCIA (PCI7411 & PCI6411 only)

U17

VPPD1 3 20
D 30 DATA_CB DATA 12V D
VCCD0# 4 7
30 CLOCK_CB CLOCK 12V +3VS
VPPD0 JP14
30 LATCH_CB
27,39,40,42,47,49 SUSP#
5
12
LATCH 7464@ CardBus Socket 1 35
RESET# C245 0.1U_0402_16V4Z S1_D3 GND GND S1_CD1#
15 OC# NC3 14 2 1 2 D3 / CAD0 CD1# / CCD1# 36 S1_CD1# 30
+3VS 2 1 21 13 R161 @ 0_1206_5% 7464@ S1_D4 3 37 S1_D11
SHDN# 3.3V D4 / CAD1 D11 / CAD2
1

R177 R176 10K_0402_5% C246 4.7U_0805_10V4Z S1_D5 4 38 S1_D12

47K_0402_5% 7464@ +5VS S1_D6 D5 / CAD3 D12 / CAD4 S1_D13
20mil 5 D6 / CAD5 D13/ CAD6 39
7464@ +S1_VPP 8 24 2 1 S1_D7 6 40 S1_D14
AVPP NC4 R180 @ 0_1206_5% 7464@ S1_CE1# D7 / CAD7 D14/ RFU S1_D15
19 NC0 5V 2 30 S1_CE1# 7 CE1# / CCBE0# D15 / CAD8 41
1 1 C289 0.1U_0402_16V4Z S1_A10 8 42 S1_CE2#
2

+S1_VCC 5V 7464@ S1_OE# A10 / CAD9 CE2# / CAD10 S1_VS1 S1_CE2# 30

30 S1_OE# 9 OE# / CAD11 VS1# / CVS1 43 S1_VS1 30
C262 7464@ 9 11 C269 4.7U_0805_10V4Z S1_A11 10 44 S1_IORD#
AVCC GND S1_A9 A11 / CAD12 IORD# / CAD13 S1_IOWR# S1_IORD# 30
10 AVCC 11 A9 / CAD14 IOWR# /CAD15 45 S1_IOWR# 30
2 1U_0603_10V4Z 2 1 40mil S1_A8 12 46 S1_A17
A8 / CCBE1# A17 / CAD16
0.01U_0402_16V7K

17 23 S1_A13 13 47 S1_A18
C247 NC1 NC5 S1_A14 A13 / CPAR A18 / RFU S1_A19
18 NC2 NC6 22 14 A14 / CPERR# A19 / CBLOCK# 48
7464@ 7464@ 16 S1_WE# 15 49 S1_A20
1 C261 NC7 30 S1_WE# WE# / CGNT# A20 / CSTOP#
10U_0805_10V4Z2 6 S1_RDY# 16 50 S1_A21
NC8 30 S1_RDY# IREQ# / CINT# A21 / CDEVSEL#
+S1_VCC 17 VCC VCC 51 +S1_VCC
+S1_VPP 18 VPP1 VPP2 52 +S1_VPP
TPS2220ADBR_SSOP24 S1_A16 19 53 S1_A22
7464@ S1_A15 A16 / CCLK A22 / CTRDY# S1_A23
20 A15 / CIRDY# A23 / CFRAME# 54
S1_A12 21 55 S1_A24
S1_A7 A12 / CCBE2# A24 / CAD17 S1_A25
22 A7 / CAD18 A25 / CAD19 56
S1_A6 23 57 S1_VS2
S1_A5 A6 / CAD20 VS2# / CVS2 S1_RST S1_VS2 30
24 A5 / CAD21 RESET / CRST# 58 S1_RST 30
S1_A4 25 59 S1_WAIT#
S1_A3 A4 / CAD22 WAIT# / CSERR# S1_INPACK# S1_WAIT# 30
26 A3 / CAD23 INPACK# / CREQ# 60 S1_INPACK# 30
S1_A2 27 61 S1_REG#
S1_A1 A2 / CAD24 REG# / CCBE3# S1_BVD2 S1_REG# 30
28 A1 / CAD25 SPKR# / CAUDIO 62 S1_BVD2 30
S1_A0 29 63 S1_BVD1
C S1_D0 A0 / CAD26 STSCHG# / CSTSCHG S1_D8 S1_BVD1 30 C
30 D0 / CAD27 D8 / CAD28 64
S1_D1 31 65 S1_D9
S1_D2 D1 / CAD29 D9 / CAD30 S1_D10
32 D2 / RFU D10 / CAD31 66
S1_WP 33 67 S1_CD2#
30 S1_WP IOIS16# / CCLKRUN# CD2# / CCD2# S1_CD2# 30
34 GND GND 68

69 GND GND 70
S1_A[0..25] 71 72
30 S1_A[0..25] GND GND
73 GND GND 74
S1_D[0..15] 75 76
30 S1_D[0..15] GND GND
77 GND GND 78
79 GND GND 80
81 GND GND 82
83 GND GND 84
85 GND GND 86
87 GND GND 88

FOX_WZ21131-G2-P4_RT

Power Switch for PCMCIA (PCI1510 & PCI4510 only)

U18 +S1_VCC 2 15PWS@
1 Close to +S1_VCC
B 13 40mil C296 0.1U_0402_16V4Z B
VCC
12 15PWS@ CardBus Conn.
VCC C297 0.1U_0402_16V4Z
9 12V VCC 11
1 2 15PWS@ 1 1 1
C298 10U_0805_10V4Z C756
+S1_VPP 1 2 15PWS@ C753 C752
20mil C302 0.01U_0402_25V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+5VS 2 2 2
VPP 10 1 2 15PWS@
15PWS@ C305 1U_0603_10V4Z
0.1U_0402_16V4Z C304 5 5V
6 5V
4.7U_0805_10V4Z C307
15PWS@ 1 VCCD0#
VCCD0 +S1_VPP
VCCD1 2 VCCD1# 31
15 VPPD0
+3VS VPPD0 VPPD1
VPPD1 14
15PWS@ 1 2

0.01U_0402_16V7K
0.1U_0402_16V4Z C294 3 3.3V C751
4 3.3V OC 8
SHDN

4.7U_0805_10V4Z C292 4.7U_0805_10V4Z

GND

15PWS@ 2 C747 1
2

R182 TPS2211AIDBR_SSOP16
7

16

10K_0402_5% 15PWS@ 15PWS@

1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
PCMCIA Socket
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom EAL30 LA-2691 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期四, 三月 03, 2005 Sheet 33 of 52
5 4 3 2 1
 A B C D E

+3V
+5VS +3VS +3VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1 1 1
C760 C784 C776 KS@ C732 C749 C727 KS@ C748 C738 C121 KS@ C702 C240 C239 KS@
KS@ KS@ 10U_0805_10V4Z KS@ KS@ 4.7U_0805_10V4Z KS@ KS@ KS@ KS@
2 2 2 2 2 2 2 2 2
4.7U_0805_10V4Z 2 2 2
4.7U_0805_10V4Z
1 1
1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K
1000P_0402_50V7K

+3VALW PCI_AD[0..31]
PCI_AD[0..31] 23,29,31
C709 0.1U_0402_16V4Z
KS@

KS@

5
U51 TC7SH08FU_SSOP5 JP11
1 TIP 1 2 RING

P
39 WL_OFF# B 1 2
Y 4 KEY KEY
37,39 KILL_SW# 2 A 3 3 4 4

G
5 5 6 6
7 8

3
7 8
9 9 10 10
D10
11 11 12 12
KS@ 1 2 13 14
RB751V_SOD323 13 14
15 15 16 16
23 PCI_PIRQH# 17 17 18 18 W=40mils +5VS
+3VS W=40mils 19 19 20 20 PCI_PIRQG# 23
21 21 22 22
23 23 24 24 W=40mils +3V
CLK_PCI_MINI 25 26
2 14 CLK_PCI_MINI 25 26 PCI_RST# 23,28,29,31,35,39 2
27 27 28 28 W=40mils +3VS
PCI_REQ#1 29 30 PCI_GNT#1
23 PCI_REQ#1 29 30 PCI_GNT#1 23
31 32 R842 @ 0_0402_5%
PCI_AD31 31 32
33 33 34 34 1 2 MINI_PME# 29,39
PCI_AD29 35 36
35 36 PCI_AD30
37 37 38 38
PCI_AD27 39 40
PCI_AD25 39 40 PCI_AD28
41 41 42 42
43 44 PCI_AD26
43 44 PCI_AD24
23,29,31 PCI_CBE#3 45 45 46 46
CLK_PCI_MINI PCI_AD23 47 48 MINI_IDSEL 1 2 R525 PCI_AD18
47 48 KS@ 100_0402_5%
49 49 50 50
PCI_AD21 51 52 PCI_AD22
51 52
1

PCI_AD19 53 54 PCI_AD20
R494 53 54
55 55 56 56 PCI_PAR 23,29,31
PCI_AD17 57 58 PCI_AD18
@ 10_0402_5% PCI_CBE#2 57 58 PCI_AD16
23,29,31 PCI_CBE#2 59 59 60 60
PCI_IRDY# 61 62
23,29,31 PCI_IRDY#
2

61 62 PCI_FRAME#
1 63 63 64 64 PCI_FRAME# 23,29,31
C699 65 66 PCI_TRDY#
25,29,35 PM_CLKRUN# 65 66 PCI_TRDY# 23,29,31
PCI_SERR# 67 68 PCI_STOP#
23,29,31 PCI_SERR# 67 68 PCI_STOP# 23,29,31
@ 10P_0402_50V8K 69 70
2 PCI_PERR# 69 70 PCI_DEVSEL#
23,29,31 PCI_PERR# 71 71 72 72 PCI_DEVSEL# 23,29,31
PCI_CBE#1 73 74
23,29,31 PCI_CBE#1 PCI_AD14 73 74 PCI_AD15
75 75 76 76
77 78 PCI_AD13
PCI_AD12 77 78 PCI_AD11
79 79 80 80
PCI_AD10 81 82
81 82 PCI_AD9
83 83 84 84
PCI_AD8 85 86 PCI_CBE#0
PCI_AD7 85 86 PCI_CBE#0 23,29,31
87 87 88 88
3 89 90 PCI_AD6 3
PCI_AD5 89 90 PCI_AD4
91 91 92 92
93 94 PCI_AD2
PCI_AD3 93 94 PCI_AD0
95 95 96 96
+5VS W=40mils 97 97 98 98
PCI_AD1 99 100
99 100
101 101 102 102
103 103 104 104
105 105 106 106
107 107 108 108
109 109 110 110
111 111 112 112
113 113 114 114
115 115 116 116
117 117 118 118
119 119 120 120
W=30mils 121 121 122 122 W=40mils
+5VS 123 123 124 124 +3V
KS@ AMP_1318644-1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini PCI Slot
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EAL30 LA-2691
Date: 星期五, 三月 04, 2005 Sheet 34 of 52
A B C D E
 10 9 8 7 6 5 4 3 2 1

SUPER I/O SMsC LPC47N217+3VS FIR Module L: R POP; FIR Enable

H: R De-POPFIR Disable

1 1 1 1
H C59
4.7U_0805_10V4Z SIO@ C70 SIO@ C57 SIO@ C626 SIO@ H

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
+3VS FIR_DET# 1 2
FIR@ R546 0_0402_5%
2 2 2 2 RP5
DCD#1 8 1
RI#1 7 2
DSR#1 6 3
CTS#1 5 4 +3VS
SIO@ +IR_ANODE
4.7K_1206_8P4R_5% 1
1 2
FIR@ C853 R299 4.7_1206_5% FIR@
22U_1206_16V4Z_V1 1 2 W=60mil
2 R300 4.7_1206_5% FIR@

G G
U10 SIO@ 1K_0402_5%
LPC_AD0 10 62 RXD1 R40 1 2 U11
24,39 LPC_AD0 LPC_AD1 LAD0 RXD1 TXD1

SERIAL I/F
24,39 LPC_AD1 12 LAD1 TXD1 63 IRED_A 1
LPC_AD2 13 64 DSR#1 +IR_3VS 2 3 T = 12mil IRTXOUT
24,39 LPC_AD2 LPC_AD3 LAD2 DSR1# RTS#1 IRRX IRED_C TXD IRMODE
24,39 LPC_AD3 14 LAD3 RTS1# 1 4 RXD SD/MODE 5 T = 12mil
2 CTS#1 +3VS 2 1 +IR_3VS 6 7
LPC_FRAME# CTS1# DTR#1 FIR@ R549 VCC MODE
24,39 LPC_FRAME# LPC_DRQ#1
15 LFRAME# DTR1# 3
RI#1 47_1206_5%
W=40mil 8 GND
24 LPC_DRQ#1 16 LDRQ# RI1# 4 1 1

LPC I/F
R57 10_0402_5%2 5 DCD#1 C388 C387 TFDU6102-TR3_8P FIR@
3,28,29,31,34,39 PCI_RST# R58 DCD1#
1 2@ 0_0402_5% 17 PCI_RESET#
FIR@ FIR@
3,25,27,28,31,39 PLT_RST# R56 1 SIO@ 2 10K_0402_5% SIO_PD# 18 37 IRRX 1 2 10U_0805_10V4Z 0.1U_0402_16V4Z
+3VS LPCPD# IRRX2 IRTXOUT R48 SIO@ 2 2
FIR IRTX2 38
PM_CLKRUN# 19 39 IRMODE 10K_0402_5%
25,29,34 PM_CLKRUN# CLK_PCI_SIO CLKRUN# IRMODE/IRRX3
14 CLK_PCI_SIO 20 PCI_CLK
SERIRQ 21 41 LPTINIT#
F 25,31,39 SERIRQ SER_IRQ INIT# F
1 2 SIO_PME# 6 42 LPTSLCTIN#
+3VS R37 SIO@ 10K_0402_5% IO_PME# SLCTIN# LPD0
PD0 44
CLK_14M_SIO 9 46 LPD1
14 CLK_14M_SIO CLK14 PD1 LPD2
CLOCK PD2 47
23 48 LPD3
GPIO40 PD3
Parallel Port

PARALLEL I/F
R67 100K_0402_5% NOT-FIR@ 24 49 LPD4
GPIO41 PD4 LPD5
+3VS 2 1 25 GPIO42 PD5 50
27 51 LPD6
FIR_DET# GPIO43 PD6 LPD7 +5V_PRN

GPIO
28 GPIO44 PD7 53
29 55 LPTSLCT D19
LPT_DET# GPIO45 SLCT LPTPE W=20mil
30 GPIO46 PE 56 +5VS 2 1
R193 100K_0402_5% NOT-PIO@ 31 57 LPTBUSY PIO@
GPIO47 BUSY LPTACK#
+3VS 2 1 32 GPIO10 ACK# 58 RB420D_SOT23 1

1
R53 2 1 1K_0402_5% SIO_GPIO11 33 59 LPTERR# PIO@
SIO@ R51 1 SIO@ SIO_SMI# GPIO11/SYSOPT ERROR# LPTAFD#
+3VS 2 10K_0402_5% 34 GPIO12/IO_SMI# ALF# 60 R308 C394 RP40
R50 1 SIO@ 2 10K_0402_5% SIO_IRQ 35 61 LPTSTB# PIO@ 0.1U_0402_16V4Z
E GPIO13/IRQIN1 STROBE# 2 E
36 2.2K_0402_5% LPD3 1 8 F D3
GPIO14/IRQIN2 LPD2 F D2
40 2 7

2
GPIO23 LPD1 F D1
W=20mil LPD0
3 6
F D0
8 VSS VTR 7 +3VS 4 5
22 11 LPTSTB# 1 2 +5V_PRN_R
VSS VCC PIO@ R307 33_0402_5% PIO@ 33_1206_8P4R_5%
43 VSS POWER VCC 26
52 45 JP2
VSS VCC RP43
VCC 54
1 LPD7 1 8 F D7
CLK_14M_SIO CLK_PCI_SIO LPC47N217_STQFP64 SIO@ LPTAFD# 1 2 AFD/3M# 14 LPD6 2 7 F D6
PIO@ R304 33_0402_5% F D0 2 LPD5 3 6 F D5
2

Base I/O Address LPTERR# 15 LPD4 4 5 F D4

R52 R72 * 0 = 02Eh F D1 3
10_0402_5% 33_0402_5% 1 = 04Eh LPT_INIT# 16 PIO@ 33_1206_8P4R_5%
@ @ F D2 4
D SLCTIN# 17 LPTINIT# 1 2 LPT_INIT# D
1

2 2 F D3 5 PIO@ R306 33_0402_5%

18
C88 C101 F D4 6 LPTSLCTIN# 1 2 SLCTIN#
@ 15P_0402_50V8J @ 22P_0402_50V8J 19 PIO@ R305 33_0402_5%
1 1 F D5 7
20
F D6 8
21 +5V_PRN
F D7 9
22
LPTACK# 10 RP41 CP2
23 1 8 F D0 AFD/3M# 1 8
LPTBUSY 11 2 7 F D1 LPTERR# 2 7
24 3 6 F D2 LPT_INIT# 3 6
C LPTPE 12 4 5 F D3 SLCTIN# 4 5 C
25 PIO@
LPTSLCT 13 PIO@ 2.7K_1206_8P4R_5% 220P_1206_8P4C_50V8K

RP42 CP4
PIO@ FOX_DZ11391-H7 1 8 F D7 LPTACK# 1 8
2 7 F D6 LPTBUSY 2 7
3 6 F D5 LPTPE 3 6
4 5 F D4 LPTSLCT 4 5
PIO@
PIO@ 2.7K_1206_8P4R_5% 220P_1206_8P4C_50V8K
L: R POP; PIO Enable
H: R De-POP PIO Disable RP39 CP3
1 8 SLCTIN# F D0 1 8
2 7 LPT_INIT# F D1 2 7
3 6 LPTERR# F D2 3 6
B Place on the TOP side(Under MDC conn.) 4 5 AFD/3M# F D3 4 5 B
LPT_DET# 1 2 PIO@
PIO@ R68 0_0402_5% PIO@ 2.7K_1206_8P4R_5% 220P_1206_8P4C_50V8K
+5VS
RP44 CP1
1 8 LPTACK# F D4 1 8
JP10 2 7 LPTBUSY F D5 2 7
1 3 6 LPTPE F D6 3 6
1 LPTSLCT F D7
2 2 4 5 4 5
RXD1 3 PIO@
TXD1 3 PIO@ 2.7K_1206_8P4R_5% 220P_1206_8P4C_50V8K
4 4
DSR#1 5
RTS#1 5
6 6
CTS#1 7
DTR#1 7
8
A RI#1 9
8
9
Security Classification Compal Secret Data Compal Electronics, Inc. A
DCD#1 10 2005/03/01 2006/03/01 Title
10 Issued Date Deciphered Date
@ E&T_96212-1011S
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SMsC LAP47N217 SIO,PIO,FIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
For SW debug use when no seial port Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EAL30 LA-2691
Date: 星期五, 三月 04, 2005 Sheet 35 of 52
10 9 8 7 6 5 4 3 2 1
 A B C D E F G H

+AVDD_AC97 +AC97_DVDD
L30
AC97 Codec +5VAMP 1 2
1 2
@ L31 0_0805_5%
+3VS
0_0805_5% 1 2 +3V
L29 1 1 0_0805_5%
INT_CD_L 2 1 CD_L 1 1
28 INT_CD_L
R579 20K_0402_5% C765 C807
INT_CD_R2 1 CD_R 0.1U_0402_16V4Z 10U_0805_10V4Z C770 C792
28 INT_CD_R 2 2 10U_0805_10V4Z
R583 20K_0402_5% 0.1U_0402_16V4Z
CD_GNA 2 2
2 1
28 CD_AGND R581 20K_0402_5%

25

38
2

9
R589 R582 R580 R584 1 2

6.8K_0402_5%

6.8K_0402_5%
C778 @ 1000P_0402_50V7K

6.8K_0402_5%

AVDD1

AVDD2

DVDD1

DVDD2
1 0_0402_5% 1
1 2
C774 @ 1000P_0402_50V7K

2
1

14 35 LINEL 1 2 AMP_LEFT
AUX_L LINE_OUT_L C777 1U_0402_6.3V4Z AMP_LEFT 37
15 36 LINER 1 2 AMP_RIGHT
AUX_R LINE_OUT_R C775 1U_0402_6.3V4Z AMP_RIGHT 37
39 SPEAKER_ID
SPEAKER_ID 16 37
NBA_PLUG JD2 MONO_OUT/VREFOUT3
37 NBA_PLUG
1 2 17 JD1 HP_OUT_L 39
C812 1U_0402_6.3V4Z
bypass EQ when NBA_PLUG = High 1 2 23 41 C788 @ 47P_0402_50V8J
C809 0.1U_0402_16V4Z LINE_IN_L HP_OUT_R
2 1
1 2 24 LINE_IN_R
C810 0.1U_0402_16V4Z 6 1 2
BIT_CLK AC97_BITCLK 24
CD_L 2 1 CD_LIN 18 R570 22_0402_5%
C800 1U_0402_6.3V4Z CD_L
SDATA_IN 8 1 2 AC97_SDIN0 24
CD_R 2 1 CD_R IN 20 R572 22_0402_5% R801
C802 1U_0402_6.3V4Z CD_R XTL_IN
XTL_IN 2 1 2 0_0402_5% CLK_14M_CODEC 14
CD_GNA 2 1 CD_GNA1 19
C801 1U_0402_6.3V4Z CD_GND
MIC 2 1 C_MIC 21
37 MIC MIC1
C803 1U_0402_6.3V4Z
22 3 XTL_OUT +AVDD_AC97
MIC2 XTL_OUT
2 1 13 PHONE AFILT1 29 1 2

2
C806 1U_0402_6.3V4Z C791 1000P_0402_50V7K
MONO_IN 12 30 1 2 @
PC_BEEP AFILT2 C789 1000P_0402_50V7K R574
Use to isolate +5VALW and +AC97_DVDD
28 +VREFOUT 1 2 1M_0402_5%
VREFOUT +AUD_VREF
AC97_RST# 1 2 11 R573 0_0603_5%
24 AC97_RST#

1
R576 22_0402_5% RESET#
2 1 VREF 27
2 R823@ 10K_0402_5% AC97_SYNC 2
24 AC97_SYNC 2 1 10 SYNC
+AC97_DVDD 2 1 R575 22_0402_5% 32
R824@ 1K_0402_5% AC97_SDOUT 2 DCVOL
24 AC97_SDOUT 1 5 SDATA_OUT

0.01U_0402_16V7K

1U_0402_6.3V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z
R569 22_0402_5%
2

Q61 EC_SM_D2
G

45 SDA NC 31 1 1 1 1
@ 2N7002_SOT23 46 33 C785 C786 C793 C794
XTLSEL VREFOUT2

1U_0402_6.3V4Z
1 3 EC_SM_D2 34
4,39 EC_SMD_2 VAUX

1
47 43 R567
D

37,39 EAPD SPDIFI/EAPD DISABLE# 1 2 2 2 2

0_0402_5%
44 EC_SM_C2
SCK
1

1 2 48 @
R825 @ 0_0402_5% R562 SPDIFO C787
NC 40
0_0402_5% 2
2 1 Ra 4 26

2
R826@ 10K_0402_5% DVSS1 AVSS1 AGND
7 DVSS2 AVSS2 42
+AC97_DVDD 2 1
2

R827@ 1K_0402_5% U45 ALC250-VD_LQFP48

DGND AGND 1 2 +3VS
2

Q62 R563 10K_0402_5%

G

@ 2N7002_SOT23
Place these components
UnPoped:Clock source from X'tal
4,39 EC_SMC_2 1 3 EC_SM_C2
Poped: Clock source from Clock Gen
close to Codec 1 2 EC_IDERST 27,39
R828 0_0402_5%
D

1 2 1 2
R829 @ 0_0402_5% R566 @ 1M_0402_5%
X4
XTL_IN 2 1 XTL_OUT
22P_0402_50V8J

22P_0402_50V8J
24.576MHz_16P_3XG-24576-43E1 C796 4.7U_0805_10V4Z
1 @ 1 +AUD_VREF 1 2
C773 C781
1 2
2 2 C790 0.1U_0402_16V4Z
3 3
@ @

+AVDD_AC97

MDC Connector
1

System Sound R577

10K_0402_5%
+3V 2 1
0_0805_5% R132 2 JP16 L12
2

+5VS_MDC 1 2 +5VS
1 C193 1 2 2 0_0603_5%
MONO_OUT/PC_BEEP AUDIO_PWRDN/DETECH
1

C325 R188 C821

+3V_MDC
10U_0805_10V4Z 3 GND MONO_PHONE 4
R588 10U_0805_10V4Z 1 C228 1U_0603_10V4Z
39 BEEP# 1 2 1 2 5 AUXA_RIGHT RESERVED/BT_ON# 6
10K_0402_5% 0_0603_5% 7 8
2 AUXA_LEFT GND 1
1U_0402_6.3V4Z 560_0402_5%
+3VS 1 2+3VS_MDC 9 CD_GND +5Vmain 10
L9 2 11 12
2

C805 CD_RIGHT RESERVED/USB+ R149

13 CD_LEFT RESERVED/USB- 14
MONO_IN_O 2 1 MONO_IN C192 15 16 +3VS_MDC_R 1 2
GND RESERVED/PRIMARY_DN +3VS
10U_0805_10V4Z 17 18 10K_0402_5%
1U_0402_6.3V4Z 1 +3.3Vaux/BT_VCC RESERVED/+5VD/WAKEUP
19 GND RESERVED/GND 20
R547 21 22 R554 1 2 0_0402_5% AC97_SYNC
+3.3Vmain AC97_SYNC
2

R189 AC97_SDOUT 1 2 0_0402_5% 23 24 2 1 1 2

AC97_SDATA_OUT AC97_SDATA_IN1 AC97_SDIN1 24
1

C326 C Q42 R586 AC97_RST# 1 2 0_0402_5% 25 26 R148 0_0402_5% R151 22_0402_5%

MONO_IN_I R548 AC97_RESET# AC97_SDATA_IN0
31 PCM_SPK# 1 2 1 2 2 27 GND GND 28
2.4K_0402_5%

B 29 30 R147 1 2 22_0402_5% AC97_BITCLK

AC97_MSTRCLK AC97_BITCLK
2SC2411K_SC59

2 1U_0402_6.3V4Z 560_0402_5% E
3

C866 ACES_88018-3010
4 4
0.01U_0402_16V7K
1

C327 R190
25 SB_SPKR 1 2 1 2

1U_0402_6.3V4Z 560_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
1

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

R191 D17
10K_0402_5% RB751V_SOD323
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AC97 CODEC ALC250 Ver.C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2

1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 36 of 52
A B C D E F G H
 A B C D E

+5VAMP

1
R592
100K_0402_5%
Audio Board Connector
Audio AMP

2
+5VAMP SHUTDOWN#

2N7002_SOT23 JP22

1
W=40Mil D
+5VAMP 1 1 13 13
Q41 2 EC_MUTE 39 NBA_PLUG 2 14
1 G VOL_AMP 2 14 1
1 1 3 3 15 15
S +AUD_VREF 4 16

3
C293 C826 4 16
5 5 17 17

1
0.1U_0402_16V4Z 4.7U_0805_10V4Z D MIC
36 MIC 6 6 18 18
2 2 Q24 2 EAPD 36,39 7 7 19 19
fo=1/(2*3.14*R*C)=260Hz G INTSPK_R1 8 20
@ 2N7002_SOT23 INTSPK_L1 8 20
R=1.5K / C=0.47U S 9 21

3
9 21
10 10 22 22
39 WL_LED# 11 11 23 23
HIGH PIN 10,4 ACTIVE 34,39 KILL_SW# 12 24
U16 12 24
Pin 22
LOW PIN 9,5 ACTIVE 7 22 ACES_85203-1202
PVDD SHUTDOWN# NBA_PLUG
18 PVDD SE/BTL# 15
19 VDD PC-BEEP 14 1 2
11 C268 0.1U_0402_16V4Z
36 NBA_PLUG BYPASS
NBA_PLUG 2 9 INTSPK_L2
VOL_AMP HP/LINE# LOUT- INTSPK_R2
2 1 3 VOLUME ROUT- 16
C265 0.1U_0402_16V4Z INTSPK_L1 4 10
INTSPK_R1 LOUT+ LIN
21 ROUT+ RIN 8
AMP_LEFT 1 2 AMP_L 1 2 AMP_LIN 5
36 AMP_LEFT LLINEIN
C270 0.47U_0603_16V4Z C266 0.47U_0603_16V4Z AMP_RIN 23 1
RLINEIN GND

0.47U_0603_16V4Z

0.47U_0603_16V4Z

0.47U_0603_16V4Z
AMP_RIGHT 1 2 AMP_R 1 2 6 12
36 AMP_RIGHT LHPIN GND
C824 0.47U_0603_16V4Z C828 0.47U_0603_16V4Z 20 13 2 1 1
AMP_LEFT HP_L RHPIN GND
1 2 GND 24
C271 0.47U_0603_16V4Z 17
AMP_RIGHT HP_R CLK C301 C299 C300
1 2
C829 0.47U_0603_16V4Z TPA0232PWP_TSSOP24 1 2 2
1
C328
1.5K_0402_5% 2 1 R178 AMP_L
2
0.047U_0402_16V4Z
(0.47U~1U)
Speaker Connector
1.5K_0402_5% 2 1 R591 AMP_R
2 2

change 0 ohm
JP21
INTSPK_R1 L37 1 2 FBM-11-160808-121-T_0603
INTSPK_R2 L36 FBM-11-160808-121-T_0603 1
1 2 2
INTSPK_L1 L35 1 2 FBM-11-160808-121-T_0603
Regulator for AMP INTSPK_L2 L34 1 2 FBM-11-160808-121-T_0603 3
4
ACES_85204-0400

2
+5VALW DECOUPLING D39
+5VALW TO +5VLDO D38 @ @ SM05_SOT23
SM05_SOT23

+5VALWP

1
+5VALWP
3

R184 10K_0402_5%
22U_1206_16V4Z_V1

1 2 2
22U_1206_16V4Z_V1

1U_0603_10V4Z

1U_0603_10V4Z
1
Q12
C303 1 1 1 1
1U_0603_10V4Z AOS 3401_SOT23 C291 C290
1

2 C306 C295
3 @ 3
+5VALW_LDO 2 2 2 2
Moat Bridge
5
6
7
8

+5VALWP +12VALW
U15
D
D
D
D

SI4800DY_SO8
1

R183 R171
G
S
S
S

(4.5V)
10K_0402_5% 1K_0402_5%
4
3
2
1

+5VLDO DECOUPLING
2

+5VLDO
1

D
1U_0805_25V4Z

1
2 Q13 C264 +5VLDO (4.5V)
G 1 2
S 2N7002_SOT23 @ R179 0_0805_5%
3

2
1 2
1

D
0.1U_0402_10V6K
22U_1206_16V4Z_V1

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1U_0603_10V4Z

0.1U_0402_16V4Z

R590 R561 0_0805_5%

1U_0603_10V4Z

2 LM431SB_SOT23 1 2
38,39,42,49 SYSON
G 3.9K_0603_1% R571 0_0805_5%
Q14 S 2 1 1 1 1 1 1 1
3

2N7002_SOT23 K C804 C822 C813 C819 C820

C825 C827
1 A @ @ @
2 2 2 2 2 2 2
R 3
1

D12 R593

4.99K_0603_1%
2

4 4

+5VAMP TO +5VLDO
L32
+5VLDO 1 2 +5VAMP
Security Classification Compal Secret Data Compal Electronics, Inc.
0_0805_5% 2005/03/01 2006/03/01 Title
Issued Date Deciphered Date
L33
AMP & Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0_0805_5% Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 37 of 52
A B C D E
 +3VALW
LID Switch ON/OFF BUTTON for ON/OFF switch KSI[0..7]
KSI[0..7] 39

INT_KBD CONN.

1
KSO[0..15]
+3VALW KSO[0..15] 39
R319

100K_0402_5% DAN202U_SC70
KEYBOARD CONN.

1
D22

2
2 SW1 R194 ACES_88172-3400
39 LID_SW#
1 1 2 100K_0402_5%
S4_LID_SW# 3 37 38
BTN TOP

1
D28 34 NUM_LED#
NUM_LED# 39

2
2 ON/OFFBTN# PADS_LED#
33
ON/OFFBTN# 39 39 PADS_LED#
D5 1 3 1 3 ON /OFF 1 32 CAPS_LED#
CAPS_LED# 39
V-PORT-0603-220 M-V05_0603 3 4 3 51_ON# 2 R181 1 31
51_ON# 43 +3VS
@ ESE11MV9_4P 2 4 2 4 300_0402_5% 30 KSO15
+3VALW DAN202U_SC70 KSO14 29

2
SW2 SW3 28 KSO10

6
5

6
5
KSO11 27

1
@ SMT1-05_4P @ SMT1-05_4P 1 26 KSO8

1
R219 D13 KSO9 25
4.7K_0402_5% Q15 RLZ20A_LL34 24 KSO13
C329 KSI7 23
2 0.01U_0402_16V7K

DTC124EK_SC59
22 KSO3

2
1 R220 2 2 KSO7 21
39 EC_ON 0_0402_5% KSO12
SW/LED Connector 20
C229 0.1U_0402_16V4Z KSI4 19
1 2 18 KSI6
JP17 KSI5 17

3
1 16 KSO6
1 +5V

1
D KSO5
2 2 MODE_LED# 39 15
3 Q16 2 14 KSI3
3 HDD_LED# 39
4 PWR_LED# G KSI0 13
4 PWR_SUSP_LED @ 2N7002_SOT23 WHEN R=0,Vbe=1.35V KSO0
5 S 12

3
5 EC_STOPBTN# WHEN R=33K,Vbe=0.8V KSO1
6 6 KSI1 39 11
7 EC_PLAYBTN# 10 KSI1
7 KSI0 39
8 EC_FRDBTN# KSI2 9
8 KSI3 39
9 EC_REVBTN# 8 KSO2
9 KSI2 39 D11
10 EC_UTXD/KSO17 KSO4 7
10 KSO17 39
11 11 3 51_ON# 6 1 R174 2 +3VS
12 MUL_KEY_ESD# 1 5 300_0402_5%
12 ON /OFF
13 13 2 MUL_KEY# MUL_KEY# 39 +5V 1 2 4
14 C867 @ 470P_0402_50V7K 3
14 MODE_LED# R173
DAN202U_SC70 1 2 2
ACES_85203-1402 C868 @ 470P_0402_50V7K 2 1 1
HDD_LED# +3VS 300_0402_5%
1 2 35 36
+5VS C869 @ 470P_0402_50V7K
PWR_LED# 1 2 JP19
2 C870 @ 470P_0402_50V7K
C249 PWR_SUSP_LED 1 2
C871 @ 470P_0402_50V7K
0.1U_0402_16V4Z EC_STOPBTN# 1 2
1 C872 @ 470P_0402_50V7K
Touch Pad Connector EC_PLAYBTN# 1 2
ACES_85203-1202 C873 @ 470P_0402_50V7K
24 12 EC_FRDBTN# 1 2
24 12 C874 @ 470P_0402_50V7K
23 23 11 11 TP_CLK 39
22 10 EC_REVBTN# 1 2 2 1PADS_LED# NUM_LED# 1 2
22 10 TP_DATA 39 C875 @ 470P_0402_50V7K 100P_0402_50V8J C287 C288 100P_0402_50V8J
21 21 9 9 +5VS
20 8 EC_UTXD/KSO17 1 2 2 1 KSO14 CAPS_LED# 1 2
20 8 +5V C876 @ 470P_0402_50V7K 100P_0402_50V8J C284 C286 100P_0402_50V8J
19 19 7 7 +5VALW
18 6 MUL_KEY_ESD# 1 2 2 1 KSO11 KSO15 1 2
18 6 ACIN 25,39,43
17 5 PWR_LED# C877 @ 470P_0402_50V7K 100P_0402_50V8J C282 C285 100P_0402_50V8J
17 5 POWER_LED# 39
16 4 PWR_SUSP_LED ON /OFF 1 2 2 1 KSO9 KSO10 1 2
16 4 SUSP_LED 39
15 3 C878 @ 470P_0402_50V7K 1 2 100P_0402_50V8J C281 C283 100P_0402_50V8J
15 3 BATT_CHGI_LED# 39
14 2 @ R297 0_0805_5% 2 1 KSI7 KSO8 1 2
14 2 BATT_LOW_LED# 39
13 1 100P_0402_50V8J C280 C260 100P_0402_50V8J
13 1
2 1 KSO7 KSO13 1 2
JP18 AO3402_SOT23 100P_0402_50V8J C279 C259 100P_0402_50V8J
Q17 2 1 KSI4 KSO3 1 2
100P_0402_50V8J C278 C258 100P_0402_50V8J
2 1 KSI5 KSO12 1 2
Battery mode Hibernation 100P_0402_50V8J C277 C257 100P_0402_50V8J

S
+5VALW 1 3 +5V
2 1 KSO5 KSI6 1 2
RTCVREF 100P_0402_50V8J C272 C256 100P_0402_50V8J
1
RTCVREF C330 2 1 KSI0 KSO6 1 2

G
2
100P_0402_50V8J C276 C255 100P_0402_50V8J
RTCVREF 0.1U_0402_16V4Z 2 1 KSO1 KSI3 1 2
42 SUSON 2 100P_0402_50V8J C275 C254 100P_0402_50V8J
680K_0402_5% C331 0.1U_0402_16V4Z 2 1 KSI2 KSO0 1 2
1

1 2 ON /OFF 100P_0402_50V8J C274 C253 100P_0402_50V8J

1

D18 2 1 KSO4 KSI1 1 2

R195 R196 R197 1N4148_SOD80 100P_0402_50V8J C273 C252 100P_0402_50V8J
1 KSO2 1 2
5

3
100K_0402_5% 100K_0402_5% U19 C251 100P_0402_50V8J
2

D C858 D34
P
2

1 2 2 4 1 2 2 Q43 220P_0402_50V7K PSOT24C_SOT23

A Y R198 G 2N7002_SOT23 2
1

D C372 1U_0603_10V6K 10K_0402_5% S

3

S4_LID_SW# 2 Q44 NC7SZ14M5X_SOT23-5

Power OK Circuit
3

G 2N7002_SOT23
S
3

+3VS
1

37,39,42,49 SYSON 2 +3VALW +3VALW

G

1
Q45 S C332
3

2N7002_SOT23 R199 1 2
330K_0402_5%

14

14
RTCVREF 1 2 1 2 U48A U48B 0.1U_0402_16V4Z
R200 C366 1U_0603_10V4Z

P
2
10K_0402_5% 1 2 3 4
RTCVREF I O I O SYS_PWROK 25

G
R221 U47 0.1U_0402_16V4Z 1

1
1 2 1 14 1 2

7
10K_0402_5% CD1# VCC C333 C364 SN74LVC14APWLE_TSSOP14 R222
2 D1 CD2# 13
3 12 1U_0603_10V6K 100K_0402_5%
39 S4_LATCH CP1 D2 2
RTCVREF 1 2 4 11 @
R201 SD1# CP2 SN74LVC14APWLE_TSSOP14
5 10
1 Pull Low

2
10K_0402_5% C365 Q1 SD2#
6 Q1# Q2 09
7 08
1U_0805_25V4Z @ GND Q2# at SB
2 74LCX74MTC_TSSOP14
220P_0402_50V7K
+3VALW 1 2 1
R202 Q18
Security Classification Compal Secret Data Compal Electronics, Inc.
1

10K_0402_5% D15 D C341

2 1 D_SET_S4 2 2005/03/01 2006/03/01 Title
39 S4_DATA
G 2 Issued Date Deciphered Date
RB751V_SOD323 2N7002_SOT23 S S4R,LID,PIO,SYS CONN
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 38 of 52
 A B C D E

+3VALW +EC_RTCVCC
+EC_AVCC
1
R223
2
0_0402_5%
+3VALW
JP24 For EC Tools
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z 1 2 1
+3VALW +RTCVCC 1 +3VALW
1 1 1 1 1 1 2 R224 @ 0_0402_5% JP26 2
2

ECAGND
C367 C342 C343 C344 C368 C347 C373
For ENE KB910 Rev.B4 1 1
E51_RXD
+3VALW 3 3
E51_TXD
2 2 4 4
1U_0603_10V4Z 3 E51_TXD 5
2 2 2 2 2 2 1 3 5
4 4 6 6
7 7

123
136
157
166

161

159
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z @ ACES_85205-0400 E51_RXD

16
34
45

95

96
8 8
U33 9
9
15 10

VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCA

AGND

VCCBAT

BATGND
L15 24,35 LPC_AD0 LAD0 10
1 2 14 49 KSO0
+3VALW +EC_AVCC 24,35 LPC_AD1 LAD1 GPOK0/KSO0
FBM-L11-160808-800LMT_0603 2 1 13 50 KSO1 @ E&T_96212-1011S
24,35 LPC_AD2 LAD2 GPOK1/KSO1
10 51 KSO2
1 C348 24,35 LPC_AD3 LAD3 GPOK2/KSO2 +3VALW 1
C345 KSO3
0.1U_0402_16V4Z
24,35 LPC_FRAME#
LRST#
9 LFRAME# LPC Interface GPOK3/KSO3 52
KSO4
165 LRST#/GPIO2C GPOK4/KSO4 53
1 2

ENE-KB910-B4
CLK_PCI_LPC 18 56 KSO5 KSO[0..15]
L16 14 CLK_PCI_LPC LCLK GPOK5/KSO5 KSO[0..15] 38
1 2 ECAGND 7 57 KSO6 KBA5 1 2
25,31,35 SERIRQ SERIRQ GPOK6/KSO6 KSI[0..7]
FBM-L11-160808-800LMT_0603 1000P_0402_50V7K SKU_ID1 25 58 KSO7 KSI[0..7] 38 R225 1K_0402_5%
CLKRUN#/GPIO0C * GPOK7/KSO7 KSO8 KBA4
24 LPCPD#/GPIO0B * GPOK8/KSO8 59 1 2
60 KSO9 ADB[0..7] R226 1K_0402_5%
GPOK9/KSO9 ADB[0..7] 40
FREAD# 150 61 KSO10 KBA1 1 2
+5VS 40 FREAD# RD# GPOK10/KSO10 KBA[0..19]
FW R# KSO11 R227 1K_0402_5%

Internal Keyboard
40 FWR# 151 WR# GPOK11/KSO11 64 KBA[0..19] 40
FSEL# 173 65 KSO12
40 FSEL# MEMCS# GPOK12/KSO12
1 2 PSCLK1 SELIO# 152 IOCS# GPOK13/KSO13 66 KSO13
R807 10K_0402_5% ADB0 138 67 KSO14
D0 GPOK14/KSO14
1 2 PSDATA1 ADB1 139 D1 GPOK15/KSO15 68 KSO15
R808 10K_0402_5% ADB2 140 153 1 2
D2 GPOK16/KSO16
1 2 TP_DATA ADB3 141 D3 GPOK17/KSO17 154 KSO17
KSO17 38
R228 @ 10K_0402_5%
R809 10K_0402_5% ADB4 144 1 2
D4
1 2 TP_CLK ADB5 145 D5 GPIK0/KSI0 71 KSI0 R229 @ 10K_0402_5%

X-BUS Interface
R810 10K_0402_5% ADB6 146 72 KSI1
D6 GPIK1/KSI1
1 2 PSDATA2 ADB7 147 D7 GPIK2/KSI2 73 KSI2
R231 10K_0402_5% KBA0 124 74 KSI3
A0 GPIK3/KSI3
1 2 PSCLK2 KBA1 125 A1/XIOP_TP GPIK4/KSI4 77 KSI4 SKU_ID0 1 2
R233 10K_0402_5% KBA2 126 78 KSI5 R230 10K_0402_5%
KBA3 A2 GPIK5/KSI5 KSI6 SKU_ID1
127 A3 GPIK6/KSI6 79 1 2
KBA4 128 80 KSI7 R232 10K_0402_5%
KBA5 A4/DMRP_TP GPIK7/KSI7
131 A5/EMWB_TP
KBA6 132 32
A6 GPOW0/PWM0 INVT_PWM 21
R234 1 2 0_0402_5% LRST# KBA7 133 33
23,28,29,31,34,35 PCI_RST# A7 GPOW1/PWM1 BEEP# 36
KBA8 143 36
A8 FAN2PWM/GPOW2/PWM2 SUSP_LED 38
R235 1 2 @ 0_0402_5% KBA9 142 37
5,23,25,27,28,31,35 PLT_RST# A9 GPOW3/PWM3 ACOFF 45
KBA10 135 Pulse Width GPOW4/PWM4 38 EC dont use this function
KBA11 A10
134 A11 GPOW5/PWM5 39 EC_ON 38
2 KBA12 2
130 A12 GPOW6/PWM6 40 EC_LID_OUT# 25 R239
KBA13 129 43 EC_MUTE 37 10K_0402_5%
KBA14 A13 FAN1PWM/GPOW7/PWM7
121 A14 2 1 +3VALW
KBA15 120 2
+3VALW A15 GPWU0 ON/OFFBTN# 38
KBA16 113 26 ACIN_D 2 1
A16 GPWU1 ACIN 25,38,43
KBA17 112 29 RB751V_SOD323 D16
A17 GPWU2 KILL_SW# 34,37
1 2 FSEL# KBA18 104 30
A18 GPWU3 PM_SLP_S3# 25
R236 10K_0402_5% KBA19 103 Wake Up Pin 44
A19 GPWU4 PM_SLP_S5# 25
1 2 MUL_KEY# 108 76
A20/GPIO23 GPWU5 IDE_ODDRST# 25
R237 10K_0402_5% +3VALW R595 2 1 10K_0402_5% EC_TINIT# 105 172 PCI_PME#
E51CS#/GPIO20/ISPEN TIN1/GPWU6 PCI_PME# 29,34
1 2 FREAD# 176
TIN2/FANFB2/GPWU7 BATT_TEMP 44
R596 10K_0402_5% PSCLK1 110
EC_SMI# PSDATA1 PSCLK1 ECAGND
1 2 111 PSDAT1 GPIAD0/AD0 81 1 2 R238
R203 10K_0402_5% PSCLK2 114 82 SKU_ID0 C334 0.01U_0402_16V7K ADP_IR 1 2
PSCLK2 GPIAD1/AD1 ADP_I 45
SELIO# PSDATA2
1
R241
2
10K_0402_5% TP_CLK
115 PSDAT2PS2 Interface GPIAD2/AD2 83 BATT_OVP 45 10K_0402_5%
38 TP_CLK 116 PSCLK3 GPIAD3/AD3 84
+5VALWP TP_DATA 117 Analog To Digital 87 1
38 TP_DATA PSDAT3 GPIAD4/AD4 LI/NIMH# 44
GPIAD5/AD5 88
1 2 EC_SMD_2 EC_SMC_1 163 89 AD_BID0 C374
40,44 EC_SMC_1 SCL1 GPIAD6/AD6 0.22U_0603_16V7K
R811 10K_0402_5% EC_SMD_1 164 90 ADP_IR
40,44 EC_SMD_1 SDA1 GPIAD7/AD7 2
1 2 EC_SMC_2 EC_SMC_2 169 SMBus
4,36 EC_SMC_2 SCL2
R812 10K_0402_5% 4,36 EC_SMD_2 EC_SMD_2 170 99
SDA2 GPODA0/DA0 DAC_BRIG 21
1 2 EC_SMC_1 100
R813 10K_0402_5% GPODA1/DA1
8 101
1 2 EC_SMD_1
25 EC_SCI# 20
GPIO04
GPIO07
GPODA2/DA2
GPODA3/DA3 102
IREF 45
EN_DFAN1 4
Board ID
R814 10K_0402_5% SPEAKER_ID 21 Digital To Analog 1 CD_PLAY
36 SPEAKER_ID GPIO08 GPODA4/DA4 CD_PLAY 28 +3VALW
22 42 CD_PLAY
ENBKL GPIO09 GPODA5/DA5
7,15 ENBKL 27 GPIO0D GPODA6/DA6 47 EC_IDERST 27,36
21 BKOFF# 28 GPIO0E GPODA7/DA7 174

1
45 FSTCHG 48 GPIO10
EC_SMI# 62 85 D40 R594
3
25 EC_SMI#
63
GPIO13 * GPIO18/XIO8CS# 86
POWER_LED# 38
@ SM05_SOT23 Ra 10K_0402_5% 3
28 ODD_RST# GPIO14 * GPIO19/XIO9CS# WL_LED# 37
34 WL_OFF# 69 GPIO15 91 HDD_LED# 38
* GPIO1A/XIOACS#
70 GPIO 92 BATT_LOW_LED# 38

2
+3VALW 25 EC_SWI# GPIO16 * GPIO1B/XIOBCS# AD_BID0
38 S4_LATCH 75 Expanded I/O * GPIO1C/XIOCCS# 93 BATT_CHGI_LED# 38

1
GPIO17
38 S4_DATA 109 GPIO24 94 MODE_LED# 38
* GPIO1D/XIODCS#

1
1 2 LID_SW# LID_SW# 118 97
R205 20K_0402_5%
38
38
LID_SW#
MUL_KEY#
MUL_KEY# 119
GPIO25
GPIO26
* GPIO1E/XIOECS#
* GPIO1F/XIOFCS#
98 * Rb R204
148 0_0402_5%
37,38,42,49 SYSON GPIO27 FANSPEED1 4
27,33,40,42,47,49 SUSP# 149 GPIO28 GPIO2E/TOUT1/FANFB1 171
CLK_PCI_LPC 155 12 1K_0402_5% 1 2 R169
50 VR_ON

2
GPIO29 DPLL_TP/GPIO06/FANFB3 1K_0402_5% 1
156 GPIO2A FANTEST_TP/GPIO05/FAN3PWM 11 2 R175 +3VALW
162 GPIO2B
1

25 PBTN_OUT# 168 GPIO2D 175 EC_THERM# 25

Timer Pin TOUT2/GPIO2F

1
R399
PADS_LED# 55 3 R84
38 PADS_LED# FnLock#/GPIO12 * E51IT0/GPIO00 EC_RSMRST# 25
@ 10_0402_5% CAPS_LED# 54 4 100K_0402_5%
38 CAPS_LED# CapLock#/GPIO011 * E51IT1/GPIO01 SHDD_LED# 28
NUM_LED# 23 106 E51_RXD 1 2 EAPD 36,37
38 NUM_LED#
2

R172 PHDD_LED# NumLock#/GPIO0A * E51RXD/GPIO21/ISPCLK E51_TXD R242 0_0402_5%

1 24 PHDD_LED# 41 107

2
C476 EC_RST# ScrollLock#/GPIO0F * E51TXD/GPIO22/ISPDAT
+3VALW 1 2 19 ECRST# MISC
47K_0402_5% 5 158 CRY1
24 EC_GA20 GA20/GPIO02 XCLKI
@ 10P_0402_50V8K 2 1 6 160 CRY2 R165 2 1
2 24 EC_KBRST# KBRST#/GPIO03 XCLKO 29,34 MINI_PME#
C335 31 @ 20M_0603_5%
GND
GND
GND
GND
GND
GND

ECSCI#

10P_0402_50V8K
0.1U_0402_16V4Z 1 R163 2
0_0402_5% 29,34 ONBD_LAN_PME#
1 1

10P_0402_50V8K
KB910Q B4_LQFP176 C336 C337
17
35
46
122
137
167

1
Y2 PCI_PME#

OUT

IN
2 2

NC

NC
4 4

2
32.768KHZ_12.5P_1TJS125DJ2A073

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB910(LPC)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 39 of 52
A B C D E
 5 4 3 2 1

14
U48C

14
U13C

P
9 6 5

P
A O I SB_INT_FLASH_SEL# 25
INT_FLASH_SEL 8
O

G
B 10 SN74LVC14APWLE_TSSOP14

G
SN74LVC08APW_TSSOP14

7
SUS_STAT# 25

7
D D

+3VALW

14
U23B
4 FSEL# 39

P
INT_FSEL# A
6 O
5 INT_FLASH_EN#
B

G
SN74LVC32APWLE_TSSOP14 2 1 R289

7
100K_0402_5%
2 1 C318
KBA[0..19] 0.1U_0402_16V4Z
39 KBA[0..19]
ADB[0..7]
39 ADB[0..7]

1MBU38Flash ROM +3VALW

KBA0 21 31
KBA1 A0 VCC0
20 A1 VCC1 30 1
KBA2 19
KBA3 A2 C113
18 A3
KBA4 17 25 ADB0 0.1U_0402_16V4Z
KBA5 A4 D0 ADB1 2
16 A5 D1 26
KBA6 15 27 ADB2
KBA7 A6 D2 ADB3
14 A7 D3 28
KBA8 8 32 ADB4
KBA9 A8 D4 ADB5 +3VALW
7 A9 D5 33
C KBA10 ADB6 C
36 A10 D6 34
KBA11 6 35 ADB7
A11 D7

20K_0402_5%
KBA12 5 A12

1
KBA13 4 +3VALW
KBA14 A13 RESET# R207
3 A14 RP# 10 1 2 +3VALW SUSP# 27,33,39,42,47,49
KBA15 2 11 R87 100K_0402_5%
A15 NC

2
KBA16 Q19

G
14
1 A16 READY/BUSY# 12
KBA17 40 29 U23A 2N7002_SOT23

2
KBA18 A17 NC0
13 38 1 1 3

P
KBA19 A18 NC1 FWE# A EC_FLASH# 25
37 3

S
A19 O
B 2

G
INT_FSEL# 22
FREAD# CE# SN74LVC32APWLE_TSSOP14
24 23

7
39 FREAD# FWE# OE# GND0
9 WE# GND1 39
FWR# 39
SST39VF080-70_TSOP40

+3VALW +3VALW
1MB ROM Socket
B B
1

JP9
1 2 C311 R186 KBA16 KBA17
0.1U_0402_16V4Z 100K_0402_5% KBA15 1 2
KBA14 3 4
U20 KBA13 5 6 KBA19
2

KBA12 7 8 KBA10
8 VCC A0 1 9 10
7 2 KBA11 ADB7
WP A1 KBA9 11 12 ADB6
39,44 EC_SMC_1 6 SCL A2 3 13 14
5 4 KBA8 ADB5
39,44 EC_SMD_1 SDA GND 15 16
FWE# ADB4
AT24C16N-10SI-2.7_SO8 RESET# 17 18
19 20 +3VALW
INT_FLASH_EN#
INT_FLASH_SEL 21 22
KBA18 23 24 ADB3
KBA7 25 26 ADB2
27 28
1

KBA6 ADB1
R185 KBA5 29 30 ADB0
KBA4 31 32 FREAD#
100K_0402_5% KBA3 33 34
KBA2 35 36 FSEL#
2

KBA1 37 38 KBA0
39 40
@ SUYIN_80065AR-040G2T

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS/WL-SW/Screw Hole/USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 40 of 52
5 4 3 2 1
 +USB_VCCA +3VALW +USB_VCCC +3VALW

1
R17 R598
U29 U46 100K_0402_5%
1 8 100K_0402_5% 1 8
GND OUT GND OUT
+5VALWP 2 7 +5VALWP 2 7

2
IN OUT R16 R15 IN OUT R597 R599
3 IN OUT 6 USB_OC#2 25 3 IN OUT 6
SYSON# 4 5 1 2 1 2 SYSON# 4 5 1 2 1 2
42 SYSON# EN# FLG USB_OC#0 25 EN# FLG USB_OC#4 25
1 1
C443 G528_SO8 @ 0_0402_5% 47K_0402_5% C830 G528_SO8 @ 0_0402_5% 47K_0402_5%
1 1
4.7U_0805_10V4Z C13 4.7U_0805_10V4Z C831
2 2
+3VALW
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
Close to JP21

14
Close to JP20 U48D

P
9 I O 8

G
USB CONN. 3 SN74LVC14APWLE_TSSOP14

7
USB CONN. 1 USB CONN. 2
+USB_VCCA +USB_VCCA +USB_VCCC +3VALW
W=40mils W=40mils W=40mils

14
1 1 1 U23C
1 1 1 1 1 1 9

P
C431 + C406 C411 C405 C410 + C430 C309 + C308 C310 A
O 8
150U_D2_6.3VM 150U_D2_6.3VM 10 B

G
0.1U_0402_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 0.1U_0402_16V4Z 150U_D2_6.3VM 0.1U_0402_16V4Z 1000P_0402_50V7K
2 2 2 2 2 2 2 2 2 SN74LVC32APWLE_TSSOP14

7
JP5 JP23
5 VCC VCC 1 1 +3VALW
25 USB20_N0 6 D1- D0- 2 USB20_N2 25 25 USB20_N4 2
25 USB20_P0 7 D1+ D0+ 3 USB20_P2 25 25 USB20_P4 3

14
8 VSS VSS 4 4
3

2
C408
1 1 C407 1 C413 1 C414 1 C833 1 C832 U23D
10P_0402_50V8K

10P_0402_50V8K

10P_0402_50V8K

10P_0402_50V8K

10P_0402_50V8K

10P_0402_50V8K
D35 9 10 D36 D37 SUYIN_2569A-04G3T 12

P
@ SM05_SOT23 G1 G2 @ SM05_SOT23 @ SM05_SOT23 A
11 G3 G4 12 O 11
@ @ @ @ @ @ 13 B

G
2 2 SUYIN_020122MR008S540ZU 2 2 2 2
SN74LVC32APWLE_TSSOP14
1

10
U50C

OE#
9 I O 8

@ SN74LVC125APWLE_TSSOP14

13
U50D

OE#
12 I O 11

@ SN74LVC125APWLE_TSSOP14

H13 H12 H11 H21 H20 H24 H23 H25 H5 H8 H2

H_S315D126 H_S315D126 H_S315D126 H_S315D126 H_S315D126 H_S315D126 H_S315D126 H_S315D126 H_S315D161 H_S315D161 H_S315D161
FD4 FD3 FD1 FD2 FD5 FD6 CF11 CF20 CF1
1 1 1 @ @ @ @ @ @ @ @ @ @ @
@ @ @ @ @ @ @ @ @
1

1
1

CF21 CF15 CF4 CF18 CF13 CF8 CF5 CF22 CF3 CF16 H26 H27 H28 H29
1 1 1 1 1 1 1 1 1 1 H4 H9 H22 H10 H3 H7 H_C315D157 H_C315D157 H_C315D161
H_C315D161
@ @ @ @ @ @ @ @ @ @ H_O126X157D126X157N H_C126D126N H_C126D126N H_O157X126D157X126N H_T256D161 H_T256D161
@ @ @ @
@ @ @ @ @ @

1
CF9 CF19 CF6 CF17 CF12 CF14 CF10 CF2 CF7
1

1
1 1 1 1 1 1 1 1 1
@ @ @ @ @ @ @ @ @

H16 H17 H18 H19

H_C394D122 H_C394D122 H_C394D122 H_C394D122 H15 H14 H6 H1
H_O79X126D40X87 H_O79X126D40X87 H_S276D118 H_S276D118
@ @ @ @
@ @ @ @
1

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS/WL-SW/Screw Hole/USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 41 of 52
 A B C D E

+3VALW to +3V Transfer +5VALW to +5VS Transfer

+5VALW +5VS
+3VALW +3V
U14
U42 +12VALW 8 1
1 +12VALW D S 1
8 D S 1 7 D S 2
7 D S 2 1 6 D S 3

1
1 1 6 D S 3 5 D G 4 1 1

1
C376 5 4 1 1 R208 C384 C377 R209
R210 D G C354 C378 R211 100K_0402_5% SI4800DY_SO8 C353 470_0402_5%
100K_0402_5% SI4800DY_SO8 470_0402_5% 2 10U_0805_10V4Z 10U_0805_10V4Z
2 10U_0805_10V4Z 2 2

0.1U_0402_16V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

1 2
2 2
2

1 2
5VS_ON D
SUSON D Q20
38 SUSON 2 SUSP +5VALW
2 SYSON# 1 2N7002_SOT23 G

1
G D C355
1 S

3
1

1
D Q26 C356 Q21 SUSP Q25
S 2

3
SYSON# 2 2N7002_SOT23 G 2N7002_SOT23 0.01U_0402_16V7K R212
G 0.01U_0402_16V7K S 2 100K_0402_5%

3
S 2N7002_SOT23 2
3

2
SYSON#
41 SYSON#

1
D
+3VALW to +3VS Transfer 37,38,39,49 SYSON
SYSON 2
G
Q27
2N7002_SOT23
S

3
+3VALW +3VS

U39
+12VALW 8
7
D S 1
2
+1.5VALW to +1.5VS Transfer
2 D S 2
1 6 D S 3
1

1
5 4 1 1 +5VALW
R213 C379 D G R214
100K_0402_5% SI4800DY_SO8 C357 C380 470_0402_5%

1
2 10U_0805_10V4Z 10U_0805_10V4Z +1.5VALW +1.5VS
2 2 R215
2

1 2
U3 100K_0402_5%
RUNON D
8 D S 1
0.1U_0402_16V4Z 2 SUSP 7 2

2
D S

1
1 G 6 3 1 1
D S
1

D C358 Q28 R216

S
3 5 D G 4
SUSP 2 Q11 2N7002_SOT23 C17 C16 @ 470_0402_5% SUSP
48 SUSP
G 2N7002_SOT23 0.1U_0402_16V4Z 1 1 1 SI4800DY_SO8 22U_1206_16V4Z_V1
S 2 C10 C12 2 2
0.1U_0402_16V4Z
3

1
C11 D
10U_0805_10V4Z 10U_0805_10V4Z 2 Q40
27,33,39,40,47,49 SUSP#

1
2 2 2 D G 2N7002_SOT23
Q22
2 SUSP S

3
10U_0805_10V4Z RUNON G @ 2N7002_SOT23
S

3
3 3

+2.5V to +2.5VS Transfer

+2.5V +2.5VS

U49
8 D S 1
7 D S 2
1 6 D S 3
1

5 D G 4 1 1
C381 R217
SI4800DY_SO8 C359 C382
2 10U_0805_10V4Z @ 470_0402_5%
2 2
1 2

10U_0805_10V4Z RUNON
D
0.1U_0402_16V4Z 2 SUSP
G Q23
S @ 2N7002_SOT23
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EAL30 LA-2691
Date: 星期四, 三月 03, 2005 Sheet 42 of 52
A B C D E
 A B C D

VS

VIN VIN
1 2
PF1 PL1 PR1 1M_0402_1%

1
DC_IN_S1 1 2 DC_IN_S2 1 2

1
VS PR2
PJP1 7A_24VDC_429007 FBM-L18-453215-900LMA90T_1812 PR3
5.6K_0402_5%

1
1 1 84.5K_0402_1% 1 2

2
ACIN 25,38,39

1
6 G PC1 PR4

8
5 G 1000P_0402_50V7K PC2 PC3 PC4 PU1A 1K_0402_5%

2
4 2 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 1 2 3

P
G

2
2 +
3 G PR5 22K_0402_1% 1 PACIN
1
O PACIN 45,46 1

2 -

G
1

1
SINGA_2DC-G213-B20 PR6 LM393M_SO8 PD1

4
PC5 PC6 PR7
1000P_0402_50V7K 20K_0402_1% 0.1U_0402_16V7K 10K_0402_5%

2
RLZ4.3B_LL34

2
PR8
2 1
Vin Detector
RTCVREF
10K_0402_5%
VIN 3.3V High 18.384 17.901 17.430
Low 17.728 17.257 16.976

2
PD2

1N4148_SOD80

1
PD3
BATT+ 2 1

1
1N4148_SOD80 PR9
VS
PQ1 47_1206_5% 1 2
TP0610K_SOT23 PR10

2
1K_1206_5%
CHGRTCP 1 2 N1 3 1
PR11
200_0603_5% PD4
1

2 1 N3 1 2
VIN B+
1

1
2
PR13 PR12 2

PC7 PC8 1N4148_SOD80 1K_1206_5%

100K_0402_5% 0.22U_1206_25V7M 0.1U_0603_25V7K
2

2
2

38 51_ON# 1 2 1 2
PR14 22K_0402_5% PR15
1K_1206_5%
1

RTCVREF
PR16
PU2

1
S-812C33AUA-C2N-T2_SOT89 200_0603_5% 1 2 2 1
VL PR17 100K_0402_5% PR18 2.2M_0402_5% PR19
3.3V
2

PR20 PR21 499K_0402_1%

1 2 1 2 3 2 N2
+CHGRTC OUT IN
1

2
1

8
200_0603_5% 200_0603_5% PD5 PD6 PU1B
1

GND PC9 RLZ16B_LL34 2 5

P
PC10 1U_0805_25V4Z 24,44,46 MAINPWON 1 7
+
2

10U_0805_10V4Z 1 O
3 6 2 PR22 1 VL
45 ACON
2

1
G
LM393M_SO8

1
RB715F_SOT323 34K_0402_1% PR23

4
1

1
PC11
PJ21 PC13 PR24 499K_0402_1% 1000P_0402_50V7K

2
2 1 PC12 1000P_0402_50V7K 66.5K_0402_1% PR25

2
2 1 1000P_0402_50V7K 191K_0402_1%

2
@ JUMP_43X118

2
PJ1 PJ2
3 +3VALWP 2 2 1 1 +3VALW +1.8VSP 2 2 1 1 +1.8VS 3

@ JUMP_43X118 @ JUMP_43X118
(5A,200mils ,Via NO.= 10) (1A,40mils ,Via NO.= 2)

1
PJ3 D
+5VALWP 2 1 +5VALW PJ4 PQ2
2 2 1 PACIN
2 1 2N7002_SOT23
G PR26 47K_0402_5%
@ JUMP_43X118
+1.5VALWP 2 2 1 1 +1.5VALW Precharge detector S

3
@ JUMP_43X118
(5A,200mils ,Via NO.= 10)
(3.5A,140mils ,Via NO.= 7)
15.97V/14.84V FOR
PJ5

1
2 1
ADAPTOR PQ3
+12VALWP 2 1 +12VALW
DTC115EUA_SC70
@ PJ6
JUMP_43X39
+1.25VSP 2 2 1 1 +1.25VS 2 +5VALWP
(120mA,40mils ,Via NO.= 2)
@ JUMP_43X118
PJ7 (2A,80mils ,Via NO.= 4)
+2.5VP 2 1 +2.5V

3
2 1
@ JUMP_43X118 PJ8
+1.2VSP 2 2 1 1 +1.2VS
(8A,320mils ,Via NO.= 16)
@ JUMP_43X118
(2A,80mils ,Via NO.= 4)
PJ11
+1.05VSP 2 1 +1.05VS PJ9
2 1
+VGA_COREP 2 2 1 1 +VGA_CORE
@JUMP_43X118
(3.5A,140mils ,Via NO.= 7) @ JUMP_43X118
4 4

PJ10
2 2 1 1

@ JUMP_43X118

(11A,440mils ,Via NO.= 22)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期五, 三月 04, 2005 Sheet 43 of 52
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 84 degree C
Recovery at 45 degree C

VMB VL VS VL
1 1

PF2
PJP2 12A_65VDC_451012

2
BATT_S1 1 2 1 PL2 2
BATT+
1 1K_0402_5% FBM-L18-453215-900LMA90T_1812 PR27
BATT+

1
2 ALI/NIMH# 1 PR28 2
ID AB/I PR29 2 PH1 PC14 47K_0402_1%
B/I 3 1 +3VALWP MAINPWON 24,43,46

1
4 TS_A 47K_0402_5% 0.1U_0603_25V7K

1
TS EC_SMDA PC15 PC16 PR30
SMD 5

1
6 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7Z 10KB_0603_1%_TH11-3H103FT 1 2

2
SMC PR31 47K_0402_1% PQ4
8 GND GND- 7

8
9 1K_0402_5% PR32 DTC115EUA_SC70
GND PU3A PD7
1 2 3

P
2
16.9K_0402_1% +
1 2 1 2

2
O

2
SUYIN_200275MR007G170ZR TM_REF1 2 -

G
PR33 PR34 1SS355_SOD323
100_0402_5% 100_0402_5% LM393M_SO8

4
1

3
LI/NIMH# 39
1

1
PC17
PR36
PR35 PR37
2 1 0.22U_0805_16V7K_V2 3.32K_0402_1% 2 1
+3VALWP VL

1
100K_0402_1%
PC18

2
6.49K_0402_1%
1

PR38 1000P_0402_50V7K

1
1K_0402_5%
PR39
2

100K_0402_1%
2 2

2
BATT_TEMP 39

EC_SMD_1 39,40 PH2 near main Battery CONN :

EC_SMC_1 39,40 BAT. thermal protection at 79 degree C
Recovery at 45 degree C

VL VL

2
PH2 PR40
47K_0402_1%
10KB_0603_1%_TH11-3H103FT
PR41

1
1 2
47K_0402_1%
PR42

8
3 3

14.7K_0402_1% PU3B
1 2 5 PD8

P
+
O 7 2 1
TM_REF1 6 -

G
1SS355_SOD323

1
PC19 PR43 LM393M_SO8

4
0.22U_0805_16V7K_V2 3.48K_0402_1%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期五, 三月 04, 2005 Sheet 44 of 52
A B C D
 A B C D

Iadp=0~3.52A B+ PQ5
P2 P3 AO4407_SO8
PQ6 PQ7 1 8
2 7
AO4407_SO8 AO4407_SO8 PR44 3 6
VIN 8 1 1 8 2 1 5
7 2 2 7 1 PL3 2 B++
6 3 3 6 0.02_2512_1% FBM-L18-453215-900LMA90T_1812

4
5 5

1
PC20 PC21 PC22

4
4.7U_1206_25V6K 4.7U_1206_25V6K 4.7U_1206_25V6K

2
1
1 1

PR45
1

3
PR46 PQ8 200K_0402_1%
47K_0402_5% DTA144EUA_SC70 PR47

2
47K

1
1 2 VIN
2 PC23 PU4 47K_0402_5%
47K

2
0.1U_0603_25V7K 1 -INC2 24
39 ADP_I
2

2
+INC2

3
2
1
PR48
PQ9 10K_0402_5%
2 1 2 23 AO4407_SO8
OUTC2 GND
1

PR49 100K_0402_5% PC24 N18 4 ACOFF#

1

1
0.022U_0402_16V7K
3 22 CS 1 2
+INE2 CS

1
PQ10
2 PC25

1
DTC115EUA_SC70 4 21 1 2
-INE2 VCC(o)

1
0.1U_0402_16V7K PR50

5
6
7
8
1
PC27 PR52 0.1U_0603_25V7K 2 ACOFF 39
1

D PC26 PR51 25.5K_0402_1% 1 2 1 2 5 20

3

PQ12 PR53 10K_0402_1% 10K_0402_5% FB2 OUT PQ11

2

2
G 2N7002_SOT23 150K_0402_1% 4700P_0402_25V7K

2
S 6 19 1 2 LXCHRG DTC115EUA_SC70
3

3
VREF VH PC28
2

1
PC29 PC30 PR54 0.1U_0603_25V7K
PD12 0.1U_0402_16V7K 1 2 1 2 7 18 1 2
ACOFF#1 1K_0402_5% FB1 VCC PC31
2
CC=0.5~2.7A
2
1000P_0402_50V7K 0.1U_0603_25V7K
1SS355_SOD323 8 17 1 2
-INE1 RT PR55 CV=16.8V(12 CELLS LI-ION)
205K_0402_1% 68K_0402_5%
1

2 D 2

39 IREF 1 2 9 +INE1 -INE3 16

PACIN 1 2 2 PQ13 PR56 PL4 PR58
43,46 PACIN
PR57 G 2N7002_SOT23 PR60 PC32 1 2 1 2 BATT+
3K_0402_1% S 2 1 10 15 1 2 1 2 16UH_D104C-919AS-160M_3.7A_20%
3

OUTC1 FB3
1

1 PR59 10K_0402_5% 47K_0402_5% 0.02_2512_1%

PR61 1500P_0402_50V7K 4.7U_1206_25V6K
ACON PC33 11 14 ACON
43 ACON OUTD CTL

1
100K_0402_1% PD13 PC34 PC35 PC36
2
2

0.1U_0402_16V7K 12 13 EC31QS04 4.7U_1206_25V6K 4.7U_1206_25V6K

2
-INC1 +INC1
IREF=1.31*Icharge

2
MB3887_SSOP24
IREF=0.73~3.3V

+3VALWP
CS
PR62 PR63
4.2V
1

2 1 2 1
1

PR64
47K_0402_5% PQ14 95.3K_0603_0.1% 143K_0603_0.1%
DTC115EUA_SC70
PR65
2

2 2 1
1

95.3K_0603_0.1%
PQ15
DTC115EUA_SC70 65W UMA 75W M22/M24
3

3
39 FSTCHG 2 3
VMB Iadp=2.87A Iadp=3.52A
PR50=33.2K PR50=25.5K
3

PR66
340K_0402_1%
2

OVP voltage : LI
1

4S2P : 17.4V--> BATT_OVP= 1.935V +12VALWP PR67

499K_0402_1%
(BAT_OVP=0.1111 *VMB)
2
8

PU5A
LM358A_SO8 3
P

+
1 0
39 BATT_OVP 2
-
G
4
1

PR68
1

PR69 PC37

2.2K_0402_5% 0.01U_0402_25V7Z
2

105K_0402_1%
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期五, 三月 04, 2005 Sheet 45 of 52
A B C D
 5 4 3 2 1

PC38
N4 1 2

1
PD14
4.7U_1206_25V6K

2
PC39
B+++ 470P_0805_100V7K EC11FS2_SOD106

1
PJ17 1 2 PC40 BST31 BST51

2
2 1 0.1U_0603_25V7K SNB 2 1 FLYBACK
D B+ 2 1 D
PR70 22_1206_5%

2
@ JUMP_43X118 PT1

8
7
6
5
1

1 PC42 PQ16

D
D
D
D

2
PC41 SI4800DY-T1_SO8 PD15
4.7U_1206_25V6K VS
2

4.7U_1206_25V6K DAP202U_SOT323 1 2 PC43 10uH_SDT-1205P-100-118_5A_20%

3
G
S
S
S
0.1U_0603_25V7K B+++

1
2
3
4

1
PD16 VL
PLX3

5
6
7
8
1SS355_SOD323 +12VALWP PQ17

8
7
6
5

D
D
D
D
1

1
PQ18 SI4800DY-T1_SO8

D
D
D
D

1
SI4810DY_SO8 PC44 PC45

1
PC46 4.7U_1206_25V6K 4.7U_1206_25V6K

2
1

G
S
S
S
4.7U_0805_6.3V6K PR71

1
G
S
S
S
PC47

4
3
2
1
0.1U_0603_25V7K PC48 1.27K_0402_1%
1
2
3
4

2
1

PC49 4.7U_1206_25V6K

PDH3

2
1

47P_0402_50V8J PDL3
PL6 PDH5

5
6
7
8

1
10UH_D104C-919AS-100M_4.5A_20% PR72
2

2 1 PC50

D
D
D
D
1.87K_0402_1% 47P_0402_50V8J
2

2
22

21
2

1
PC51 PU6 PQ19

1
G
S
S
S
PR73 25 4 SI4810DY_SO8

V+

VL
3.74K_0402_1% 0.47U_0603_16V7K BST3 12OUT PR74
5
2

4
3
2
1
VDD
2

PR76 27 DH3 BST5 18

C 2M_0402_1% C
16
1

1M_0402_1% DH5 PLX5

2 1 26 17

2
LX3 LX5 PDL5
24 DL3 DL5 19
+3VALWP PR75 20
1

0_0402_5% PGND
CSH5 14
PR77 CSH3 1 13 CSH5
CSL3 CSH3 CSL5
2 1.24K_0402_1%
1 2 CSL3 FB5 12

1
3 FB3 SEQ 15

1
1 3.32K_0402_1% 1 2 10 9 +2.5VREF PC52 PR79
43,45 PACIN SKIP# REF
1

470U_6.3V_M PD17 PR78 23 6 1.82K_0402_1%

SHDN# SYNC
1

+ PR80 10K_0402_5% 11 0.47U_0603_16V7K

2
RST#

1
PC54 7

2
PC53 SKUL30-02AT_SMA 100P_0402_50V8J TIME/ON5 PC55
2

2 4.7U_0805_6.3V6K
28

GND
+5VALWP
2

2
RUN/ON3

PR81
1

1
MAX1902EAI_SSOP28

1
VS 1 2 PC56 PR82 1
2

1
1000P_0402_50V7K PC57 470U_6.3V_M PD18
2

PR83 47K_0402_5% 10.2K_0402_1% 100P_0402_50V8J PC58 +

2
2
1

10K_0402_1% SKUL30-02AT_SMA
PC59 2
1

2
1
@ 0.047U_0402_16V4Z
2

PR84

2 1 VL
PR85 10K_0402_1%

2
220K_0402_5%

B B
MAINPWON 24,43,44
1

PC60
0.47U_0603_16V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3V / 5V / 12V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期五, 三月 04, 2005 Sheet 46 of 52
5 4 3 2 1
 A B C D

PJ18
2 1 B+
2 1

1
PC61 PC141 @ JUMP_43X118

1
1@ 4.7U_1206_25V6K 1@ 4.7U_1206_25V6K PR86 PC62

1
1@ 4.7U_1206_25V6K
1@ 0_1206_5% PC63

2
1@ 4.7U_1206_25V6K

2
1
+5VALWP 1

2
PD19 PC142

1
1@ DAP202U_SOT323 1@ 4.7U_0805_6.3V6K PR87 PC65

2
PC64 1@ 2.2_0603_5% 1@ 2.2U_0805_10V6K

2
1@ 0.1U_0603_25V7K

1
2

3
8
7
6
5
+1.8V

D
D
D
D
PQ20
1@SI4800DY-T1_SO8

14

28
G
S
S
S
+1.8VSP PL8 PC66 PU7 PC67

5
6
7
8
1@1.8UH_D104C-919AS-1R8N_9.5A_20% 2 1 12 17 2 1

VIN

VCC
1
2
3
4
1@ 0.01U_0402_25V7Z SOFT1 SOFT2 1@ 0.01U_0402_25V7Z

D
D
D
D
1 2 1.8V_PHASE
PR88 PQ21
1 2 1 1 2 6 23 1 2 2 1 1@ SI4800DY-T1_SO8
BOOT1 BOOT2
+1.2V/+1.0V

8
7
6
5

G
S
S
S
PR89
PC70 + PC68 1@ 0_0603_5% 1@ 0_0603_5% PC69

D
D
D
D

4
3
2
1
PQ22 1@ 0.1U_0402_16V7K 1@ 0.1U_0402_16V7K
1@ 470U_6.3V_M 1@ 0.01U_0402_25V7Z 1@SI4810DY_SO8 N9 5 24 N11 PL9 +VGA_COREP
2 UGATE1 UGATE2 1@ 1.8UH_D104C-919AS-1R8N_9.5A_20%
1

G
S
S
S
PC71 4 25 VGA_PHASE 1 2
PHASE1 PHASE2
1
2
3
4
PR90 PR92
2

5
6
7
8
2
1@ 10K_0402_1% 1@ 2K_0402_1% 2

PR144 1 PR91
2 7 22 1 2 PQ23 1@ 0.01U_0402_25V7Z

D
D
D
D
2

ISEN1 ISEN2

1
1@ 0_0402_5% 1@ 2K_0402_1% 1@ SI4810DY_SO8 PC73 1
N10 2 27 PR145
LGATE1 LGATE2

1
1@ 0_0402_5% PR93 +
1

G
S
S
S
1@ 2.21K_0402_1% PC72
1@ 470U_6.3V_M

4
3
2
1

2
2
3 PGND1 PGND2 26
N12

9 VOUT1 VOUT2 20
10 VSEN1 VSEN2 19
SUSP# 1 2 8 21 1 2 SUSP#
EN1 EN2

2
27,33,39,40,42,49 SUSP# PR94 15 16 PR95
PG1 PG2/REF
1

1
0_0402_5% 1@ 10K_0402_1% PR147

GND

DDR
PR97 11 18 PC75 @ 0_0402_5%
1@ PC74 OCSET1 OCSET2 @ 0.1U_0402_16V7K
2

2
2

1
1@ 10K_0402_1% 1@ ISL6227CA-T_SSOP28

13

1
1
PR146 @ 0.1U_0402_16V7K
2

@ 0_0402_5% PR99 PR98

1@ 100K_0402_1%
1@ 71.5K_0402_1%
1

2
2

2
PR105

1
@ 10K_0402_1%
with selector without selector PR96
fix 1.2V

1
3 1@ 6.49K_0402_1% 3

PR105=10K unpop PR105

2
PR143 @ 2N7002_SOT23

1
@ 100K_0402_5% PQ28 D
PR96=20K PR96=6.49K
VL 2 1 2
G

1
S @ 0.1U_0402_16V7K

3
PR102

1
@ 100K_0402_5% D PC144

2
2 1 2 PQ43
15 POWER_SEL G @ 2N7002_SOT23
Low:1.2V S

3
2
High:1.0V
PC83

1
@ 0.01U_0402_16V7K

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8V / VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期五, 三月 04, 2005 Sheet 47 of 52
A B C D
 5 4 3 2 1

PR100
PJ12
1 2 2 2 1 1 +5VALWP

2
10_0603_5% @ JUMP_43X118

1
PC76 1
PD20 PC78

1
1U_0603_6.3V6M 1N4148_SOD80 4.7U_1206_25V6K + PC77

2
2
470U_6.3V_M

1
1
PR101 PC79

2
5
6
7
8
470P_0402_50V8J 2

5
6.81K_0402_1% PU8

D
D
D
D
2
0.1U_0402_16V7K

VCC
1
D D

1
PC80 PQ24
1 SI4800DY-T1_SO8
BOOT

G
S
S
S
7

2
OCSET

4
3
2
1
PL10
2 N20
UGATE 1.8UH_D104C-919AS-1R8N_9.5A_20%
6 FB 2 1 +1.5VALWP
8 1.5V_PHASE
PHASE

5
6
7
8
1

D
D
D
D
+ PC81
3 4 PQ26 470U_6.3V_M
GND LGATE SI4810DY_SO8

G
2

S
S
S
APW7057KC-TR_SOP8

4
3
2
1
N21
PR104
9.53K_0402_1%
1 2

2 PC84
1 2
PR106
10.7K_0402_1% 0.1U_0402_16V7K
1

C +2.5V C

1
PJ15

1
@ JUMP_43X118

2
2
PU11
1 VIN VCNTL 6 +3VALWP
2 GND NC 5

1
1
PC96 3 7 PC97
1@ 10U_1206_6.3V7K VREF NC 1@ 1U_0603_6.3V6M

2
PR114 4 8
1@ 1.07K_0402_1% VOUT NC
9

2
TP
1@ APL5331KAC-TR_SO8
PR115

1
PQ33 +1.2VSP

1
1@ 0_0402_5% D
1@ 2N7002_SOT23 PC98
SUSP 1 2 2 1@ 0.1U_0402_16V7K

1
G PR116
S 1@ 1K_0402_1% PC99

3
1
+2.5V 1@ 10U_1206_6.3V7K

2
PC100
B @ 0.1U_0402_16V7K B

2
1

PJ16
1

@ JUMP_43X118
2 2

PU12
1 VIN VCNTL 6 +3VALWP
2 GND NC 5
1

1
1

PC101 3 7 PC102
10U_1206_6.3V7K VREF NC 1U_0603_6.3V6M
2

PR117 4 8
1K_0402_1% VOUT NC
9
2

TP
APL5331KAC-TR_SO8
PR118
+1.25VSP
1

0_0402_5% D PQ34
1

SUSP 1 2 2 2N7002_SOT23
1

42 SUSP G PR119 PC103

S 1K_0402_1% 0.1U_0402_16V7K PC104
3

2
1

10U_1206_6.3V7K
2

PC105
@ 0.1U_0402_16V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5V / 1.25V / 1.2V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期五, 三月 04, 2005 Sheet 48 of 52
5 4 3 2 1
 5 4 3 2 1

PJ19
2 1 B+
2 1

1
@ JUMP_43X118

1
PR148 PC127

1
PC125 PC126 4.7U_1206_25V6K
4.7U_1206_25V6K 4.7U_1206_25V6K 0_1206_5% PC128

2
4.7U_1206_25V6K

2
D
+5VALWP D

PC143

2
PD26 4.7U_0805_6.3V6K

1
DAP202U_SOT323 PR149 PC130

2
PC129 2.2U_0805_10V6K

2
0.1U_0603_25V7K 2.2_0603_5%

1
2

3
8
7
6
5
+1.05V

D
D
D
D
PQ44
SI4800DY-T1_SO8

14

28
G
S
S
S
+1.05VSP PL16 PC131 PU14 PC132

5
6
7
8
1.8UH_D104C-919AS-1R8N_9.5A_20% 2 1 12 17 2 1

VIN

VCC
1
2
3
4
N13 0.01U_0402_25V7Z SOFT1 SOFT2 0.01U_0402_25V7Z

D
D
D
D
1 2 1.05V_PHASE
PR150 PQ45
1 2 1 1 2 6 23 1 2 2 1 SI4800DY-T1_SO8
BOOT1 BOOT2

8
7
6
5

G
S
S
S
0_0603_5% PR151
PC135 + PC133 0_0603_5% PC134 +2.5V

D
D
D
D

4
3
2
1
PQ46 0.1U_0402_16V7K 0.1U_0402_16V7K
220U_6.3VM_R15 0.01U_0402_25V7Z SI4810DY_SO8 5 24 N15 PL17 +2.5VP
2 UGATE1 UGATE2 1.8UH_D104C-919AS-1R8N_9.5A_20%
1

G
S
S
S
PC136 4 25 2.5V_PHASE 1 2
PHASE1 PHASE2

1
2
3
4
2

PR152 PR155
2

5
6
7
8
C 1.65K_0402_1% PR153 2K_0402_1% C

0_0402_5% 1 PR154
2 7 22 1 2 0.01U_0402_25V7Z

D
D
D
D
2

2K_0402_1% ISEN1 ISEN2 PQ47 PC138 1

N14 2 27 SI4810DY_SO8
1

LGATE1 LGATE2

1
PC137 +

1
G
S
S
S
PR156
0_0402_5% 220U_6.3VM_R15

4
3
2
1

2
PR157 2
3 PGND1 PGND2 26
N16 17.8K_0402_1%

2
PR158 9 VOUT1 VOUT2 20
10 VSEN1 VSEN2 19
SUSP# 1 2 8 21 1 PR159 2
EN1 EN2

1
27,33,39,40,42,47 SUSP# 15 16 SYSON 37,38,39,42
PG1 PG2/REF
1

1
10K_0402_1% PR160

GND

DDR
0_0402_5%
2

PR161 11 18 PC140
OCSET1 OCSET2

2
PR162 PC139 @ 0.1U_0402_16V7K 10K_0402_1%

2
1
10K_0402_1% @ 0_0402_5% ISL6227CA-T_SSOP28 PR163

13

2
1
@ 0.1U_0402_16V7K @ 0_0402_5%
2

PR165 PR164
1

100K_0402_1%

1
100K_0402_1%

2
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2.5V / 1.05V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期五, 三月 04, 2005 Sheet 49 of 52
5 4 3 2 1
 CPU_B+ B+
+5VS
PL12
1 2
FBM-L18-453215-900LMA90T_1812

4.7U_1206_25V6K

4.7U_1206_25V6K
PD22 1

1
EP10QY03

1
PR120 + PC106
10_0402_5% 220U_25V_M

PC107

PC108
2 1

2
2

2
2

5
6
7
8
PC109

0.01U_0402_25V7Z
PC110 PQ35

2
1U_0603_6.3V6M 2.2U_0603_6.3V6K AO4408_SO8

1
1

PC111
PU13

0.22U_0603_16V7K
1

1
4

PC112
V CC 10 30
VCC VDD

2
5 CPU_VID0 24 D0 V+ 36

3
2
1
5 CPU_VID1 23 D1 BSTM 26 2PR121 1
2.2_0603_5% +CPU_CORE
22 28 N5
5 CPU_VID2 D2 DHM PL13 PR122
21 27 CPUPHASE1 1 2 1 2
5 CPU_VID3 D3 LXM 0.56UH_ETQP4LR56WFC_21A_20%

5
6
7
8
20 29 N6 0.001_2512_5%
5 CPU_VID4 D4 DLM

1
19 31 PD23 CPU VCC SENSE
5 CPU_VID5 D5 PGND

909_0402_1%
@ EC31QS04

1
25 VROK CMP 37
6,14,25 VGATE

499_0402_1%

499_0402_1%
4

1
4 38

2
S0 CMN

1000P_0402_50V7K
PC113
PR127 PQ36

2
0_0402_5% V CC 5 17 AO4410_SO8

2
S1 OAIN+ PC114

3
2
1

PR123
1 2 6 16 1 2 PR126

1
PR128 30.1K_0402_1% SHDN# OAIN- 2.7K_0402_1%

PR124

PR125
2 1 1 15 FB 0.47U_0603_16V7K
VR_ON 39

1
TIME FB PR129 909_0402_1%
PC1151 2 12 14 1 2 1 2
CCV CCI PC116 470P_0402_50V8J @
1 2 270P_0402_50V7K 2 35
TON BSTS
PR132 PR130 200K_0402_1% 1 2 8 33
78.7K_0402_1% REF DHS
1 2 PR131
1 2 PC117 0.22U_0603_16V7K 9 34 2.7K_0402_1%
ILIM LXS
+5VS
FB 1 2 7 32 1 2 1 2
OFS DLS
10.7K_0402_1%

100P_0402_50V8J

PR133 100K_0402_1% 3 40 PC118 PR134

SUS CSP
2

1 2 2200P_0402_50V7K 0_0402_5%
PR135

PC119

18 SKIP CSN 39
2
1

2
D CPU_B+

2.2_0603_5%
27P_0402_50V8J

PQ37 11 13 PD24
GND GNDS
1

PR136
2 PQ38 EP10QY03
14,25 PM_STP_CPU#
1

PC120

G RHU002N06_SOT323 2
S G RHU002N06_SOT323
3

4.7U_1206_25V6K

4.7U_1206_25V6K
S MAX1532AETL_TQFN40
3

5
6
7
8

1
PR137 PQ39

PC121

PC122
0_0402_5% AO4408_SO8

2
0.22U_0603_16V7K
25 PM_DPRSLPVR 1 2

1
N7 4

PC123
+5VS 1 2

2
PR138

3
2
1
2

20K_0402_1%
2

PR139 PL14
PR140 10K_0402_1% CPUPHASE2 1 2
100K_0402_1% 0.56UH_ETQP4LR56WFC_21A_20%

909_0402_1%
1 1

5
6
7
8

1
1

1
PQ41 D PQ40
2
G RHU002N06_SOT323 AO4410_SO8 PD25
S @ EC31QS04
3

2
1

C N8 4

2
5 PSI# 2

PR141
B 1 2
E PQ42
3

HMBT2222A_SOT23 PC124

3
2
1
0.47U_0603_16V7K

909_0402_1%
1 2

PR142

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期五, 三月 04, 2005 Sheet 50 of 52
 5 4 3 2 1

REV 0.2
Date Page Location Description

12/06 P.38 Add ESD diode D34 for ESD protection

12/06 P.37 Delete C267 For sound volume change slow issue

12/06 P.32 ADD C854 To solve PCI 4510 1394 issue

D D
12/06 P.21 Change L4,L5 to FBM-L11-201209-121LMT To solve EMI issue

12/26 P.22 Change C398,C397 from 270P to 100P For customer request
C401,C402 from 330P to 100P
12/26 P.22 Change R320,R321,R7,R8,R9 from 150_0402_5% For customer request
to 150_0402_1%
12/26 P.07 Change R124,R127,R119,R531,R532 For customer request
from 150_0402_5% to 150_0402_1%
12/26 P.15 Change R273,R274,R267,R270,R271 For customer request
from 150_0402_5% to 150_0402_1%
12/26 P.32 Change 5in1 SMWP design ,Add R836,R837 follow EAT10 design

REV 0.3
Date Page Location Description

2/06 P.09 Change R160 size to 0805 0 ohm Add rating current
C C
2/06 P.24 Add C859,C864 change R841 to 2.2 ohm For TV-out wave issue

2/06 P.32 Add R838,R839 Change 5in1 card reader discharge control from card detect to card power enable .

2/06 P.27 Reserve R840,C862,X5 Reserve for chip issue

REV 1.0
Date Page Location Description

2/14 P.34 ADD R842 Reserve for CyberTan issue

2/26 P.36 Add C866 Add for solve modem card noise

2/26 P.24 Add C865 Add for solve 3Dmark low performace issue

2/26 P.24 Add R842 Reserve for New Wireless Lan Card

B B

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date Title
Deciphered Date
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS EAL30 LA-2691 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 三月 04, 2005 Sheet 51 of 52
A A

5 4 3 2 1
 5 4 3 2 1

Page Location Description Reason

45 PR50 Change from 33.2K_0402_1% to 25.5K_0402_1% For ATI M22/M24 sku, update to 75W

47 PR96 Change from 20K_0402_1% to 6.49K_0402_1% Fix POWER_SEL at 1.2V

Unpop PR105,PQ28,PR143,PQ43,PR102,PC83,PC144
D 47 PR98 Change from 90.9K_0402_1% to 71.5K_0402_1% Enlarge VGA_CORE OCP point D

43 PD3 Change from RB751 to 1N4148 For common design

43 PR9 Change from 33_1206_5% to 47_1206_5% For common design

48 Delete PC96,PR114,PU11,PC97,PR115,PQ33,PR116, For UMA SKU, delete 1.2VS

PC98,PC99
48 PR104 Change PR104 from 9.09K_0402_1% to 9.53K_0402_1% For HW requirement to raise 1.5V voltage
PR106 Change PR106 from 10.5K_0402_1% to 10.7K_0402_1%

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
POWER PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL30 LA-2691
Date: 星期五, 三月 04, 2005 Sheet 52 of 52
5 4 3 2 1
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