Er63419 Rev101 140628

Specification
R63419
16,777,216–Color, 1600RGB x 2560 -Dot Graphics Liquid
Crystal Controller Driver for TFT Panel
Rev.1.01
June 28, 2014
Description .......................................................................................................... 9
Features ............................................................................................................... 9
Power Supply Specification ................................................................................ 11
Term Definition .................................................................................................. 12
Restriction in using R63419................................................................................ 12
Block Diagram .................................................................................................... 14
Block Function .................................................................................................... 15

(1)System Interface (MIPI-DSI)................................................................................................................................. 15
(2)Video Image Interface ........................................................................................................................................... 15
(3)Frame memory ...................................................................................................................................................... 15
(4)Grayscale Voltage Generating Circuit .................................................................................................................. 16
(5)LCD Drive Power Supply Circuit ......................................................................................................................... 16
(6)Timing Generator.................................................................................................................................................. 16
(7)Oscillator (OSC) ................................................................................................................................................... 16
(8)LCD Driver Circuit ............................................................................................................................................... 16
(9)Panel Interface Circuit.......................................................................................................................................... 16
(10)Internal Logic Power Supply Regulator .............................................................................................................. 16
(11)Image processing IP............................................................................................................................................ 17
(12)NVM .................................................................................................................................................................... 17
(13) Synchronization signal Output for touch panel controller ................................................................................. 17
Pin Function ........................................................................................................ 18
Alignment Mark .................................................................................................. 26
Power Supply Generating Circuit ....................................................................... 27

Power Supply Circuit Connection Example ............................................................................................................... 27
Specifications of External Elements Connected to the Power Supply Circuit ... 28
Voltage Setting Pattern Diagram ........................................................................ 29
Reset .................................................................................................................... 32
(1) Command Default Values .................................................................................................................................... 32
(2) Initial States of Input/Output Pins and Output Pins ............................................................................................. 32
Rev.1.01 June 28, 2014 1

R63419 Specification
System Configuration for Dual MIPI-DSI Ports ................................................ 33

(1) DSI Command Swap function .............................................................................................................................. 34
(2) Relationship with LCD Panel position and Display. ............................................................................................ 35
Absolute Maximum Rating ................................................................................. 38
Electrical Characteristics .................................................................................... 39

(1) Power Supply Voltage Range ............................................................................................................................... 39
(2) DC Characteristics .............................................................................................................................................. 39
(3) DC Characteristics (MIPI DSI) ........................................................................................................................... 41
Note on Electrical Characteristics ....................................................................................................................... 42
(4) Step-up Circuit Characteristics ............................................................................................................................ 43
(5) Clock Characteristics........................................................................................................................................... 43
(6) Reset Timing Characteristics ............................................................................................................................... 44
(7) Liquid Crystal Driver Output Characteristics ...................................................................................................... 45
(8) MIPI DSI Characteristics .................................................................................................................................... 46
MIPI DSI HS-RX Clock and Data-Clock Specifications..................................................................................... 47
MIPI DSI LP-RX/TX Clock and Data-Clock Specifications ............................................................................... 48
Command List ..................................................................................................... 52
Command Accessibility ...................................................................................... 57
Default Modes and Values .................................................................................. 62
User Command ................................................................................................... 66

nop: 00h .................................................................................................................................................................... 66
soft_reset: 01h ........................................................................................................................................................... 67
Read_Display_Idetification_Information: 04h .......................................................................................................... 68
Read_Number _of_the_Errors_on_DSI: 05h ............................................................................................................. 70
get_red_channel: 06h ................................................................................................................................................ 71
get_green_channel: 07h ............................................................................................................................................ 72
get_blue_channel: 08h .............................................................................................................................................. 73
get_power_mode: 0Ah ............................................................................................................................................... 74
get_address_mode: 0Bh............................................................................................................................................. 76
get_pixel_format: 0Ch ............................................................................................................................................... 78
get_display_mode: 0Dh ............................................................................................................................................. 80
get_signal_mode: 0Eh ............................................................................................................................................... 82
get_diagnostic_result: 0Fh ........................................................................................................................................ 84
enter_sleep_mode: 10h .............................................................................................................................................. 86
exit_sleep_mode: 11h ................................................................................................................................................ 87
enter_partial_mode: 12h ........................................................................................................................................... 88
enter_normal_mode: 13h........................................................................................................................................... 89
set_all_pixels_off: 22h ............................................................................................................................................... 90
set_all_pixels_on: 23h ............................................................................................................................................... 91
set_gamma_curve: 26h .............................................................................................................................................. 92
set_display_off: 28h................................................................................................................................................... 93
set_display_on: 29h ................................................................................................................................................... 94
set_column_address: 2Ah .......................................................................................................................................... 95
set_page_address: 2Bh .............................................................................................................................................. 97
write_memory_start: 2Ch .......................................................................................................................................... 99
set_partial_area: 30h ................................................................................................................................................ 100
Rev.1.01 June 28, 2014 2

set_tear_off: 34h........................................................................................................................................................ 102

set_tear_on: 35h ........................................................................................................................................................ 103
set_address_mode: 36h ............................................................................................................................................. 104
exit_idle_mode: 38h .................................................................................................................................................. 107
enter_idle_mode: 39h ................................................................................................................................................ 108
set_pixel_format: 3Ah................................................................................................................................................ 110
write_memory_continue: 3Ch.................................................................................................................................... 112
set_tear_scanline:44h ................................................................................................................................................ 113
Write_Display_Brightness: 51h ................................................................................................................................. 114
Read_Display_Brightness_Value: 52h ...................................................................................................................... 115
Write_Control_Display: 53h ..................................................................................................................................... 116
Read_Control_Value_Display: 54h ........................................................................................................................... 117
Write_Content_Adaptive_Brightness_Control: 55h .................................................................................................. 118
Read_Content_Adaptive_Brightness_Control: 56h ................................................................................................... 120
Write_CABC_Minimum_Brightness: 5Eh.................................................................................................................. 122
Read_CABC_Minimum_Brightness: 5Fh .................................................................................................................. 123
Read_Automatic_Brightness_Control_Self_Diagnostic_Result: 68h......................................................................... 124
read_Black/White_Low_Bit: 70h ............................................................................................................................... 126
read_Bkx: 71h ........................................................................................................................................................... 126
read_Bky: 72h ........................................................................................................................................................... 127
read_Wx: 73h ............................................................................................................................................................ 127
read_Wy: 74h ............................................................................................................................................................ 128
read_Red/Green_Low_Bit: 75h ................................................................................................................................. 128
read_Rx: 76h ............................................................................................................................................................. 129
read_Ry: 77h ............................................................................................................................................................. 129
read_Gx: 78h............................................................................................................................................................. 130
read_Gy: 79h............................................................................................................................................................. 130
read_Blue/Acolor_Low_Bit: 7Ah............................................................................................................................... 131
read_Bx: 7Bh............................................................................................................................................................. 131
read_By: 7Ch ............................................................................................................................................................ 132
read_Ax: 7Dh ............................................................................................................................................................ 132
read_Ay: 7Eh............................................................................................................................................................. 133
read_DDB_start: A1h................................................................................................................................................ 134
read_DDB_continue: A8h ......................................................................................................................................... 136
read_ID1: DAh .......................................................................................................................................................... 138
read_ID2: DBh .......................................................................................................................................................... 139
read_ID3: DCh.......................................................................................................................................................... 140
idlemode_BL_control: E1h ........................................................................................................................................ 141
read_idlemode_BL_control: E2h............................................................................................................................... 142
Manufacturer Command ..................................................................................... 143

・Manufacturer Command Access Protect : B0h ...................................................................................................... 143
MCAP ................................................................................................................................................................. 143
・Low Power Mode Function : B1h .......................................................................................................................... 144
DSTB .................................................................................................................................................................. 144
・Interface Setting : B3h ........................................................................................................................................... 145
RM, DM .............................................................................................................................................................. 145
V2CRM ............................................................................................................................................................... 146
WEM ................................................................................................................................................................... 146
TEI ...................................................................................................................................................................... 147
EPF ..................................................................................................................................................................... 147
EPFV ................................................................................................................................................................... 148
Rev.1.01 June 28, 2014 3

・Interface ID setting : B4h ...................................................................................................................................... 149

DSIVCA.............................................................................................................................................................. 149
DSIVCB .............................................................................................................................................................. 149
・Read Checksum and ECC Error Count : B5h ........................................................................................................ 150
DSICSOUTA ...................................................................................................................................................... 150
DSICSOUTB ...................................................................................................................................................... 150
DSIECPA ............................................................................................................................................................ 151
DSIECPB ............................................................................................................................................................ 151
DSIECEA ............................................................................................................................................................ 151
DSIECEB ............................................................................................................................................................ 151
・DSI Control : B6h .................................................................................................................................................. 152
DSITXDIV .......................................................................................................................................................... 152
DSI_THSSET...................................................................................................................................................... 153
・Checksum and ECC Count : B7h ........................................................................................................................... 154
ERR_CNT_RST.................................................................................................................................................. 154
・Back Light Control 1 : B8h ................................................................................................................................... 155
・Back Light Control 2 : B9h ................................................................................................................................... 156
・Back Light Control 3 : BAh ................................................................................................................................... 157
・SRE Control 1 : BBh .............................................................................................................................................. 158
・SRE Control 2 : BCh ............................................................................................................................................. 159
・SRE Control 3 : BDh ............................................................................................................................................. 160
・Test Register : BEh ................................................................................................................................................ 161
・Device Code Read Function : BFh ........................................................................................................................ 162
ALMID1 ............................................................................................................................................................. 162
ALMID2 ............................................................................................................................................................. 163
ALMID3 ............................................................................................................................................................. 163
・Slew rate adjustment : C0h .................................................................................................................................... 164
SOUTTR1/2/3/4/5/6, SOUTTF1/2/3/4/5/6 .......................................................................................................... 164
・Display Setting 1 : C1h ......................................................................................................................................... 165
SS1 ...................................................................................................................................................................... 166
BGR1 .................................................................................................................................................................. 166
REV .................................................................................................................................................................... 167
PTLREV ............................................................................................................................................................. 167
BLREV, BLS ...................................................................................................................................................... 167
HRE1 .................................................................................................................................................................. 168
UDS .................................................................................................................................................................... 168
ABSI ................................................................................................................................................................... 169
・Display Setting 2 : C2h .......................................................................................................................................... 170
PNSET ................................................................................................................................................................ 170
MUX3EN ............................................................................................................................................................ 170
LINEINV ............................................................................................................................................................ 171
NL ....................................................................................................................................................................... 175
BP ....................................................................................................................................................................... 175
FP ........................................................................................................................................................................ 175
FP2 ...................................................................................................................................................................... 176
・Touch Panel Sync Function : C3h ......................................................................................................................... 177
TPSYNEN........................................................................................................................................................... 177
HSOM ................................................................................................................................................................. 177
VSOD.................................................................................................................................................................. 178
HSOD.................................................................................................................................................................. 178
HSOHW .............................................................................................................................................................. 178
・Source Timing Setting : C4h .................................................................................................................................. 179
Rev.1.01 June 28, 2014 4

DIV ..................................................................................................................................................................... 180

EQWx ................................................................................................................................................................. 180
SNTx ................................................................................................................................................................... 182
・Realtime Scaling : C5h .......................................................................................................................................... 183
RTSON ............................................................................................................................................................... 183
RTSRAM ............................................................................................................................................................ 183
・LTPS Timing Setting : C6h .................................................................................................................................... 184
STx, SWx, PSWTx, PWWx, PSWGx, ................................................................................................................ 185
RTN0 .................................................................................................................................................................. 186
RTN2 .................................................................................................................................................................. 186
・Gamma Function : C7h ......................................................................................................................................... 187
VGMPn, VGMNn ............................................................................................................................................... 188
・Digital Gamma Function : C8h ............................................................................................................................. 189
GAMADJ ............................................................................................................................................................ 190
BR0_R, BR1_R, BR0_G, BR1_G, BR0_B, BR1_B ........................................................................................... 190
GAM0_R, GAM1_R, GAM2_R, GAM0_G, GAM1_G, GAM2_G, GAM0_B, GAM1_B, GAM2_B ............... 190
TILT0_R, TILT1_R, TILT0_G, TILT1_G, TILT0_B, TILT1_B ........................................................................ 190
・Color Enhancement : CAh .................................................................................................................................... 192
CE_ON, PPEN2 .................................................................................................................................................. 194
・Panel Pin Control : CBh ....................................................................................................................................... 195
SOUTENx SOUTPLx ...................................................................................................................................... 195
SOUTABSPLEN SOUTABSPLx .................................................................................................................... 196
・Panel Interface Control : CCh ............................................................................................................................... 197
LIM ..................................................................................................................................................................... 197
・Test Register: CDh ................................................................................................................................................ 198
・Back Light Control 4 : CEh .................................................................................................................................. 199
・Power Setting for Charge Pump : D0h ................................................................................................................... 200
DC2 ..................................................................................................................................................................... 200
BT2 ..................................................................................................................................................................... 201
DC3 ..................................................................................................................................................................... 201
BT3 ..................................................................................................................................................................... 201
VLM2.................................................................................................................................................................. 202
VLM3.................................................................................................................................................................. 203
・Test Register: D1h ................................................................................................................................................. 204
・Power Setting for Internal Power : D2h .................................................................................................................. 205
VC2 ..................................................................................................................................................................... 206
VC3 ..................................................................................................................................................................... 206
VPL ..................................................................................................................................................................... 207
VNL .................................................................................................................................................................... 208
APAN.................................................................................................................................................................. 209
APAP .................................................................................................................................................................. 209
VBTS .................................................................................................................................................................. 210
・Test Register : D3h ............................................................................................................................................... 211
・ Test register : D4h ............................................................................................................................................... 212
・ VCOM Setting Function : D5h ............................................................................................................................ 213
WCVDC .............................................................................................................................................................. 213
WCVDCB ........................................................................................................................................................... 213
VDC .................................................................................................................................................................... 214
VDCB ................................................................................................................................................................. 218
・Test Register : D6h ................................................................................................................................................ 222
・Test Register : D7h ................................................................................................................................................ 223
・Test Register : D8h ................................................................................................................................................ 224
Rev.1.01 June 28, 2014 5

・Test Register : D9h ................................................................................................................................................ 225

・Test Image Generator : E5h .................................................................................................................................. 226
TIGON ................................................................................................................................................................ 226
TIGCYC .............................................................................................................................................................. 226
TIP ...................................................................................................................................................................... 227
・NVM Access Control : E6h .................................................................................................................................... 230
NVMAEN ........................................................................................................................................................... 230
TEM .................................................................................................................................................................... 230
NVMFTT ............................................................................................................................................................ 231
NVMVFFLGER .................................................................................................................................................. 231
NVMVFFLGWR ................................................................................................................................................ 231
・set_DDB write Control :E7h ................................................................................................................................. 232
WCDDB .............................................................................................................................................................. 232
WCDDBCOL ...................................................................................................................................................... 232
WCRDID ............................................................................................................................................................ 233
・NVM Load Control : E8h....................................................................................................................................... 234
NVMLD .............................................................................................................................................................. 234
NVMWECNT ..................................................................................................................................................... 235
・Test Register : E9h ................................................................................................................................................ 236
・Supported Compression Method : EAh ................................................................................................................. 238
COMP_ENTRY1, COMP_ENTRY2, COMP_ENTRY3, COMP_ENTRY4, COMP_ENTRY5 ........................ 238
・ Compression Method : EBh ................................................................................................................................. 239
COMPV_METHOD............................................................................................................................................ 239
COMPC_METHOD ............................................................................................................................................ 239
・Test Register : ECh ................................................................................................................................................ 240
・Test Register : EDh................................................................................................................................................ 241
・Test Register : EEh ................................................................................................................................................ 242
・Test Register : EFh ................................................................................................................................................ 242
・Realtime Scaling Off Control : F1h ....................................................................................................................... 243
System Interface Configuration (MIPI DSI)....................................................... 244

(1) Basic DSI Specification ........................................................................................................................................ 244
(2) DSI System Configuration .................................................................................................................................... 244
(3) Lane State Definition ........................................................................................................................................... 245
(4) DSI-CLK Lane ..................................................................................................................................................... 245
1) Low Power Mode (LP-11: STOP)................................................................................................................... 246
2) Ultra Low Power Mode (LP-00: ULPM) ........................................................................................................ 246
3) High Speed Clock Mode ................................................................................................................................. 247
4) High Speed Clock Burst .................................................................................................................................. 247
(5) DSI-D0 Data Lane ............................................................................................................................................... 248
1) Power On, HWRESET  LP-11 .................................................................................................................... 249
2) Escape Mode ................................................................................................................................................... 249
3) Escape Mode (Host >Client): Low Power Data Transmission (LPDT) ........................................................... 250
4) Escape Mode (Host>Client): Ultra Low Power State (ULPS) ......................................................................... 251
5) Escape Mode (Host>Client): Remote Application Reset (RAR) ..................................................................... 251
6) Escape Mode (Client>Host): Tearing Report (TER) ....................................................................................... 251
7) Escape Mode (Client > Host): Acknowledge Trigger (ACKT) ....................................................................... 251
8) High Speed Data Transmission (HST) ............................................................................................................ 251
9) Bus Turnaround (Host>Client) (BTA) ............................................................................................................ 251
10) Bus Turnaround (Client>Host) (BTA) .......................................................................................................... 251
(6) Packet Level Communication ............................................................................................................................... 252
1) Short Packet (SPa) Structure ........................................................................................................................... 252
Rev.1.01 June 28, 2014 6

2) Long Packet (LPa) Structure ........................................................................................................................... 253

3) Multiple Packet Sending ................................................................................................................................. 253
(7) Data Identification (DI) ....................................................................................................................................... 254
1) Virtual Channel (VC) ...................................................................................................................................... 254
2) Data Type (DT) ............................................................................................................................................... 254
(8) Word Count (WC) on Long Packet (LPa)............................................................................................................. 257
(9) Error Correction Code (ECC) ............................................................................................................................. 257
(10) Command Mode Pixel Data Format (PD).......................................................................................................... 257
(11) Packet Footer on Long Packet (LPa) ................................................................................................................. 258
(12) Acknowledge with Error Report (AwER) ........................................................................................................... 259
(13) DCS, MCS, and Data Type List .......................................................................................................................... 260
(14) Video Mode ........................................................................................................................................................ 263
1) Display Timing (Video Mode) ........................................................................................................................ 263
2) Vertical Display Timing (Video Mode) .......................................................................................................... 264
3) Horizontal Display Timing (Video Mode) ...................................................................................................... 265
4) Packed Pixel Stream........................................................................................................................................ 269
5) Packet Footer on Long Packet (LPa) ............................................................................................................... 271
6) Line Contention Detection .............................................................................................................................. 271
Display Mode ...................................................................................................... 272

(1) Display mode change in SleepIn .......................................................................................................................... 272
(2) Display Interface switching flow .......................................................................................................................... 272
Frame Memory.................................................................................................... 276

Address Mapping from Memory to Display ............................................................................................................... 276
Normal Display On or Partial Mode On .............................................................................................................. 276
Host Processor to Memory Write Direction ........................................................................................................ 276
Reference Clock Generating Function ................................................................ 278
Output Waveform Mode of Panel Control Signals ............................................. 278
Frame Frequency Adjustment Function.............................................................. 279

Relationship between the Liquid Crystal Drive Duty and the Frame Frequency ....................................................... 279
Example of Calculation: when Maximum Frame Frequency = 60 Hz ....................................................................... 279
TE Pin Output Signal .......................................................................................... 280
Self-Diagnostic Function .................................................................................... 281
Content Adaptive Brightness Control (Dynamic Backlight Control Function) .. 282

System Configuration ................................................................................................................................................ 283
Color Enhancement Function ............................................................................. 284

Overview.................................................................................................................................................................... 284
Sunlight Readability Enhancement Function ...................................................... 287
Local Area Auto Contrast Optimze Function ..................................................... 288
Compression Data Transfer ................................................................................ 289

(1)Compression unit size ........................................................................................................................................... 289
Rev.1.01 June 28, 2014 7

(2)Long Packet mapping for compression data ......................................................................................................... 290

(3)Memory access setting for compression data in Command mode ......................................................................... 293
(4) Compression data transfer in Video mode ........................................................................................................... 294
(5)Data transfer rate ................................................................................................................................................. 295
(6)BP setting .............................................................................................................................................................. 295
Real Time Scaling ............................................................................................... 296

(1) Real Time Scaling Switching flow ........................................................................................................................ 296
(2) Real Time Scaling Operation diagram ................................................................................................................. 297
(3) Display Interface switching Flow-1 ..................................................................................................................... 298
(4) Display Interface switching diagram-1 ................................................................................................................ 299
(5) Display Interface switching Flow-2 ..................................................................................................................... 301
(6) Display Interface switching diagram-2 ................................................................................................................ 302
(7) Real Time Scaling Mode Internal Vsync, Hsync Timing ...................................................................................... 304
(8) Realtime Scaling Video Through Mode Setting .................................................................................................... 305
Synchronization signal Output for touch panel controller .................................. 306

(1) VSOUT output Timing ......................................................................................................................................... 306
(2) HSOUT output Timing ......................................................................................................................................... 306
State Transition Diagram (Display Mode) .......................................................... 307

(1) Definition of Display Modes ............................................................................................................................... 307
(2) Power/Display On/Off Sequence .......................................................................................................................... 309
(3) Deep Standby Mode On/Off Sequence ................................................................................................................. 310
Gamma Correction Function............................................................................... 311

Gamma Correction Registers .................................................................................................................................... 313
Relationship between Gamma Correction Register and Voltage ............................................................................... 314
Grayscale Voltage Calculation Formula ................................................................................................................... 315
Gamma Correction Register Setting Example ........................................................................................................... 319
Relationship between Display Data and Grayscale Voltage ...................................................................................... 320
NVM Control ...................................................................................................... 321

NVM Write Sequence ................................................................................................................................................. 322
Abnormal Sequence ............................................................................................ 323
Revision Record .................................................................................................. 324
Rev.1.01 June 28, 2014 8

Description
The R63419 is liquid crystal controller driver LSI for TFT panel sized 1600RGB x 2560-dot at
maximum. For high-speed data transfer, the R63419 supports MIPI DSI (4 lanes) with 2 ports as
system interface to microcomputer.
The R63419 incorporates step-up and voltage follower circuits to generate drive voltage required for
TFT liquid crystal panel and a dynamic backlight control function to control backlight brightness
depending on image data, reducing power consumption at the backlight with the slightest influence on
image quality.
Other features include a power management function, making the R63419 best suitable for small-and-
mid-sized portable devices with color graphics display such as digital mobile phones, Smartphone,
Tablet PC, and photo frames.
*MIPI: Mobile Industry Processor Interface, *DSI: Display Serial Interface
Features
 Single chip driver for 16, 777, 216-color TFT 1600RGB x 2560-dot graphics (with power supply
circuits and supporting LTPS panel )
 Resolution: 1600RGB x 2560 dots, 1536RGB x 2560dots,1440RGB x 2560dots
 Command set (Compliant with MIPI DCS Version 1.01.00) *DCS: Display Command Set
 System interface
– MIPI DSI : 4 data lanes and 1 clock lane with 2 ports
MIPI DSI: Version 1.01.00r11 21-Feb-2008 (Video Mode supported)
MIPI D-PHY: Version 1.00.00 14-May-2009
 Video image display interface (see Note 1)
－ MIPI DSI TE-reporting
 Direct compressed data input
－ Video through mode : 1/2 or 1/3 data compressed data input
－ Command mode : 1/3 data compressed data input (see Note.3)
 Abundant color display and drawing functions
– 16,777,216-color display
– Partial display function
– Digital Gamma Adjustment for RGB separate gamma correction function
– Color Enhancement with skin tone correction function
– Sunlight Readability Enhancement function
– Local area Auto Contrast Optimization
 Low-power consumption architecture (allowing direct input of interface I/O power supply)
– Deep standby mode
– Input power supply voltage:
Interface and logic power supply: IOVCC
Analog power supply:,VSP,VSN
MIPI D-PHY power supply: DPHYVCC
 Real time scaling function

 Dynamic backlight control function
 Synchronization function for touch panel controller
Rev.1.01 June 28, 2014 9

 Internal liquid crystal drive power supply circuit

– Source driver: VSP-AGND
VSN-AGND
– DC power supply for VCOM drive: VCOM
– VCOM driver: VCI-VCL
– Interface to the panel: VGH-AGND
AGND-VGL
 Internal frame memory with an advanced data compression technology
－ RAM size : 4,096,000 bytes (1600 x 2560 x 24 / 3bits)
 Interface to the panel : SOUT1-32
 Liquid crystal panel drive circuits:
2400 source signal lines (2mux), 1600 source signal lines (3mux)
 One-chip solution for COG module
 Internal NVM: Data can be rewritten up to 40 times.
 Dummy pins used to fix pin to IOVCC, or GND (see Note 2)
Notes: 1. Japanese Patent No. 3,826,159

Korean Patent No. 747,636
United States Patent No. 7,176,870
2. Japanese Patent No. 3,980,066
Korean Patent No. 401,270
Taiwan Patent No. 175,413
Japanese Patent No. 4,226,627
3. Video to RAM mode and Video RAM capture mode are same as Command mode.
Rev.1.01 June 28, 2014 10

Power Supply Specification

Table 1 R63419 Power Supply Specification
No. Item R63419
1 TFT data lines drive circuit 2400 outputs

2 Liquid crystal drive output S1-S2400 256 grayscales
VCOM -2.00V ~ 2.00 V
3 Panel interface SOUTn VGH-VGL
4 Input voltages IOVCC (interface voltage) 1.65V ~1.95V (See note)
VSP 4.5V~6.3V
(Power supply voltage for LCD drive)
VSN -4.5V~-6.3V
(Power supply voltage for LCD drive)
DPHYVCC 1.65V ~ 1.95V (See note)
(MIPI DSI-PHYpower supply)
5 System interface IM[2:0], RESX IOVCC - GND (See note)
6 Differential small-amplitude CLKP/N_A/B, DATA0P/N_A/B, DPHYVCC - DPHYGND
interface (MIPI DSI) DATA1P/N_A/B
DATA2P/N_A/B, DATA3P/N_A/B (note2)
7 LED I/F LEDPWM IOVCC - GND (See note)
8 TPC synchronization signal VSOUT, HSOUT IOVCC - GND (See note)
9 LCD drive supply voltages VSP 4.5V ~ 6.3V (max.)
VSN -4.5V ~ -6.3V (min.)
VCL ~ -3.0V(min.)
VGH, VGHP 5.0V ~ 13.0V
VGL, VGLP -12.0V ~ -5.0V
VGH-VGL Max. 30V
Note1: Connect these power supplies to other power supplies on the FPC when they are set at the same
electrical potential as other power supplies. For voltage, see DC Characteristics in Electrical
Characteristics.
Note2: The voltage of this terminal should not exceed DPHYVCC.
Rev.1.01 June 28, 2014 11

Term Definition
RSP LCD Driver: an RSP product to be used according to its data sheet
Column_Address_Max: a maximum column address in frame memory
Row_Address_Max: a maximum row address in frame memory
Table 2 Resolution Example

HRE1=’h0 HRE1=’h1 HRE1=’h2
Size(dots) 1600RGB x 2560 1440 RGB x 2560 1440 RGB x 1440 1536RGB x 2560
(WQXGA) (WQHD)
PN2PTX pin Low Low High Low
DSI Port Number Dual Port Mode Dual Port Mode Single Port Mode Dual Port Mode
Grayscale Vmax VP255 VP255 VP255
(positive polarity) (positive polarity) (positive polarity)
VN255 VN255 VN255
(negative polarity) (negative polarity) (negative polarity)
Restriction in using R63419

Writing uncompressed data to Frame memory by MIPI DSI command mode
(1) Unit which data is written to data should be written to Frame memory in unit of 2 lines
If writing to Frame memory stops halfway, the wirte data is not reflected in Frame memory.
(2) The window should be set in unit of 4 pixels × 2 lines.
(3) To keep the write speed at 1Gbps/lane, the range of SC and EC of the window address needs to be
set as following table.
Table 3 Range of window address (SC, EC) at write speed of 1Gbps/lane horizontal resolution
HRE1 Horizontal resolution SC EC

‘h0 1600RGB ‘h0 - ‘h1B0 ‘h487 – ‘h63F
‘h1 1440RGB ‘h0 – ‘h1D0 ‘h3C7 – ‘h59F
‘h2 1536RGB ‘h0 – ‘h200 ‘h3F7 – ‘h5FF
Rev.1.01 June 28, 2014 12

(4) The interface which enable writting to Frame memory is DSI.
(5) If writing to Frame memory is started by the 2Ch command during Sleep In state, the internal OSC
starts operating.
To stop the internal OSC after the end of writing to Frame memory, wait 200us and then execute
the Sleep In command via DSI.
Writing compressed data to Frame memory by MIPI DSI command mode
Refer “Compression Data Transfer”.
Writing compressed data by MIPI DSI video mode
Refer “Compression Data Transfer”.
Rev.1.01 June 28, 2014 13

Block Diagram
LEDPWM GNDRF
Command GND
Register (CDR) Parameter Address Image processing IP AGND
Register Counter
(PR)
CABC, CE, SRE, ACO
DUMMYR1-2
IOVCC DUMMY
IOVCCRF NV
IM2-IM0 Memory
CSX
DCX System Data
WRX/SCL Interface compress
circuit
Data extract circuit

DIN
Test Pin
Source Driver
DOUT
Latch circuit
Latch circuit
Latch circuit
Frame
Write Data Memory
TE Register S1-S2400
TE2 (WDR)
RESX 4,096,000
bytes
DPHYVCC
DPHYGND
VDDLP_A/B
CLKP/N_A/B MIPI-DSI
DATA0P/N_A/B 4 lane
DATA1P/N_A/B
Gamma calculation
Gray scale voltage

generating circuit
DATA2P/N_A/B
DATA3P/N_A/B
VGS
circuit
PNSLV
Timing Generator
DBIST
VSOUT
HSOUT Touch panel
sync. output
Panel Interface circuit
EXCK
(for LTPS)
OSC
SOUT1-32
Internal reference
Voltage generator
Internal logic
power supply
regulator
VDD
LCD drive level generating circuit

TEST circuit
VPP1
VREFD
DE
VSYNC
PCLK
VREF
TESTE
VREFC
HSYNC
DB7-1
VREFM
TS1-0
TEST1-4,6
VDDTEST
VSP
VSN
VGLP
VSNRF
VGHP
VCL
VGL
VPLVL
VNLVL
VGH
VCOM
C21P/C21M
VSPRF
C31P/C31M
VCI
Figure 1
Rev.1.01 June 28, 2014 14

Block Function
(1)System Interface (MIPI-DSI)
The RSP LCD driver supports MIPI DSI Command Mode, MIPI DSI Video Mode. The RSP LCD
driver also supports TE synchronization signal as display interface for video mode.
Table 4
Number of available
IM2 IM1 IM0 Interface Used pin
colors
0 0 0 Setting disabled - -
DATA0P/N_A/B,
DATA1P/N_A/B,
1 1 0 MIPI DSI 262,144/16,777,216
DATA2P/N_A/B,
DATA3P/N_A/B
The number of data lanes is 4lanes support only.
(2)Video Image Interface
When MIPI DSI command mode is selected, display data is written in synchronization with a start of
the frame period by TE-reporting function. This enables updating image data without flicker on the
panel.
Data written in MIPI DSI video mode is directly output as display data without being written to internal
GRAM.
(3)Frame memory
R63419 incorporates the frame memory that has a capacity of 4,096,000 bytes, which can store pattern
data of 1600RGB x 2560 graphics display at the maximum using. Send display data in units of 4 pixels
because of data compression.
Rev.1.01 June 28, 2014 15

(4)Grayscale Voltage Generating Circuit
The grayscale voltage generating circuit generates liquid crystal drive voltage according to the
grayscale setting value in the gamma correction registers. RGB separate gamma correction setting
enables maximum 16,777,216-color display.
(5)LCD Drive Power Supply Circuit
The LCD drive power supply circuit generates voltage levels to drive the liquid crystal panel.
(6)Timing Generator
The timing generator is used to generate timing signals for operating internal circuits.
(7)Oscillator (OSC)
The RSP LCD driver incorporates an oscillator.
(8)LCD Driver Circuit
The LCD driver circuit has the 2400-channels source driver (S1-S2400). When 1600RGB pixels of
data are input, the display pattern data is latched. The voltage is output from the source driver
according to the latched data.
(9)Panel Interface Circuit
The panel interface circuit generates and outputs the interface signals (SOUTn) to the TFT panel.
(10)Internal Logic Power Supply Regulator
The internal logic power supply regulator generates power supply for the internal logic circuit.
Rev.1.01 June 28, 2014 16

(11)Image processing IP
The backlight control circuit(CABC) adjusts backlight brightness according to the histogram of image
to reduce power consumption at the backlight. Brightness of the backlight and display data is adjusted.
The color enhancement control circuit (CE) enhances the saturation of the image displays on the liquid
crystal panel and displays image with color enhanced.
The sunlight readability control circuit (SRE) enhances the image data to make it easier to read under
strong sunlight.
(12)NVM
The RSP LCD driver supports NVM that stores manufacturer command setting values.
(13) Synchronization signal Output for touch panel controller
The RSP LCD driver can output the synchronization signals to capture touch sensing signal for touch
panel controller. To use these signals, touch panel controller can capture touch sensing signal while
avoiding display changing noise.
Rev.1.01 June 28, 2014 17

Pin Function
Table 5 External Power Supply Pins
Signal I/O Connect to Function Connection
when signal
is unused
IOVCC I Power supply Power supply to interface pins. Power supply
IOVCC < 0.3V (When power is turned off.) Stabilizing
Stabilizing
capacitor capacitor
IOVCCRF I Power supply Connect to IOVCC on the FPC to prevent noise in case of COG. Power supply
DPHYVCC I Power supply Power supply to MIPI DSI D-PHY Power supply
Connect to IOVCC on the FPC when DPHYVCC is set at the same Stabilizing
Stabilizing
electrical potential as IOVCC. capacitor
capacitor
GND I Power supply GND for internal logic and interface pins. GND=0V. Power supply
GNDRF I Power supply Connect to GND on the FPC to prevent noise in case of COG. Power supply
AGND I Power supply Analog GND (logic regulator and LCD power supply circuit). AGND = Power supply
0V. Connect to GND on the FPC to prevent noise in case of COG.
AGNDRF I Power supply Connect to AGND on the FPC to prevent noise in case of COG Power supply
VSP I Power supply Power supply analog circuit Power supply
Stabilizing Stabilizing
capacitor capacitor
VSPRF I Power supply Connect to VSP on the FPC to prevent noise in case of COG Power supply
VSN I Power supply Power supply analog circuit Power supply
Stabilizing Stabilizing
capacitor capacitor
VSNRF I Power supply Connect to VSN on the FPC to prevent noise in case of COG Power supply
DPHYGND I Power supply GND for MIPI DSI D-PHY Connect to GND on the FPC to prevent Power supply
noise in case of COG.
Table 6 System Interface Pins (Amplitude: IOVCC - GND)

when signal
is unused
IM2-0 I IOVCC or GND Interface select signal. Select interface from MIPI DSI, MIPI DBI Type IOVCC or
C (Option 1 and Option 3) and I2C. GND
RESX I Host Processor Reset pin. The RSP LCD driver is initialized when RESX is Low. Host
or external RC Make sure to execute power-on reset when turning power supply on. Processor or
circuit external RC
circuit
TE O Host processor Tearing effect output signal. Open
By register settings, it can be used as a verify signal for NVM write.
Leave it open when not in use.
Rev.1.01 June 28, 2014 18

Table 7 MIPI DSI Pins

when signal
is unused
Host
CLKP_A I MIPI DSI Clock (+) of PortA. DPHYGND
Processor
Host
CLKN_A I MIPI DSI Clock (-) of PortA. DPHYGND
Processor
Host
DATA0P_A I/O MIPI DSI (+) of PortA. DPHYGND
Processor
Host
DATA0N_A I/O MIPI DSI (-) of PortA. DPHYGND
Processor
Host
DATA1P_A I MIPI DSI (+) of PortA. DPHYGND
Processor
Host
DATA1N_A I MIPI DSI (-) of PortA. DPHYGND
Processor
Host
Processor
Host
Processor
Host
Processor
Host
Processor
Host
CLKP_B I MIPI DSI Clock (+) of PortB. DPHYGND
Processor
Host
CLKN_B I MIPI DSI Clock (-) of PortB. DPHYGND
Processor
Host
DATA0P_B I/O MIPI DSI (+) of PortB. DPHYGND
Processor
Host
DATA0N_B I/O MIPI DSI (-) of PortB. DPHYGND
Processor
Host
DATA1P_B I MIPI DSI (+) of PortB. DPHYGND
Processor
Host
DATA1N_B I MIPI DSI (-) of PortB. DPHYGND
Processor
Host
Processor
Host
Processor
Host
Processor
Host
Processor
Rev.1.01 June 28, 2014 19

Table 8 LED Driver Control Pins (Amplitude: IOVCC - GND)

when signal
is unused
Control signal for brightness of LED backlight. PWM signal’s width is
selected from 256 values between 0% (Low) and 100% (High).
LEDPWM O LED driver Open
When light is turned on, LEDPWM is High. When light is turned off,
LEDPWM is Low.
Table 9 Power Supply Circuit Pins

Signal I/O Connect to Function
VDD O Stabilizing capacitor A pin to output voltage from internal logic power supply regulator.
Connect to stabilizing capacitor.
VDDLP_A O Stabilizing capacitor Internal LDO output (1.2V typical).
Used as power supply for the MIPI low power receiver.
VDDLP_B O Stabilizing capacitor Internal LDO output (1.2V typical).
Used as power supply for the MIPI low power receiver.
VGH O Stabilizing capacitor Internal regulator output for pins to output positive voltage for the liquid
crystal panel.
VGHP O Liquid crystal panel, Internal regulator output for liquid crystal driving power supply.
Stabilizing capacitor This pin’s output level is GND during NVM erase/write operation.
VGL O Stabilizing capacitor Internal regulator output for pins to output negative voltage for the liquid
crystal panel.
VGLP O Liquid crystal panel, Internal regulator output for liquid crystal driving power supply.
Stabilizing capacitor This pin’s output level is GND during NVM erase/write operation.
C21P/M, I/O Step-up capacitor Capacitor connection pins for the step-up circuit. For details, see “Power
C31P/M, Supply Generating Circuit.”
VCL O Stabilizing capacitor Internal analog power supply for VCOM generator.
Connect to stabilizing capacitor.
VCI O Stabilizing capacitor Power supply to analog circuit
Rev.1.01 June 28, 2014 20

Table 10 Liquid Crystal Drive Pins

when signal
is unused
VCOM O Liquid crystal VCOM level, which is set by internal electric volume (VDC). Stabilizing
panel capacitor
VGS I Power supply Reference level of the grayscale voltage generating circuit (GND Power supply
level). Connect to GND on the FPC to prevent noise in case of
COG.
VPLVL O Open Positive reference voltage for the liquid crystal panel. Put on the Open
FPC to monitor voltage.
VNLVL O Open Negative reference voltage for the liquid crystal panel. Put on the Open
FPC to monitor voltage.
S1-S2400 O Liquid crystal Liquid crystal application voltages. Open
panel
Table 11 Liquid Crystal Panel Power Supply Interface Pins

when signal
is unused
Liquid crystal
SOUT1-32 O Panel control signals Open
panel
Table 12 TPC synchronization pin

when signal
is unused
Signal to synchronize LCD driver and touch panel controller.
VSOUT O Host Processor Open
(Vertical scan)
Signal to synchronize LCD driver and touch panel controller.
HSOUT O Host Processor Open
(Horizontal scan)
Table 13 Clock External Application Control pin (Amplitude: IOVCC - GND) (Test mode)
when signal
is unused
External clock input pin. The internal clock and the external
EXCK I Host Processor GND
supply clock can be switched by register control.
Rev.1.01 June 28, 2014 21

Table 14 DSI Master Port select pin (Amplitude: IOVCC - GND)

when signal
is unused
PNSLV determine the Master port.
High : Port B is set the master
Low : Port A is set the master. (default)
Pixel Data from Host
PNSLV Command
SlotA SlotB
PNSLV I IOVCC or GND GND
DATA0P/N_B DATA0P/N_A DATA0P/N_B
High ～～～
DATA3P/N_B DATA3P/N_A DATA3P/N_B
DATA0P/N_A DATA0P/N_B DATA0P/N_A
Low(default) ～～～
DATA3P/N_A DATA3P/N_B DATA3P/N_A
Table 15 DSI select port number select pin (Amplitude: IOVCC - GND)
Signal I/O Connect to Function
PN2PTX controls the port number od DSI.

PN2PTX I Host Processor High : 1 port mode
Low : 2 ports mode
Table 16 DSI PortB arrangement select pin (Amplitude: IOVCC - GND)

when signal
is unused
PNMRX control arrangement of DSI PortB.

PNMRX I IOVCC or GND High : PortB is same arrangement for PortA. GND
Low : PortB is mirror arrangement for PortA (default).
Rev.1.01 June 28, 2014 22

Table 17 DSI Pin Arrangement Control pin (Amplitude: IOVCC - GND)

when signal
is unused
LNSW1/0 control swapping MIPI Lane, PNMRX=High
LNSW1/0 PortA arrangement(bump to top)
Low/Low DATA3 DATA2 CLK DATA1 DATA0
Low/High DATA3 DATA0 CLK DATA1 DATA2
High/Low DATA0 DATA1 CLK DATA2 DATA3
High/High DATA2 DATA1 CLK DATA0 DATA3
PortB arrangement(bump to top)
LNSW1/0 control swapping MIPI Lane, PNMRX=Low
LNSW1/0 PortA arrangement(bump to top)
LNSW1/0 PortB arrangement(bump to top)

I IOVCC or GND GND
PNSW Low/Low DATA0 DATA1 CLK DATA2 DATA3
PNSW control Polarity of MIPI Pin, PNMRX=High

PNSW PortA arrangement(bump to top)
Low DATAxN DATAxP CLKxN CLKxP
High DATAxP DATAxN CLKxP CLKxN
PNSW control Polarity of MIPI Pin, PNMRX=Low

PNSW PortA arrangement(bump to top)
Low DATAxP DATAxN CLKxP CLKxN
High DATAxN DATAxP CLKxN CLKxP
Rev.1.01 June 28, 2014 23

Physical pin name (PortA) Physical pin name (PortB)

PNMRX PNSW LNSW[1:0]
DATA2P_A DATA2N_A DATA1P_A DATA1N_A CLKP_A CLKN_A DATA0P_A DATA0N_A DATA3P_A DATA3N_A DATA3N_B DATA3P_B DATA0N_B DATA0P_B CLKN_B CLKP_B DATA1N_B DATA1P_B DATA2N_B DATA2P_B
0 0 0 0 DATA3N DATA3P DATA2N DATA2P CLKN CLKP DATA1N DATA1P DATA0N DATA0P DATA0P DATA0N DATA1P DATA1N CLKP CLKN DATA2P DATA2N DATA3P DATA3N
0 1 0 0 DATA3P DATA3N DATA2P DATA2N CLKP CLKN DATA1P DATA1N DATA0P DATA0N DATA0N DATA0P DATA1N DATA1P CLKN CLKP DATA2N DATA2P DATA3N DATA3P
1 0 0 0 DATA3N DATA3P DATA2N DATA2P CLKN CLKP DATA1N DATA1P DATA0N DATA0P DATA3N DATA3P DATA2N DATA2P CLKN CLKP DATA1N DATA1P DATA0N DATA0P
1 1 0 0 DATA3P DATA3N DATA2P DATA2N CLKP CLKN DATA1P DATA1N DATA0P DATA0N DATA3P DATA3N DATA2P DATA2N CLKP CLKN DATA1P DATA1N DATA0P DATA0N
Table 18 The test free running mode Control pin (Amplitude: IOVCC - GND)
when signal
is unused
Enables the Test Image Generation function
DBIST Test Image Generator
DBIST I IOVCC or GND Low Off GND
High On
Rev.1.01 June 28, 2014 24

Table 19 Other Pins (Test and Dummy)

when signal
is unused
Dummy pins to measure contact resistance. DUMMYR1 and
DUMMYR1-2 O Open Open
DUMMYR2 are short-circuited within the LSI.
TESTE I GND Test pins. Connect to GND. Don’t draw the wire on to FPC. GND
TEST1-4,6 I Open or GND Test pins. Fix to GND or leave open. Open or GND
VDDTEST I Open or GND Test pins. Fix to GND or leave open. Open or GND
Test pins. Fix to GND or leave open. Don’t draw the wire on to
VREFC I Open or GND Open or GND
FPC.
VREF O Open Test pin. Leave open. Open

VREFD O Open Test pin. Leave open. Open
VREFM O Open Test pin. Leave open. Open
TE2 O Open Test pin. Leave open. Open
VSYNC I Open or GND Test pins. Fix to GND or leave open. Open or GND
HSYNC I Open or GND Test pins. Fix to GND or leave open. Open or GND
PCLK I Open or GND Test pins. Fix to GND or leave open. Open or GND
DE I Open or GND Test pins. Fix to GND or leave open. Open or GND
DB7-1 I Open or GND Test pins. Fix to GND or leave open. Open or GND
TS1-0 O Open Test pin. Leave open. Open
Open or Test pin. Fix to AGND or leave open. To leave open, do not pull Open or
VPP1 I
AGND out ITO wiring. AGND
DUMMY1-422 O Open Dummy pins. Leave open. Open
CSX I IOVCC Test pins. Fix to IOVCC. IOVCC

DCX I IOVCC Test pins. Fix to IOVCC. IOVCC
WRX/SCL I IOVCC Test pins. Fix to IOVCC. IOVCC
DIN I/O IOVCC Test pins. Fix to IOVCC. IOVCC

DOUT O Open Test pin. Leave open. Open
Rev.1.01 June 28, 2014 25

Alignment Mark
 Chip thickness: 170 um (typ.)
 Pad coordinates: Pad center
 Coordinate origin: Chip center
 Au bump pitch: Refer to “Pad Coordinate.”
 Au bump height: 15 um
 Alignment mark
15um 30um 30um 30um 15um
15um
30um
120um 30um
Y-size
30um
Alignment
Mark Area 15um
120um
Alignment Mark Area X-size
Bump View
(0,0)
IO side
BUMP
Bump View
Chip
Figure 2
Rev.1.01 June 28, 2014 26

Power Supply Generating Circuit

The following figure shows the configuration of liquid crystal drive voltage generating circuit of the
R63419.
Power Supply Circuit Connection Example
IOVCC
DPHYVCC (8)
(5)
IOVCCRF
VDDLP_A VDD
(1) (4)
VDDLP_B
(2)
VCOM
VCI (7)
(6)
VCL
(3)
R63419
C21P
(11)
C21M
VGH
(14)
VSP
(10)
VGHP
(16)
C31P
(12)
C31M
VGLP
VSN (17)
(9)
VGL
(13)
(15)
Figure 3
Rev.1.01 June 28, 2014 27

Specifications of External Elements Connected to the Power Supply Circuit

The following table shows specifications of external elements connected to the R63419’s power supply
circuit. The numbers of the connection pins correspond to the numbers shown in “Power Supply
Generating Circuit.”
Table 20 Capacitor Specifications

Recommended
Capacitor Pins to connect
voltage
3V (1) VDDLP_A , (2) VDDLP_B

1µF (B characteristics)
6V (3) VCL,
2.2µF (B characteristics) 3V (4) VDD,
2.2µF (B characteristics) 6V (5) DPHYVCC, (6) VCI, (7) VCOM, (8) IOVCC,
2.2µF (B characteristics) 10V (9) VSN, (10) VSP
1.0µF (B characteristics) 25V (11) C21P/M, (12) C31P/M
2.2µF (B characteristics) 25V (13) VGL, (14) VGH, (16) VGHP, (17) VGLP
Table 21 Schottky Diode Specifications

Specifications Pins to connect
VF < 0.4V/10mA@25°C, VR ≥ 25V (15) VSN – VGL
Rev.1.01 June 28, 2014 28

Voltage Setting Pattern Diagram

The following are the diagrams of voltage generation using External VSP/VSN supply in the R63419
and the relationship between TFT display application voltages.
VGH/VGHP ( 5V to 13.0V )
Charge pump
VSP VSP ( 4.5V to 6.3V )

Regulator
( 0.2V Step ) Regulator ( 25mV Step )
VCI2 ( 2.4V to 5.4V )
Regulator VPLVL ( 3.5V to VSP-0.3V )
( 0.2V Step )
VCI3 ( 2.4V to 5.4V ) Regulator
VCI( ~ 3.0V )
DPHYVCC
Source(Posi)
VDDLP ( 1.2V )
VCOM(-2V～2V)
IOVCC
VDD ( 1.2V )
Panel I/F
GND ( 0V )
Source(Nega)
VCL ( ~ -3.0V ) Regulator
Regulator
VNLVL ( -3.5V to VSN+0.3V )

Regulator ( 25mV Step )
VSN VSN ( -4.5V to -6.3V )
Charge pump
VGL/VGLP ( -5.0V to -12.0V )
Notes: 1. Make sure that the following relationships are satisfied:
(VSP-VPLVL)≧0.3V
(VSN-VNLVL)≦-0.3V
(VSP-VCI2) ≧ 0.2V
(VSP-VCI3) ≧ 0.2V
2. The above voltage ranges are recommended.

3. VCI2, VCI3 is internal voltage
4. VGHP/VGLP is for power supply of panel.
Rev.1.01 June 28, 2014 29

R63419 can be operated by supplying VSP and VSN power supply directly.
Refer to "Power Supply Generating Circuit" for detail.
a)Power On Sequence
90% 90%
IOVCC
DPHYVCC thVSP
tsVSP
90%
tRW1
50% tPOFF2 50%
VSP 10% 10%
tPON2
tPON1 tPOFF1
10% 10%
VSN 50% 50%
90%
tRW1 VIH
RESX VIL
tRT
RSP LCD
driver status Reset Initial condition
b)Deep standby mode Sequence
IOVCC
DPHYVCC
90%
tRW1
VSP 50%
tPOFF2 50%
10% 10%
tPON2
tPON1
VSN 10%
50%
50%
90%
tRW1 VIH
RESX tRW2
VIL VIL
tRT
RSP LCD
driver status DSTB Reset Initial condition
Rev.1.01 June 28, 2014 30

Item Symbol Unit Test Condition Min Max

VSP-VSN delay time
tPON1 us Power On 0 －
(10% to 10%)
VSP-VSN delay time
tPON2 us Power On 0 －
(50% to 50%)
System power on to
tsVSP ms Power On 1 －
VSP ON time
Reset low-level width1 tRW1 ms Power On 1 －
Reset low-level width2 tRW2 ms Power Off 1 －
Reset time
tRT ms Power On 3 －
(Sleep IN)
VSN-VSP delay time
tPOFF1 us Power Off 0 －
(10% to 10%)
VSN-VSP delay time
tPOFF2 us Power Off 0 －
(50% to 50%)
VSP OFF to system
thVSP us Power Off 0 －
power off time
Figure 4 Power supply on sequence
Notes: 1. Make sure that the following relationships are power supply sequence.
Rev.1.01 June 28, 2014 31

Reset
The RSP LCD driver is initialized by reset input. During the reset period, the RSP LCD driver is set to
its internal initial setting and no command is accepted from the processor. The source driver unit and
the power supply circuit unit are also reset to the respective initial states when reset signal is input to
the RSP LCD driver.
(1) Command Default Values
The initial states of commands are shown in the “register map” table. See “register map” The command
setting is initialized to the default value when hardware reset is executed.
(2) Initial States of Input/Output Pins and Output Pins
A table below shows initial states of input/output pins and output pins after reset.
Table 22 Initial States of Input/Output Pins and Output Pins after Reset
External power supply IOVCC DPHYVCC VSP VSN
Pin name Pin state Pin name Pin state

VSP VSP VSOUT GND
VSN VSN HSOUT GND
VCI GND DIN note1
VPLVL Hi-Z DOUT GND
VNLVL Hi-Z LEDPWM GND
VCL GND DATA0P/N_A/B Hi-Z
VGH GND DATA1P/N_A/B Hi-Z
VGHP GND DATA2P/N_A/B Hi-Z
VGL VSN DATA3P/N_A/B Hi-Z
VGLP GND C21P Hi-Z
VGS GND C21M Hi-Z
VCOM GND C31P Hi-Z
SOUTn GND C31M Hi-Z
S1-2400 GND
Notes : Please keep the input of High or Low.
Rev.1.01 June 28, 2014 32

System Configuration for Dual MIPI-DSI Ports

R63419 has Dual MIPI-DSI ports that are named PortA and PortB. When PNSLV is connected to GND,
PortA is assigned to Master Port and PortB is assigned to Slave Port. The host processor need to
provide the pixel data divided into left and right picture one to Master and Slave ports.
System Configuration is shown below. (ex. 1600RGB x 2560 is selected)
P1 P801
2560
1600RGB
R63419
Slave Master
Host
MIPI MIPI
DSI COM DSI COM

（Invalid）
VS HS P1 P2 VS HS P801 P802
P3 P4 P5 P6 P803 P804 P805 P806
P7 P8 P9 P10 P807 P808 P809 P810
DSI Video DSI Video

（Left）（Right）
Rev.1.01 June 28, 2014 33

(1) DSI Command Swap function
R63419 has PNSLV pin that can select the execution DSI port of User and Manufacture Command.
When PNSLV is connected to GND, PortA is assigned to Master port that is valid to the execution of
command, and when connected to IOVCC, PortB is assigned to Master port. The host processor need
to control via PortA or PortB assigned to Master port function selected by PNSLV pin.
PNSLV PortA PortB

Low Master Slave
Execution of Command is Valid Execution of Command is Invalid
High Slave Master
Execution of Command is Invalid Execution of Command is Valid
Rev.1.01 June 28, 2014 34

(2) Relationship with LCD Panel position and Display.
R63419 can select Sn output direction by D6 (36h), SS1 (C1h) and PNSLV pin. LCM needs to
consider the relationship with Panel position and Display. The relationship between Sn output and
D6/SS1/PNSLV is shown below.
Driver on Top Side of LCM Driver on Top Side of LCM

PNSLV Low (User/Manufacture Command can be executed via PortA.) High (User/Manufacture Command can be executed via PortB.)
B6 (36h) 0 1 0 1
SS1(C1h) 0 0 1 1
PN2PTX Low
Slot0 Slot1 Slot0 Slot1 Slot1 Slot0 Slot1 Slot0

Master Slave Master Slave Slave Master Slave Master
PortA PortB PortA PortB PortA PortB PortA PortB
RSP LCD Driver RSP LCD Driver RSP LCD Driver RSP LCD Driver
S1 S1200 S1201 S2400 S1 S1200 S1201 S2400 S1 S1200 S1201 S2400 S1 S1200 S1201 S2400
L1 L800 R1 R800 R800 R1 L800 L1 L1 L800 R1 R800 R800 R1 L800 L1
Display
Slot0(COM) Slot1 Slot0(COM) Slot1 Slot0(COM) Slot1 Slot0(COM) Slot1

L1 L800 R1 R800 L1 L800 R1 R800 L1 L800 R1 R800 L1 L800 R1 R800
Host
Host Processor Host Processor Host Processor Host Processor
Figure 5 Driver on Top Side of LCM and DSI-Dual Port
Rev.1.01 June 28, 2014 35

Driver on Bottom Side of LCM Driver on Bottom Side of LCM

PNSLV High (User/Manufacture Command can be executed via PortB.) Low (User/Manufacture Command can be executed via PortA.)
B6 (36h) 0 1 0 1
SS1(C1h) 0 0 1 1
PN2PTX Low
Display
L1 L800 R1 R800 R800 R1 L800 L1 L1 L800 R1 R800 R800 R1 L800 L1
S2400 S1201 S1200 S1 S2400 S1201 S1200 S1 S2400 S1201 S1200 S1 S2400 S1201 S1200 S1
RSP LCD Driver RSP LCD Driver RSP LCD Driver RSP LCD Driver
PortB PortA PortB PortA PortB PortA PortB PortA
Master Slave Master Slave Slave Master Slave Master
Slot0 Slot1 Slot0 Slot1 Slot1 Slot0 Slot1 Slot0
Slot0(COM) Slot1 Slot0(COM) Slot1 Slot0(COM) Slot1 Slot0(COM) Slot1

Host
Figure 6 Driver on Bottom Side of LCM and DSI-Dual Port
Rev.1.01 June 28, 2014 36

Driver on Top Side of LCM Driver on Bottom Side of LCM

PNSLV Low (User/Manufacture Command can be executed via PortA.)
B6 (36h) 0 1 0 1
SS1(C1h) 0 0 1 1
PN2PTX High
Slot0 Slot1 Slot0 Slot1

Master Slave Master Slave
PortA PortB PortA PortB
RSP LCD Driver RSP LCD Driver
S1 S1200 S1201 S2400 S1 S1200 S1201 S2400
L1 L800 R1 R800 R800 R1 L800 L1
Display
L1 L800 R1 R800 R800 R1 L800 L1
S2400 S1201 S1200 S1 S2400 S1201 S1200 S1

RSP LCD Driver RSP LCD Driver
PortB PortA PortB PortA
Slave Master Slave Master
Slot1 Slot0 Slot1 Slot0
Slot0(COM) Slot0(COM) Slot0(COM) Slot0(COM)

Host
Figure 7 DSI-Single Port
Rev.1.01 June 28, 2014 37

Absolute Maximum Rating

Table 23
Item Symbol Unit Value Note
Power supply voltage (1) IOVCC – GND V -0.3 ~ +4.6 1,2
Power supply voltage (2) DPHYVCC – DPHYGND V -0.3 ~ +4.6 1,2
Power supply voltage (3) VSP – AGND V -0.3 ~ +6.5 1,3
Power supply voltage (4) AGND – VSN V -0.3 ~ +6.5 1,3
Power supply voltage (5) AGND– VGL V -0.3 ~ +16.0 1,4

Power supply voltage (6) VGH– AGND V -0.3 ~ +19.0 1
Power supply voltage (7) VGH – VGL V -0.3 ~ +32.0 1
Input voltage Vt V -0.3 ~ IOVCC + 0.3 1,6
Input voltage (DSI) Vt(DSI) V -0.3 ~ 1.8 1,7
Operating temperature Topr C -40 ~ +85 1,5
Storage temperature Tstg C -55 ~ +110 1
Notes: 1. If used beyond the absolute maximum ratings, the LSI may be destroyed. It is strongly recommended to use the
LSI within the limits of its electrical characteristics during normal operation. The reliability of LSI is not
guaranteed if used in the conditions beyond the limits and it may lead to malfunction.
2. Make sure (High) IOVCC ≥ GND (Low), (High) DPHYVCC ≥ DPHYGND (Low)
3. Make sure (High) VSP ≥ AGND (Low), (Low) VSN  AGND (High).
4. Make sure (High) AGND ≥ VGL (Low).
5. The DC/AC characteristics of die and wafer products are guaranteed at 85C.
6. IOVCC amplitude input pin.
7. DSI input pin. (CLKP/N_A/B,DATA0P/N_A/B,DATA1P/N_A/B, DATA2P/N_A/B, DATA3P/N_A/B)
Rev.1.01 June 28, 2014 38

Electrical Characteristics
(1) Power Supply Voltage Range
Table 24 (Ta = -40C ~ +85C)

Test
Item Symbol Unit Min. Typ. Max. Note
condition
IOVCC V － 1.65 1.80 1.95 1
Power supply voltage DPHYVCC V － 1.65 1.80 1.95 1
External VSP/VSN supply mode VSP V － 4.50 5.60 6.30 1
VSN V － -6.30 -5.60 -4.50 1
Notes: 1. The DC/AC electrical characteristics of bare die and wafer are guaranteed at +85C.
(2) DC Characteristics
Table 25 (Ta= -40℃ ~ +85℃)

Item Symbol Unit Test condition Min. Typ. Max. Note
0.70 x
Input high-level voltage 1 VIH1 V IOVCC=1.65V ~ 1.95V － IOVCC 1, 2
IOVCC
0.30 x
Input low-level voltage 1 VIL1 V IOVCC=1.65V ~ 1.95V 0 － 1, 2
IOVCC
IOVCC=1.65V ~ 1.95V, 0.80 x
Output high-level voltage 1 VOH1 V －－ 1
IOUT = -0.1mA IOVCC
IOVCC=1.65V~1.95V, 0.20 x
Output low-level voltage 1 VOL1 V －－ 1
IOUT=0.1mA IOVCC
Input high-level current IIH µA Vin=IOVCC －－ 10 4
Input low-level current IIL µA Vin=0V -10 －－ 4
2560-line drive, IOVCC=1.80V,

fFRM=60Hz,Ta=25℃
Normal RAM Data: 24’h000000,
Mode + IOPN mA C[1:0]=2'h0,DSI 4Lanes× －－ 30 5
Current Sleep out 2port, fDSICLK=500MHz,
consumption RM=1’h0,DM[2:0]=3'h0,
(IOVCC-GND) 1600RGB(HRE1[2:0]=3'h0)
Deep
Standby IDST µA IOVCC=1.80V, Ta= 25℃ － 1.0 10 5
Mode
Rev.1.01 June 28, 2014 39

Table 26 (continued) (Ta= -40℃ ~ +85℃)

VSP=5.60V,
VSN=-5.60V,
fFRM=60Hz, Ta= 25℃,
RAM Data: 24’h000000,
no load on the panel,
REV=0,LINEINV=4'hF,
BT2=1'h0,BT3=1'h0,
Normal
VSP: VC2=4'hD,
Mode + ICIN4 mA － 12.0 15.0 5
VC3=4'hA,
Current Sleep out
VLM2=6'h14,VLM3=6'h14,
consumption DC2=3'h1,
(VSP-GND) DC3=3'h1
APAP=3'h3,APAN=3'h3,
VPL=7'h2B,VNL=7'h2B
Gamma Register setting
=Default Value
1600RGB(HRE1=3’h0)
Deep
IOVCC=1.80V, VSP =5.6V,
Standby IDST4 µA － 1 20 5
VSN=-5.6V, Ta= 25℃
Mode
VSP =5.60V,
VSN=-5.60V,
fFRM=60Hz, Ta= 25℃,
DSI Data: 24’h000000,
no load on the panel,
REV=0,LINEINV=4'hF,
BT2=1'h0,BT3=1'h0,
Normal
VSN: VC2=4'hD,
Mode + ICIN5 mA -15.0 -12.0 － 5
VC3=4'hA,
Current Sleep out
VLM2=6'h14,VLM3=6'h14,
consumption DC2=3'h1,
(GND-VSN) DC3=3'h1,
VPL=7'h2B,VNL=7'h2B,
Gamma Register setting
=Default Value
1600RGB(HRE1=3’h0)
Deep
IOVCC=1.80V, VSP =5.60V,
Standby IDST5 µA -20 -1 － 5
VSN=-5.60V, Ta= 25℃
Mode
Table 27
Vo1 mV V0～V63,V192～V255 －－ 35 6
Output voltage dispersion
Vo2 mV V64～V191 －－ 15 6
Average output variance ⊿V⊿ mV － -35 － +35 7
Rev.1.01 June 28, 2014 40

(3) DC Characteristics (MIPI DSI)
Table 28 (Ta= -40℃ ~ +85℃)

IOVCC=1.800V,
DPHYVCC=1.800V,
DSI 4 lanes×2port,
HS mode IHS mA －－ 11 -
fDSICLK=500MHz,
DSI current DSI Data:24’h000000
consumption Ta=25C
(DPHYVCC- IOVCC=1.800V,
DPHYGND) DPHYVCC=1.800V,
LP mode ILP µA －－ 900 -

Clock lane=LP11,
Data lane=LP11,
Ta=25C
Rev.1.01 June 28, 2014 41

Note on Electrical Characteristics
Notes: 1. The DC/AC electrical characteristics of bare die and wafer are guaranteed at +85C.
2. The following figures illustrate the configurations of input, I/O, and output pins.
Pins : IM2-0,RESX Pins : LEDPWM,DOUT,VSOUT,HSOUT,TE
Pins : DIN(Test pin)
Figure 8
3. The TESTE pin must be grounded (GND).

4. This excludes the current in the output-drive MOS.
5. This excludes the current in the input/output units. Make sure that the input level is fixed
because through current will increase in the input circuit when the CMOS input level takes a
middle range level.
6. The output voltage deviation is the difference in the voltages between output pins that are
placed side by side in the same display mode. The output voltage deviation is reference value.
7. The average output voltage dispersion is the variance of average source-output voltage of
different chips of the same product. The average source output voltage is measured for each
chip with same display data.
Rev.1.01 June 28, 2014 42

(4) Step-up Circuit Characteristics
Table 29
Item Symbol Unit Test condition Min. Typ. Max.
Ta=25℃, VSP=5.60V, VSN=-5.60V

Step-up output voltage VC2=4'h8, VC3= 4'h0, VLM2=6’h14
VGH V 7.6 7.7 -
Charge Pump APAP=3’h3, APAN=3’h3, BT2=1'h0,
Iload= -1 [mA]
Ta=25℃, VSP=5.60V, VSN=-5.60V
VC2= 4'h8, VC3=4'h0, VLM3=6’h14,
VGL V - -7.7 -7.6
APAP=3’h3, APAN=3’h3, BT3=1'h0,
Iload= +1 [mA]
(5) Clock Characteristics
Table 30
Item Symbol Unit Test condition Min. Typ. Max.
Oscillation clock fosc MHz IOVCC = 1.8V 53.2 56.0 58.8
Rev.1.01 June 28, 2014 43

(6) Reset Timing Characteristics
Table 31
Item Symbol Unit Test condition Min. Max.
Reset low-level width1 tRW1 us Power supply on 1000 －
Reset low-level width2 tRW2 us Operation 1000 －
Reset time (Sleep IN) tRT1 ms －－ 3
Reset time (Sleep OUT) tRT2 ms －－ 3
Noise reject width tRESNR us －－ 1
Figure 9 Reset Timing Characteristics (1)
Note: Refer to the appendix for details of “Panel off sequence”.
Rev.1.01 June 28, 2014 44

(7) Liquid Crystal Driver Output Characteristics
Table 32
Item Symbol Unit Test condition Min. Typ. Max Note
IOVCC=1.8V, , Ta=25℃,
VSP=5.60V, VSN=-5.60V,
reached voltage: defined grayscale
Source driver output delay voltage ±35mV

tdds us －－ 1.6 1
time VPL=7'h2B,VNL=7'h2B
Load resister R = 4kΩ
Load capacitance C = 30pF
Note1: LCD driver output delay time depends on load on the liquid crystal panel. Therefore, frame frequency and one-line
cycle needs to be specified checking image quality on the panel to be used.
Figure 10 Liquid Crystal Driver Output Timing
Load resistance R
Test Point
Source Pin
Load capacitance C
Figure 11 Load Circuit for Testing LCD Driver Output Characteristics
Rev.1.01 June 28, 2014 45

(8) MIPI DSI Characteristics
Table 33
Differential input IOVCC=1.65V~ 1.95V

VIDTH mV - - 70
high threshold DPHYVCC=1.65V~ 1.95V

VIDTL mV -70 - -
low threshold DPHYVCC=1.65V~ 1.95V
Single-ended IOVCC=1.65V~ 1.95V

VILHS mV -40 - -
input low voltage DPHYVCC=1.65V~ 1.95V
HS-RX
Single-ended IOVCC=1.65V~ 1.95V
VIHHS mV - - 460
input high voltage DPHYVCC=1.65V~ 1.95V
Common-mode voltage IOVCC=1.65V~ 1.95V

VCMRX(DC) mV 70 - 330 1
HS receive mode DPHYVCC=1.65V~ 1.95V

ZID Ω - 100 - 2
impedance DPHYVCC=1.65V~ 1.95V
Logic 0 input voltage IOVCC=1.65V~ 1.95V

VIL mV -50 - 550
not in ULP State DPHYVCC=1.65V~ 1.95V
LP-RX IOVCC=1.65V~ 1.95V

Logic 1 input voltage VIH mV 880 - 1350
I/O leakage current ILEAK µA Vin = -50mV - 1350mV -10 - 10
Thevenin output IOVCC=1.65V~ 1.95V

VOL mV -50 - 50
low level DPHYVCC=1.65V~ 1.95V
Thevenin output IOVCC=1.65V~ 1.95V

LP-TX VOH V 1.1 1.2 1.3
high level DPHYVCC=1.65V~ 1.95V
Output impedance of IOVCC=DPHYVCC=

ZOLP Ω 110 - - 2
LP transmitter 1.80V
Logic 0 IOVCC=1.65V~ 1.95V

VILCD mV - - 200
contention threshold DPHYVCC=1.65V~ 1.95V
CD-RX
Logic 1 IOVCC=1.65V~ 1.95V
VIHCD mV 450 - -
contention threshold DPHYVCC=1.65V~ 1.95V
Notes: 1. VCMRX (DC) = (VP+VDN)/2

2. Excluding COG resistance (contact resistance and ITO wiring resistance).
Rev.1.01 June 28, 2014 46

MIPI DSI HS-RX Clock and Data-Clock Specifications
Table 34
IOVCC=1.65V~ 1.95V
DSICLK Frequency fDSICLK MHz 100 - 500 4
DPHYVCC=1.65V~ 1.95V
IOVCC=1.65V~ 1.95V
DSICLK Cycle time tCLKP ns 1 - 10
IOVCC=1.65V~ 1.95V
DSI Data Transfer Rate tDSIR Mbps 200 - 1000 4
IOVCC=1.65V~ 1.95V
UI 0.15 - - 6
DPHYVCC=1.65V~ 1,95V
Data to Clock Setup Time tSETUP
IOVCC=1.65V~ 1.95V
ns 0.15 - - 5,6
IOVCC=1.65V~ 1.95V
UI 0.15 - - 6
Clock to Data Hold Time tHOLD
IOVCC=1.65V~ 1.95V
ns 0.15 - - 5,6
Notes: 4. When fDSICLK<125MHz, change auto load NV setting so that it is compliant with THS-PREPARE+THS-ZERO
spec.
5. Minimum tSETUP/tHOLD Time is 0.15UI. This value may change according to DSI transfer rate.
6. tSETUP/tHOLD Time is measured without HS-TX Jitter.
Rev.1.01 June 28, 2014 47

MIPI DSI LP-RX/TX Clock and Data-Clock Specifications
Table 35
Test
Item Symbol Unit Min Typ Max Notes
condition
Time to drive LP-00 to prepare IOVCC=DPHYVCC

THS-PREPARE =1.65 ~ 1.95V
40 ns + 4*UI - 85ns + 6*UI
for HS transmission
THS-PREPARE + Time to drive HS-0 THS-PREPARE IOVCC=DPHYVCC
=1.65 ~ 1.95V
145ns + 10*UI - -
before the Sync sequence + THS-ZERO
Time to drive flipped differential
max
state IOVCC=DPHYVCC
THS-TRAIL =1.65 ~ 1.95V
( n*8*UI, - - 1,2
after last payload data bit
60 ns + n*4*UI )
of a HS transmission burst
IOVCC=DPHYVCC
Time to drive LP-11after HS burst THS-EXIT ns =1.65 ~ 1.95V
100 - -
Time to drive LP-00

TTA-GO IOVCC=DPHYVCC 4*TLPTX
after Turnaround Request =1.65 ~ 1.95V
Time-out before new TX side IOVCC=DPHYVCC

TTA-SURE =1.65 ~ 1.95V
1*TLPTX - 2*TLPTX
starts driving
IOVCC=DPHYVCC
Time to drive LP-00 by new TX TTA-GET =1.65 ~ 1.95V
5*TLPTX
Length of any Low-Power state IOVCC=DPHYVCC

TLPX ns =1.65 ~ 1.95V
50 - -
period
Ratio of TLPX(MASTER)/TLPX(SLAVE) IOVCC=DPHYVCC
Ratio TLPX =1.65 ~ 1.95V
2/3 - 3/2
between Master and Slave side
Time that the transmitter shall
continue sending HS clock after the
IOVCC=DPHYVCC
last associated TCLK-POST =1.65 ~ 1.95V
60 ns + 52UI - - 3
Data Lane has transitioned to LP
mode
TCLK-PREPARE +time for lead HS-0 TCLK-PREPARE IOVCC=DPHYVCC

ns =1.65 ~ 1.95V
300 - -
drive period before starting Clock +TCLK-ZERO
Time that the HS clock shall be
driven prior to any associated IOVCC=DPHYVCC
TCLK-PRE UI =1.65 ~ 1.95V
8 - -
Data Lane beginning the transition
from LP to HS mode
Time to drive LP-00 to prepare IOVCC=DPHYVCC
TCLK-PREPARE ns =1.65 ~ 1.95V
38 - 95
for HS clock transmission
Time to drive HS differential state
IOVCC=DPHYVCC
after last payload clock bit TCLK-TRAIL ns =1.65 ~ 1.95V
60 - -
of an HS transmission burst
Time from start of THS-TRAIL IOVCC=DPHYVCC 105 ns +
TEOT =1.65 ~ 1.95V
- - 2
period to start of LP-11 state n*12*UI
Length of Low-Power TX period IOVCC=DPHYVCC
TLPTX1 UI =1.65 ~ 1.95V
- 32 -
in case of using DSI clock
4
Length of Low-Power TX period IOVCC=DPHYVCC
TLPTX2 ns =1.65 ~ 1.95V
- 1/(fosc/4) -
in case of using internal OSC clock
Rev.1.01 June 28, 2014 48

Notes: 1. If a > b then max( a, b ) = a, otherwise max( a, b ) = b

2. Where n = 1 for Forward-direction HS mode.
3. The R63419 can work with this specification although the end part of internal process is remained when Clock
Lane enter LP-11 and the R63419 can work without the remained process if tCLK-POST is more than 512 UI.
4. The R63419 uses DSI clock from the Host processor if Clock Lane is active, and internal oscillator clock if Clock
Lane is disabled.
Figure 12 Data to Clock Timing Definitions
Figure 13 DSI LP Mode
Rev.1.01 June 28, 2014 49

CLK
D0p/D0n
D1p/D1n TLPX THS-PREPARE THS-ZERO

Disconnect
Terminator
VIH(min)
VIL(max)
Capture
LP-11 LP-01 LP-00 1ST Data Bit TEOT LP-11
THS-TRAIL THS-EXIT
Figure 14 HS Data Transmission in Bursts
Clock Lane Disconnect

CLKp/CLKn Terminator
TCLK-POST TEOT
VIH(min)
VIL(max)
TCLK-TRAIL THS-EXIT TLPX TCLK-PREPARE TCLK-ZERO TCLK-PRE
Data Lane Disconnect

TLPX THS-PREPARE
Dp/Dn Terminator
VIH(min)
VIL(max)
Figure 15 Switching the Clock Lane between Clock Transmission and LP Mode
Rev.1.01 June 28, 2014 50

Figure 16 DSI LP Mode
Rev.1.01 June 28, 2014 51

Command List
Table 36 User Command
Command (C) MIPI DCS
Operational Number Of RSP LCD driver
Command /Read (R) Type 1 Note
Code (Hex) Parameter Implementation
/Write(W) Requirement
00h nop C 0 Yes Yes
01h soft_reset C 0 Yes Yes
Read_Display_Idetificat
04h R 15 No Yes
ion_Infomation
Read_Number_of_the_
05h R 1 No Yes
Errors_on_DSI
06h get_red_channel R 1 Yes Yes
07h get_green_channel R 1 Yes Yes
08h get_blue_channel R 1 Yes Yes
Yes
0Ah get_power_mode R 1 Yes
(Bit 6/5/4/3/2 only)
Yes
0Bh get_address_mode R 1 Yes
(Bit 7/6/4/3/0 only)
0Ch get_pixel_format R 1 Yes Yes
0Dh get_display_mode R 1 Yes Yes
Yes
0Eh get_signal_mode R 1 Yes
(Bit 7/6/0 only)
Bit 7/6: Yes
0Fh get_diagnostic_result R 1 Yes (Bit 6 only)
Bit 5/4: Optional
10h enter_sleep_mode C 0 Yes Yes
11h exit_sleep_mode C 0 Yes Yes
12h enter_partial_mode C 0 Yes Yes
13h enter_normal_mode C 0 Yes Yes
20h exit_invert_mode C 0 Yes No
21h enter_invert_mode C 0 Yes No
22h set_all_pixels_off C 0 No Yes
23h set_all_pixels_on C 0 No Yes
26h set_gamma_curve W 1 Yes Yes
28h set_display_off C 0 Yes Yes
29h set_display_on C 0 Yes Yes
2Ah set_column_address W 4 No Yes
2Bh set_page_address W 4 No Yes
2Ch write_memory_start W Variable No Yes
2Dh write_LUT W Variable Optional No
2Eh read_memory_start R Variable No No
30h set_partial_area W 4 Yes Yes
33h set_scroll_area W 6 No No
34h set_tear_off C 0 No Yes
35h set_tear_on W 1 No Yes
Yes
36h set_address_mode W 1 Yes
(Bit 7/6/4/3/0 only)
37h set_scroll_start W 2 No No
Rev.1.01 June 28, 2014 52

Table 37 User Command (continued)

38h exit_idle_mode C 0 Yes Yes
39h enter_idle_mode C 0 Yes Yes
3Ah set_pixel_format W 1 Yes Yes
3Ch write_memory_continue W Variable No Yes
3Eh read_memory_continue R Variable Yes No
44h set_tear_scanline W 2 Yes Yes
45h get_scanline R 2 No No
Write_Display_Brightnes
51h W 1 No Yes
s
Read_Display_Brightnes
52h R 2 No Yes
s_Value
53h Write_Control_Display W 1 No Yes (Bit 5/3/2 only)
Read_Control_Value_Dis
54h R 1 No Yes (Bit 5/3/2 only)
play
Write_Content_Adaptive
55h W 1 No Yes
_Brightness_Control
Read_Content_Adaptive
56h R 1 No Yes
_Brightness_Control
Write_CABC_Minimum_
5Eh W 1 No Yes
Brightness
Read_CABC_Minimum_
5Fh R 2 No Yes
Brightness
Read_Automatic_Brightn
68h ess_Control_Self_Diagno R 1 No Yes (Bit 6 only)
stic_Result
read_Black/White_Low_
70h R 1 No Yes
Bits
71h read_Bkx R 1 No Yes
72h read_Bky R 1 No Yes
73h read_Wx R 1 No Yes
74h read_Wy R 1 No Yes
read_Red/Green_Low_Bi
75h R 1 No Yes
ts
76h read_Rx R 1 No Yes
77h read_Ry R 1 No Yes
78h read_Gx R 1 No Yes
79h read_Gy R 1 No Yes
read_Blue/Acolor_Low_B
7Ah R 1 No Yes
its
7Bh read_Bx R 1 No Yes
7Ch read_By R 1 No Yes
7Dh read_Ax R 1 No Yes
7Eh read_Ay R 1 No Yes
Rev.1.01 June 28, 2014 53


A1h read_DDB_start R 16 Yes Yes
A8h read_DDB_continue R Variable Yes Yes
DAh read_ID1 R 1 No Yes
DBh read_ID2 R 1 No Yes
DCh read_ID3 R 1 No Yes
E1h idlemode BL control W 1 No Yes
read_idlemode_BL_contr
E2h R 1 No Yes
ol
Rev.1.01 June 28, 2014 54

Table 39 Manufacturer Command

Command(C)
Operational Number Of
Function /Read(R) Category
Code (Hex) Parameter
/Write(W)
Manufacturer Command
B0h W/R 1
Access Protect
B1h Low Power Mode Control W/R 1
B3h Interface Setting W/R 3
B4h Interface ID Setting W/R 1
Read Checksum and ECC
B5h R 6
Error Count
B6h DSI Control W/R 3
Checksum and ECC Error
B7h W/R 1
Count Reset
Back Light Control 1 (C=1
B8h W/R 7
GUI)
B9h W/R 7
Still)
BAh W/R 7
Movie)
SRE Control 1 (SRE=1 Weak
BBh W/R 2
setting)
SRE Control 2 (SRE=2
BCh W/R 2
Middle setting)
BDh W/R 2
Strong setting)
BEh External Clock Setting W/R 1
BFh Device code Read R 5
C0h Slew rate adjustment W/R 4
C1h Display Setting 1 W/R 35
C2h Display Setting 2 W/R 8
C3h TPC Sync Control W/R 3
C4h Source Timing Setting W/R 14
C5h Realtime Scaling W/R 1
C6h LTPS Timing Setting W/R 21
C7h Gamma Setting Common Set W/R 30
C8h Digtal Gamma Setting W/R 19
C9h Test Register W/R 19
CAh Color enhancement W/R 57
CBh Panel PIN Control W/R 15
CCh Panel Interface Control W/R 1
CDh Test Register W/R 27
CEh Back Light Control 4 W/R 25
Rev.1.01 June 28, 2014 55

Table 40 Manufacturer Command (continued)

Command(C)
Operational Number Of
Function /Read(R) Category
Code (Hex) Parameter
/Write(W)
Power Setting
D0h W/R 3
(Charge Pump Setting)
D1h Test Register W/R 2
D2h Power Setting for Common W/R 16
D5h VCOM Setting W/R 7

E5h Test Image Generator W/R 4
E6h NVM Access Control W/R 6
E7h Set_DDB write Control W/R 1
E8h NVM Load Control W/R 1
E9h Test Register W/R 38
Compression Method
EAh W/R 6
supported
EBh Compression Method W/R 2
ECh Test Register W/R 4
EDh Test Register W/R 20
EEh Test Register W/R 4
EFh Test Register W/R 2
F0h Test Register W/R 3
FAh Test Register W/R 1
FBh Test Register W/R 1
FCh Test Register W/R 12
FDh Test Register W/R 7
FEh Test Register W/R 11
Refer to the Appendix for a detailed Manufacturer Command list.
Rev.1.01 June 28, 2014 56

Command Accessibility
In the default status, only User Commands and Manufacturer Command Access Protect (MCAP)
register can be accessed. Other commands are recognized as “nop”.
Manufacturer Commands except the MCAP register are accessible by releasing Access Protect. See
Command the description of the MCAP register for details.
Rev.1.01 June 28, 2014 57


Operational Code (Hex) Normal Mode On Normal Mode On Partial Mode On Partial Mode On
Command Idle Mode Off Idle Mode On Idle Mode Off Idle Mode On Sleep Mode On
Sleep Mode Off Sleep Mode Off Sleep Mode Off Sleep Mode Off
00h nop Yes Yes Yes Yes Yes

01h soft_reset Yes Yes Yes Yes Yes
04h read_DDB_start Yes Yes Yes Yes Yes
read_Number_of_the_Erro
05h Yes Yes Yes Yes Yes
rs_on_DSI
0Ah get_power_mode Yes Yes Yes Yes Yes
0Bh get_address_mode Yes Yes Yes Yes Yes
0Ch get_pixel_format Yes Yes Yes Yes Yes
0Dh get_display_mode Yes Yes Yes Yes Yes
0Eh get_signal_mode Yes Yes Yes Yes Yes
0Fh get_diagnostic_result Yes Yes Yes Yes Yes
10h enter_sleep_mode Yes Yes Yes Yes Yes
11h exit_sleep_mode Yes Yes Yes Yes Yes
12h enter_partial_mode Yes Yes Yes Yes Yes
13h enter_normal_mode Yes Yes Yes Yes Yes
22h set_all_pixels_off Yes Yes Yes Yes Yes
23h set_all_pixels_on Yes Yes Yes Yes Yes
26h Set_gamma_curve Yes Yes Yes Yes Yes
28h set_display_off Yes Yes Yes Yes Yes
29h set_display_on Yes Yes Yes Yes Yes
2Ah set_column_address Yes Yes Yes Yes Yes
2Bh set_page_address Yes Yes Yes Yes Yes
2Ch write_memory_start Yes Yes Yes Yes Yes
30h set_partial_area Yes Yes Yes Yes Yes
34h set_tear_off Yes Yes Yes Yes Yes
35h set_tear_on Yes Yes Yes Yes Yes
36h set_address_mode Yes Yes Yes Yes Yes
38h exit_idle_mode Yes Yes Yes Yes Yes
39h enter_idle_mode Yes Yes Yes Yes Yes
3Ah set_pixel_format Yes Yes Yes Yes Yes
3Ch write_memory_continue Yes Yes Yes Yes Yes
44h set_tear_scanline Yes Yes Yes Yes Yes
45h get_scanline Yes Yes Yes Yes No
Rev.1.01 June 28, 2014 58


Normal Mode Normal Mode
Operational Code (Hex) Command Partial Mode On Partial Mode On
On On
Idle Mode Off Idle Mode On Sleep Mode On
Idle Mode Off Idle Mode On
Sleep Mode Off Sleep Mode Off
Sleep Mode Off Sleep Mode Off
51h write_display_brightness Yes Yes Yes Yes Yes

read_display_brightness_
value
53h write_control_display Yes Yes Yes Yes Yes
read_control_value_
display
write_content_adaptive_
brightness_control
read_content_adaptive_
brightness_control
read_automatic_
68h brightness_control_ self- Yes Yes Yes Yes Yes
diagnostic_result
70h read_Black/White_Low_Bits Yes Yes Yes Yes Yes
71h read_Bkx Yes Yes Yes Yes Yes
72h read_Bky Yes Yes Yes Yes Yes
73h read_Wx Yes Yes Yes Yes Yes
74h read_Wy Yes Yes Yes Yes Yes
75h read_Red/Green_Low_Bits Yes Yes Yes Yes Yes
76h read_Rx Yes Yes Yes Yes Yes
77h read_Ry Yes Yes Yes Yes Yes
78h read_Gx Yes Yes Yes Yes Yes
79h read_Gy Yes Yes Yes Yes Yes
7Ah read_Blue/Acolor_Low_Bits Yes Yes Yes Yes Yes
7Bh read_Bx Yes Yes Yes Yes Yes
7Ch read_By Yes Yes Yes Yes Yes
7Dh read_Ax Yes Yes Yes Yes Yes
7Eh read_Ay Yes Yes Yes Yes Yes
A1h read_DDB_start Yes Yes Yes Yes Yes
A8h read_DDB_continue Yes Yes Yes Yes Yes
DAh Read ID1 Yes Yes Yes Yes Yes
DBh Read ID2 Yes Yes Yes Yes Yes
DCh Read ID3 Yes Yes Yes Yes Yes
E1h idlemode_BL_control Yes Yes Yes Yes Yes
E1h read_idlemode_BL_control Yes Yes Yes Yes Yes
Rev.1.01 June 28, 2014 59

Table 43 Manufacturer Command

Operational Code(Hex)
Normal Mode On Normal Mode On Partial Mode On Partial Mode On
Sleep
Command Idle Mode Off Idle Mode On Idle Mode Off Idle Mode On
Mode On
B0h Yes Yes Yes Yes Yes
Access Protect
B1h Low Power Mode Control No No No No Yes
B3h Interface Setting Yes Yes Yes Yes Yes
B4h Interface ID Setting Yes Yes Yes Yes Yes
Read Checksum and ECC
Error Count
B6h DSI Control Yes Yes Yes Yes Yes
Checksum and ECC Error
Count Reset
B8h Backlight Control (1) (GUI) Yes Yes Yes Yes Yes
B9h Backlight Control (2) (Still) Yes Yes Yes Yes Yes
BAh Backlight Control (3) (Movie) Yes Yes Yes Yes Yes
BBh Yes Yes Yes Yes Yes
Weak setting)
BCh Yes Yes Yes Yes Yes
Middle setting)
BDh Yes Yes Yes Yes Yes
Strong setting)
BEh Test Register No No No No No
BFh Device code Read Yes Yes Yes Yes Yes
C0h Slew rate adjustment Yes Yes Yes Yes Yes
C1h Display Setting 1 Yes Yes Yes Yes Yes
C2h Display Setting 2 Yes Yes Yes Yes Yes
C3h TPC Sync. Control Yes Yes Yes Yes Yes
C4h Source Timing Setting Yes Yes Yes Yes Yes
C5h Real Time scaling Yes Yes Yes Yes Yes
C6h LTPS Timing Setting Yes Yes Yes Yes Yes
C7h Gamma Setting Yes Yes Yes Yes Yes
C8h Digital Gamma Setting Yes Yes Yes Yes Yes
C9h Test Register No No No No No
CAh Color enhancement Yes Yes Yes Yes Yes
CBh Panel PIN Control Yes Yes Yes Yes Yes
CCh Panel Interface Control Yes Yes Yes Yes Yes
CDh Test Register No No No No No
CEh Backlight Control (4) Yes Yes Yes Yes Yes
Rev.1.01 June 28, 2014 60

Table 44 Manufacturer Command (continued)

Operational Code(Hex)
Normal Mode On Normal Mode On Partial Mode On Partial Mode On
Sleep
Command Idle Mode Off Idle Mode On Idle Mode Off Idle Mode On
Mode On
Power Setting
D0h Yes Yes Yes Yes Yes
(Charge Pump Setting)
D1h Test Register No No No No No
D2h Power Setting for Common Yes Yes Yes Yes Yes
D3h Test Register Yes Yes Yes Yes Yes
D4h Test Register Yes Yes Yes Yes Yes
D5h VCOM Setting Yes Yes Yes Yes Yes
E5h Test Image Generator Yes Yes Yes Yes Yes
E6h NVM Access control Yes Yes Yes Yes Yes
E7h Set_DDB write control Yes Yes Yes Yes Yes
E8h NVM load control Yes Yes Yes Yes Yes
E9h Test Register No No No No No
Compression Method
EAh No No No No No
supported
EBh Compression Method No No No No No
ECh Test Register No No No No No
EDh Test Register No No No No No
EEh Test Register No No No No No
EFh Test Register No No No No No
F0h Test Register No No No No No
FAh Test Register No No No No No
FBh Test Register No No No No No
FCh Test Register No No No No No
FDh Test Register No No No No No
FEh Test Register No No No No No
Rev.1.01 June 28, 2014 61

Default Modes and Values

Operational Default Modes and Values(Hex)
Command Parameters
Code(Hex) After Power-on After SW Reset After HW Reset
00h nop None N/A N/A N/A
01h soft_reset None N/A N/A N/A
MS byte of Supplier MS byte of Supplier MS byte of Supplier
1st
ID (Note2) ID (Note2) ID (Note2)
LS byte of Supplier LS byte of Supplier LS byte of Supplier
2nd
3rd Elective Data Elective Data Elective Data
(Note2) (Note2) (Note2)
LS byte of Supplier LS byte of Supplier MS byte of Supplier
4th Elective Data Elective Data Elective Data
04h read_DDB_start (Note2) (Note2) (Note2)
Extend DDB ID1 Extend DDB ID1 Extend DDB ID1
5th
6th
7th
8th-14th XXh XXh XXh
th
15 FFh FFh FFh
read_Number_of_the_Er
05h 1st 00h 00h 00h
rors_on_DSI
06h get_red_channel 1st 00h 00h 00h
07h get_green_channel 1st 00h 00h 00h
st
08h get_blue_channel 1 00h 00h 00h
st
0Ah get_power_mode 1 08h 08h 08h
st
0Bh get_address_mode 1 00h 00h 00h
st
0Ch get_pixel_format 1 70h 70h 70h
st
0Dh get_display_mode 1 00h 00h 00h
st
0Eh get_signal_mode 1 00h 00h 00h
st
0Fh get_diagnostic_result 1 00h 00h 00h
10h enter_sleep_mode None Sleep Mode On Sleep Mode On Sleep Mode On
11h exit_sleep_mode None Sleep Mode On Sleep Mode On Sleep Mode On
Normal Display Normal Display Normal Display
12h enter_partial_mode None
Mode On Mode On Mode On
13h enter_normal_mode None
22h set_all_pixels_off None
23h set_all_pixels_on None
26h set_gamma_curve 1st 01h 01h 01h
Rev.1.01 June 28, 2014 62


Command Parameters
28h set_display_off None Display Off Display Off Display Off
29h set_display_on None Display Off Display Off Display Off
/
1st 2nd
000h 000h 000h
SC[10:0]
2Ah set_column_address 5FF(HRE1=1’h2)
3rd/4th
63Fh 59Fh(HRE1=1’h1) 63Fh
EC[10:0]
63Fh(HRE1=1’h0)
/
1st 2nd
000h 000h 000h
SP[10:0]
2Bh set_page_address
3rd/4th
9FFh 9FFh 9FFh
EP[11:0]
2Ch write_memory_start all Random values Not cleared Not cleared
1st/2nd
000h 000h 000h
SR[10:0]
30h set_partial_area
3rd/4th
77Fh 77Fh 77Fh
ER[10:0]
34h set_tear_off 6 TE line output Off TE line output Off TE line output Off
35h set_tear_on 1st TE line output Off TE line output Off TE line output Off
36h set_address_mode 1st 00h No Change (Note1) 00h
38h exit_idle_mode None
39h enter_idle_mode None
3Ah set_pixel_format 1st 70h 70h 70h
3Ch write_memory_continue all Random values Not cleared Not cleared
1st/2nd
44h set_tear_scanline 000h 000h 000h
STS[11:0]
51h write_display_brightness 1st 00h 00h 00h
read_display_brightness
52h 1st 00h 00h 00h
_ value
53h wite_CTRL_display 1st 00h 00h 00h
read_control_value_
54h 1st 00h 00h 00h
display
write_content_adaptive_
55h 1st 00h 00h 00h
brightness_control
read_content_adaptive_
56h 1st 00h 00h 00h
brightness_control
Rev.1.01 June 28, 2014 63


Command Parameters
write_CABC_minimum_
5Eh 1st 00h 00h 00h
brightness
read_CABC_minimum_
5Fh 1st 00h 00h 00h
brightness
read_automatic_
68h brightness_control_ self- 1st 00h 00h 00h
diagnostic_result
read_Black/White_Low_
70h 1st 00h 00h 00h
Bits
71h read_Bkx 1st 00h 00h 00h
72h read_Bky 1st 00h 00h 00h
73h read_Wx 1st 00h 00h 00h
74h read_Wy 1st 00h 00h 00h
read_Red/Green_Low_B
75h 1st 00h 00h 00h
its
76h read_Rx 1st 00h 00h 00h
77h read_Ry 1st 00h 00h 00h
78h read_Gx 1st 00h 00h 00h
79h read_Gy 1st 00h 00h 00h
read_Blue/Acolor_Low_
7Ah 1st 00h 00h 00h
Bits
7Bh read_Bx 1st 00h 00h 00h
7Ch read_By 1st 00h 00h 00h
7Dh read_Ax 1st 00h 00h 00h
Rev.1.01 June 28, 2014 64


Command Parameters
1st
LS byte of Supplier LS byte of Supplier LS byte of Supplier
2nd
3rd Elective Data Elective Data Elective Data
LS byte of Supplier LS byte of Supplier MS byte of Supplier
4th Elective Data Elective Data Elective Data
A1h read_DDB_start (Note2) (Note2) (Note2)
5th
6th
7th
8th - 14th xxh xxh xxh
15th FFh FFh FFh
See See See
A8h read_DDB_continue Variable
read_DDB_start. read_DDB_start. read_DDB_start.
DAh Read ID1 1st 00h 00h 00h
DBh Read ID2 1st 00h 00h 00h
DCh Read ID3 1st 00h 00h 00h
E1h idlemode_BL_control 1st 00h 00h 00h
read_dlemode_BL_contr
E2h 1st 00h 00h 00h
ol
Notes: 1. No change from the value before soft_reset command.

2. Data are loaded from internal NVM. If user writes VCM register values, Supplier ID, and Supplier
Elective Data to the NVM, the values are set to default.
Rev.1.01 June 28, 2014 65

User Command
nop: 00h
00h nop
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1  0 0 0 0 0 0 0 0 00h
Parameter None
Description This command is an empty command. It has no effect on the display module.
X = Don’t care
Restriction -
Flow chart -
Rev.1.01 June 28, 2014 66

soft_reset: 01h
01h soft_reset
Command 0 1  0 0 0 0 0 0 0 1 01h
Parameter None
Description When the Software Reset command is written, it causes a software reset. It resets the commands and
parameters to their S/W Reset default values. (See “Default Modes and Values”)
X = Don’t care
Restriction If a soft_reset is sent when the display module is not in Sleep Mode, the host processor needs wait time
before sending an exit_sleep_mode command. (Please refer to the Appendix for maritime.)
soft_reset shall not be sent during exit_sleep_mode sequence.
No new command setting is allowed until the RSP LCD driver enters the Sleep Mode.
See “State Transition Diagram” for the sequence to enter Sleep Mode.
If a soft_reset is sent when the display module is in Sleep Mode, data in NVM are read. No new command
setting is inhibited when data are read (3 ms).
Flow chart
Rev.1.01 June 28, 2014 67

Read_Display_Idetification_Information: 04h
04h Read_Display_Idetification_Infomation
Command 0 1  0 0 0 0 0 1 0 0 04h
Dummy
1  1 X X X X X X X X xxh
parameter
1st ID1 ID1 ID1 ID1 ID1 ID1 ID1 ID1
1  1 XXh
parameter [15] [14] [13] [12] [11] [10] [9] [8]
2nd ID1 ID1 ID1 ID1 ID1 ID1 ID ID1
1  1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
3rd ID2 ID2 ID2 ID2 ID2 ID2 ID2 ID2
1  1 XXh
parameter [15] [14] [13] [12] [11] [10] [9] [8]
4th ID2 ID2 ID2 ID2 ID2 ID2 ID2 ID2
1  1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
1  1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
1  1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
7th - 14th
1  1 X X X X X X X X XXh
parameter
15th
1  1 1 1 1 1 1 1 1 1 FFh
parameter
Description ID1[15:0]
ID2[15:0]
ID3[7:0]
ID4[7:0]
The command returns information from the display module as follows:

1st parameter: MS byte of Supplier ID (ID1[15:8])
2nd parameter: LS byte of Supplier ID (ID1[7:0])
3rd parameter: Supplier Elective Data (ID2[15:8])
4th parameter: Supplier Elective Data (ID2[7:0])
5th parameter: Extend DDB ID1 (ID3[7:0])
6th parameter: Extend DDB ID2 (ID4[7:0])
15th parameter: Exit code (FFh)
Supplier ID and Supplier Elective Data stored in internal NVM are read.
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 68

04h Read_Display_Idetification_Infomation
Flow chart
Read_Display_Idetification_Information Legend
Host
Command
RSP LCD driver
Dummy Read Parameter
Display
1st parameter ID1[15:8]
(MS byte of Supplier ID) Action
Mode
2nd parameter ID1[7:0]
(LS byte of Supplier ID) Sequential
transfer
3rd parameter ID2[15:8]

(MS byte of Supplier
Elective Data)
4th parameter ID2[[7:0]

(LS byte of Supplier
Elective Data)
5th parameter ID3[7:0]

(Extend DDB ID1)

(Extend DDB ID2)
7th - 14th parameter xxh
15th parameter FFh

(Exit code)
Note : When this command is read via DSI, dummy read operation is not preformed.
Rev.1.01 June 28, 2014 69

Read_Number _of_the_Errors_on_DSI: 05h
05h Read_Number_of_the_Errors_on_DSI
Command 0 1  0 0 0 0 0 1 0 1 05h
Dummy
parameter
1st
1  1 P7 P6 P5 P4 P3 P2 P1 P0 XXh
parameter
Description This command returns an error count when DSI is used.
P[6:0] indicates an error count. When a count overflows, P[7] is set to 1.
When P[7:0] is 0, D0 (0Eh of get_signal_mode) is set to 0.
When this command is read via DSI, P[7:0] is cleared. When this command is read via interface except
DSI, P[7:0] is not cleared.
X = Don’t care
Restriction -
Flow chart
Rev.1.01 June 28, 2014 70

get_red_channel: 06h
06h get_red_channel
Command 0 1  0 0 0 0 0 1 1 0 06h
Dummy
parameter
1st
1  1 R7 R6 R5 R4 R3 R2 R1 R0 XXh
parameter
Description The display module returns the red component value of the first pixel in the active frame.
This command is only valid for Type 2 and Type 3 display modules.
R7 is the MSB and R0 is the LSB.
Only the relevant bits are used according to the pixel format; unused bits are set to ‘0’
• 18 bit format: R5 is MSB andR0 is LSB. R7 and R6 are set to ‘0’.

• 24 bit format: R7 is MSB and R0 is LSB. All bits are used.
18bit format D7 D6 D5 D4 D3 D2 D1 D0
0 0 R5 R4 R3 R2 R1 R0
R7 R6 R5 R4 R3 R2 R1 R0
Restriction If using compression data transfer, this command does not support.
Flow chart
Rev.1.01 June 28, 2014 71

get_green_channel: 07h
07h get_green_channel
Command 0 1  0 0 0 0 0 1 1 1 07h
Dummy
parameter
1st
1  1 G7 G6 G5 G4 G3 G2 G1 G0 XXh
parameter
Description The display module returns the green component value of the first pixel in the active frame.
G7 is the MSB and G0 is the LSB.
•18 bit format: G5 is MSB and G0 is LSB. G7 and G6 are set to ‘0’.
• 24 bit format: G7 is MSB and G0 is LSB. All bits are used.
0 0 G5 G4 G3 G2 G1 G0
G7 G6 G5 G4 G3 G2 G1 G0
Flow chart
Rev.1.01 June 28, 2014 72

get_blue_channel: 08h
08h get_blue_channel
Command 0 1  0 0 0 0 1 0 0 0 08h
Dummy
parameter
1st
1  1 B7 B6 B5 B4 B3 B2 B1 B0 XXh
parameter
Description The display module returns the blue component value of the first pixel in the active frame.
B7 is the MSB and B0 is the LSB.
• 18 bit format: B5 is MSB and B0 is LSB. B7 and B6 are set to ‘0’.

• 24 bit format: B7 is MSB and B0 is LSB. All bits are used.
0 0 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
Flow chart
Rev.1.01 June 28, 2014 73

get_power_mode: 0Ah
0Ah get_power_mode
Command 0 1  0 0 0 0 1 0 1 0 0Ah
Dummy
parameter
1st IDM PTL SLP NOR DSP
1  1 0 0 0 XXh
parameter ON ON OUT ON ON
Description The display module returns the current power mode as listed below.
Bit Description Comment Command list symbol
D7 Reserved Set to ‘0’. -
D6 Idle Mode On/Off IDMON
D5 Partial Mode On/Off PTLON
D4 Sleep Mode On/Off SLPOUT
D3 Display Normal Mode On/Off NORON
D2 Display On/Off DSPON
 Bit D7 – Reserved
This bit is not applicable. Set to ‘0’. (Not supported)
IDMON
 Bit D6 – Idle Mode On/Off

‘0’ = Idle Mode Off
‘1’ = Idle Mode On
PTLON
 Bit D5 – Partial Mode On/Off

‘0’ = Partial Mode Off
‘1’ = Partial Mode On
SLPOUT
 Bit D4 – Sleep Mode On/Off

‘0’ = Sleep Mode On
‘1’ = Sleep Mode Off
Rev.1.01 June 28, 2014 74

0Ah get_power_mode
Description
NORON
 Bit D3 – Display Normal Mode On/Off

‘0’ = Display Normal Mode Off
‘1’ = Display Normal Mode On
DSPON
 Bit D2 – Display On/Off

‘0’ = Display is Off.
‘1’ = Display is On.
X = Don’t care
Restriction -
Flow chart
Rev.1.01 June 28, 2014 75

get_address_mode: 0Bh
0Bh get_address_mode
Command 0 1  0 0 0 0 1 0 1 1 0Bh
Dummy
0 1  X X X X X X X X XXh
parameter
1st
1  1 B7 B6 0 B4 B3 0 0 B0 XXh
parameter
Description For B4, B3 and B0, please refer to the Appendix for each mode.
Bit Description Comment Command list
symbol
D7 Page Address Order B7
D6 Column Address Order B6
D5 Page/column Order Set to ‘0’ -
D4 Line Address Order B4
D3 RGB/BGR Order B3
D2 Display Data Latch Order Set to ‘0’. -
D0 Switching between common outputs and frame memory B0
 Bit D7 - Page Address Order

‘0’ = Top to Bottom (When set_address_mode D7=’0’)
‘1’ = Bottom to Top (When set_address_mode D7=’1’)
 Bit D6 – Column Address Order

‘0’ = Left to Right (When set_address_mode D6=’0’)
‘1’ = Right to Left (When set_address_mode D6=’1’)
 Bit D5 – Page/column Order

This bit is not applicable. Set to ’0’. (Not supported)
Note : B4, B3 and B0 depand on each Panel Interface mode. See the appendix of each mode.
 Bit D4 – Line Address Order

For bit D4, see “set_address_mode (36h)” and the appendix data sheet.
Rev.1.01 June 28, 2014 76

0Bh get_address_mode
Description
 Bit D3 – RGB/BGR Order
 Bit D2 –Display DataLatch Data Order

 Bit D0 – Switching between common outputs and frame memory

X = Don’t care
Restriction -
Flow Chart
Note: For display mode transition, see “State Transition Diagram.”
Rev.1.01 June 28, 2014 77

get_pixel_format: 0Ch
0Ch get_pixel_format
Command 0 1  0 0 0 0 1 1 0 0 0Ch
Dummy
parameter
1st
1  1 0 D6 D5 D4 0 D2 D2 D0 XXh
parameter
Description This command indicates the current status of the display as described in the table below. This command
setting depends on set_pixel_format (3Ah).
Bit Description Comment
D7 Set to ’0’.
D6 DPI Pixel Format D6
D5 (RGB Interface Color Format) D5
D4 D4
D3 Set to ’0’.
D2 DBI Pixel Format D2
D1 (Control Interface Color Format) D1
D0 D0
 Bits D[6:4] – DPI Pixel Format (DSI Video Mode Control Interface Color Format Selection)
 Bits D[2:1] – DBI Pixel Format (Control Interface and DSI Command Mode ColorFormat
Selection)
 Bits D7 and D3
This bit is not applicable. Set to ‘0’.
Note: See “set_pixel_format (3Ah).”

Control Interface Color Format D6/D2 D5/D1 D4/D0
Setting inhibited 0 0 0
18 bits/pixel (262,144 colors) 1 1 0
24 bits/pixel (16,777,216 colors) 1 1 1
X = Don’t care
Rev.1.01 June 28, 2014 78

0Ch get_pixel_format
Flow chart
Rev.1.01 June 28, 2014 79

get_display_mode: 0Dh
0Dh get_display_mode
DCX RDX WRX DB23-8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1  X 0 0 0 0 1 1 0 1 0Dh
Dummy
1  1 X X X X X X X X X XXh
parameter
1st
1  1 X 0 0 0 D4 D3 D2 D1 D0 XXh
parameter
Description The display module returns the current status of the display as described in the table below.
Command list
symbol
D7 Vertical Scrolling Status Set to ‘0’.
D6 Horizontal Scrolling Status Set to ‘0’.
D5 Inversion On/Off Set to ‘0’.
D4 All Pixels On
D3 All Pixels Off
D2 Gamma Curve Selection D2
 Bit D7 – Vertical Scrolling Status

 Bit D6 – Horizontal Scrolling Status
 Bit D5 – Inversion On/Off
 Bit D4 – All Pixels On
‘0’ = Normal Display, ‘1’ = White Display
 Bit D3 – All Pixels Off
‘0’ = Normal Display, ‘1’ = Black Display
 Bit D[2:0] – Gamma Curve Selection
Gamma Curve Selection D2 D1 D0 Gamma Set(26h) Parameter

Gamma Curve 1 0 0 0 GC0
Gamma Curve 2 0 0 1 Not Defined
Not Defined 1 0 0 Not Defined
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 80

0Dh get_display_mode
Flow chart
Rev.1.01 June 28, 2014 81

get_signal_mode: 0Eh
0Eh get_signal_mode
Command 0 1  0 0 0 0 1 1 1 0 0Eh
Dummy
parameter
RDD
1st
1  1 TEON TELOM 0 0 0 0 0 SM_ xxh
parameter
D0
Description The display module returns the current status of the display as described in the table below.
Command list
symbol
D7 Tearing Effect Line On/Off TEON
D6 Tearing Effect Line Output Mode TELOM
D0 Errors on DSI RDDSM_D0
 Bit D7 – Tearing Effect Line On/Off

‘0’ = Tearing Effect Line is Off.
‘1’ = Tearing Effect Line is On.
 Bit D6 – Tearing Effect Line Output Mode (See “set_tear_on: 35h”)

‘0’ = Mode 1
‘1’ = Mode 2
 Bit D[5:1] – Reserved

 Bit D0 – Errors on DSI (See “read_Number_of_the_Errors_on_DSI: 05h”)

‘0’ = No error
‘1’ = Error
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 82

0Eh get_signal_mode
Flow chart
Rev.1.01 June 28, 2014 83

get_diagnostic_result: 0Fh
0Fh get_diagnostic_result
Command 0 1  0 0 0 0 1 1 1 1 0F
Dummy
parameter
1st 0  1 0 FUNCD 0 0 0 0 0 0 XXh
parameter
Command list
symbol
D7 Register Loading Detection Set to ‘0’. -
D6 Functionality Detection FUNCD
D5 Chip Attachment Detection Set to ‘0’. -
D4 Display Glass Break Detection Set to ‘0’. -
The display module returns the self-diagnostic results following the exit_sleep_mode (11h) as shown in the
table above.
Description  Bit D7 – Register Loading Detection
This bit is not applicable. Set to “0”.
FUNCD
 Bit D6 – Functionality Detection
Note: For D6, see “Self-Diagnostic Function.”
 Bit D5 – Chip Attachment Detection
 Bit D4 –Display Glass Break Detection
Reserved. Set to 0.
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 84

0Fh get_diagnostic_result
Flow chart
Rev.1.01 June 28, 2014 85

enter_sleep_mode: 10h
10h enter_sleep_mode
Command 0 1  0 0 0 1 0 0 0 0 10h
Parameter None
Description This command causes the LCD module to enter the Sleep mode. In this mode, the DC/DC converter, internal
oscillator and panel scanning stop.
See “State Transition Diagram” for each stage of transition.
X = Don’t care
Restriction This command has no effect when the module is already in Sleep mode. Sleep mode can be exited only
when the exit_sleep_mode (11h) is transmitted.
Sending a new command is prohibited while the RSP LCD driver performs either display off sequence or
power off sequence.
Flow chart
Rev.1.01 June 28, 2014 86

exit_sleep_mode: 11h
11h exit_sleep_mode
Command 0 1  0 0 0 1 0 0 0 1 11h
Parameter None
Description This command causes the display module to exit Sleep mode. The DC/DC converter, internal oscillator,
and panel scanning start.
See “State Transition Diagram” for each stage of transition.
X = Don’t care
Restriction This command shall not cause any visual effect on display device when the display module is not in Sleep
mode.
No new command setting is allowed during power on sequence. Operation may continue due to power on
sequence setting. The host processor needs waittime. (Please refer to the Appendix for waittime.) Do not
send any command either in this case.
The host processor needs waittime after sending an enter_sleep_mode command before sending an
exit_sleep_mode command. (Please refer to the Appendix for waittime.)
The display runs the self-diagnostic function after this command is received.
Flow chart
Rev.1.01 June 28, 2014 87

enter_partial_mode: 12h
12h enter_partial_mode
Command 0 1  X 0 0 0 1 0 0 1 0 12h
Parameter None
Description This command causes the display module to enter the Partial Display Mode. In this mode, LEDPWM and
RGB switch signal for panel stop except display area to achieve low power.
The Partial Display Mode window is described by the set_partial_area command (30h). To leave Partial
Display Mode, the enter_normal_mode (13h) should be written.
X = Don’t care
Note: When a command breaks in the middle of frame period in Normal mode, the command is enabled
from the next frame period.
Restriction This command has no effect when the module is already in Partial mode.
Flow chart See “set_partial_area (30h)”.
Rev.1.01 June 28, 2014 88

enter_normal_mode: 13h
13h enter_normal_mode
Command 0 1  X 0 0 0 1 0 0 1 1 13h
Parameter None
Description This command causes the display module to enter the Normal mode. Normal Mode means Partial mode is
off.
X = Don’t care
Note: When a command breaks in the middle of frame period in Partial mode, that command becomes valid
from the next frame period.
Restriction This command has no effect when Normal mode is already active.
Flow chart See the description of command set_partial_area (30h) when using this command.
Rev.1.01 June 28, 2014 89

set_all_pixels_off: 22h
22h set_all_pixels_off
Command 0 1  0 0 1 0 0 0 1 0 22h
Parameter None
Description This command turns the display panel black in “Sleep Out” mode and a status of the “Display On/Off” register
can be “on“ or “off”.
This command makes no change of contents of frame memory.
This command does not change any other status.
(Example)
Host Processor Display Device
“set_all_pixels_on”, “enter_normal_mode” or “enter_partial_mode” commands are used to leave this mode.

The display panel is showing the contents of the frame memory after “enter_normal_mode” and
“enter_partial_mode” command.
Restriction Setting parameters except the above ones is disabled. A selected gamma curve is not changed until a correct
value is set.
Flow chart
Normal display Legend
Command
set_all_pixels_off Parameter
Display
Black display
Action
Mode
Sequential
transter
Rev.1.01 June 28, 2014 90

set_all_pixels_on: 23h
23h set_all_pixels_on
Command 0 1  0 0 1 0 0 0 1 1 23h
Parameter None
Description This command turns the display panel white in “Sleep Out” mode and a status of the “Display On/Off” register
can be “on“ or “off”.
This command makes no change of contents of frame memory.
This command does not change any other status.
(Example)
Host Processor Display Device
“set_all_pixels_off”, “enter_normal_mode” or “enter_partial_mode” commands are used to leave this mode.

The display panel is showing the contents of the frame memory after “enter_normal_mode” and
“enter_partial_mode” command.
value is set.
Flow chart
Normal display Legend
Command
set_all_pixels_off Parameter
Display
White display
Action
Mode
Sequential
transter
Rev.1.01 June 28, 2014 91

set_gamma_curve: 26h
26h set_gamma_curve
Command 0 1  0 0 1 0 0 1 1 0 26h
GC GC GC GC GC GC GC GC
Parameter 1 1  XXh
[7] [6] [5] [4] [3] [2] [1] [0]
Description This command selects a gamma curve set beforehand. A gamma curve is selected from four curves according
to image data.
GC[7:0] parameter Selection
1 GC[0] Gamma Curve 1
- GC[7:1] Reserved (Set to”0”)
X=Don’t care
value is set.
Flow chart
Rev.1.01 June 28, 2014 92

set_display_off: 28h
28h set_display_off
Command 0 1  0 0 1 0 1 0 0 0 28h
Parameter None
Description This command causes the display module to stop displaying image data on the display device.
X = Don’t care
Restriction This command has no effect when the display panel is already off.
Flow chart
Rev.1.01 June 28, 2014 93

set_display_on: 29h
29h set_display_on
Command 0 1  0 0 1 0 1 0 0 1 29h
Parameter None
Description This command causes the display module to start displaying the image data on the display device
X = Don’t care
Restriction This command has no effect when the display panel is already on.
Flow chart
Rev.1.01 June 28, 2014 94

set_column_address: 2Ah
2Ah set_column_address
Command 0 1  0 0 1 0 1 0 1 0 2Ah
1st SC
1 1  0 0 0 0 0 SC[9] SC[8] XXh
parameter [10]
2nd
1 1  SC[7] SC[6] SC[5] SC[4] SC[3] SC[2] SC[1] SC[0] XXh
parameter
3rd EC
1 1  0 0 0 0 0 EC[9] EC[8] XXh
parameter [10]
4th
1 1  EC[7] EC[6] EC[5] EC[4] EC[3] EC[2] EC[1] EC[0] XXh
parameter
Description SC[n:0]
EC[n:0]
This command defines the column extent of the frame memory accessed by the host processor. The
values of SC[n:0] and EC[n:0] are referred when write_memory_start (2Ch) commands are written. No
status bits are changed.
X=Don’t care
Restriction 1.SC [n:0] must be equal to or less than EC[n:0].
2. Set the parameters as follows.
SC[n:0] = 8n ( n = 0, 1, 2, ・・・)
EC[n:0] = 8m - 1 ( m = 1, 2, 3, ・・・)
EC - SC : Refer “Restriction in Using R63419”.
3. The parameters are disregarded in following cases.
SC[n:0] or EC[n:0] > (Column_Address_Max)h
4. The host processor must wait more 15us between the end of write data transfer and this command
5. There is the restriction about EC/SC setting in case of using 2port data transfer.
Refer “Restriction of R63419”.
For the number of bits (n) supported in SC[n:0] and EC[n:0], See “Term Definition.”
X = Don’t care
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2Ah set_column_address
Flow chart
Rev.1.01 June 28, 2014 96

set_page_address: 2Bh
Command 0 1  0 0 1 0 1 0 1 1 2Bh
st
1 SP SP
1 1  0 0 0 0 SP[9] SP[8] XXh
parameter [11] [10]
2nd
1 1  SP[7] SP[6] SP[5] SP[4] SP[3] SP[2] SP[1] SP[0] XXh
parameter
3rd EP EP
1 1  0 0 0 0 EP[9] EP[8] XXh
parameter [11] [10]
4th
1 1  EP[7] EP[6] EP[5] EP[4] EP[3] EP[2] EP[1] EP[0] XXh
parameter
Description SP[n:0]
EP[n:0]
This command defines the page extent of the frame memory accessed by the host processor. The values of
SP[n:0] and EP[n:0] are referred when write_memory_start (2Ch) are written. No status bits are changed.
X=Don’t care
Restriction SP [n:0] must be equal to or less than EP[n:0].
Note: Set the parameters as follows.
SP[n:0] or EP[n:0] > (Row_Address_Max)h
SP[n:0] = 2n (n=0,1,2,…)
EP[n:0] = 2m-1 (m=1,2,3,…)
EP – SP ≧ 2lines
For the number of bits (n) supported in SP[n:0] and EP[n:0], See “Term Definition.”
X = Don’t care
The host processor must wait more 15us between the end of write data transfer and this command.
D7/D0 and D6/D1 flips all display area regardless any window address setting.
Rev.1.01 June 28, 2014 97

Flow chart
Rev.1.01 June 28, 2014 98

write_memory_start: 2Ch
2Ch write_memory_start
Command 0 1  X 0 0 1 0 1 1 0 0 2Ch
st
1 D1 D1 D1 D1 D1 D1 D1 D1 D1 000h
1 1 
pixel data [23:8] [7] [6] [5] [4] [3] [2] [1] [0] …3Fh
Dx Dx Dx Dx Dx Dx Dx Dx Dx 000h
: 1 1 
[23:8] [7] [6] [5] [4] [3] [2] [1] [0] …3Fh
Nth Dn Dn Dn Dn Dn Dn Dn Dn Dn 000h
1 1 
pixel data [23:8] [7] [6] [5] [4] [3] [2] [1] [0] …3Fh
Description This command transfers image data from the host processor to the display module’s frame memory.
No status bits are changed.
If this command is received, the column and page registers are set to the Start Column (SC) and Start Page
(SP) respectively.
If Frame Memory Access and Interface setting (B3h) WEM = 0:
If the number of pixels in transfer data exceed (EC-SC+1)*(EP-SP+1), the extra pixels are ignored.
If Frame Memory Access and Interface setting (B3h) WEM = 1
When the number of pixels in transfer data exceed (EC-SC+1)*(EP-SP+1), the column register and the page
register are set to the Start Column and Start Page respectively. Then subsequent data are written to the
frame memory. Sending any other command will stop writing to the frame memory.
See “Data Format” for each interface write data format.
X=Don’t care.
Restriction In all color modes, there are no restrictions on the length of parameters.
If data is not transferred in units of multiple of 4, the extra data is regarded as invalid.
The host processor must wait more 40 ByteClock between register setting and this command.
Data lane should send Null packet , Nop command or LP-11 during the wait period.
Note: fByteClock = (1/4) * fDSICLK. fByteClock = frequency of ByteClock.
Flow chart
Rev.1.01 June 28, 2014 99

set_partial_area: 30h
Command 0 1  X 0 0 1 1 0 0 0 0 30h
1st SR SR 000h
1 1  X X X 0 0 SR[9] SR[8]
parameter [11] [10] …
2nd XXX
1 1  X SR[7] SR[6] SR[5] SR[4] SR[3] SR[2] SR[1] SR[0] h
parameter
3rd ER ER 000h
1 1  X X X 0 0 ER[9] ER[8]
parameter [11] [10] …
4th XXX
1 1  X ER[7] ER[6] ER[5] ER[4] ER[3] ER[2] ER[1] ER[0] h
parameter
Description
This command defines the partial mode’s display area. There are 2 parameters associated with this
command, the first defines the Start Row (SR) and the second the End Row (ER), as illustrated in the figures
below. SR and ER refer to the Frame Memory Line Pointer.
Rev.1.01 June 28, 2014 100

Description
When End Row is Start Row, a partial area is a 1-row area. X = Don’t care
Restriction SR[n:0] and ER[n:0] must not be greater than a value set by NL. The bits other than SR[n:0] and ER[n:0] are
“Don’t care”. This function cannot be used in MIPI DPI, MIPI DSI Video mode, and Active Refresh mode, in
which display data is written to RAM without using frame memory. For the number of bits (n) supported in
SR[n:0] and ER[n:0], See “Term Definition.”
Flow chart
Rev.1.01 June 28, 2014 101

set_tear_off: 34h
34h set_tear_off
Command 0 1  0 0 1 1 0 1 0 0 34h
Parameter None
Description This command turns off the Tearing Effect output signal from the TE signal line.
X = Don’t care
Restriction This command has no effect when Tearing Effect output is already off.
Flow chart
Rev.1.01 June 28, 2014 102

set_tear_on: 35h
35h set_tear_on
Command 0 1  0 0 1 1 0 1 0 1 35h
st
1 TELO
1 1  X X X X X X X XXh
parameter M
Description This command turns on the display module’s Tearing Effect output signal on the TE signal line. Changing
B4 (Line Refresh Order of set_address_mode (36h)) does not change this output. The Tearing Effect Line
On has one parameter, TELOM, which describes the Tearing Effect Output Line mode. See “TE Pin Output
Signal” for detail.
Vertical blanking period: BP + FP

Note 1: The Tearing Effect Output line shall be low when the display module is in Sleep mode. X = Don’t
care
Restriction This command has no effect when Tearing Effect output is already ON. Changes in parameter TELOM is
enabled from the next frame period.
Flow Chart
Rev.1.01 June 28, 2014 103

set_address_mode: 36h
36h set_address_mode
Command 0 1  0 0 1 1 0 1 1 0 36h
st
1
1 1  B7 B6 0 B4 B3 0 0 B0 XXh
parameter
Description For B7(Video mode), B3 and B0, please see the appendix for each mode.
Bit Description Comment Symbol
D7 Page Address Order B7
D6 Column Address Order B6
D5 Page/Column Addressing Order Set to “0” -
D4 Display Device Line Refresh Order B4
D3 RGB/BGR Order B3
D2 Display Data Latch Data Order Set to “0” -
D1 Flip Horizontal Set to “0” -
D0 Flip Vertical B0
 Bit D7 – Page Address Order

‘0’ = Top to Bottom
‘1’ = Bottom to Top
Note : This function is same as B0. See description of UDS(manufacture command :C1h).
 Bit D6 – Column Address Order

‘0’ = Left to Right
‘1’ = Right to Left
B6=0 B6=1
Host Processor Display Device Host Processor Display Device
SP SP SP SP
B7=0
EP EP EP EP
SC EC SC EC SC EC EC SC
Rev.1.01 June 28, 2014 104

Description
 Bit D5 – Page/Column Addressing Order
 Bit D4 – Display Device Line Refresh Order

See description of UDS(manufacture command :C1h).
 Bit D3 – RGB/BGR Order

‘0’ = RGB When set_address_mode D3 =’0’
‘1’ = BGR When set_address_mode D3 =’1’
 Bit D2 – Display Data Latch Order

 Bit D1 – Flip Horizontal

This bit is not applicable. Set to ‘0’(Not supported)
 Bit D0 – Flip Vertical

‘0’ = Top to Bottom
‘1’ = Bottom to Top
Note : See description of UDS(manufacture command :C1h).
X = Don’t care
Rev.1.01 June 28, 2014 105

Restriction Display flips vertical by setting D7 or D0.
D0
0 1
0 Normal display Flip vertical
D7
1 Flip vertical Flip vertical
D7/D0 flips all display area regardless any window address setting.
Flow chart
Rev.1.01 June 28, 2014 106

exit_idle_mode: 38h
38h exit_idle_mode
Command 0 1 ↑ x 0 0 1 1 1 0 0 0 38h
Parameter None
Description This command causes the display module to exit Idle mode. LCD can display up to maximum 16,777,216
colors.
X = Don’t care
Restriction This command has no effect when the display module is not in Idle mode.
Flow chart
Rev.1.01 June 28, 2014 107

enter_idle_mode: 39h
39h enter_idle_mode
Command 0 1  X 0 0 1 1 1 0 0 1 39h
Parameter None
Description This command causes the display modules to enter Idle mode.
In the idle mode, color expression is reduced. Eight color depth data are displayed using MSB of each R, G,
and B color components in the frame memory.
And frequency of RCLK changes for idle mode. Refer “Reference Clock Generating Function “for detail.
Memory contents vs. Display Color

R[7:0] G[7:0] B[7:0]
Black 0 X X X X X 0 X X X X X 0 X X X X X
Blue 0 X X X X X 0 X X X X X 1 X X X X X
Red 1 X X X X X 0 X X X X X 0 X X X X X
Magenta 1 X X X X X 0 X X X X X 1 X X X X X
Green 0 X X X X X 1 X X X X X 0 X X X X X
Cyan 0 X X X X X 1 X X X X X 1 X X X X X
Yellow 1 X X X X X 1 X X X X X 0 X X X X X
White 1 X X X X X 1 X X X X X 1 X X X X X
X = Don’t care
Restriction This command has no effect when module is already in Idle mode.
Rev.1.01 June 28, 2014 108

39h enter_idle_mode
Flow chart
Rev.1.01 June 28, 2014 109

set_pixel_format: 3Ah
3Ah set_pixel_format
Command 0 1  0 0 1 1 1 0 1 0 3Ah
st
1
1 1  0 D6 D5 D4 0 D2 D1 D0 XXh
parameter
Description This command is used to define the format of RGB picture data, which are to be transferred via the interface.
The formats are shown in the following table.
 Bit D[6:4] – DPI Pixel Format (Video Mode Control Interface Color Format Selection)
 Bit D[2:0] – DBI Pixel Format (Control Interface and DSI Command Mode Color Format
Selection)
 Bits D7 and D3
Control Interface Color Format D6/D2 D5/D1 D4/D0

18 bits/pixel (262,144 colors) 1 1 0
24 bits/pixel (16,777,216 colors) 1 1 1
See "Data Format" for each interface data format.
Note : When the setting disabled bits are set, undesirable image will be displayed on the panel.
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 110

3Ah set_pixel_format
Flow chart
Rev.1.01 June 28, 2014 111

write_memory_continue: 3Ch
3Ch write_memory_continue
Command 0 1  X 0 0 1 1 1 1 0 0 3Ch
000h
1st D1 D1 D1 D1 D1 D1 D1 D1 D1
1 1  ...
pixel data [23:8] [7] [6] [5] [4] [3] [2] [1] [0]
FFFh
000h
Dx Dx Dx Dx Dx Dx Dx Dx Dx
: 1 1  ...
[23:8] [7] [6] [5] [4] [3] [2] [1] [0]
FFFh
000h
Nth Dn Dn Dn Dn Dn Dn Dn Dn Dn
1 1  ...
pixel data [23:8] [7] [6] [5] [4] [3] [2] [1] [0]
FFFh
Description This command transfers image data from the host processor to the display module’s frame memory
continuing from the pixel location following the previous write_memory_continue or write_memory_start
command.
Frame Memory Access and Interface setting (B3h): WEM = 0
If the number of pixels in the transfer data exceed (EC-SC+1)*(EP-SP+1), the extra pixels are ignored.
Frame Memory Access and Interface setting (B3h): WEM = 1
When the number of pixels in the transfer data exceed (EC-SC+1)*(EP-SP+1), the column register and the
page register are reset to the Start Column/Start Page positions, and the subsequent data are written to the
frame memory.
X=Don’t care
Restriction If write_memory_continue command is executed without setting set_column_address (2Ah),
set_page_address (2Bh), and set_address_mode (36h), there is no guarantee that data are correctly written
to the frame memory. If data is not transferred in units of multiple of 4, the extra data is regarded as invalid.
The host processor must wait more 40 ByteClock between register setting and this command.
Data lane should send Null packet , Nop command or LP-11 during the wait period.
Flow chart
Rev.1.01 June 28, 2014 112

set_tear_scanline:44h
44h set_tear_scanline
Command 0 1  0 1 0 0 0 1 0 0 44h
1st STS STS STS STS
1 1  0 0 0 0 0Xh
parameter [11] [10] [9] [8]
2nd STS STS STS STS STS STS STS STS
1 1  XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
Description This command turns on the display module’s Tearing Effect output signal on the TE signal line when the
display module reaches line N defined by STS [n:0].
TE line is unaffected by change in B4 bit of set_address_mode command.
See figure in “TE Pin Output Signal”.
X = Don’t care.
Restriction The command takes affect on the frame following the current frame. Therefore, if the TE signal is already
ON, TE signal is output according to the old set_tear_on and set_tear_scanline commands until the end of
currently scanned frame.
Setting is disabled when TELOM=1 of set_tear_on (35h).
Make sure that STS [n:0] ≤ NL (number of line) + 1.
For the number of bits (n) supported in STS[n:0], See “Term Definition.”
Flow chart
Rev.1.01 June 28, 2014 113

Write_Display_Brightness: 51h
51h Write_Display_Brigtness
Command 0 1  0 1 0 1 0 0 0 1 51h
st
1 DBV DBV DBV DBV DBV DBV DBV DBV
1 1  XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
Description This command is used to adjust the amount of LED light.
DBV
When the amount of LED light is adjusted externally, PWM signal's width is selected by setting DBV
register. This register setting is enabled when CABC function is off.
DBV[7:0] Amount of light
8’ｈ00 None (0%)
8’h01 1/255
8’h02 2/255
8’h03 3/255
: :
8’hFE 254/255
8’hFＦ 255/255 （100%）
X = Don’t care
Restriction
Flow chart
Rev.1.01 June 28, 2014 114

Read_Display_Brightness_Value: 52h
52h Read_Display_Brightness_Value
Command 0 1  0 1 0 1 0 0 1 0 52h
Dummy
parameter
RD_D RD_D RD_D RD_D RD_D RD_D RD_D RD_D
1st
1  1 BV BV BV BV BV BV BV BV XXh
parameter
[7] [6] [5] [4] [3] [2] [1] [0]
RD_D RD_D RD_D RD_D
2nd
1  1 BV_L BV_L BV_L BV_L 0 0 0 0 XXh
parameter
[3] [2] [1] [0]
Description This command returns the current brightness value.
RD_DBV[7:0], RD_DBV_L[3:0]
This register returns the brightness data of the LED that is the source of the current LEDPWM signal, whether
the CABC function is on or off.
X = Don’t care
Restriction In Sleep Mode On, this register setting value is disabled.
Flow chart
Rev.1.01 June 28, 2014 115

Write_Control_Display: 53h
53h Write_Control_Display
Command 0 1  0 1 0 1 0 0 1 1 53h
st
1 BCTR
1 1  X X X DD BL X X XXh
parameter L
Description This command is used to control the CABC function. Set each register only in Sleep Mode On. Do not
change the setting during operation.
BCTRL
The register is used to enable LEDPWM pin output. Set to 0 in a system configuration without the
LEDPWM pin. Set to 1 in a system configuration with the LEDPWM pin.
DD
This register is used to enable / disable PWM's dimming function. The register is used to control change in
brightness (change in PWM signal) when DBV register is rewritten or LEDPWM pin is turned on. This bit is
applied to DBV register setting and not to brightness change by the CABC function.
DD Dimming function Brightness change
0 Off Changes immediately.
1 On Changes about PWM_DIV
setting.
BL
This register controls on/off of the LEDPWM signal output. Note that LEDPWM is off in sleep mode
regardless of BL value.
BL LEDPWM signal output
0 Off
1 On
X = Don’t care
Restriction
Flow chart
Rev.1.01 June 28, 2014 116

Read_Control_Value_Display: 54h
54h Read_Control_Value_Display
Command 0 1  0 1 0 1 0 1 0 0 54h
Dummy
parameter
1st
1  1 X X BCTRL X DD BL X X XXh
parameter
Description This command indicates the current status of the CABC function set by write_control_display (53h) as
follows.
BCTRL
This register controls on/off of the LEDPWM signal output.
Note that LEDPWM is off in sleep mode regardless of BL value.
DD
This register is used to enable / disable LEDPWM's dimming function.
DD Dimming function Brightness change
0 Off Changes immediately.
1 On Changes about PWM_DIV setting.
BL
The register is used to enable LEDPWM pin output.
BL LEDPWM signal output
0 Off system configuration without the LEDPWM pin.
1 On system configuration with the LEDPWM pin.
X = Don’t care
Restriction
Flow chart
Rev.1.01 June 28, 2014 117

Write_Content_Adaptive_Brightness_Control: 55h
55h Write_Content_Adaptive_Brightness_Control
Command 0 1  0 1 0 1 0 1 0 1 55h
st
1 LOCAL SRE
1 1  SRE[1] SRE[0] X X C[1] C[0] XXh
parameter _ON _ON
Description This command is used to control the CABC and the SRE function. Set each register only in Sleep Mode
On. Do not change the setting during operation.
C[1:0]
The CABC function adjusts backlight brightness dynamically and processes image. This register can select
one mode from three according to image data.
C[1] C[0] Function
0 0 Off
0 1 User interface image
1 0 Still image
1 1 Video image
SRE_ON
This register is used to enable / disable the SRE function.
SRE_ON SRE function
0 Off
1 On
SRE[1:0]
This register can select one mode from three setting.
SRE[1] SRE[0] Function
0 0 User Setting
0 1 Weak setting
1 0 Middle setting
1 1 Strong setting
LOCAL_ON
This register is used to enable / disable the Local Area ACO function.
LOCAL_ON Local Area ACO function
0 Off
1 On
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 118

Flow chart
Rev.1.01 June 28, 2014 119

Read_Content_Adaptive_Brightness_Control: 56h
56h Read_Content_Adaptive_Brightness_Control
Command 0 1  0 1 0 1 0 1 1 0 56h
Dummy
parameter
1st LOCA SRE_ SRE SRE
1  1 X X C[1] C[0] XXh
parameter L_ON ON [1] [0]
Description This command indicates the current mode set by write_content_adaptive_brightness_control (55h) as
follows.
C[1:0]
The CABC function adjusts backlight brightness dynamically and processes image. This register can select
one mode from three according to image data.
C[1] C[0] Function
0 0 Off
0 1 User interface image
1 0 Still image
1 1 Video image
SRE_ON
This register is used to enable / disable the SRE function.
SRE_ON SRE function
0 Off
1 On
SRE[1:0]
This register can select one mode from three setting.
SRE[1] SRE[0] Function
0 0 User Setting
0 1 Weak setting
1 0 Middle setting
1 1 Strong setting
LOCAL_ON
This register is used to enable / disable the Local Area ACO function.
LOCAL_ON Local Area ACO function
0 Off
1 On
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 120

Flow chart
Rev.1.01 June 28, 2014 121

Write_CABC_Minimum_Brightness: 5Eh
5Eh Write_CABC_Minimum_Brightness
Command 0 1  0 1 0 1 1 1 1 0 5Eh
st
1 CMB CMB CMB CMB CMB CMB CMB CMB
1 1  XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
Description This command is used to adjust the brightness of the CABC function.
CMB
When the CABC function is used, minimum brightness data is set by setting CMB register. This register
setting value is enabled when the CABC function is on.
CMB[7:0] Amount of light
8’ｈ00 None (0%)
8’h01 1/255
8’h02 2/255
8’h03 3/255
: :
8’hFE 254/255
8’hFＦ 255/255 (100%)
X = Don’t care
Restriction
Flow chart
Rev.1.01 June 28, 2014 122

Read_CABC_Minimum_Brightness: 5Fh
5Fh Read_CABC_Minimum_Brightness
Command 0 1 ↑ 0 1 0 1 1 1 1 1 5Fh
Dummy
parameter
1st CMB CMB CMB CMB CMB CMB CMB CMB
1  1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
2nd
1  1 0 0 0 0 0 0 0 0 XXh
parameter
Description This command returns the current minimum brightness value of the CABC function.
CMB
This register returns the minimum brightness data of the CABC function.
X = Don’t care
Restriction -
Flow chart
Rev.1.01 June 28, 2014 123

Read_Automatic_Brightness_Control_Self_Diagnostic_Result: 68h
68h Read_Automatic_Brightness_Control_Self_Diagnostic_Result
Command 0 1  0 1 1 0 1 0 0 0 68h
Dummy
parameter
1st 1  1 0 FUNCD 0 0 0 0 0 0 XXh
parameter
Command list
symbol
D7 Register Loading Detection Set to ‘0’. -
D6 Functionality Detection FUNCD
D5 Chip Attachment Detection Set to ‘0’. -
D4 Display Glass Break Detection Set to ‘0’. -
The display module returns the self-diagnostic results following the exit_sleep_mode (11h) as shown in the
table above.
Description  Bit D7 – Register Loading Detection
FUNCD
 Bit D6 – Functionality Detection
Note: For D6, see “Self-Diagnostic Function.”
 Bit D5 – Chip Attachment Detection
 Bit D4 –Display Glass Break Detection
Reserved. Set to 0.
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 124

68h Read_Automatic_Brightness_Control_Self_Diagnostic_Result
Legend
read_automatic_
Command
brightness_control_
self_diagnostic_result Parameter
Host
RSP LCD driver Display

Flow chart
Dummy Read
Action
Send 1st parameter Mode
Sequential
transfer
Rev.1.01 June 28, 2014 125

read_Black/White_Low_Bit: 70h
70h read_Black/White_Low_Bit
Command 0 1 ↑ 0 1 1 1 0 0 0 0 70h
Dummy
parameter
1st Bkx Bkx Bky Bky Wx Wx Wy Wy
1  1 XXh
parameter [1] [0] [1] [0] [1] [0] [1] [0]
Description This command returns the lowest bits of black and white color characteristics.
Black : Bkx and Bky
White : Wx and Wy
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_Bkx: 71h
71h read_Bkx
Command 0 1 ↑ 0 1 1 1 0 0 0 1 71h
Dummy
parameter
1st Bkx Bkx Bkx Bkx Bkx Bkx Bkx Bkx
1  1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Bkx[9:2] of black color characteristics.
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 126

read_Bky: 72h
72h read_Bky
Command 0 1 ↑ 0 1 1 1 0 0 1 0 72h
Dummy
parameter
1st Bky Bky Bky Bky Bky Bky Bky Bky
1  1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Bky[9:2] of black color characteristics.
X = Don’t care
Restriction -
read_Wx: 73h
73h read_Wx
Command 0 1 ↑ 0 1 1 1 0 0 1 1 73h
Dummy
parameter
1st Wx Wx Wx Wx Wx Wx Wx Wx
1  1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Wx[9:2] of white color characteristics.
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 127

read_Wy: 74h
74h read_Wy
Command 0 1 ↑ 0 1 1 1 0 1 0 0 74h
Dummy
parameter
1st Wy Wy Wy Wy Wy Wy Wy Wy
1  1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Wy[9:2] of white color characteristics.
X = Don’t care
Restriction -
read_Red/Green_Low_Bit: 75h
75h read_Red/Green_Low_Bit
Command 0 1 ↑ 0 1 1 1 0 1 0 1 75h
Dummy
parameter
1st Rx Rx Ry Ry Gx Gx Gy Gy
1  1 XXh
parameter [1] [0] [1] [0] [1] [0] [1] [0]
Description This command returns the lowest bits of red and green color characteristics.
Red : Rx and Ry
Green : Gx and Gy
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 128

read_Rx: 76h
76h read_Rx
Command 0 1 ↑ 0 1 1 1 0 1 1 0 76h
Dummy
parameter
1st Rx Rx Rx Rx Rx Rx Rx Rx
1  1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Rx[9:2] of red color characteristics.
X = Don’t care
Restriction -
read_Ry: 77h
77h read_Ry
Command 0 1 ↑ 0 1 1 1 0 1 1 1 77h
Dummy
parameter
1st Ry Ry Ry Ry Ry Ry Ry Ry
1  1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Ry[9:2] of red color characteristics.
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 129

read_Gx: 78h
78h read_Gx
Command 0 1 ↑ 0 1 1 1 1 0 0 0 78h
Dummy
parameter
1st Gx Gx Gx Gx Gx Gx Gx Gx
1  1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Gx[9:2] of green color characteristics.
X = Don’t care
Restriction -
read_Gy: 79h
79h read_Gy
Command 0 1 ↑ 0 1 1 1 1 0 0 1 79h
Dummy
parameter
1st Gy Gy Gy Gy Gy Gy Gy Gy
1  1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Gy[9:2] of green color characteristics.
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 130

read_Blue/Acolor_Low_Bit: 7Ah
7Ah read_Blue/Acolor_Low_Bit
Command 0 1 ↑ 0 1 1 1 1 1 0 0 7Ah
Dummy
parameter
1st Bx Bx By By Ax Ax Ay Ay
1  1 XXh
parameter [1] [0] [1] [0] [1] [0] [1] [0]
Description This command returns the lowest bits of blue and A color characteristics.
Blue : Bx and By
A : Ax and Ay
X = Don’t care
Restriction -
read_Bx: 7Bh
7Bh read_Bx
Command 0 1 ↑ 0 1 1 1 1 0 1 1 7Bh
Dummy
parameter
1st Bx Bx Bx Bx Bx Bx Bx Bx
1  1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Bx[9:2] of blue color characteristics.
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 131

read_By: 7Ch
7Ch read_By
Command 0 1 ↑ 0 1 1 1 1 1 0 0 7Ch
Dummy
parameter
1st By By By By By By By By
1  1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the By[9:2] of blue color characteristics.
X = Don’t care
Restriction -
read_Ax: 7Dh
7Dh read_Ax
Command 0 1 ↑ 0 1 1 1 1 1 0 1 7Dh
Dummy
parameter
1st Ax Ax Ax Ax Ax Ax Ax Ax
1  1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Ax[9:2] of A color characteristics.
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 132

read_Ay: 7Eh
7Eh read_Ay
Command 0 1 ↑ 0 1 1 1 1 1 1 0 7Eh
Dummy
parameter
1st Ay Ay Ay Ay Ay Ay Ay Ay
1  1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Ay[9:2] of A color characteristics.
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 133

read_DDB_start: A1h
A1h read_DDB_start
Command 0 1  1 0 1 0 0 0 0 1 A1h
Dummy
parameter
1st ID1 ID1 ID1 ID1 ID1 ID1 ID1 ID1
1  1 XXh
parameter [15] [14] [13] [12] [11] [10] [9] [8]
2nd ID1 ID1 ID1 ID1 ID1 ID1 ID1 ID1
1  1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
3rd ID2 ID2 ID2 ID2 ID2 ID2 ID2 ID2
1  1 XXh
parameter [15] [14] [13] [12] [11] [10] [9] [8]
1  1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
1  1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
1  1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
7th - 14th
parameter
15th
1  1 1 1 1 1 1 1 1 1 FFh
parameter
Description ID1[15:0]
ID2[15:0]
ID3[7:0]
ID4[7:0]

1st parameter: MS byte of Supplier ID (ID1[15:8])
2nd parameter: LS byte of Supplier ID (ID1[7:0])
3rd parameter: Supplier Elective Data (ID2[15:8])
15th parameter: Exit code (FFh)
Supplier ID and Supplier Elective Data stored in internal NVM are read.
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 134

A1h read_DDB_start
read_DDB_start Legend
Host Command
RSP LCD driver
Dummy Read Parameter
Display
1st parameter ID1[15:8]
(MS byte of Supplier ID) Action
Mode
2nd parameter ID1[7:0]
(LS byte of Supplier ID)
Sequential
transfer
3rd parameter ID2[15:8]

(MS byte of Suppilier
Elective Data)

(LS byte of Suppilier
Flow chart Elective Data)
5th parameter ID3[7:0]

(Extend DDB ID1)

(Extend DDB ID2)
8th - 14th parameter xxh
15th parameter FFh

(Exit code)
Note : When this command is read via DSI dummy read operation is not preformed.
Rev.1.01 June 28, 2014 135

read_DDB_continue: A8h
A8h read_DDB_continue
Command 0 1  1 0 1 0 1 0 0 0 A8h
Dummy
parameter
1st DDB0 DDB0 DDB0 DDB0 DDB0 DDB0 DDB0 DDB0
1   XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
DDBx DDBx DDBx DDBx DDBx DDBx DDBx DDBx
： 1   XXh
[7] [6] [5] [4] [3] [2] [1] [0]
Nth
1  1 1 1 1 1 1 1 1 1 FFh
parameter
Description This command continues read operation from the position where the operation is halted by
read_DDB_continue or read_DDB_start. For the position that information is returned, see read_DDB_start
(A1h).
X=Don’t care
Restriction To fix the position that information is returned, execute read_DDB_start command and parameter read
operation at least once before read_DDB_continue command is executed. If they are not executed, the
value returned by read_DDB_continue command is invalid.
[When MIPI DSI is selected]
To fix the position that information is returned, execute read_DDB_start command at least once and
parameter read operation at least once before read_DDB_continue command is executed. Otherwise, data
read with a read_DDB_continue command is undefined.
Note: When this command is read via DSI , dummy read operation is not performed.
Rev.1.01 June 28, 2014 136

A8h read_DDB_continue
read_DDB_start Legend
Host
Command
RSP LCD driver
Parameter
Dummy Read
Display
Nth parameter Action

Flow chart
Mode
Sequential
transfer
Rev.1.01 June 28, 2014 137

read_ID1: DAh
DAh read_ID1
DC RD WR
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
X X X
Command 0 1  1 1 0 1 1 0 1 0 DAh
Dummy
parameter
1st RD ID1 RD ID1 RD ID1 RD ID1 RD ID1 RD ID1 RD ID1 RD ID1
1  1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
Description RDID1[7:0]

1st parameter: RDID1 [7:0]
RDID1 Data stored in internal NVM are read.
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 138

read_ID2: DBh
DBh read_ID2
DC RD WR
X X X
Command 0 1  1 1 0 1 1 0 1 1 DBh
Dummy
parameter
1  1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]

X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 139

read_ID3: DCh
DCh read_ID3
DC RD WR
X X X
Command 0 1  1 1 0 1 1 1 0 0 DCh
Dummy
parameter
1  1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]

X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 140

idlemode_BL_control: E1h
E1h idlemode_BL_control
DC RD WR
X X X
Command 0 1  1 1 1 0 0 0 0 1 E1h
IDLE_
IDLE_
1st MODE_
BL 1  0 0 PWM_ 0 0 0 0 XXh
parameter BL_
EN
EN
Description The content of the register idlemode_BL_control will define the functionality of the transmissive LCD display backlight
behavior in idle mode which is enabled by enter_idle_mode command. In this mode, the backlight power consumption
will be reduced.

 Bit D5 – IDLE_PWM_EN

 Bit D0 – IDLE_MODE_BL_EN
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 141

read_idlemode_BL_control: E2h
E2h read_idlemode_BL_control
DC RD WR
X X X
Command 0 1  1 1 1 0 0 0 0 1 E2h
Dummy
parameter
IDLE_
IDLE_
1st MODE_
BL  1 0 0 PWM_ 0 0 0 0 XXh
parameter BL_
EN
EN
Description This command returns the current state of the register idlemode_BL_control.

 Bit D5 – IDLE_PWM_EN
If entering idle_mode, this bit is ’1’.

 Bit D0 – IDLE_MODE_BL_EN
X = Don’t care
Restriction -
Rev.1.01 June 28, 2014 142

・Manufacturer Command Access Protect : B0h
DCX RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 HEX

Command 0 1 ↑ 1 0 1 1 0 0 0 0 B0
1st
1 ↑ ↑ 0 0 0 0 0 MCAP[2] MCAP[1] MCAP[0] xx
parameter
Register init - - - 0 0 0 0 0 0 1 1 03
MCAP
Description
This register controls access protect of MCS(Manufacturer command Set).
Function Table
MCAP
Command 3
0 1 2 4 other
(default)
MCAP B0h Yes Yes Yes Yes

Additional User
B1h Yes Yes No Yes
Command Setting Setting
B3h-BEh inhibited Not defined
Manufacturer C0h-D8h Yes No No Yes
E1h-E3h
NVM access E0h Fixed Fixed Fixed Yes
Yes : Access Possible(Protect Off)

No : Access impossible(Protect On)
Fixed : Fixed to initial value
Restriction
The all MCS read data in Access Protect On (“No”, “Fixed” in above function table) is “0”.
(Excluding Device Code Read(ALMIDx)).
Rev.1.01 June 28, 2014 143

・Low Power Mode Function : B1h

Command 0 1 ↑ 1 0 1 1 0 0 0 1 B1
1st
1 ↑ ↑ 0 0 0 0 0 0 0 DSTB xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
DSTB
Description
This register controls Deep Standby mode.
Function Table
DSTB Deep Standby mode
0 off
1 on
Restriction
・In enter_sleep_mode only, DSTB can set to 1.
・If read data of BFh/5th parameter is 00h, this command is not supported. Please use RESX=L to
enter deep standby mode..
Rev.1.01 June 28, 2014 144

・Interface Setting : B3h

Command 0 1 ↑ 1 0 1 1 0 0 1 1 B3
1st
1 ↑ ↑ 0 DM[2] DM[1] DM[0] V2CRM WEM 0 RM xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ 0 EPFV[2] EPFV[1] EPFV[0] 0 EPF[2] EPF[1] EPF[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
3rd
1 ↑ ↑ 0 TEI[2] TEI[1] TEI[0] 0 0 0 0 00..FF
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
RM, DM
Description
These registers control display interface.
Function Table
Display control
Display Display data
RM DM Input data Display CABC
interface mode path VSYNC HSYNC
Clock PWM
Command
‘h0 Command RAM->Source Register Register OSC OSC
mode
‘h0 Video through
‘h1 Video Video->Source DSI DSI OSC OSC
mode
‘h2-‘h7 Setting inhibit
‘h0-2 Setting inhibit
Video RAM
‘h1 Video Video->Source DSI DSI OSC OSC
capture mode
‘h1 ‘h2 Setting inhibit
Video to RAM
‘h3 Video RAM->Source DSI Register OSC OSC
mode
Command RAM Mode Video to RAM Mode

RM RM
DM DM
Command Command
mode mode
RAM RAM
Video Video
mode mode
Video Through Mode Video RAM capture Mode

RM RM
DM DM
Command Command
mode mode
RAM RAM
Video Video
mode mode
Restriction
When DM register is changed, please follow a display mode change sequence.
Please input display clock of each interface before sending exit_sleep_mode command.
When using Video to RAM mode, keep following restriction.
Frame rate > BP+NL+FP
Rev.1.01 June 28, 2014 145

V2CRM
Description
This register controls video data capture operation at last frame when display interface is switched
from video mode to command mode by DM register. Refer to “Display mode” for detail.
Function Table
V2CRM Video capture at last frame
‘h0 Disable
‘h1 Enable
Restriction -
WEM
Description
This register controls addressing when memory access reaches to end of window address.
Function Table
WEM Addressing when memory access reaches to end of window address

Stop at end of window address.
0
Address pointer do not return to start point. the extra pixels are ignored.
Return to start point.
1
Sending data are overwritten.
Restriction
Rev.1.01 June 28, 2014 146

TEI
Description
This register controls interval of TE output frame.
Please adjust the value fitted pixel data refresh rate and data transfer rate.
Function Table
TEI Interval of TE signal output
‘h0 Every frame
‘h1 2 frame
‘h2 Setting inhibit
‘h3 4 frame
‘h5 6 frame
Restriction -
EPF
Description
This register controls data format of 18bpp(R,G,B)→24bpp(r,g,b) expansion when data are stored
to internal memory(24bpp).
Function Table
< 24bpp Frame Memory >
set_pixel_format = 18bpp
EPF 18bpp(R,G,B)→24bpp(r,g,b) set_pixel_format = 24bpp
expansion
Set “0” to lower bit
r[7:0]={ R[5:0], 2’h0 }
g[7:0]={ G[5:0], 2’h0 }
’h0 b[7:0]={ B[5:0], 2’h0 }
Exception :
R[5:0], G[5:0],B[5:0]=6’h3F
→ r[7:0],g[7:0],b[7:0]=8’hFF
Set “1” to lower bit r[7:0] = { R[7:0] }
r[7:0]={ R[5:0], 2’h3 } g[7:0] = { G[7:0] }
g[7:0]={ G[5:0], 2’h3 } b[7:0] = { B[7:0] }
’h1 b[7:0]={ B[5:0], 2’h3 }
Exception :
R[5:0], G[5:0],B[5:0]=6’h00
→ r[7:0],g[7:0],b[7:0]=8’h00
Set upper bit data to lower bit
r[7:0]={ R[5:0], R[5:4] }
’h2
g[7:0]={ G[5:0], G[5:4] }
b[7:0]={ B[5:0], B[5:4] }
’h3-7 Setting inhibit Setting inhibit
Restriction -
Rev.1.01 June 28, 2014 147

EPFV
Description
This register controls data format of 18bpp(R,G,B)→24bpp(r,g,b) expansion in video mode.
Function Table
< 24bpp Gray Scale(video mode) >
set_pixel_format = 18bpp
EPFV set_pixel_format = 24bpp
18bpp(R,G,B)→24bpp(r,g,b) expansion
r[7:0]={ R[5:0], 2’h0 }
g[7:0]={ G[5:0], 2’h0 }
’h0 b[7:0]={ B[5:0], 2’h0 }
Exception :
R[5:0], G[5:0],B[5:0]=6’h3F
→ r[7:0],g[7:0],b[7:0]=8’hFF
r[7:0] = { R[7:0] }
r[7:0]={ R[5:0], 2’h3 }
g[7:0] = { G[7:0] }
g[7:0]={ G[5:0], 2’h3 }
b[7:0] = { B[7:0] }
’h1 b[7:0]={ B[5:0], 2’h3 }
Exception :
R[5:0], G[5:0],B[5:0]=6’h00
→ r[7:0],g[7:0],b[7:0]=8’h00
Set upper bit data to lower bit
r[7:0]={ R[5:0], R[5:4] }
’h2
g[7:0]={ G[5:0], G[5:4] }
b[7:0]={ B[5:0], B[5:4] }
’h3-7 Setting inhibit Setting inhibit
Restriction -
Rev.1.01 June 28, 2014 148

・Interface ID setting : B4h

Command 0 1 ↑ 1 0 1 1 0 1 0 0 B4
1st
1 ↑ ↑ DSIVCB[1] DSIVCB[0] 0 0 0 0 DSIVCA[1] DSIVCA[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
DSIVCA
Description
This register controls DSI virtual channel of PortA setting.
The corresponding packets to DSIVCA[1:0] are acceptable.
Function Table
DSIVCA Configuration
‘h0 VC=00
‘h1 VC=01
‘h2 VC=10
‘h3 VC=11
Restriction
Initial value(without writing to NVM) is “0”.
If changing DSIVCA value, please use excluding DSI PortA I/F and write the setting to NVM.
DSIVCB
Description
This register controls DSI virtual channel of PortB setting.
The corresponding packets to DSIVCB[1:0] are acceptable.
Function Table
DSIVCB Configuration
‘h0 VC=00
‘h1 VC=01
‘h2 VC=10
‘h3 VC=11
Restriction
Initial value(without writing to NVM) is “0”.
If changing DSIVCB value, please use excluding DSI PortB I/F and write the setting to NVM.
Rev.1.01 June 28, 2014 149

・Read Checksum and ECC Error Count : B5h

Command 0 1 ↑ 1 0 1 1 0 1 0 1 B5
1st DSICSOUTA[ DSICSOUTA[ DSICSOUTA[ DSICSOUTA[ DSICSOUTA[ DSICSOUTA[ DSICSOUTA[ DSICSOUTA[
1 ↑ 1 xx
parameter 7] 6] 5] 4] 3] 2] 1] 0]
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ 1 DSIECPA[7] DSIECPA[6] DSIECPA[5] DSIECPA[4] DSIECPA[3] DSIECPA[2] DSIECPA[1] DSIECPA[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
3rd
1 ↑ 1 DSIECEA[7] DSIECEA[6] DSIECEA[5] DSIECEA[4] DSIECEA[3] DSIECEA[2] DSIECEA[1] DSIECEA[0] 00..FF
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th DSICSOUTB[ DSICSOUTB[ DSICSOUTB[ DSICSOUTB[ DSICSOUTB[ DSICSOUTB[ DSICSOUTB[ DSICSOUTB[
1 ↑ 1 xx
parameter 7] 6] 5] 4] 3] 2] 1] 0]
Register init - - - 0 0 0 0 0 0 0 0 00
5th
1 ↑ 1 DSIECPB[7] DSIECPB[6] DSIECPB[5] DSIECPB[4] DSIECPB[3] DSIECPB[2] DSIECPB[1] DSIECPB[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
6th
1 ↑ 1 DSIECEB[7] DSIECEB[6] DSIECEB[5] DSIECEB[4] DSIECEB[3] DSIECEB[2] DSIECEB[1] DSIECEB[0] 00..FF
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
DSICSOUTA
Description
The value of Checksum Error count is read out.
Checksum Error count is count up when Checksum Error occurs at receiving DSI Long Packet
This register is cleared to 0 after read out and soft reset. (only operating DSI PortA I/F)
Function Table -
Restriction
The clear operation at DSICSOUTA read out is executed only selected DSI PortA I/F.
Other I/F can read this register’s value. (Zero value is returned in case of using other I/F.)
DSICSOUTB
Description
The value of Checksum Error count is read out.
Checksum Error count is count up when Checksum Error occurs at receiving DSI Long Packet
This register is cleared to 0 after read out and soft reset. (only operating DSI PortB I/F)
Function Table -
Restriction
The clear operation at DSICSOUTB read out is executed only selected DSI PortB I/F.
Other I/F can read this register’s value. (Zero value is returned in case of using other I/F.)
Rev.1.01 June 28, 2014 150

DSIECPA
Description
The value of single ECC Error count is read out. Single bit ECC Error count is count up when 1bit
ECC Error occurs at receiving、DSI Packet Header.
This register is clear to 0 after read out and soft reset. (only operating DSI PortA I/F)
Function Table -
Restriction
The clear operation at DSIECPA read out is executed only selected DSI PortA I/F.
Other I/F cannot read this register’s value.(Zero value is kept in case of using other I/F.)
DSIECPB
Description
The value of single ECC Error count is read out. Single bit ECC Error count is count up when 1bit
ECC Error occurs at receiving、DSI Packet Header.
This register is clear to 0 after read out and soft reset. (only operating DSI PortB I/F)
Function Table -
Restriction
The clear operation at DSIECPB read out is executed only selected DSI PortB I/F.
DSIECEA
Description
The value of Multi bits ECC Error count is read out. Multi bits ECC Error count is count up when
2bit or more ECC Error occurs at receiving、DSI Packet Header.
This register is clear to 0 after read out and soft reset. (only operating DSI PortA I/F)
Function Table -
Restriction
The clear operation at DSIECEA read out is executed only selected DSI PortA I/F.
DSIECEB
Description
The value of Multi bits ECC Error count is read out. Multi bits ECC Error count is count up when
2bit or more ECC Error occurs at receiving、DSI Packet Header.
This register is clear to 0 after read out and soft reset. (only operating DSI PortB I/F)
Function Table -
Restriction
The clear operation at DSIECEB read out is executed only selected DSI PortB I/F.
Other I/F cannot read this register’s value.(Zero value is kept in case of using other me /F.)
Rev.1.01 June 28, 2014 151

・DSI Control : B6h

Command 0 1 ↑ 1 0 1 1 0 1 1 0 B6
1st
1 ↑ ↑ 0 0 1 1 1 DSITXDIV[2] DSITXDIV[1] DSITXDIV[0] xx
parameter
Register init - - - 0 0 1 1 1 0 1 0 3A
2nd DSI_THSSET DSI_THSSET DSI_THSSET
1 ↑ ↑ 1 0 0 1 1 xx
parameter [2] [1] [0]
Register init - - - 1 1 0 0 0 0 1 1 C3
3rd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
DSITXDIV
Description
This register controls the DSICLK dividing ratio for LP mode data transmission.
In case of stopping DSICLK, internal OSC is selected for data transmission clock instead of
DSICLK. Refer “Electrical characteristics” about OSC frequency.
Function Table
DSITXDIV DSICLK dividing ratio
’b00 fDSICLK/8
‘b01 fDSICLK/16
‘b10 fDSICLK/24 (default)
’b11 fDSICLK/32
Configuration of DSITXDIV
Host to DriverIC DriverIC to Host
fTXCLK
Status of Clock Lane Bit Rate fDSICLK Setting of DSITXDIV Bit rate
(=1/TLPTX)
[Mbps] [MHz] (example) [Mbps]
[MHz]
Active ’b11
1000 500 15.63 7.81
950 475 ’b10 19.79 9.90
900 450 18.75 9.38
850 425 17.71 8.85
800 400 16.67 8.33
750 375 15.63 7.81
700 350 14.58 7.29
650 325 13.54 6.77
600 300 ’b01 18.75 9.38
550 275 17.19 8.59
500 250 15.63 7.81
450 225 14.06 7.03
400 200 12.50 6.25
350 175 10.94 5.47
300 150 ’b00 18.75 9.38
250 125 15.63 7.81
200 100 12.50 6.25
Inactive - - -
fOSCCLK/4 fTXCLK/2
(Stop)
Restriction -
Rev.1.01 June 28, 2014 152

DSI_THSSET
Description
This register controls MIPI-DSI DPHY operating frequency.
Please set the suitable value for tHS-PREPARE and tHS-PREPARE+tHS-ZERO.
Function Table
DSI DPHY operating frequency
DSI_THSSET
Min Max
‘h0 100Mbps 180Mbps
‘h6 Reserved Reserved
‘h7 Reserved Reserved
Restriction -
Rev.1.01 June 28, 2014 153

・Checksum and ECC Count : B7h

Command 0 1 ↑ 1 0 1 1 0 1 1 1 B7
1st ERR_CNT_R
1 ↑ ↑ 0 0 0 0 0 0 0 xx
parameter ST
Register init - - - 0 0 0 0 0 0 0 0 00
ERR_CNT_RST
Description
This register resets a DSI error count.
Function Table
ERR_CNT_RST DSI Error count
0 Not clear
1 0 clear
Restriction
After resetting an error count by ERR_CNT_RST=1, it returns to ERR_CNT_RST=0.
Rev.1.01 June 28, 2014 154

・Back Light Control 1 : B8h Please refer to Application Note

Please refer to Appendix

Command 0 1 ↑ 1 0 1 1 1 0 0 0 B8
1st BL_PERCEN BL_PERCEN BL_PERCEN BL_PERCEN BL_PERCEN BL_PERCEN BL_PERCEN
1 ↑ ↑ AUTO_BL1 xx
parameter T1[7] T1[6] T1[5] T1[4] T1[3] T1[2] T1[1]
Register init - - - 0 1 0 1 0 1 1 1 57
2nd AUTO_IMAGE
1 ↑ ↑ BR_INI1[7] BR_INI1[6] BR_INI1[5] BR_INI1[4] BR_INI1[3] BR_INI1[2] BR_INI1[1] xx
parameter 1
Register init - - - 0 0 1 1 1 1 0 1 3D
3rd
1 ↑ ↑ BR_SET1[7] BR_SET1[6] BR_SET1[5] BR_SET1[4] BR_SET1[3] BR_SET1[2] BR_SET1[1] BR_SET1[0] xx
parameter
Register init - - - 0 0 0 1 1 0 0 1 19
4th
1 ↑ ↑ CR_SET1[7] CR_SET1[6] CR_SET1[5] CR_SET1[4] CR_SET1[3] CR_SET1[2] CR_SET1[1] CR_SET1[0] xx
parameter
Register init - - - 0 0 0 1 1 1 1 0 1E
5th APLCR_SET APLCR_SET APLCR_SET APLCR_SET APLCR_SET APLCR_SET APLCR_SET APLCR_SET
1 ↑ ↑ xx
parameter 1[7] 1[6] 1[5] 1[4] 1[3] 1[2] 1[1] 1[0]
Register init - - - 0 0 0 0 1 0 1 0 0A
6th SATU_INI_C1 SATU_INI_C1 SATU_INI_C1 SATU_INI_C1 SATU_INI_C1 SATU_INI_C1 SATU_INI_C1 SATU_INI_C1
1 ↑ ↑ xx
parameter [7] [6] [5] [4] [3] [2] [1] [0]
Register init - - - 0 1 0 1 0 0 0 0 50
7th SATU_SET_ SATU_SET_ SATU_SET_ SATU_SET_ SATU_SET_ SATU_SET_ SATU_SET_ SATU_SET_
1 ↑ ↑ xx
parameter C1[7] C1[6] C1[5] C1[4] C1[3] C1[2] C1[1] C1[0]
Register init - - - 0 1 0 1 0 0 0 0 50
Note) Please refer to Application Note.
Rev.1.01 June 28, 2014 155

・Back Light Control 2 : B9h Please refer to Application Note


Command 0 1 ↑ 1 0 1 1 1 0 0 1 B9
Register init - - - 0 1 1 0 1 1 1 1 6F
2nd AUTO_IMAGE
parameter 2
Register init - - - 0 0 1 1 1 1 0 1 3D
3rd
parameter
Register init - - - 0 0 1 0 1 0 0 0 28
4th
parameter
Register init - - - 0 0 1 1 1 1 0 0 3C
1 ↑ ↑ xx
parameter 2[7] 2[6] 2[5] 2[4] 2[3] 2[2] 2[1] 2[0]
Register init - - - 0 0 0 1 0 1 0 0 14
1 ↑ ↑ xx
parameter [7] [6] [5] [4] [3] [2] [1] [0]
Register init - - - 1 1 0 0 1 0 0 0 C8
1 ↑ ↑ xx
Register init - - - 1 1 0 0 1 0 0 0 C8
Rev.1.01 June 28, 2014 156

・Back Light Control 3 : BAh Please refer to Application Note


Command 0 1 ↑ 1 0 1 1 1 0 1 0 BA
Register init - - - 1 0 1 1 0 1 0 1 B5
2nd AUTO_IMAGE
parameter 3
Register init - - - 0 0 1 1 0 0 1 1 33
3rd
parameter
Register init - - - 0 1 0 0 0 0 0 1 41
4th
parameter
Register init - - - 0 1 1 0 0 1 0 0 64
1 ↑ ↑ xx
parameter 3[7] 3[6] 3[5] 3[4] 3[3] 3[2] 3[1] 3[0]
Register init - - - 0 0 1 0 0 0 1 1 23
1 ↑ ↑ xx
parameter [7] [6] [5] [4] [3] [2] [1] [0]
Register init - - - 1 0 1 0 0 0 0 0 A0
1 ↑ ↑ xx
Register init - - - 1 0 1 0 0 0 0 0 A0
Rev.1.01 June 28, 2014 157

・SRE Control 1 : BBh

Please refer to Application Note

Command 0 1 ↑ 1 0 1 1 1 0 1 1 BB
1st LIGHT_BR1[7 LIGHT_BR1[6 LIGHT_BR1[5 LIGHT_BR1[4 LIGHT_BR1[3 LIGHT_BR1[2 LIGHT_BR1[1 LIGHT_BR1[0
1 ↑ ↑ xx
parameter ] ] ] ] ] ] ] ]
Register init - - - 0 0 0 1 0 1 0 0 14
2nd LIGHT_CR1[7 LIGHT_CR1[6 LIGHT_CR1[5 LIGHT_CR1[4 LIGHT_CR1[3 LIGHT_CR1[2 LIGHT_CR1[1 LIGHT_CR1[0
1 ↑ ↑ xx
parameter ] ] ] ] ] ] ] ]
Register init - - - 0 0 0 1 0 1 0 0 14
Rev.1.01 June 28, 2014 158

・SRE Control 2 : BCh Please refer to Application Note


Command 0 1 ↑ 1 0 1 1 1 1 0 0 BC
1 ↑ ↑ xx
parameter ] ] ] ] ] ] ] ]
Register init - - - 0 0 1 1 0 1 1 1 37
1 ↑ ↑ xx
parameter ] ] ] ] ] ] ] ]
Register init - - - 0 0 1 1 0 0 1 0 32
Rev.1.01 June 28, 2014 159

・SRE Control 3 : BDh Please refer to Application Note


Command 0 1 ↑ 1 0 1 1 1 1 0 1 BD
1 ↑ ↑ xx
parameter ] ] ] ] ] ] ] ]
Register init - - - 0 1 1 0 0 1 0 0 64
1 ↑ ↑ xx
parameter ] ] ] ] ] ] ] ]
Register init - - - 0 0 1 1 0 0 1 0 32
Rev.1.01 June 28, 2014 160

・Test Register : BEh

Command 0 1 ↑ 1 0 1 1 1 1 1 0 BE
1st
1 ↑ ↑ 0 0 0 0 0 1 0 0 xx
parameter
Register init - - - 0 0 0 0 0 1 0 0 04
Rev.1.01 June 28, 2014 161

・Device Code Read Function : BFh

D/CX RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ 1 0 1 1 1 1 1 1 BF
1st
1 ↑ 1 ALMID0[7] ALMID0[6] ALMID0[5] ALMID0[4] ALMID0[3] ALMID0[2] ALMID0[1] ALMID0[0] 00..FF
parameter
Register init - - - 0 0 0 0 0 0 0 1 01
2nd
parameter
Register init - - - 0 0 1 0 0 0 1 0 22
3rd
parameter
Register init - - - 0 0 1 1 0 1 0 0 34
4th
parameter
Register init - - - 0 0 0 1 1 0 0 1 19
5th
1 ↑ 1 0 0 0 0 0 0 1 0 00..FF
parameter
Register init - - - 0 0 0 0 0 0 1 0 02
ALMID0
Description
Upper 8bit of Supplier ID can read by accessing this register.
Function Table
D7 D6 D5 D4 D3 D2 D1 D0 HEX
ALMID0 ALMID0 ALMID0 ALMID0 ALMID0 ALMID0 ALMID0 ALMID0
parameter
[7] [6] [5] [4] [3] [2] [1] [0]
Register
0 0 0 0 0 0 0 1 01h
init
Restriction
ALMID0 can be reading at all MCAP protect level.
ALMID1
Description
Lower 8bit of Supplier ID can read by accessing this register.
Function Table
parameter ALMID1 ALMID1 ALMID1 ALMID1 ALMID1 ALMID1 ALMID1 ALMID1
[7] [6] [5] [4] [3] [2] [1] [0]
Register 0 0 1 0 0 0 1 0 22h
init
Restriction
Rev.1.01 June 28, 2014 162

ALMID2
Description
Upper 8bit of IC part number can read by accessing this register.
Function Table
parameter
[7] [6] [5] [4] [3] [2] [1] [0]
Register
0 0 1 1 0 1 0 0 34h
init
Restriction
ALMID3
Description
Lower 8bit of IC part number can read by accessing this register.
Function Table
parameter
[7] [6] [5] [4] [3] [2] [1] [0]
Register
0 0 0 1 1 0 0 1 19h
init
Restriction
Rev.1.01 June 28, 2014 163

・Slew rate adjustment : C0h

Command 0 1 ↑ 1 1 0 0 0 0 0 0 C0
1st
1 ↑ ↑ SOUTTF2[1] SOUTTF2[0] SOUTTR2[1] SOUTTR2[0] SOUTTF1[1] SOUTTF1[0] SOUTTR1[1] SOUTTR1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
3rd
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
SOUTTR1/2/3/4/5/6, SOUTTF1/2/3/4/5/6
Description
These registers set s Driving ability(Tr/Tf)
SOUTTR1, SOUTTF1: sets a Driving ability(Tr/Tf) SOUT14,15,16
SOUTTR2, SOUTTF2: sets a Driving ability(Tr/Tf) SOUT17,18,19
SOUTTR3, SOUTTF3: sets a Driving ability(Tr/Tf) SOUT1,2,3,4,5,6,7,8
SOUTTR4, SOUTTF4: sets a Driving ability(Tr/Tf) SOUT25,26,27,28,29,30,31,32
SOUTTR5, SOUTTF5: sets a Driving ability(Tr/Tf) SOUT9,10,11,12,13
SOUTTR6, SOUTTF6: sets a Driving ability(Tr/Tf) SOUT20,21,22,23,24
Function Table
Driving
SOUTTR1/2/3/4/5/6 SOUTTF1/2/3/4/5/6 Driving ability(Tf)
ability(Tr)
‘h00 100% ‘h0 100%
‘h01 67% ‘h1 67%
‘h02 33% ‘h2 33%
‘h03 17% ‘h3 17%
SOUTTR1/2/3/4/5/6
SOUTTR1/2 SOUTTF1/2/3/4/5/6
SOUTTF1/2
100% 100%
67% 67%
33% 33%
17% 17%
Rev.1.01 June 28, 2014 164

・Display Setting 1 : C1h


Command 0 1 ↑ 1 1 0 0 0 0 0 1 C1
1st
1 ↑ ↑ BLS BLREV PTLREV REV BGR1 SS1 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ 0 1 1 0 0 HRE1[2] HRE1[1] HRE1[0] xx
parameter
Register init - - - 0 1 1 0 0 0 0 0 60
3rd
1 ↑ ↑ 0 0 0 0 0 0 0 UDS xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th
1 ↑ ↑ GSWAP[7] GSWAP[6] GSWAP[5] GSWAP[4] GSWAP[3] GSWAP[2] GSWAP[1] GSWAP[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
5th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
6th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
7th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
8th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
9th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
10th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
11th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
12th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
13th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
14th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
15th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
16th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
17th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
18th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
19th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
20th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
21th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
22th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
23th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
24th
1 ↑ ↑ 0 DSPODR1[2] DSPODR1[1] DSPODR1[0] 0 DSPODR0[2] DSPODR0[1] DSPODR0[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
25th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
Rev.1.01 June 28, 2014 165

26th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
27th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
28th
1 ↑ ↑ 0 0 SPCON[1] SPCON[0] 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
29th
1 ↑ ↑ 0 BLGCK BLPSW[1] BLPSW[0] 0 0 1 0 xx
parameter
Register init - - - 0 0 0 0 0 0 1 0 02
30th
1 ↑ ↑ FDBS_SW[2] FDBS_SW[1] FDBS_SW[0] 0 0 FDBS[2] FDBS[1] FDBS[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
31th
1 ↑ ↑ HIZ_CANCEL 0 1 BLSOUT1[4] BLSOUT1[3] BLSOUT1[2] BLSOUT1[1] BLSOUT1[0] xx
parameter
Register init - - - 0 0 1 0 0 0 0 0 20
32th
1 ↑ ↑ 0 0 0 0 BLSOUT2[3] BLSOUT2[2] BLSOUT2[1] BLSOUT2[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
33th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
34th
1 ↑ ↑ 0 0 0 0 0 0 0 1 xx
parameter
Register init - - - 0 0 0 0 0 0 0 1 01
35th
1 ↑ ↑ ABSI[1] ABSI[0] 0 1 0 0 0 1 xx
parameter
Register init - - - 0 0 0 1 0 0 0 1 11
Note) Other registers are described in Appendix.
SS1
Description
This register controls output shift direction of source driver.
Register’s value reflects when data are written to line buffer.
Function Table
Source output direction
SS1 BGR1=0 BGR1=1
S1→Sn S1→Sn
0
“R”,”G”,”B” “B”,”G”,”R”
Sn→S1 Sn→S1
1
“R”,”G”,”B” “B”,”G”,”R”
Restriction About relationship between 36h command, SS1 command and PNSLV pin,
refer to “System Configuration for Dual MIPI-DSI Ports”.
BGR1
Description
This register controls data order when display data are written to line buffer.
Please set the suitable value of color filter.
Function Table
BGR1 Order of RGB data when data are written to line buffer
0 (R) (G) (B) → (R) (G) (B)
1 (R) (G) (B) → (B) (G) (R)
Restriction -
Rev.1.01 June 28, 2014 166

REV
Description
This register controls source output level of display period in Normal/Partial/Idle mode.
And this register defines the relation of display data and source level.
Function Table
＜Column/Dot inversion＞
Source output level in display period
REV Image Data
Positive polarity Negative polarity
24’h000000 V255P V255N
0 : : :
24’hFFFFFF V0P V0N
24’h000000 V0P V0N
1 : : :
24’hFFFFFF V255P V255N
Restriction -
PTLREV
Description
This register controls source output level of non-display period.
Function Table
<Column/Dot inversion>
Source output level of non-display period Source Amp. operation in
PTLREV
Positive polarity Negative polarity non-display period
0 VP255 VN255 ON
1 VP0 VN0 ON
Restriction -
BLREV, BLS
Description
This register controls source output level of blank period in Normal/Partial mode.
Function Table
<Column/Dot inversion>
Source output level of blank period Source Amp. operation in blank
BLREV BLS
Positive polarity Negative polarity period
0 0 V255P V255N ON
1 GND GND OFF
1 0 V0P V0N ON
1 HiZ HiZ OFF
Restriction -
Rev.1.01 June 28, 2014 167

HRE1
Description
This register controls assignment of source output.
According to this register setting, display operation mode is defined.
Function Table
Panel resolution control
Assignment of Source pins Output level of
(=CABC resolution)
HRE1 non-assigend
source pins
X(HRE) Y(NL) 2MUX 3MUX
S[1:800],
‘h0 1600RGB 2560 S[1:2400] -
S[1601:2400]
S[1:1080], S[1:720],
‘h1 1440RGB 2560 GND
S[1321:2400] S[1681:2400]
S[1:1152], S[1:768],
‘h2 1536RGB 2560 Random data
S[1249:2400] S[1633:2400]
Restriction
This register is setted in sleep in mode. Please do not change in sleep out mode.
Please set set_column_address and set_page_address again after releasing HWRESET, releasing
DSTB, changing HRE1.
UDS
Description
This register controls scan direction of vertical.
Function Table
DM=’h1(Video through mode)

36h : set_address_mode
UDS
B7 Gate scan direction
0 Forward scan
0
1 Backward scan
0 Backward scan
1
1 Forward scan
DM=’h0(Command mode), ‘h3(Video to RAM mode)

36h : set_address_mode
UDS
B4 B0 or B7 Gate scan direction
0 Forward scan
0
1 Backward scan
0
0 Backward scan
1
1 Forward scan
0 Backward scan
0
1 Forward scan
1
0 Forward scan
1
1 Backward scan
Restriction -
Rev.1.01 June 28, 2014 168

ABSI
Description
This register controls avoiding initial-noisy-pattern lights up.
Only when it’s a mode using RAM, this command becomes effective.
Function Table
ABSI Operation
Initial-noisy-pattern display
‘h0 When establishing the DISPON command before the SLPOUT command, the
DISPON command becomes effective automatically after power-on sequence. In
this case initial-noisy-pattern lights up, if RAM data are not written.
Black image display
‘h1 In case of using this setting, black image data is written to GRAM during power-on
sequence. If any image data are written to GRAM before exit_sleep_mode
command, display starts using this data after set_display_on command.
Written data display
‘h2 The DISPON command does not become effective until 1 frame data are written.
In case of using this setting, be sure to write data for 1frame. If not doing this
operation, display does not start to display wrote data.
Restriction -
Rev.1.01 June 28, 2014 169

・Display Setting 2 : C2h Please refer to Application Note


Command 0 1 ↑ 1 1 0 0 0 0 1 0 C2
1st
1 ↑ ↑ 0 0 0 0 MUX3EN PNSET PNLSEL[1] PNLSEL[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ 0 0 0 0 NL[11] NL[10] NL[9] NL[8] xx
parameter
Register init - - - 0 0 0 0 1 0 1 0 0A
3rd
1 ↑ ↑ NL[7] NL[6] NL[5] NL[4] NL[3] NL[2] NL[1] NL[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th
1 ↑ ↑ 0 0 0 BP[4] BP[3] BP[2] BP[1] BP[0] xx
parameter
Register init - - - 0 0 0 0 1 0 0 0 08
5th
1 ↑ ↑ 0 0 0 FP[4] FP[3] FP[2] FP[1] FP[0] xx
parameter
Register init - - - 0 0 0 0 1 0 0 0 08
6th
1 ↑ ↑ LINEINV[3] LINEINV[2] LINEINV[1] LINEINV[0] 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
7th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
8th
1 ↑ ↑ 0 0 0 FP2[4] FP2[3] FP2[2] FP2[1] FP2[0] xx
parameter
Register init - - - 0 0 0 0 1 0 0 0 08
Note) Other registers are described in Appendix.
PNSET
Description
This register sets a dot inversion method.
Details are described in a paragraph “LINEINV”, please refer it.
Function Table
PNSET Method
‘h0 Spatial configuration mode 1
‘h1 Spatial configuration mode 2
Restriction
This register setting is not usable at the time of 1-line, 3-line, over 14-line and Column inversion.
MUX3EN
Description
This register sets the number of MUX.
Using source pins in 2MUX/3MUX are described in a paragraph “HRE1”, please refer it.
Function Table
MUX3EN MUX mode
‘h0 2MUX
‘h1 3MUX
Restriction
-
Rev.1.01 June 28, 2014 170

LINEINV
Description
This register sets a dot inversion method.
Function Table
LINEINV Method
‘h0 1-line inversion drive
‘hA 24-line inversion drive
‘hB 32-line inversion drive
‘hC 48-line inversion drive
‘hD 64-line inversion drive
‘hE Setting inhibited
‘hF Column inversion
1line inversion drive [spatial configuration mode1] (LINEINV=’h0, PNSET=Don’t care)
2-line inversion drive [spatial configuration mode1] (LINEINV =’h1, PNSET=’h0)
Rev.1.01 June 28, 2014 171

2-line inversion drive [spatial configuration mode2] (LINEINV =’h1, PNSET=’h1
3-line inversion drive [spatial configuration mode1] (LINEINV =’h2, PNSET=Don’t care
Rev.1.01 June 28, 2014 172

odd frame even frame
Line↓ + - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
Rev.1.01 June 28, 2014 173

odd frame even frame
Line↓ + - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
Column inversion
Restriction -
Rev.1.01 June 28, 2014 174

NL
Description
This register controls the number of lines to drive panel.
Function Table
NL Number of lines [line]
‘hA00 2560 lines
Restriction
BP
Description
This register controls the number of line of back porch.
Function Table
BP Number of line of back porch[line]
n＜2 Setting inhibit
‘h2 2 lines
‘h3 3 lines
: :
n n lines
: :
‘h1F 31 lines
Restriction
Setting of BP is different from VBP if using compression data transfer. Refer to “Compression data
transfer”.
Please do not change this register in displaying.
Please refer to Appendix data sheet for detail of setting.
FP
Description
This register controls the number of lines of front porch.
Function Table
FP Number of lines of front porch [line]
‘h2 2 lines
‘h3 3 lines
: :
n n lines
: :
‘h1F 31 lines
Restriction
Rev.1.01 June 28, 2014 175

FP2
Description
This register controls the number of lines of front porch during idle mode (entering by 39h
command).
Function Table
FP2 Number of lines of front porch [line]
‘h2 2 lines
‘h3 3 lines
: :
n n lines
: :
‘h1F 31 lines
Restriction
Rev.1.01 June 28, 2014 176

・Touch Panel Sync Function : C3h

Command 0 1 ↑ 1 1 0 0 0 0 1 1 C3
1st
1 ↑ ↑ 0 0 VSOD[1] VSOD[0] HSOM[1] HSOM[0] 0 TPSYNEN xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ 0 HSOD[6] HSOD[5] HSOD[4] HSOD[3] HSOD[2] HSOD[1] HSOD[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
3rd
1 ↑ ↑ HSOHW[7] HSOHW[6] HSOHW[5] HSOHW[4] HSOHW[3] HSOHW[2] HSOHW[1] HSOHW[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
TPSYNEN
Description
This register set to enable VSOUT, HSOUT output.
Function Table
TPSYNEN VSOUT, HSOUT output
‘h0 OFF (Fixed Low)
‘h1 ON (Active)
Restriction -
HSOM
Description
This register set the HSOUT output timing.
Refer to “Synchronization signal Output for touch panel controller” for details.
Function Table
HSOUT output period
HSOM
Back porch Display period Front porch
(BP) (NL) (FP)
‘h0 Output Output Output
‘h1 Fixed low Output Fixed Low
‘h2 Output Fixed low Output
‘h3 Setting inhibited
Restriction -
Rev.1.01 June 28, 2014 177

VSOD
Description
This register set the VSOUT output timing.
Refer to “Synchronization signal Output for touch panel controller” for details.
Function Table
VSOD VSOUT output timing
‘h0 0 line (First line of back porch)
‘h1 +1 line
‘h2 +2 line
‘h3 +3 line
Restriction -
HSOD
Description
This register set the HSOUT output timing
Function Table
HSOD HSOUT output timing
‘h0 0clk
‘h1 1clk
‘h2 2clk
: :
n n clk
: :
‘h7F 127clk
(1clk=1RCLK)
Restriction -
HSOHW
Description
This register set the high period of HSOUT.
Function Table
HSOHW HSOUT high period
‘h0 0clk
‘h1 1clk
‘h2 2clk
: :
n n clk
: :
‘hFF 255 clk
(1clk=1RCLK)
Restriction -
Rev.1.01 June 28, 2014 178

・Source Timing Setting : C4h

Command 0 1 ↑ 1 1 0 0 0 1 0 0 C4
1st
1 ↑ ↑ 0 1 1 1 0 DIV[2] DIV[1] DIV[0] xx
parameter
Register init - - - 0 1 1 1 0 0 0 0 70
2nd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
3rd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th
1 ↑ ↑ EQW5[3] EQW5[2] EQW5[1] EQW5[0] EQW3[3] EQW3[2] EQW3[1] EQW3[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
5th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
6th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
7th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
8th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
9th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
10th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
11th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
12th
1 ↑ ↑ SNT1[7] SNT1[6] SNT1[5] SNT1[4] SNT1[3] SNT1[2] SNT1[1] SNT1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 1 01
13th
1 ↑ ↑ 0 SNT2[6] SNT2[5] SNT2[4] SNT2[3] SNT2[2] SNT2[1] SNT2[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 1 01
14th
1 ↑ ↑ 0 0 0 0 0 0 0 1 xx
parameter
Register init - - - 0 0 0 0 0 0 0 1 01
Rev.1.01 June 28, 2014 179

DIV
Description
These registers sets the OSC divide ratio of RCLK.
Please refer the paragraph “Internal Reference Clock Generating Function”.
Function Table
DIV Divide ratio on internal display clock

‘h0 1
‘h1 2
Restriction -
EQWx
Description
These registers set the horizontal period of pre-charge, equalize operation.
EQW3-19 : Setting SOUTx pre-charge period.
EQW3,6,8,16 : sets pre-charge(GND) period for rising edge

EQW5,7,9,17 : sets pre-charge(GND) period for falling edge
EQW10,12,14,18 : sets pre-charge (VSP) period for rising edge
EQW11,13,15,19 : sets pre-charge(VSN) period for falling edge
See Appendix for detail which register control which SOUT.
Function Table
EQW3-19 Period
‘h00 0clk
‘h01 1clk
‘h02 2clk
‘h03 3clk
: :
‘hFh 15 clk
(1clk = 1RCLK)
Rev.1.01 June 28, 2014 180

SOUTn EQ
SOUTn timing
EQW3 EQW10 EQW5 EQW11
VGH
SOUTn
VSP
GND
VSN
VGL
<rise> <fall>
Restriction -
Rev.1.01 June 28, 2014 181

SNTx
Description
These registers set s source output delay.
See Appendix for detail of panel control signal timing.
Function Table
SNT1 Delay SNT2,3 Delay

‘h00 1clk ‘h0 1clk
: : : :
n n clk n n clk
: : : :
‘hFF 256clk ‘h7F 126clk
(1clk = 1RCLK)
Please refer to Appendix for detail.
Restriction -
Rev.1.01 June 28, 2014 182

・Realtime Scaling : C5h

Command 0 1 ↑ 1 1 0 0 0 1 0 1 C5
1st
1 ↑ ↑ 0 0 0 0 0 0 RTSRAM RTSON xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
RTSON
Description
This register controls on/off of the Real time Scaling function.
Function Table
RTSON Real Time Scaling
0 Real Time Scaling Off
1 Real Time Scaling On
Restriction
ON/OFF switching of Real time scaling function is possible in Command mode only.
RTSRAM
Description
This register selects input data size.
Function Table
RTSRAM Input data size
0 ×1
1 × 1/4
Restriction
Rev.1.01 June 28, 2014 183

・LTPS Timing Setting : C6h

Command 0 1 ↑ 1 1 0 0 0 1 1 0 C6
1st
1 ↑ ↑ RTN0[7] RTN0[6] RTN0[5] RTN0[4] RTN0[3] RTN0[2] RTN0[1] RTN0[0] xx
parameter
Register init - - - 1 1 0 0 1 0 0 0 C8
2nd
1 ↑ ↑ 0 ST1[6] ST1[5] ST1[4] ST1[3] ST1[2] ST1[1] ST1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
3rd
1 ↑ ↑ SW1[7] SW1[6] SW1[5] SW1[4] SW1[3] SW1[2] SW1[1] SW1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
5th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
6th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
7th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
8th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
9th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
10th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
11th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
12th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
13th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
14th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
15th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
16th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
17th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
18th
1 ↑ ↑ 0 PSWT1[6] PSWT1[5] PSWT1[4] PSWT1[3] PSWT1[2] PSWT1[1] PSWT1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
19th
1 ↑ ↑ PSWW1[7] PSWW1[6] PSWW1[5] PSWW1[4] PSWW1[3] PSWW1[2] PSWW1[1] PSWW1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
20th
1 ↑ ↑ 0 0 PSWG1[5] PSWG1[4] PSWG1[3] PSWG1[2] PSWG1[1] PSWG1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
21th
1 ↑ ↑ RTN2[7] RTN2[6] RTN2[5] RTN2[4] RTN2[3] RTN2[2] RTN2[1] RTN2[0] xx
parameter
Register init - - - 1 1 0 0 1 0 0 0 C8
Rev.1.01 June 28, 2014 184

STx, SWx, PSWTx, PWWx, PSWGx,
Description
The output timing of each panel control signal is set.
STx : Sets the Rising or Falling position of the SOUT signal.
SWx : Sets the High or Low period of the SOUT signal.
PSWTx : Sets the Rising or Falling position of the SOUT signal.
PWWx : Sets the High or Low period of the SOUT signal.
PSWGx : Sets the Non-overlap period of the SOUT signal
Function Table
SWx, PSWWx, Timing STx, Timing
‘h0 Setting inhibit ‘h0 Setting inhibit

: : : :
n n clk n n clk
: : : :
‘hFF 255clk ‘h7F 127clk
PSWGx, Timing PSWTx, Timing
‘h0 Setting inhibit ‘h0 Setting inhibit

: : : :
n n clk n n clk
: : : :
‘h3F 63clk ‘h7F 127clk
(1clk = 1RCLK)
Please refer to Appendix for detail.
Restriction -
Rev.1.01 June 28, 2014 185

RTN0
Description
Sets 1H (line) period.
Function Table
RTN0 Clocks per Line RTN0 Clocks per Line
‘h50 ＞ Setting inhibited ‘h5A 90 clocks

‘h50 80 clocks ‘h5B 91 clocks
‘h51 81 clocks ‘h5C 92 clocks
‘h52 82 clocks ‘h5D 93 clocks
‘h53 83 clocks ‘h5E 94 clocks
‘h54 84 clocks ‘h5F 95 clocks
‘h55 85 clocks : :
‘h56 86 clocks n n clocks
‘h57 87 clocks : :
‘h58 88 clocks ‘hFF 255 clocks
‘h59 89 clocks
(1clk=1RCLK)
Restriction -
RTN2
Description
Sets 1H (line) period.
See Appendix for detail of panel control signal timing during idle mode(entering by 39h command).
Function Table
RTN0 Clocks per Line RTN0 Clocks per Line
‘h50 ＞ Setting inhibited ‘h5A 90 clocks

‘h50 80 clocks ‘h5B 91 clocks
‘h51 81 clocks ‘h5C 92 clocks
‘h52 82 clocks ‘h5D 93 clocks
‘h53 83 clocks ‘h5E 94 clocks
‘h54 84 clocks ‘h5F 95 clocks
‘h55 85 clocks : :
‘h56 86 clocks n n clocks
‘h57 87 clocks : :
‘h58 88 clocks ‘hFF 255 clocks
‘h59 89 clocks
(1clk=1RCLK)
Restriction -
Rev.1.01 June 28, 2014 186

・Gamma Function : C7h

Command 0 1 ↑ 1 1 0 0 0 1 1 1 C7
1st
1 ↑ ↑ 0 VGMP0[6] VGMP0[5] VGMP0[4] VGMP0[3] VGMP0[2] VGMP0[1] VGMP0[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
parameter
Register init - - - 0 0 0 0 1 0 0 0 08
3rd
parameter
Register init - - - 0 0 0 1 0 0 0 0 10
4th
parameter
Register init - - - 0 0 1 0 0 0 0 0 20
5th
parameter
Register init - - - 0 0 1 1 0 0 0 0 30
6th
parameter
Register init - - - 0 0 1 1 1 0 0 0 38
7th
parameter
Register init - - - 0 1 0 0 0 0 0 0 40
8th
parameter
Register init - - - 0 1 0 0 1 0 0 1 49
9th
parameter
Register init - - - 0 0 1 0 1 1 1 1 2F
10th
parameter
Register init - - - 0 0 1 1 1 0 0 0 38
11th
parameter
Register init - - - 0 1 0 0 0 0 1 0 42
12th
parameter
Register init - - - 0 1 0 0 1 1 1 1 4F
13th
parameter
Register init - - - 0 1 0 1 0 1 1 1 57
14th
parameter
Register init - - - 0 1 0 1 1 1 1 1 5F
15th
parameter
Register init - - - 0 1 1 0 0 1 1 1 67
16th
1 ↑ ↑ 0 VGMN0[6] VGMN0[5] VGMN0[4] VGMN0[3] VGMN0[2] VGMN0[1] VGMN0[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
17th
parameter
Register init - - - 0 0 0 0 1 0 0 0 08
18th
parameter
Register init - - - 0 0 0 1 0 0 0 0 10
19th
parameter
Register init - - - 0 0 1 0 0 0 0 0 20
20th
parameter
Register init - - - 0 0 1 1 0 0 0 0 30
21th
parameter
Register init - - - 0 0 1 1 1 0 0 0 38
22th
parameter
Register init - - - 0 1 0 0 0 0 0 0 40
23th
parameter
Register init - - - 0 1 0 0 1 0 0 1 49
24th
parameter
Register init - - - 0 0 1 0 1 1 1 1 2F
25th
parameter
Register init - - - 0 0 1 1 1 0 0 0 38
26th
parameter
Register init - - - 0 1 0 0 0 0 1 0 42
27th
parameter
Register init - - - 0 1 0 0 1 1 1 1 4F
Rev.1.01 June 28, 2014 187

28th
parameter
Register init - - - 0 1 0 1 0 1 1 1 57
29th
parameter
Register init - - - 0 1 0 1 1 1 1 1 5F
30th
parameter
Register init - - - 0 1 1 0 0 1 1 1 67
VGMPn, VGMNn
Description
This registers are applied to source pins.
See “Gamma Correction Function” for detailed description of the parameters.
Function Table -
Restriction -
Rev.1.01 June 28, 2014 188

・Digital Gamma Function : C8h

Command 0 1 ↑ 1 1 0 0 1 0 0 0 C8
1st
1 ↑ ↑ 0 0 0 0 0 0 0 GAMADJ xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ BR0_R1[7] BR0_R1[6] BR0_R1[5] BR0_R1[4] BR0_R1[3] BR0_R1[2] BR0_R1[1] BR0_R1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
3rd
1 ↑ ↑ GAM0_R1[7] GAM0_R1[6] GAM0_R1[5] GAM0_R1[4] GAM0_R1[3] GAM0_R1[2] GAM0_R1[1] GAM0_R1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
5th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
6th
1 ↑ ↑ BR1_R1[7] BR1_R1[6] BR1_R1[5] BR1_R1[4] BR1_R1[3] BR1_R1[2] BR1_R1[1] BR1_R1[0] xx
parameter
Register init - - - 1 1 1 1 1 1 0 0 FC
7th
1 ↑ ↑ TILT1_R1[3] TILT1_R1[2] TILT1_R1[1] TILT1_R1[0] TILT0_R1[3] TILT0_R1[2] TILT0_R1[1] TILT0_R1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
8th
1 ↑ ↑ BR0_G1[7] BR0_G1[6] BR0_G1[5] BR0_G1[4] BR0_G1[3] BR0_G1[2] BR0_G1[1] BR0_G1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
9th
1 ↑ ↑ GAM0_G1[7] GAM0_G1[6] GAM0_G1[5] GAM0_G1[4] GAM0_G1[3] GAM0_G1[2] GAM0_G1[1] GAM0_G1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
10th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
11th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
12th
1 ↑ ↑ BR1_G1[7] BR1_G1[6] BR1_G1[5] BR1_G1[4] BR1_G1[3] BR1_G1[2] BR1_G1[1] BR1_G1[0] xx
parameter
Register init - - - 1 1 1 1 1 1 0 0 FC
13th
1 ↑ ↑ TILT1_G1[3] TILT1_G1[2] TILT1_G1[1] TILT1_G1[0] TILT0_G1[3] TILT0_G1[2] TILT0_G1[1] TILT0_G1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
14th
1 ↑ ↑ BR0_B1[7] BR0_B1[6] BR0_B1[5] BR0_B1[4] BR0_B1[3] BR0_B1[2] BR0_B1[1] BR0_B1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
15th
1 ↑ ↑ GAM0_B1[7] GAM0_B1[6] GAM0_B1[5] GAM0_B1[4] GAM0_B1[3] GAM0_B1[2] GAM0_B1[1] GAM0_B1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
16th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
17th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
18th
1 ↑ ↑ BR1_B1[7] BR1_B1[6] BR1_B1[5] BR1_B1[4] BR1_B1[3] BR1_B1[2] BR1_B1[1] BR1_B1[0] xx
parameter
Register init - - - 1 1 1 1 1 1 0 0 FC
19th
1 ↑ ↑ TILT1_B1[3] TILT1_B1[2] TILT1_B1[1] TILT1_B1[0] TILT0_B1[3] TILT0_B1[2] TILT0_B1[1] TILT0_B1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
Rev.1.01 June 28, 2014 189

GAMADJ
Description
This register is independent gamma adjustment enable On/Off
Refer to the Application Note for Digital Gamma Function.
Function Table
GAMADJ Gamma adjustment
0 Off
1 On
Restriction -
BR0_R, BR1_R, BR0_G, BR1_G, BR0_B, BR1_B
Description
These registers are used to set brightness and contrast
Function Table
Adjustment registers Function
BR0_R,BR1_R Adjustment for Red Brightness and Contrast
BR0_G, BR1_G Adjustment for Green Brightness and Contrast
BR0_B, BR1_B Adjustment for Blue Brightness and Contrast
Restriction -
GAM0_R, GAM1_R, GAM2_R, GAM0_G, GAM1_G, GAM2_G, GAM0_B, GAM1_B, GAM2_B
Description
These registers are used to set gamma curve
Function Table
GAM0_R, GAM1_R, GAM2_R Adjustment for Red gamma curve
GAM0_G, GAM1_G, GAM2_G Adjustment for Green gamma curve
GAM0_B, GAM1_B, GAM2_B Adjustment for Blue gamma curve
Restriction -
TILT0_R, TILT1_R, TILT0_G, TILT1_G, TILT0_B, TILT1_B
Description
These registers are used to fine adjustment of gamma curve
Function Table
TILT0_R, TILT1_R Fine adjustment for Red gamma curve
TILT0_G, TILT1_G Fine adjustment for Green gamma curve
TILT0_B, TILT1_B Fine adjustment for Blue gamma curve
Restriction -
Rev.1.01 June 28, 2014 190

・Test Register : C9h

Command 0 1 ↑ 1 1 0 0 1 0 0 1 C9
1st
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
3rd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
5th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
6th
1 ↑ ↑ 1 1 1 1 1 1 0 0 xx
parameter
Register init - - - 1 1 1 1 1 1 0 0 FC
7th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
8th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
9th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
10th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
11th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
12th
1 ↑ ↑ 1 1 1 1 1 1 0 0 xx
parameter
Register init - - - 1 1 1 1 1 1 0 0 FC
13th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
14th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
15th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
16th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
17th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
18th
1 ↑ ↑ 1 1 1 1 1 1 0 0 xx
parameter
Register init - - - 1 1 1 1 1 1 0 0 FC
19th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
Rev.1.01 June 28, 2014 191

・Color Enhancement : CAh


1st
1 ↑ ↑ PPEN2 Y[2] Y[1] Y[0] YLIM 0 0 CE_ON xx
parameter
Register init - - - 1 0 0 0 0 0 0 0 80
2nd
1 ↑ ↑ PMAX_R[7] PMAX_R[6] PMAX_R[5] PMAX_R[4] PMAX_R[3] PMAX_R[2] PMAX_R[1] PMAX_R[0] xx
parameter
Register init - - - 1 0 0 0 0 0 0 0 80
3rd
1 ↑ ↑ PMAX_Y[7] PMAX_Y[6] PMAX_Y[5] PMAX_Y[4] PMAX_Y[3] PMAX_Y[2] PMAX_Y[1] PMAX_Y[0] xx
parameter
Register init - - - 1 0 0 0 0 0 0 0 80
4th
1 ↑ ↑ PMAX_G[7] PMAX_G[6] PMAX_G[5] PMAX_G[4] PMAX_G[3] PMAX_G[2] PMAX_G[1] PMAX_G[0] xx
parameter
Register init - - - 1 0 0 0 0 0 0 0 80
5th
1 ↑ ↑ PMAX_C[7] PMAX_C[6] PMAX_C[5] PMAX_C[4] PMAX_C[3] PMAX_C[2] PMAX_C[1] PMAX_C[0] xx
parameter
Register init - - - 1 0 0 0 0 0 0 0 80
6th
1 ↑ ↑ PMAX_B[7] PMAX_B[6] PMAX_B[5] PMAX_B[4] PMAX_B[3] PMAX_B[2] PMAX_B[1] PMAX_B[0] xx
parameter
Register init - - - 1 0 0 0 0 0 0 0 80
7th
1 ↑ ↑ PMAX_M[7] PMAX_M[6] PMAX_M[5] PMAX_M[4] PMAX_M[3] PMAX_M[2] PMAX_M[1] PMAX_M[0] xx
parameter
Register init - - - 1 0 0 0 0 0 0 0 80
8th
1 ↑ ↑ 0 0 CENH[9] CENH[8] CENH[7] CENH[6] CENH[5] CENH[4] xx
parameter
Register init - - - 0 0 0 0 1 0 0 0 08
9th
1 ↑ ↑ 0 0 CENL[9] CENL[8] CENL[7] CENL[6] CENL[5] CENL[4] xx
parameter
Register init - - - 0 0 1 0 0 0 0 0 20
10th
1 ↑ ↑ SLOFS[7] SLOFS[6] SLOFS[5] SLOFS[4] SLOFS[3] SLOFS[2] SLOFS[1] SLOFS[0] xx
parameter
Register init - - - 1 0 0 0 0 0 0 0 80
11th
1 ↑ ↑ CEP[7] CEP[6] CEP[5] CEP[4] CEP[3] CEP[2] CEP[1] CEP[0] xx
parameter
Register init - - - 1 1 1 1 1 1 1 1 FF
12th
1 ↑ ↑ CEC_R[7] CEC_R[6] CEC_R[5] CEC_R[4] CEC_R[3] CEC_R[2] CEC_R[1] CEC_R[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
13th
1 ↑ ↑ CEC_Y[7] CEC_Y[6] CEC_Y[5] CEC_Y[4] CEC_Y[3] CEC_Y[2] CEC_Y[1] CEC_Y[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
14th
1 ↑ ↑ CEC_G[7] CEC_G[6] CEC_G[5] CEC_G[4] CEC_G[3] CEC_G[2] CEC_G[1] CEC_G[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
15th
1 ↑ ↑ CEC_C[7] CEC_C[6] CEC_C[5] CEC_C[4] CEC_C[3] CEC_C[2] CEC_C[1] CEC_C[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
16th
1 ↑ ↑ CEC_B[7] CEC_B[6] CEC_B[5] CEC_B[4] CEC_B[3] CEC_B[2] CEC_B[1] CEC_B[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
17th
1 ↑ ↑ CEC_M[7] CEC_M[6] CEC_M[5] CEC_M[4] CEC_M[3] CEC_M[2] CEC_M[1] CEC_M[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
18th
1 ↑ ↑ CEC[7] CEC[6] CEC[5] CEC[4] CEC[3] CEC[2] CEC[1] CEC[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
19th
1 ↑ ↑ CEA1[7] CEA1[6] CEA1[5] CEA1[4] CEA1[3] CEA1[2] CEA1[1] CEA1[0] xx
parameter
Register init - - - 0 0 0 0 1 0 1 0 0A
20th
parameter
Register init - - - 0 1 0 0 1 0 1 0 4A
21th
parameter
Register init - - - 0 0 1 1 0 1 1 1 37
22th
parameter
Register init - - - 1 0 1 0 0 0 0 0 A0
23th
parameter
Register init - - - 0 1 0 1 0 1 0 1 55
24th
parameter
Register init - - - 1 1 1 1 1 0 0 0 F8
25th
1 ↑ ↑ 0 0 CEP1[5] CEP1[4] CEP1[3] CEP1[2] CEP1[1] CEP1[0] xx
parameter
Register init - - - 0 0 0 0 1 1 0 0 0C
26th
parameter
Register init - - - 0 0 0 0 1 1 0 0 0C
27th
parameter
Register init - - - 0 0 1 0 0 0 0 0 20
Rev.1.01 June 28, 2014 192

28th
parameter
Register init - - - 0 0 0 1 0 0 0 0 10
29th
parameter
Register init - - - 0 0 1 1 1 1 1 1 3F
30th
parameter
Register init - - - 0 0 1 1 1 1 1 1 3F
31th
1 ↑ ↑ 0 0 CEC1[5] CEC1[4] CEC1[3] CEC1[2] CEC1[1] CEC1[0] xx
parameter
Register init - - - 0 0 0 1 0 0 0 0 10
32th
parameter
Register init - - - 0 0 0 1 0 0 0 0 10
33th
parameter
Register init - - - 0 0 1 1 1 1 1 1 3F
34th
parameter
Register init - - - 0 0 1 1 1 1 1 1 3F
35th
parameter
Register init - - - 0 0 1 1 1 1 1 1 3F
36th
parameter
Register init - - - 0 0 1 1 1 1 1 1 3F
37th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
38th
1 ↑ ↑ 1 1 1 1 1 1 1 1 xx
parameter
Register init - - - 1 1 1 1 1 1 1 1 FF
39th
1 ↑ ↑ 1 1 1 1 1 1 1 1 xx
parameter
Register init - - - 1 1 1 1 1 1 1 1 FF
40th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
41th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
42th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
43th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
44th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
45th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
46th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
47th
1 ↑ ↑ 1 1 1 1 1 1 1 1 xx
parameter
Register init - - - 1 1 1 1 1 1 1 1 FF
48th
1 ↑ ↑ 1 1 1 1 1 1 1 1 xx
parameter
Register init - - - 1 1 1 1 1 1 1 1 FF
49th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
50th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
51th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
52th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
53th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
54th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
55th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
56th
1 ↑ ↑ 1 1 1 1 1 1 1 1 xx
parameter
Register init - - - 1 1 1 1 1 1 1 1 FF
57th
1 ↑ ↑ 1 1 1 1 1 1 1 1 xx
parameter
Register init - - - 1 1 1 1 1 1 1 1 FF
Note) Please refer to Application Note for Color Enhancement Function.
Rev.1.01 June 28, 2014 193

CE_ON, PPEN2
Description
These registers cotnrol CE on/off.
Function Table
CE_ON PPEN2 CE
0 0 Disable
0 1 Setting inihibit
1 0 Setting inhibit
1 1 Enable
Restriction Do not change these register during displaying.
Rev.1.01 June 28, 2014 194

・Panel Pin Control : CBh


Command 0 1 ↑ 1 1 0 0 1 0 1 1 CB
1st
1 ↑ ↑ SOUTEN[7] SOUTEN[6] SOUTEN[5] SOUTEN[4] SOUTEN[3] SOUTEN[2] SOUTEN[1] SOUTEN[0] xx
parameter
Register init - - - 1 1 1 1 1 1 1 1 FF
2nd
parameter
Register init - - - 1 1 1 1 1 1 1 1 FF
3rd
parameter
Register init - - - 1 1 1 1 1 1 1 1 FF
4th
parameter
Register init - - - 1 1 1 1 1 1 1 1 FF
5th
1 ↑ ↑ SOUTPL[7] SOUTPL[6] SOUTPL[5] SOUTPL[4] SOUTPL[3] SOUTPL[2] SOUTPL[1] SOUTPL[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
6th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
7th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
8th
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
9th SOUTABSPL[ SOUTABSPL[ SOUTABSPL[ SOUTABSPL[ SOUTABSPL[ SOUTABSPL[ SOUTABSPL[ SOUTABSPL[
1 ↑ ↑ xx
parameter 7] 6] 5] 4] 3] 2] 1] 0]
Register init - - - 0 0 0 0 0 0 0 0 00
1 ↑ ↑ xx
parameter 15] 14] 13] 12] 11] 10] 9] 8]
Register init - - - 0 0 0 0 0 0 0 0 00
1 ↑ ↑ xx
parameter 23] 22] 21] 20] 19] 18] 17] 16]
Register init - - - 0 0 0 0 0 0 0 0 00
1 ↑ ↑ xx
parameter 31] 30] 29] 28] 27] 26] 25] 24]
Register init - - - 0 0 0 0 0 0 0 0 00
13th SOUTABSPL
1 ↑ ↑ 1 1 1 0 0 0 0 xx
parameter EN
Register init - - - 1 1 1 0 0 0 0 0 E0
14th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
15th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
Note) Please refer to Appendix.
SOUTENx SOUTPLx
Description
As for SOUTPLx, the control output polarity of SOUT1-n is set up.
SOUTENx controls output enable of SOUT1-n.
Function Table
Command
SOUTx output
SOUTENx SOUTPLx
‘h0 Fix Low
‘h0
‘h1 Fix High
‘h0 Operate(normal)
‘h1
‘h1 Operate(inversion)
Restriction
Rev.1.01 June 28, 2014 195

SOUTABSPLEN SOUTABSPLx
Description
These registers control the porarity of SOUT1-x during abnormal power off sequence.
Function Table
Command SOUTx output during Abnormal

SOUTABSPLEN SOUTABSPLx power-off sequence
‘h0 High or Low
‘h0
‘h1 (According to speficication)
‘h0 Fix Low
‘h1
‘h1 Fix High
Restriction -
Rev.1.01 June 28, 2014 196

・Panel Interface Control : CCh


Command 0 1 ↑ 1 1 0 0 1 1 0 0 CC
1st
1 ↑ ↑ 0 0 LIM[5] LIM[4] LIM[3] LIM[2] LIM[1] LIM[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
LIM
Description
This register controls Panel Interface Mode.
Please select suitable setting for each panel according to Panel Interface Specification.
Function Table
LIM LCD Panel interface Mode
n Please refer to the Appendix data sheet.
Restriction
LIM is defined by the Panel Specification. Please refer to the Appendix data sheet.
Rev.1.01 June 28, 2014 197

・Test Register: CDh

Command 0 1 ↑ 1 1 0 0 1 1 0 1 CD
1st
1 ↑ ↑ 0 0 0 0 0 0 1 1 xx
.
parameter
Register init - - - 0 0 0 0 0 0 1 1 03
2nd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
3rd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
5th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
6th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
7th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
8th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
9th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
10th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
11th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
12th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
13th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
14th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
15th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
16th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
17th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
18th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
19th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
20th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
21th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
22th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
23th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
24th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
25th
1 ↑ ↑ 0 0 0 1 0 0 0 1 xx
parameter
Register init - - - 0 0 0 1 0 0 0 1 11
26th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
27th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
Rev.1.01 June 28, 2014 198

・Back Light Control 4 : CEh


Command 0 1 ↑ 1 1 0 0 1 1 1 0 CE
1st MODE_DIM[2 MODE_DIM[1 MODE_DIM[0 CABC_PTLO
1 ↑ ↑ 0 IMG_DIM[2] IMG_DIM[1] IMG_DIM[0] 00..FF
parameter ] ] ] N
Register init - - - 0 1 0 1 0 1 0 1 55
2nd
1 ↑ ↑ BL_DATA0[7] BL_DATA0[6] BL_DATA0[5] BL_DATA0[4] BL_DATA0[3] BL_DATA0[2] BL_DATA0[1] BL_DATA0[0] 00..FF
parameter
Register init - - - 0 1 0 0 0 0 0 0 40
3rd
parameter
Register init - - - 0 1 0 0 1 0 0 1 49
4th
parameter
Register init - - - 0 1 0 1 0 0 1 1 53
5th
parameter
Register init - - - 0 1 0 1 1 0 0 1 59
6th
parameter
Register init - - - 0 1 0 1 1 1 1 0 5E
7th
parameter
Register init - - - 0 1 1 0 0 0 1 1 63
8th
parameter
Register init - - - 0 1 1 0 1 0 0 0 68
9th
parameter
Register init - - - 0 1 1 0 1 1 1 0 6E
10th
parameter
Register init - - - 0 1 1 1 0 1 0 0 74
11th
parameter
Register init - - - 0 1 1 1 1 1 1 0 7E
12th BL_DATA10[7 BL_DATA10[6 BL_DATA10[5 BL_DATA10[4 BL_DATA10[3 BL_DATA10[2 BL_DATA10[1 BL_DATA10[0
1 ↑ ↑ 00..FF
parameter ] ] ] ] ] ] ] ]
Register init - - - 1 0 0 0 1 0 1 0 8A
1 ↑ ↑ 00..FF
parameter ] ] ] ] ] ] ] ]
Register init - - - 1 0 0 1 1 0 0 0 98
1 ↑ ↑ 00..FF
parameter ] ] ] ] ] ] ] ]
Register init - - - 1 0 1 0 1 0 0 0 A8
1 ↑ ↑ 00..FF
parameter ] ] ] ] ] ] ] ]
Register init - - - 1 0 1 1 1 0 1 1 BB
1 ↑ ↑ 00..FF
parameter ] ] ] ] ] ] ] ]
Register init - - - 1 1 0 1 0 0 0 0 D0
1 ↑ ↑ 00..FF
parameter ] ] ] ] ] ] ] ]
Register init - - - 1 1 1 1 1 1 1 1 FF
18th
1 ↑ ↑ PWM_DIV[7] PWM_DIV[6] PWM_DIV[5] PWM_DIV[4] PWM_DIV[3] PWM_DIV[2] PWM_DIV[1] PWM_DIV[0] 00..FF
parameter
Register init - - - 0 0 0 0 0 1 0 0 04
19th PWM_CYCL PWM_CYCL PWM_CYCL PWM_CYCL PWM_CYCL PWM_CYCL PWM_CYCL PWM_CYCL
1 ↑ ↑ 00..FF
parameter E[7] E[6] E[5] E[4] E[3] E[2] E[1] E[0]
Register init - - - 0 0 0 0 0 0 0 0 00
20th PWM_PERIO PWM_PERIO PWM_PERIO PWM_PERIO PWM_PERIO PWM_PERIO PWM_PERIO PWM_PERIO
1 ↑ ↑ 00..FF
parameter D_UP[7] D_UP[6] D_UP[5] D_UP[4] D_UP[3] D_UP[2] D_UP[1] D_UP[0]
Register init - - - 0 0 0 0 0 1 0 0 04
21th PWM_PERIO PWM_PERIO PWM_PERIO PWM_PERIO PWM_PERIO PWM_PERIO PWM_PERIO PWM_PERIO
1 ↑ ↑ 00..FF
parameter D_DOWN[7] D_DOWN[6] D_DOWN[5] D_DOWN[4] D_DOWN[3] D_DOWN[2] D_DOWN[1] D_DOWN[0]
Register init - - - 0 0 0 0 0 1 0 0 04
PWM_METH PWM_METH PWM_METH PWM_METH
22th PWM_METH PWM_METH PWM_METH PWM_METH
1 ↑ ↑ OD_DOWN[3 OD_DOWN[2 OD_DOWN[1 OD_DOWN[0 00..FF
parameter OD_UP[3] OD_UP[2] OD_UP[1] OD_UP[0]
] ] ] ]
Register init - - - 0 0 0 0 0 0 0 0 00
23th LEDPWMPO PWM_BIT_LE PWM_BIT_LE PWM_BIT_LE
1 ↑ ↑ PWMWM FRC_ON[1] FRC_ON[0] LEDPWMFIX 00..FF
parameter L NGTH[2] NGTH[1] NGTH[0]
Register init - - - 0 0 0 0 0 0 0 0 00
24th BR_AREA_R BR_AREA_R BR_AREA_R BR_AREA_R BR_AREA_R BR_AREA_R BR_AREA_R BR_AREA_R
1 ↑ ↑ 00..FF
parameter ATIO[7] ATIO[6] ATIO[5] ATIO[4] ATIO[3] ATIO[2] ATIO[1] ATIO[0]
Register init - - - 0 1 1 0 1 0 0 1 69
25th CR_AREA_R CR_AREA_R CR_AREA_R CR_AREA_R CR_AREA_R CR_AREA_R CR_AREA_R CR_AREA_R
1 ↑ ↑ 00..FF
parameter ATIO[7] ATIO[6] ATIO[5] ATIO[4] ATIO[3] ATIO[2] ATIO[1] ATIO[0]
Register init - - - 0 1 0 1 1 0 1 0 5A
Rev.1.01 June 28, 2014 199

・Power Setting for Charge Pump : D0h

Command 0 1 ↑ 1 1 0 1 0 0 0 0 D0
1st
1 ↑ ↑ BT3 DC3[2] DC3[1] DC3[0] BT2 DC2[2] DC2[1] DC2[0] xx
parameter
Register init - - - 0 0 0 1 0 0 0 1 11
2nd
1 ↑ ↑ 0 0 VLM2[5] VLM2[4] VLM2[3] VLM2[2] VLM2[1] VLM2[0] xx
parameter
Register init - - - 0 0 0 1 0 1 0 0 14
3rd
1 ↑ ↑ 0 0 VLM3[5] VLM3[4] VLM3[3] VLM3[2] VLM3[1] VLM3[0] xx
parameter
Register init - - - 0 0 0 1 0 1 0 0 14
4th
1 ↑ ↑ 0 0 1 1 0 0 1 1 xx
parameter
Register init - - - 0 0 1 1 0 0 1 1 33
DC2
Description
This register controls divide ration of boost clock frequency for VGH.
Function Table
DC2 Divide ratio

’h0 Setting inhibited
’h1 210 division
’h2 240 division
’h3 280 division
’h4 330 division
’h5 410 division
Note : fCLK_DC2 = fosc /2* 1 /n
fCLK_DC2 : CLK_DC2 clock (VGH Step-up frequency)
fOSC : OSC clock
n : DC2 divided ratio ( in table)
Restriction
This command will control when power on/off sequence..
Rev.1.01 June 28, 2014 200

BT2
Description
This register controls boost ratio of VGH.
Function Table
Boost ratio
BT2
VGH boost ratio
’h0 VCI2×2
’h1 VCI2×2－VSN
Restriction
This command will control when power on/off sequence.
DC3
Description
This register controls divide ration of boost clock frequency for VGL.
Function Table
DC3 Divide ratio

’h1 210 division
’h2 240 division
’h3 280 division
’h4 330 division
’h5 410 division
Note : fCLK_DC3 = fOSC /2* 1/n
fCLK_DC3 : CLK_DC3 clock (VGL Step-up frequency)
fOSC : OSC clock
n : DC3 divided ratio ( in table)
Restriction -
BT3
Description
This register controls boost ratio of VGL.
Function Table
Boost ratio
BT3
VGL boost ratio
’h0 VSN－VCI3
’h1 VSN×2－VCI3
Restriction
Rev.1.01 June 28, 2014 201

VLM2
Description
This register controls output level of VGH.
Recommended voltage: (voltage set by BT2) – (voltage set by VLM2) ≦ 2V
Function Table
VLM2 VGH level VLM2 VGH level VLM2 VGH level
’h00 Setting inhibited ’h10 7.2V ’h20 10.4V

’h05 5.0V ’h15 8.2V ’h25 11.4V
’h06 5.2V ’h16 8.4V ’h26 11.6V
’h07 5.4V ’h17 8.6V ’h27 11.8V
’h08 5.6V ’h18 8.8V ’h28 12.0V
’h09 5.8V ’h19 9.0V ’h29 12.2V
’h0A 6.0V ’h1A 9.2V ’h2A 12.4V
’h0B 6.2V ’h1B 9.4V ’h2B 12.6V
’h0C 6.4V ’h1C 9.6V ’h2C 12.8V
’h0D 6.6V ’h1D 9.8V ’h2D 13.0V
’h0E 6.8V ’h1E 10.0V ’h2E Setting inhibited
’h0F 7.0V ’h1F 10.2V ’h2F Setting inhibited
Restriction -
Rev.1.01 June 28, 2014 202

VLM3
Description
This register controls output voltage level of VGL.
Recommended voltage: (voltage set by BT3) － (voltage set by VLM3) ≧ -2V
Function Table
VLM3 VGL level VLM3 VGL level VLM3 VGL level
’h00 Setting inhibited ’h10 -7.2V ’h20 -10.4V

’h05 -5.0V ’h15 -8.2V ’h25 -11.4V
’h06 -5.2V ’h16 -8.4V ’h26 -11.6V
’h07 -5.4V ’h17 -8.6V ’h27 -11.8V
’h08 -5.6V ’h18 -8.8V ’h28 -12.0V
’h09 -5.8V ’h19 -9.0V ’h29 Setting inhibited
’h0A -6.0V ’h1A -9.2V ’h2A Setting inhibited
’h0B -6.2V ’h1B -9.4V ’h2B Setting inhibited
’h0C -6.4V ’h1C -9.6V ’h2C Setting inhibited
’h0D -6.6V ’h1D -9.8V ’h2D Setting inhibited
’h0E -6.8V ’h1E -10.0V ’h2E Setting inhibited
’h0F -7.0V ’h1F -10.2V ’h2F Setting inhibited
Restriction -
Rev.1.01 June 28, 2014 203

・Test Register: D1h

Command 0 1 ↑ 1 1 0 1 0 0 0 1 D1
1st
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
Rev.1.01 June 28, 2014 204

・Power Setting for Internal Power : D2h


Command 0 1 ↑ 1 1 0 1 0 0 1 0 D2
1st
1 ↑ ↑ VC3[3] VC3[2] VC3[1] VC3[0] VC2[3] VC2[2] VC2[1] VC2[0] xx
parameter
Register init - - - 1 1 0 1 1 1 0 1 DD
2nd
1 ↑ ↑ 0 VPL[6] VPL[5] VPL[4] VPL[3] VPL[2] VPL[1] VPL[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
3rd
1 ↑ ↑ 0 VNL[6] VNL[5] VNL[4] VNL[3] VNL[2] VNL[1] VNL[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th
1 ↑ ↑ 0 APAP[2] APAP[1] APAP[0] 0 APAN[2] APAN[1] APAN[0] xx
parameter
Register init - - - 0 0 1 1 0 0 1 1 33
5th
1 ↑ ↑ 0 0 0 1 0 0 VBTS[1] VBTS[0] xx
parameter
Register init - - - 0 0 0 1 0 0 1 0 12
6th
1 ↑ ↑ 0 0 1 1 0 0 1 1 xx
parameter
Register init - - - 0 0 1 1 0 0 1 1 33
7th
1 ↑ ↑ 0 0 1 1 0 0 1 1 xx
parameter
Register init - - - 0 0 1 1 0 0 1 1 33
8th
1 ↑ ↑ 0 0 1 1 0 0 1 1 xx
parameter
Register init - - - 0 0 1 1 0 0 1 1 33
9th
1 ↑ ↑ 0 1 1 1 0 1 1 1 xx
parameter
Register init - - - 0 1 1 1 0 1 1 1 77
10th
1 ↑ ↑ 0 1 1 1 0 1 1 1 xx
parameter
Register init - - - 0 1 1 1 0 1 1 1 77
11th
1 ↑ ↑ 0 0 1 1 0 0 1 1 xx
parameter
Register init - - - 0 0 1 1 0 0 1 1 33
12th
1 ↑ ↑ 0 0 1 1 0 0 1 1 xx
parameter
Register init - - - 0 0 1 1 0 0 1 1 33
13th
1 ↑ ↑ 0 0 1 1 0 0 1 1 xx
parameter
Register init - - - 0 0 1 1 0 0 1 1 33
14th
1 ↑ ↑ 0 0 0 0 SEQGND1[3] SEQGND1[2] SEQGND1[1] SEQGND1[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
15th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
16th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
Rev.1.01 June 28, 2014 205

VC2
Description
This register controls output voltage of VCI2 regulator. VCI2 is internal voltage for generating VGH.
Function Table
VCI2 regulator output VCI2 regulator output

VC2 VC2
voltage voltage
‘h0 2.4V ‘h8 4.0V
‘h1 2.6V ‘h9 4.2V
‘h2 2.8V ‘hA 4.4V
‘h3 3.0V ‘hB 4.6V
‘h4 3.2V ‘hC 4.8V
‘h5 3.4V ‘hD 5.0V
‘h6 3.6V ‘hE 5.2V
‘h7 3.8V ‘hF 5.4V
Restriction
VC3
Description
This register controls output voltage of VCI3 regulator. VCI3 is internal volgtage for generating VGL.
Function Table
VCI3 regulator output VCI3 regulator output
VC3 VC3
voltage voltage
‘h0 2.4V ‘h8 4.0V
‘h1 2.6V ‘h9 4.2V
‘h2 2.8V ‘hA 4.4V
‘h3 3.0V ‘hB 4.6V
‘h4 3.2V ‘hC 4.8V
‘h5 3.4V ‘hD 5.0V
‘h6 3.6V ‘hE 5.2V
‘h7 3.8V ‘hF 5.4V
Restriction
Rev.1.01 June 28, 2014 206

VPL
Description
This register controls output voltage of positive gray scale reference level.
Function Table
VPL VPLVL [V] VPL VPLVL [V] VPL VPLVL [V] VPL VPLVL [V]
'h00 'h20 3.725 'h40 4.525 'h60 5.325
'h01 'h21 3.750 'h41 4.550 'h61 5.350
'h02 'h22 3.775 'h42 4.575 'h62 5.375
'h03 'h23 3.800 'h43 4.600 'h63 5.400
'h04 'h24 3.825 'h44 4.625 'h64 5.425
'h05 'h25 3.850 'h45 4.650 'h65 5.450
'h06 'h26 3.875 'h46 4.675 'h66 5.475
'h07 'h27 3.900 'h47 4.700 'h67 5.500
'h08 'h28 3.925 'h48 4.725 'h68 5.525
Setting
'h09 inhibited 'h29 3.950 'h49 4.750 'h69 5.550
'h0A 'h2A 3.975 'h4A 4.775 'h6A 5.575
'h0B 'h2B 4.000 'h4B 4.800 'h6B 5.600
'h0C 'h2C 4.025 'h4C 4.825 'h6C 5.625
'h0D 'h2D 4.050 'h4D 4.850 'h6D 5.650
'h0E 'h2E 4.075 'h4E 4.875 'h6E 5.675
'h0F 'h2F 4.100 'h4F 4.900 'h6F 5.700
'h10 'h30 4.125 'h50 4.925 'h70 5.725
'h11 'h31 4.150 'h51 4.950 'h71 5.750
'h12 'h32 4.175 'h52 4.975 'h72 5.775
'h13 'h33 4.200 'h53 5.000 'h73 5.800
'h14 'h34 4.225 'h54 5.025 'h74 5.825
'h15 'h35 4.250 'h55 5.050 'h75 5.850
'h16 'h36 4.275 'h56 5.075 'h76 5.875
'h17 3.500 'h37 4.300 'h57 5.100 'h77 5.900
'h18 3.525 'h38 4.325 'h58 5.125 'h78 5.925
'h19 3.550 'h39 4.350 'h59 5.150 'h79 5.950
'h1A 3.575 'h3A 4.375 'h5A 5.175 'h7A 5.975
'h1B 3.600 'h3B 4.400 'h5B 5.200 'h7B 6.000
'h1C 3.625 'h3C 4.425 'h5C 5.225 'h7C
'h1D 3.650 'h3D 4.450 'h5D 5.250 'h7D Setting
'h1E 3.675 'h3E 4.475 'h5E 5.275 'h7E inhibited
'h1F 3.700 'h3F 4.500 'h5F 5.300 'h7F
Restriction Set VPL to satisfy following relationship.

VSP – VPLVL ≧ 0.3V
Rev.1.01 June 28, 2014 207

VNL
Description
This register controls output voltage of negative gray scale reference level.
Function Table
VNL VNLVL [V] VNL VNLVL [V] VNL VNLVL [V] VNL VNLVL [V]
'h00 'h20 -3.725 'h40 -4.525 'h60 -5.325
'h01 'h21 -3.750 'h41 -4.550 'h61 -5.350
'h02 'h22 -3.775 'h42 -4.575 'h62 -5.375
'h03 'h23 -3.800 'h43 -4.600 'h63 -5.400
'h04 'h24 -3.825 'h44 -4.625 'h64 -5.425
'h05 'h25 -3.850 'h45 -4.650 'h65 -5.450
'h06 'h26 -3.875 'h46 -4.675 'h66 -5.475
'h07 'h27 -3.900 'h47 -4.700 'h67 -5.500
'h08 'h28 -3.925 'h48 -4.725 'h68 -5.525
'h09 'h29 -3.950 'h49 -4.750 'h69 -5.550
'h0A Setting 'h2A -3.975 'h4A -4.775 'h6A -5.575
'h0B inhibited 'h2B -4.000 'h4B -4.800 'h6B -5.600
'h0C 'h2C -4.025 'h4C -4.825 'h6C -5.625
'h0D 'h2D -4.050 'h4D -4.850 'h6D -5.650
'h0E 'h2E -4.075 'h4E -4.875 'h6E -5.675
'h0F 'h2F -4.100 'h4F -4.900 'h6F -5.700
'h10 'h30 -4.125 'h50 -4.925 'h70 -5.725
'h11 'h31 -4.150 'h51 -4.950 'h71 -5.750
'h12 'h32 -4.175 'h52 -4.975 'h72 -5.775
'h13 'h33 -4.200 'h53 -5.000 'h73 -5.800
'h14 'h34 -4.225 'h54 -5.025 'h74 -5.825
'h15 'h35 -4.250 'h55 -5.050 'h75 -5.850
'h16 'h36 -4.275 'h56 -5.075 'h76 -5.875
'h17 -3.500 'h37 -4.300 'h57 -5.100 'h77 -5.900
'h18 -3.525 'h38 -4.325 'h58 -5.125 'h78 -5.925
'h19 -3.550 'h39 -4.350 'h59 -5.150 'h79 -5.950
'h1A -3.575 'h3A -4.375 'h5A -5.175 'h7A -5.975
'h1B -3.600 'h3B -4.400 'h5B -5.200 'h7B -6.000
'h1C -3.625 'h3C -4.425 'h5C -5.225 'h7C
'h1D -3.650 'h3D -4.450 'h5D -5.250 'h7D Setting
'h1E -3.675 'h3E -4.475 'h5E -5.275 'h7E inhibited
'h1F -3.700 'h3F -4.500 'h5F -5.300 'h7F
Restriction Set VNL to satisfy following relationship.

VSN – VNLVL ≦ -0.3V
Rev.1.01 June 28, 2014 208

APAN
Description
This register controls reference current of Source amp, Gamma circuit and reference voltage circuit
for negative polarity.
In case of lower current setting, there is the potential to affect the display quality. In case of higher
current setting, there is the potential to increase IC current. If changing this register, check the
display quality and current consumption.
Function Table
APAN Current consumption

’h2 75%
’h3 100%
’h4 125%
Restriction -
APAP
Description
This register controls reference current of Source amp, Gamma circuit and reference voltage circuit
for positive polality.
In case of lower current setting, there is the potential to affect the display quality. In case of higher
current setting, there is the potential to increase IC current. If changing this register, check the
display quality and current consumption.
Function Table
APAP Current consumption

’h2 75%
’h3 100%
’h4 125%
Restriction -
Rev.1.01 June 28, 2014 209

VBTS
Description
When the value of VSP is lower than the value of VBTS, it changes to Abnormal Sequence.
Function Table
Detection level
VBTS
of VSP [V]
’h0 4.74
’h1 5.10
’h2 4.02
’h3 4.42
Restriction -
Rev.1.01 June 28, 2014 210

・Test Register : D3h

Command 0 1 ↑ 1 1 0 1 0 0 1 1 D3
1st
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ 0 0 1 0 0 0 1 0 xx
parameter
Register init - - - 0 0 1 0 0 0 1 0 22
3rd
1 ↑ ↑ 0 1 0 0 0 1 0 0 xx
parameter
Register init - - - 0 1 0 0 0 1 0 0 44
4th
1 ↑ 1 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
Rev.1.01 June 28, 2014 211

・ Test register : D4h

Command 0 1 ↑ 1 1 0 1 0 1 0 0 D4
1st
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
Rev.1.01 June 28, 2014 212

・ VCOM Setting Function : D5h

Command 0 1 ↑ 1 1 0 1 0 1 0 1 D5
1st
1 ↑ ↑ 0 0 0 0 0 WCVDC WCVDCB 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
3rd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th
1 ↑ ↑ 0 0 0 0 0 0 0 VDC[8] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
5th
1 ↑ ↑ VDC[7] VDC[6] VDC[5] VDC[4] VDC[3] VDC[2] VDC[1] VDC[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
6th
1 ↑ ↑ 0 0 0 0 0 0 0 VDCB[8] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
7th
1 ↑ ↑ VDCB[7] VDCB[6] VDCB[5] VDCB[4] VDCB[3] VDCB[2] VDCB[1] VDCB[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
WCVDC
Description
This register controls access to VCOM adjustment register (VDC).
Please use this register in case of VCOM adjustment.
Function Table
WCVDC Operation
Register access is disable.

0
VDC is kept initial value from NVM data.
Register access is enable.
1 If user wants to re-write NVM data, please set WCVDC=1 before NVM re-write
sequence.
Restriction -
WCVDCB
Description
This register controls access to VCOM adjustment register (VDCB).
Please use this register in case of adjustment.
Function Table
WCVDCB Operation
Register access is disable.

0
VDCB is kept initial value from NVM data.
Register access is enable.
1 If user wants to re-write NVM data, please set WCVDCB=1 before NVM re-write
sequence.
Restriction -
Rev.1.01 June 28, 2014 213

VDC
Description
This register controls VCOM output level. VDC is effective on forward scan.
VCOM[V] = VPLVL – (VPLVL-VNLVL) x [Setting Value]
Note : Refer to the appendix for scan mode.
Function Table
VDC VCOM VDC VCOM VDC VCOM VDC VCOM

'h0 'h20 'h40 'h60 x 0.3727
'h1 'h21 'h41 'h61 x 0.3735
'h2 'h22 'h42 'h62 x 0.3742
'h3 'h23 'h43 Setting 'h63 x 0.3750
'h4 'h24 'h44 inhibited 'h64 x 0.3758
'h5 'h25 'h45 'h65 x 0.3765
'h6 'h26 'h46 'h66 x 0.3773
'h7 'h27 'h47 'h67 x 0.3780
'h8 'h28 'h48 x 0.3545 'h68 x 0.3788
'h9 'h29 'h49 x 0.3553 'h69 x 0.3795
'hA 'h2A 'h4A x 0.3561 'h6A x 0.3803
'hB 'h2B 'h4B x 0.3568 'h6B x 0.3811
'hC 'h2C 'h4C x 0.3576 'h6C x 0.3818
'hD 'h2D 'h4D x 0.3583 'h6D x 0.3826
'hE 'h2E 'h4E x 0.3591 'h6E x 0.3833
'hF Setting 'h2F Setting 'h4F x 0.3598 'h6F x 0.3841
'h10 inhibited 'h30 inhibited 'h50 x 0.3606 'h70 x 0.3848
'h11 'h31 'h51 x 0.3614 'h71 x 0.3856
'h12 'h32 'h52 x 0.3621 'h72 x 0.3864
'h13 'h33 'h53 x 0.3629 'h73 x 0.3871
'h14 'h34 'h54 x 0.3636 'h74 x 0.3879
'h15 'h35 'h55 x 0.3644 'h75 x 0.3886
'h16 'h36 'h56 x 0.3652 'h76 x 0.3894
'h17 'h37 'h57 x 0.3659 'h77 x 0.3902
'h18 'h38 'h58 x 0.3667 'h78 x 0.3909
'h19 'h39 'h59 x 0.3674 'h79 x 0.3917
'h1A 'h3A 'h5A x 0.3682 'h7A x 0.3924
'h1B 'h3B 'h5B x 0.3689 'h7B x 0.3932
'h1C 'h3C 'h5C x 0.3697 'h7C x 0.3939
'h1D 'h3D 'h5D x 0.3705 'h7D x 0.3947
'h1E 'h3E 'h5E x 0.3712 'h7E x 0.3955
'h1F 'h3F 'h5F x 0.3720 'h7F x 0.3962
(Continued)
Rev.1.01 June 28, 2014 214

(Continued)

'h80 x 0.3970 'hA0 x 0.4212 'hC0 x 0.4455 'hE0 x 0.4697
'h81 x 0.3977 'hA1 x 0.4220 'hC1 x 0.4462 'hE1 x 0.4705
'h82 x 0.3985 'hA2 x 0.4227 'hC2 x 0.4470 'hE2 x 0.4712
'h83 x 0.3992 'hA3 x 0.4235 'hC3 x 0.4477 'hE3 x 0.4720
'h84 x 0.4000 'hA4 x 0.4242 'hC4 x 0.4485 'hE4 x 0.4727
'h85 x 0.4008 'hA5 x 0.4250 'hC5 x 0.4492 'hE5 x 0.4735
'h86 x 0.4015 'hA6 x 0.4258 'hC6 x 0.4500 'hE6 x 0.4742
'h87 x 0.4023 'hA7 x 0.4265 'hC7 x 0.4508 'hE7 x 0.4750
'h88 x 0.4030 'hA8 x 0.4273 'hC8 x 0.4515 'hE8 x 0.4758
'h89 x 0.4038 'hA9 x 0.4280 'hC9 x 0.4523 'hE9 x 0.4765
'h8A x 0.4045 'hAA x 0.4288 'hCA x 0.4530 'hEA x 0.4773
'h8B x 0.4053 'hAB x 0.4295 'hCB x 0.4538 'hEB x 0.4780
'h8C x 0.4061 'hAC x 0.4303 'hCC x 0.4545 'hEC x 0.4788
'h8D x 0.4068 'hAD x 0.4311 'hCD x 0.4553 'hED x 0.4795
'h8E x 0.4076 'hAE x 0.4318 'hCE x 0.4561 'hEE x 0.4803
'h8F x 0.4083 'hAF x 0.4326 'hCF x 0.4568 'hEF x 0.4811
'h90 x 0.4091 'hB0 x 0.4333 'hD0 x 0.4576 'hF0 x 0.4818
'h91 x 0.4098 'hB1 x 0.4341 'hD1 x 0.4583 'hF1 x 0.4826
'h92 x 0.4106 'hB2 x 0.4348 'hD2 x 0.4591 'hF2 x 0.4833
'h93 x 0.4114 'hB3 x 0.4356 'hD3 x 0.4598 'hF3 x 0.4841
'h94 x 0.4121 'hB4 x 0.4364 'hD4 x 0.4606 'hF4 x 0.4848
'h95 x 0.4129 'hB5 x 0.4371 'hD5 x 0.4614 'hF5 x 0.4856
'h96 x 0.4136 'hB6 x 0.4379 'hD6 x 0.4621 'hF6 x 0.4864
'h97 x 0.4144 'hB7 x 0.4386 'hD7 x 0.4629 'hF7 x 0.4871
'h98 x 0.4152 'hB8 x 0.4394 'hD8 x 0.4636 'hF8 x 0.4879
'h99 x 0.4159 'hB9 x 0.4402 'hD9 x 0.4644 'hF9 x 0.4886
'h9A x 0.4167 'hBA x 0.4409 'hDA x 0.4652 'hFA x 0.4894
'h9B x 0.4174 'hBB x 0.4417 'hDB x 0.4659 'hFB x 0.4902
'h9C x 0.4182 'hBC x 0.4424 'hDC x 0.4667 'hFC x 0.4909
'h9D x 0.4189 'hBD x 0.4432 'hDD x 0.4674 'hFD x 0.4917
'h9E x 0.4197 'hBE x 0.4439 'hDE x 0.4682 'hFE x 0.4924
'h9F x 0.4205 'hBF x 0.4447 'hDF x 0.4689 'hFF x 0.4932
(continued)
Rev.1.01 June 28, 2014 215

(Continued)

'h100 x 0.4939 'h120 x 0.5182 'h140 x 0.5424 'h160 x 0.5667
'h101 x 0.4947 'h121 x 0.5189 'h141 x 0.5432 'h161 x 0.5674
'h102 x 0.4955 'h122 x 0.5197 'h142 x 0.5439 'h162 x 0.5682
'h103 x 0.4962 'h123 x 0.5205 'h143 x 0.5447 'h163 x 0.5689
'h104 x 0.4970 'h124 x 0.5212 'h144 x 0.5455 'h164 x 0.5697
'h105 x 0.4977 'h125 x 0.5220 'h145 x 0.5462 'h165 x 0.5705
'h106 x 0.4985 'h126 x 0.5227 'h146 x 0.5470 'h166 x 0.5712
'h107 x 0.4992 'h127 x 0.5235 'h147 x 0.5477 'h167 x 0.5720
'h108 x 0.5000 'h128 x 0.5242 'h148 x 0.5485 'h168 x 0.5727
'h109 x 0.5008 'h129 x 0.5250 'h149 x 0.5492 'h169 x 0.5735
'h10A x 0.5015 'h12A x 0.5258 'h14A x 0.5500 'h16A x 0.5742
'h10B x 0.5023 'h12B x 0.5265 'h14B x 0.5508 'h16B x 0.5750
'h10C x 0.5030 'h12C x 0.5273 'h14C x 0.5515 'h16C x 0.5758
'h10D x 0.5038 'h12D x 0.5280 'h14D x 0.5523 'h16D x 0.5765
'h10E x 0.5045 'h12E x 0.5288 'h14E x 0.5530 'h16E x 0.5773
'h10F x 0.5053 'h12F x 0.5295 'h14F x 0.5538 'h16F x 0.5780
'h110 x 0.5061 'h130 x 0.5303 'h150 x 0.5545 'h170 x 0.5788
'h111 x 0.5068 'h131 x 0.5311 'h151 x 0.5553 'h171 x 0.5795
'h112 x 0.5076 'h132 x 0.5318 'h152 x 0.5561 'h172 x 0.5803
'h113 x 0.5083 'h133 x 0.5326 'h153 x 0.5568 'h173 x 0.5811
'h114 x 0.5091 'h134 x 0.5333 'h154 x 0.5576 'h174 x 0.5818
'h115 x 0.5098 'h135 x 0.5341 'h155 x 0.5583 'h175 x 0.5826
'h116 x 0.5106 'h136 x 0.5348 'h156 x 0.5591 'h176 x 0.5833
'h117 x 0.5114 'h137 x 0.5356 'h157 x 0.5598 'h177 x 0.5841
'h118 x 0.5121 'h138 x 0.5364 'h158 x 0.5606 'h178 x 0.5848
'h119 x 0.5129 'h139 x 0.5371 'h159 x 0.5614 'h179 x 0.5856
'h11A x 0.5136 'h13A x 0.5379 'h15A x 0.5621 'h17A x 0.5864
'h11B x 0.5144 'h13B x 0.5386 'h15B x 0.5629 'h17B x 0.5871
'h11C x 0.5152 'h13C x 0.5394 'h15C x 0.5636 'h17C x 0.5879
'h11D x 0.5159 'h13D x 0.5402 'h15D x 0.5644 'h17D x 0.5886
'h11E x 0.5167 'h13E x 0.5409 'h15E x 0.5652 'h17E x 0.5894
'h11F x 0.5174 'h13F x 0.5417 'h15F x 0.5659 'h17F x 0.5902
(Continued)
Rev.1.01 June 28, 2014 216

(Continued)

'h180 x 0.5909 'h1A0 x 0.6152 'h1C0 x 0.6394 'h1E0
'h181 x 0.5917 'h1A1 x 0.6159 'h1C1 x 0.6402 'h1E1
'h182 x 0.5924 'h1A2 x 0.6167 'h1C2 x 0.6409 'h1E2
'h183 x 0.5932 'h1A3 x 0.6174 'h1C3 x 0.6417 'h1E3
'h184 x 0.5939 'h1A4 x 0.6182 'h1C4 x 0.6424 'h1E4
'h185 x 0.5947 'h1A5 x 0.6189 'h1C5 x 0.6432 'h1E5
'h186 x 0.5955 'h1A6 x 0.6197 'h1C6 x 0.6439 'h1E6
'h187 x 0.5962 'h1A7 x 0.6205 'h1C7 x 0.6447 'h1E7
'h188 x 0.5970 'h1A8 x 0.6212 'h1C8 x 0.6455 'h1E8
'h189 x 0.5977 'h1A9 x 0.6220 'h1C9 'h1E9
'h18A x 0.5985 'h1AA x 0.6227 'h1CA 'h1EA
'h18B x 0.5992 'h1AB x 0.6235 'h1CB 'h1EB
'h18C x 0.6000 'h1AC x 0.6242 'h1CC 'h1EC
'h18D x 0.6008 'h1AD x 0.6250 'h1CD 'h1ED
'h18E x 0.6015 'h1AE x 0.6258 'h1CE 'h1EE
'h18F x 0.6023 'h1AF x 0.6265 'h1CF 'h1EF Setting
'h190 x 0.6030 'h1B0 x 0.6273 'h1D0 'h1F0 inhibited
'h191 x 0.6038 'h1B1 x 0.6280 'h1D1 'h1F1
'h192 x 0.6045 'h1B2 x 0.6288 'h1D2 'h1F2
'h193 x 0.6053 'h1B3 x 0.6295 'h1D3 'h1F3
Setting
'h194 x 0.6061 'h1B4 x 0.6303 'h1D4 'h1F4
inhibited
'h195 x 0.6068 'h1B5 x 0.6311 'h1D5 'h1F5
'h196 x 0.6076 'h1B6 x 0.6318 'h1D6 'h1F6
'h197 x 0.6083 'h1B7 x 0.6326 'h1D7 'h1F7
'h198 x 0.6091 'h1B8 x 0.6333 'h1D8 'h1F8
'h199 x 0.6098 'h1B9 x 0.6341 'h1D9 'h1F9
'h19A x 0.6106 'h1BA x 0.6348 'h1DA 'h1FA
'h19B x 0.6114 'h1BB x 0.6356 'h1DB 'h1FB
'h19C x 0.6121 'h1BC x 0.6364 'h1DC 'h1FC
'h19D x 0.6129 'h1BD x 0.6371 'h1DD 'h1FD
'h19E x 0.6136 'h1BE x 0.6379 'h1DE 'h1FE
'h19F x 0.6144 'h1BF x 0.6386 'h1DF 'h1FF
Restriction
Make sure that voltage level is (-2.0 ~ +2.0)V in setting.
Rev.1.01 June 28, 2014 217

VDCB
Description
This register controls VCOM output level. VDCB is effective on backward scan.
VCOM [V] = VPLVL – (VPLVL-VNLVL) x [Setting Value]
Note : Refer to the appendix for scan mode.
Function Table
VDCB VCOM VDCB VCOM VDCB VCOM VDCB VCOM
'h0 'h20 'h40 'h60 x 0.3727
'h1 'h21 'h41 'h61 x 0.3735
'h2 'h22 'h42 'h62 x 0.3742
'h3 'h23 'h43 Setting 'h63 x 0.3750
'h4 'h24 'h44 inhibited 'h64 x 0.3758
'h5 'h25 'h45 'h65 x 0.3765
'h6 'h26 'h46 'h66 x 0.3773
'h7 'h27 'h47 'h67 x 0.3780
'h8 'h28 'h48 x 0.3545 'h68 x 0.3788
'h9 'h29 'h49 x 0.3553 'h69 x 0.3795
'hA 'h2A 'h4A x 0.3561 'h6A x 0.3803
'hB 'h2B 'h4B x 0.3568 'h6B x 0.3811
'hC 'h2C 'h4C x 0.3576 'h6C x 0.3818
'hD 'h2D 'h4D x 0.3583 'h6D x 0.3826
'hE 'h2E 'h4E x 0.3591 'h6E x 0.3833
'hF Setting 'h2F Setting 'h4F x 0.3598 'h6F x 0.3841
'h10 inhibited 'h30 inhibited 'h50 x 0.3606 'h70 x 0.3848
'h11 'h31 'h51 x 0.3614 'h71 x 0.3856
'h12 'h32 'h52 x 0.3621 'h72 x 0.3864
'h13 'h33 'h53 x 0.3629 'h73 x 0.3871
'h14 'h34 'h54 x 0.3636 'h74 x 0.3879
'h15 'h35 'h55 x 0.3644 'h75 x 0.3886
'h16 'h36 'h56 x 0.3652 'h76 x 0.3894
'h17 'h37 'h57 x 0.3659 'h77 x 0.3902
'h18 'h38 'h58 x 0.3667 'h78 x 0.3909
'h19 'h39 'h59 x 0.3674 'h79 x 0.3917
'h1A 'h3A 'h5A x 0.3682 'h7A x 0.3924
'h1B 'h3B 'h5B x 0.3689 'h7B x 0.3932
'h1C 'h3C 'h5C x 0.3697 'h7C x 0.3939
'h1D 'h3D 'h5D x 0.3705 'h7D x 0.3947
'h1E 'h3E 'h5E x 0.3712 'h7E x 0.3955
'h1F 'h3F 'h5F x 0.3720 'h7F x 0.3962
(Continued)
Rev.1.01 June 28, 2014 218

(Continued)

'h80 x 0.3970 'hA0 x 0.4212 'hC0 x 0.4455 'hE0 x 0.4697
'h81 x 0.3977 'hA1 x 0.4220 'hC1 x 0.4462 'hE1 x 0.4705
'h82 x 0.3985 'hA2 x 0.4227 'hC2 x 0.4470 'hE2 x 0.4712
'h83 x 0.3992 'hA3 x 0.4235 'hC3 x 0.4477 'hE3 x 0.4720
'h84 x 0.4000 'hA4 x 0.4242 'hC4 x 0.4485 'hE4 x 0.4727
'h85 x 0.4008 'hA5 x 0.4250 'hC5 x 0.4492 'hE5 x 0.4735
'h86 x 0.4015 'hA6 x 0.4258 'hC6 x 0.4500 'hE6 x 0.4742
'h87 x 0.4023 'hA7 x 0.4265 'hC7 x 0.4508 'hE7 x 0.4750
'h88 x 0.4030 'hA8 x 0.4273 'hC8 x 0.4515 'hE8 x 0.4758
'h89 x 0.4038 'hA9 x 0.4280 'hC9 x 0.4523 'hE9 x 0.4765
'h8A x 0.4045 'hAA x 0.4288 'hCA x 0.4530 'hEA x 0.4773
'h8B x 0.4053 'hAB x 0.4295 'hCB x 0.4538 'hEB x 0.4780
'h8C x 0.4061 'hAC x 0.4303 'hCC x 0.4545 'hEC x 0.4788
'h8D x 0.4068 'hAD x 0.4311 'hCD x 0.4553 'hED x 0.4795
'h8E x 0.4076 'hAE x 0.4318 'hCE x 0.4561 'hEE x 0.4803
'h8F x 0.4083 'hAF x 0.4326 'hCF x 0.4568 'hEF x 0.4811
'h90 x 0.4091 'hB0 x 0.4333 'hD0 x 0.4576 'hF0 x 0.4818
'h91 x 0.4098 'hB1 x 0.4341 'hD1 x 0.4583 'hF1 x 0.4826
'h92 x 0.4106 'hB2 x 0.4348 'hD2 x 0.4591 'hF2 x 0.4833
'h93 x 0.4114 'hB3 x 0.4356 'hD3 x 0.4598 'hF3 x 0.4841
'h94 x 0.4121 'hB4 x 0.4364 'hD4 x 0.4606 'hF4 x 0.4848
'h95 x 0.4129 'hB5 x 0.4371 'hD5 x 0.4614 'hF5 x 0.4856
'h96 x 0.4136 'hB6 x 0.4379 'hD6 x 0.4621 'hF6 x 0.4864
'h97 x 0.4144 'hB7 x 0.4386 'hD7 x 0.4629 'hF7 x 0.4871
'h98 x 0.4152 'hB8 x 0.4394 'hD8 x 0.4636 'hF8 x 0.4879
'h99 x 0.4159 'hB9 x 0.4402 'hD9 x 0.4644 'hF9 x 0.4886
'h9A x 0.4167 'hBA x 0.4409 'hDA x 0.4652 'hFA x 0.4894
'h9B x 0.4174 'hBB x 0.4417 'hDB x 0.4659 'hFB x 0.4902
'h9C x 0.4182 'hBC x 0.4424 'hDC x 0.4667 'hFC x 0.4909
'h9D x 0.4189 'hBD x 0.4432 'hDD x 0.4674 'hFD x 0.4917
'h9E x 0.4197 'hBE x 0.4439 'hDE x 0.4682 'hFE x 0.4924
'h9F x 0.4205 'hBF x 0.4447 'hDF x 0.4689 'hFF x 0.4932
(Continued)
Rev.1.01 June 28, 2014 219

(Continued)

'h100 x 0.4939 'h120 x 0.5182 'h140 x 0.5424 'h160 x 0.5667
'h101 x 0.4947 'h121 x 0.5189 'h141 x 0.5432 'h161 x 0.5674
'h102 x 0.4955 'h122 x 0.5197 'h142 x 0.5439 'h162 x 0.5682
'h103 x 0.4962 'h123 x 0.5205 'h143 x 0.5447 'h163 x 0.5689
'h104 x 0.4970 'h124 x 0.5212 'h144 x 0.5455 'h164 x 0.5697
'h105 x 0.4977 'h125 x 0.5220 'h145 x 0.5462 'h165 x 0.5705
'h106 x 0.4985 'h126 x 0.5227 'h146 x 0.5470 'h166 x 0.5712
'h107 x 0.4992 'h127 x 0.5235 'h147 x 0.5477 'h167 x 0.5720
'h108 x 0.5000 'h128 x 0.5242 'h148 x 0.5485 'h168 x 0.5727
'h109 x 0.5008 'h129 x 0.5250 'h149 x 0.5492 'h169 x 0.5735
'h10A x 0.5015 'h12A x 0.5258 'h14A x 0.5500 'h16A x 0.5742
'h10B x 0.5023 'h12B x 0.5265 'h14B x 0.5508 'h16B x 0.5750
'h10C x 0.5030 'h12C x 0.5273 'h14C x 0.5515 'h16C x 0.5758
'h10D x 0.5038 'h12D x 0.5280 'h14D x 0.5523 'h16D x 0.5765
'h10E x 0.5045 'h12E x 0.5288 'h14E x 0.5530 'h16E x 0.5773
'h10F x 0.5053 'h12F x 0.5295 'h14F x 0.5538 'h16F x 0.5780
'h110 x 0.5061 'h130 x 0.5303 'h150 x 0.5545 'h170 x 0.5788
'h111 x 0.5068 'h131 x 0.5311 'h151 x 0.5553 'h171 x 0.5795
'h112 x 0.5076 'h132 x 0.5318 'h152 x 0.5561 'h172 x 0.5803
'h113 x 0.5083 'h133 x 0.5326 'h153 x 0.5568 'h173 x 0.5811
'h114 x 0.5091 'h134 x 0.5333 'h154 x 0.5576 'h174 x 0.5818
'h115 x 0.5098 'h135 x 0.5341 'h155 x 0.5583 'h175 x 0.5826
'h116 x 0.5106 'h136 x 0.5348 'h156 x 0.5591 'h176 x 0.5833
'h117 x 0.5114 'h137 x 0.5356 'h157 x 0.5598 'h177 x 0.5841
'h118 x 0.5121 'h138 x 0.5364 'h158 x 0.5606 'h178 x 0.5848
'h119 x 0.5129 'h139 x 0.5371 'h159 x 0.5614 'h179 x 0.5856
'h11A x 0.5136 'h13A x 0.5379 'h15A x 0.5621 'h17A x 0.5864
'h11B x 0.5144 'h13B x 0.5386 'h15B x 0.5629 'h17B x 0.5871
'h11C x 0.5152 'h13C x 0.5394 'h15C x 0.5636 'h17C x 0.5879
'h11D x 0.5159 'h13D x 0.5402 'h15D x 0.5644 'h17D x 0.5886
'h11E x 0.5167 'h13E x 0.5409 'h15E x 0.5652 'h17E x 0.5894
'h11F x 0.5174 'h13F x 0.5417 'h15F x 0.5659 'h17F x 0.5902
(Continued)
Rev.1.01 June 28, 2014 220

(Continued)
VDCB VCOM VDCB VCOMB VDCB VCOM VDCB VCOM

'h180 x 0.5909 'h1A0 x 0.6152 'h1C0 x 0.6394 'h1E0
'h181 x 0.5917 'h1A1 x 0.6159 'h1C1 x 0.6402 'h1E1
'h182 x 0.5924 'h1A2 x 0.6167 'h1C2 x 0.6409 'h1E2
'h183 x 0.5932 'h1A3 x 0.6174 'h1C3 x 0.6417 'h1E3
'h184 x 0.5939 'h1A4 x 0.6182 'h1C4 x 0.6424 'h1E4
'h185 x 0.5947 'h1A5 x 0.6189 'h1C5 x 0.6432 'h1E5
'h186 x 0.5955 'h1A6 x 0.6197 'h1C6 x 0.6439 'h1E6
'h187 x 0.5962 'h1A7 x 0.6205 'h1C7 x 0.6447 'h1E7
'h188 x 0.5970 'h1A8 x 0.6212 'h1C8 x 0.6455 'h1E8
'h189 x 0.5977 'h1A9 x 0.6220 'h1C9 'h1E9
'h18A x 0.5985 'h1AA x 0.6227 'h1CA 'h1EA
'h18B x 0.5992 'h1AB x 0.6235 'h1CB 'h1EB
'h18C x 0.6000 'h1AC x 0.6242 'h1CC 'h1EC
'h18D x 0.6008 'h1AD x 0.6250 'h1CD 'h1ED
'h18E x 0.6015 'h1AE x 0.6258 'h1CE 'h1EE
'h18F x 0.6023 'h1AF x 0.6265 'h1CF 'h1EF Setting
'h190 x 0.6030 'h1B0 x 0.6273 'h1D0 'h1F0 inhibited
'h191 x 0.6038 'h1B1 x 0.6280 'h1D1 'h1F1
'h192 x 0.6045 'h1B2 x 0.6288 'h1D2 'h1F2
'h193 x 0.6053 'h1B3 x 0.6295 'h1D3 'h1F3
Setting
'h194 x 0.6061 'h1B4 x 0.6303 'h1D4 'h1F4
inhibited
'h195 x 0.6068 'h1B5 x 0.6311 'h1D5 'h1F5
'h196 x 0.6076 'h1B6 x 0.6318 'h1D6 'h1F6
'h197 x 0.6083 'h1B7 x 0.6326 'h1D7 'h1F7
'h198 x 0.6091 'h1B8 x 0.6333 'h1D8 'h1F8
'h199 x 0.6098 'h1B9 x 0.6341 'h1D9 'h1F9
'h19A x 0.6106 'h1BA x 0.6348 'h1DA 'h1FA
'h19B x 0.6114 'h1BB x 0.6356 'h1DB 'h1FB
'h19C x 0.6121 'h1BC x 0.6364 'h1DC 'h1FC
'h19D x 0.6129 'h1BD x 0.6371 'h1DD 'h1FD
'h19E x 0.6136 'h1BE x 0.6379 'h1DE 'h1FE
'h19F x 0.6144 'h1BF x 0.6386 'h1DF 'h1FF
Restriction
Make sure that voltage level is (-2.0 ~ +2.0)V in setting.
Rev.1.01 June 28, 2014 221


Command 0 1 ↑ 1 1 0 1 0 1 1 0 D6
1st
1 ↑ ↑ 1 0 0 0 0 0 0 1 xx
parameter
Register init - - - 1 0 0 0 0 0 0 1 81
Rev.1.01 June 28, 2014 222


Command 0 1 ↑ 1 1 0 1 0 1 1 1 D7
1st
1 ↑ ↑ 1 1 1 1 1 0 1 0 xx
parameter
Register init - - - 1 1 1 1 1 0 1 0 FA
2nd
1 ↑ ↑ 1 1 1 1 1 1 1 1 xx
parameter
Register init - - - 1 1 1 1 1 1 1 1 FF
3rd
1 ↑ ↑ 0 0 1 0 0 0 0 1 xx
parameter
Register init - - - 0 0 1 0 0 0 0 1 21
4th
1 ↑ ↑ 1 0 0 0 1 1 1 0 xx
parameter
Register init - - - 1 0 0 0 1 1 1 0 8E
5th
1 ↑ ↑ 1 0 0 0 1 1 0 0 xx
parameter
Register init - - - 1 0 0 0 1 1 0 0 8C
6th
1 ↑ ↑ 1 1 1 1 0 0 0 1 xx
parameter
Register init - - - 1 1 1 1 0 0 0 1 F1
7th
1 ↑ ↑ 1 0 0 0 0 1 1 1 xx
parameter
Register init - - - 1 0 0 0 0 1 1 1 87
8th
1 ↑ ↑ 0 0 1 1 1 1 1 1 xx
parameter
Register init - - - 0 0 1 1 1 1 1 1 3F
9th
1 ↑ ↑ 0 1 1 1 1 1 1 0 xx
parameter
Register init - - - 0 1 1 1 1 1 1 0 7E
10th
1 ↑ ↑ 0 0 0 1 0 0 0 0 xx
parameter
Register init - - - 0 0 0 1 0 0 0 0 10
11th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
12th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
13th
1 ↑ ↑ 1 0 0 0 1 1 1 1 xx
parameter
Register init - - - 1 0 0 0 1 1 1 1 8F
Note) Please refer to Appendix.
Rev.1.01 June 28, 2014 223


Command 0 1 ↑ 1 1 0 1 1 0 0 0 D8
1st
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
3rd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
Rev.1.01 June 28, 2014 224


Command 0 1 ↑ 1 1 0 1 1 0 0 1 D9
1st
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
Rev.1.01 June 28, 2014 225

・Test Image Generator : E5h

Command 0 1 ↑ 1 1 1 0 0 1 0 1 E5
1st
1 ↑ ↑ 0 0 0 0 TIGCYC[1] TIGCYC[0] 0 TIGON xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ TIP[15] TIP[14] TIP[13] TIP[12] TIP[11] TIP[10] TIP[9] TIP[8] xx
parameter
Register init - - - 0 0 1 1 1 1 1 1 3F
3rd
1 ↑ ↑ TIP[7] TIP[6] TIP[5] TIP[4] TIP[3] TIP[2] TIP[1] TIP[0] xx
parameter
Register init - - - 1 1 1 1 1 1 1 1 FF
4th
1 ↑ ↑ 0 0 0 1 0 0 0 0 xx
parameter
Register init - - - 0 0 0 1 0 0 0 0 10
TIGON
Description
This IC supports the test free-running mode function. When TIGON is set to “1”, this IC operates in
synchronization with the internal oscillation clock.
Enables the Test Image Generation function.
Function Table
TIGON Test Image Generator
0 Off
1 On
Restriction
・In Built-in TCON Display Mode ( DM = ‘h0 ) only, TIGON can set to 1.
・In PNSLV='h1 (Master=portB), set C1h3rd paremeter to C0h.
TIGCYC
Description
TIGCYC can change the display cycle of the selected image.
Function Table
TIGCYC Display cycle

’h0 256frames
’h1 512frames
’h2 768 frames
’h3 1024 frames
Restriction -
Rev.1.01 June 28, 2014 226

TIP
Description
Setting each of the TIP[15:0] registers to 1 allows images to be displayed in the free-running mode.
The following are the relationships between the registers and display images.
Function Table
Register Display image
TIP[0] Middle Gray 127
TIP[1] Horizontal grayscale
TIP[2] Vertical grayscale
TIP[3] White 255
TIP[4] Red 255
TIP[5] Green 255
TIP[6] Blue 255
TIP[7] Black
TIP[8] SMEAR (a white window against a dark background)
TIP[9] Color bar
TIP[10] DCF (aligned dot check)
TIP[11] 2Pixel V-Stripe
Restriction
Display image TIP[1], TIP[2] , and TIP[9],[10],[11] may be repeated in a screen according to the size.
The central white window size in display image TIP[8] varies according to the display image size.
Rev.1.01 June 28, 2014 227

Test Image Generator Flow
1) Case of TIGON(Command E5h 1st parameter)
Power supply on
VSP/VSN
IOVCC Exit Sleep mode
Command：11h
GND Wait for

more than 120ms
Set_Display_On
Command 29h
Power on reset
(Hard ware reset)
Wait for
more than 3ms R63419 free running
Sleep in State
Manufacturer Command Access Set_Display_Off

Protect off Command 28h
MCAP=3’b100
Enter Sleep mode

Command：10h
Set Manufacturer Command
A command setup which is needed for LSI
operation
Wait more
A setup is unnecessary
than 120ms
when NVM has a setup.
Power supply off
VSP/VSN
Set Test Image Generator Command IOVCC
Command：E5h
1st Parameter: TIGCYC[1:0],TIGON=1
2nd Parameter: TIP[11:8] GND
3rd Parameter: TIP[7:0]
Command：B3h
1st Parameter: 00h DM=0h
* In case of Bport master, set C1h/3rd parameter = 0xC0.
Rev.1.01 June 28, 2014 228

2)case of DBIST
Power supply on
VSP/VSN
IOVCC
DBIST=High(IOVCC)
GND
R63419 free running
Power on reset
(Hard ware reset)
Wait for
more than 3ms DBIST=Low(GND)
Sleep in State
Wait more
than 120ms
Manufacturer Command Access
Protect off
Power supply off
MCAP=3’b100
VSP/VSN
IOVCC
Set Manufacturer Command GND

A command setup which is needed for LSI
operation
A setup is unnecessary
when NVM has a setup.
Set Test Image Generator Command

Command：E5h
1st Parameter: TIGCYC[1:0],TIGON=0
2nd Parameter: TIP[11:8]
3rd Parameter: TIP[7:0]
Command：B3h
1st Parameter: 00h DM=0h
* In case of Bport master, set C1h/3rd parameter = 0xC0.
Rev.1.01 June 28, 2014 229

・NVM Access Control : E6h

Command 0 1 ↑ 1 1 1 0 0 1 1 0 E6
1st
1 ↑ ↑ 0 0 0 TEM[0] 0 0 0 NVMAEN xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
スタ配置変更不可 Register init
3rd
- - - 0 0 0 0 0 0 0 0 00
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th
1 ↑ ↑ 0 NVMFTT 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
5th NVMVFFLGW NVMVFFLGE
1 ↑ ↑ 0 0 0 0 0 0 xx
parameter R R
Register init - - - 0 0 0 0 0 0 0 0 00
6th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
NVMAEN
Description
This register controls NVM accessibility. Refer to "NVM Control" for detail.
Function Table
NVMAEN NV Memory Access
0 Disable
1 Enable
Restriction -
TEM
Description
This register controls output data from TE.
Function Table
TEM TE output TE output control
sleep_mode_on
TE output is fixed low.
‘h0 Tearing Effect sleep_mode_off
set_tear_on : TE output is enabled.
set_tear_off : TE output is fixed low.
NVM automatically write data verification
result (=VERIFLGWR & VERIFLGER)
‘h1 TE output is always enabled.
TE = 0 Verification result is NG
TE = 1 Verification result is OK
Restriction -
Rev.1.01 June 28, 2014 230

NVMFTT
Description
This register controls NVM re-write sequence.
If NVMAEN=1 & NVMFTT=1, NVM start re-write(erase and write) sequence.
Function Table
NVMFTT NV Memory re-write & Verify operation
0→1 Sequence start
(1→0) Return to “0” when sequence finish
Restriction -
NVMVFFLGER
Description
NVM execute erase verify operation after NVM erase operation, and return write verify result.
(Erase operation is executed 1st step of NVM re-write sequence.)
This register is read-only, and cannot write data.
Function Table
NVMVFFLGER NV Memory Erase Verification Result
0 Fail
1 Pass
Restriction -
NVMVFFLGWR
Description
NVM execute write verify operation after NVM write operation, and return write verify result.
(Write operation is executed following erase operation.)
This register is read-only, and cannot write data.
Function Table
NVMVFFLGWR NVM Write Verification Result
0 Fail
1 Pass
Restriction -
Rev.1.01 June 28, 2014 231

・set_DDB write Control :E7h

Command 0 1 ↑ 1 1 1 0 0 1 1 1 E7
1st
1 ↑ ↑ 0 0 0 WCRDID 0 WCDDBCOL 0 WCDDB xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
WCDDB
Description
This register controls accessibility of A1h: read_DDB_start register
Function Table
WCDDB Notes
0 DDB access is disable. *Please set WCDDB=0 except NVM writing
1 DDB access is enable. *Data setted DDB register are written to NVM.
If writing the data to A1h to NVM, WCDDB=1, and send A1h command and whole parameters before
starting NVM writing (NVMFTT=1). If finishing to write A1h, turn WCDDB from 1 to 0.
Please refer “NVM Write Sequence” for detail.
Restriction -
WCDDBCOL
Description
This register controls accessibility of 70h – 7Eh registers.
Function Table
WCDDBCOL Notes
0 7xh access is disable. *Please set WCDDBCOM=0 except NVM writing
1 7xh access is enable. *Data setted 7xh register are written to NVM.
If writing the data to 7xh to NVM, WCDDBCOM=1, and send 70h command – 7Eh command before
starting NVM writing(NVMFTT=1) . If finishing to write 7xh, turn WCDDB from 1 to 0.
Restriction -
Rev.1.01 June 28, 2014 232

WCRDID
Description
This register controls accessibility of DAh, DBh, DCh registers.
Function Table
WCRDID Notes
0 DAh-DCh access is disable. *Please set WCRDID=0 except NVM writing
1 DAh-DCh access is enable. *Data setted DAh-DCh register are written to NVM.
If writing the data to DAh-DCh to NVM, WCRDID=1, and send DAh command – DCh command
before starting NVM writing(NVMFTT=1) . If finishing to write DAh-DCh, turn WCDDB from 1 to 0.
Restriction -
Rev.1.01 June 28, 2014 233

・NVM Load Control : E8h

Command 0 1 ↑ 1 1 1 0 1 0 0 0 E8
Dummy
1 ↑ 1 x x x x x x x x xx
parameter
1st
1 ↑ ↑ NVMLD[7] NVMLD[6] NVMLD[5] NVMLD[4] NVMLD[3] NVMLD[2] NVMLD[1] NVMLD[0] xx
parameter
Register init - - - 0 0 1 0 1 0 0 0 28
2nd NVMWECNT[ NVMWECNT[ NVMWECNT[ NVMWECNT[ NVMWECNT[ NVMWECNT[ NVMWECNT[ NVMWECNT[
1 ↑ 1 xx
parameter 7] 6] 5] 4] 3] 2] 1] 0]
Register init - - - 0 0 0 0 0 0 0 1 01
NVMLD
Description
These registers set commands used to load data from NVM during each sequence.
Function Table
NVMLD[x] Operation
Data is not loaded from NVM by command.

0
The setting values before data is loaded are not updated.
Data is loaded from NVM by command.

1
The setting values before data is loaded are updated.
Assignment of Command controlled by NVMLD command

NVMLD
command controlled NVM load
command
Unconditional E8h
IF Setting, ID setting, DSI control,

NVMLD[0] B3h, B4h, B6h, CAh, CEh
CE, CABC
NVMLD[1] B8h, B9h, BAh, BBh, BCh, BDh CABC, SRE, SRE
NVMLD[2] 70h-7Eh, A1h, DAh, DBh, DCh UCS
Slew rate, Display setting, TPC,

Source timing, Real Time Scaling,
C0h, C1h, C2h, C3h, C4h, C5h, C6h,
NVMLD[3] LTPS timing, Gamma setting,
C7h, C8h, C9h, CBh, CCh
Test register, Panel pin setting,
Panel I/F setting
NVMLD[4] D0h, D2h, D5h Power Setting, VCOM setting
Test register,
NVMLD[5] CDh, D6h-D9h, E5h, ECh-EFh, FBh
Test image generator,
NVMLD[6] F1h, F4h, F9h Test register
NVMLD[7] E9h Test register
Restriction -
Rev.1.01 June 28, 2014 234

NVMWECNT
Description
These registers count the times of NVM erase/write.
Function Table
Restriction
When NVM erase/write operation finish normally, this counter counts up.
If NVM erase/write operation finish abnormally, this counter cannot count correctly.
Rev.1.01 June 28, 2014 235

・Test Register : E9h

Command 0 1 ↑ 1 1 1 0 1 0 0 1 E9
1st
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
3rd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
5th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
6th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
7th
1 ↑ ↑ 1 0 0 1 0 0 0 0 xx
parameter
Register init - - - 1 0 0 1 0 0 0 0 90
8th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
9th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
10th
1 ↑ ↑ 0 0 1 1 0 0 1 1 xx
parameter
Register init - - - 0 0 1 1 0 0 1 1 33
11th
1 ↑ ↑ 1 0 0 0 0 0 0 0 xx
parameter
Register init - - - 1 0 0 0 0 0 0 0 80
12th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
13th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
14th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
15th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
16th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
17th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
18th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
19th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
20th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
21th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
22th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
23th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
24th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
25th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
26th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
27th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
Rev.1.01 June 28, 2014 236

28th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
29th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
30th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
31th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
32th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
33th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
34th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
35th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
36th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
37th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
38th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
39th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
Rev.1.01 June 28, 2014 237

・Supported Compression Method : EAh

Command 0 1 ↑ 1 1 1 0 1 0 1 0 EA
1st COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR
1 ↑ 1 xx
parameter Y_NUM[7] Y_NUM[6] Y_NUM[5] Y_NUM[4] Y_NUM[3] Y_NUM[2] Y_NUM[1] Y_NUM[0]
Register init - - - 0 0 0 0 0 1 0 1 05
2nd COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR
1 ↑ 1 xx
parameter Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0]
Register init - - - 0 0 0 0 0 0 0 1 01
3rd COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR
1 ↑ 1 xx
Register init - - - 0 0 0 0 0 0 1 0 02
4th COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR COMP_ENTR
1 ↑ 1 xx
Register init - - - 0 1 1 0 0 1 0 1 65
1 ↑ 1 xx
Register init - - - 0 1 1 0 0 1 1 0 66
1 ↑ 1 xx
Register init - - - 0 1 0 0 0 1 1 0 46
COMP_ENTRY_NUM
Description
This register indicates the number of compression method which Driver IC is supported.
Function Table
Restriction
COMP_ENTRY1, COMP_ENTRY2, COMP_ENTRY3, COMP_ENTRY4, COMP_ENTRY5
Description
In order to check the support compression ID of Driver IC have the compression method ID register.
These registers are ID register. These registers consist compression method and compression
method version for each Video mode and Command mode.
Application processor should check the compression method the Driver IC is supported.
Function Table
bit Description
0: No compression
2: 1/2 compression
[7:5] Compression ratio
3: 1/3 compression
Other: inhibit
[4:2] Compression IP version -
0: Not supported
[1] Support Video mode
1: Supported
0 :Not supported
[0] Support Command mode
1 :Supported
Restriction
Rev.1.01 June 28, 2014 238

・ Compression Method : EBh

Command 0 1 ↑ 1 1 1 0 1 0 1 1 EB
1st COMPV_MET COMPV_MET COMPV_MET COMPV_MET COMPV_MET COMPV_MET COMPV_MET COMPV_MET
1 ↑ ↑ xx
parameter HOD[7] HOD[6] HOD[5] HOD[4] HOD[3] HOD[2] HOD[1] HOD[0]
Register init - - - 0 0 0 0 0 0 0 0 00
2nd COMPC_ME COMPC_ME COMPC_ME COMPC_ME COMPC_ME COMPC_ME COMPC_ME COMPC_ME
1 ↑ ↑ xx
parameter THOD[7] THOD[6] THOD[5] THOD[4] THOD[3] THOD[2] THOD[1] THOD[0]
Register init - - - 0 0 0 0 0 0 0 0 00
COMPV_METHOD
Description
This register is for setting of compression method in Video mode.
Function Table
bit Description
0: No compression
[7] Compression enable
1: Compression
[6:3] Reserved -
0: No compression
2: 1/2 compression
[2:0] Compression Ratio
3: 1/3 compression
Other: inhibit
Restriction
-
COMPC_METHOD
Description
This register is for setting of compression method in Command mode.
Function Table
bit Description
0: No compression
[7] Compression enable
1: Compression
[6:3] Reserved -
0: No compression
[2:0] Compression Ratio 3: 1/3 compression
Other: inhibit
Restriction
-
Rev.1.01 June 28, 2014 239

・Test Register : ECh

Command 0 1 ↑ 1 1 1 0 1 1 0 0 EC
1st
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
3rd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
Rev.1.01 June 28, 2014 240

・Test Register : EDh

Command 0 1 ↑ 1 1 1 0 1 1 0 1 ED
1st
1 ↑ ↑ 0 1 1 0 1 1 0 1 xx
parameter
Register init - - - 0 1 1 0 1 1 0 1 6D
2nd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
3rd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th
1 ↑ ↑ 0 0 0 0 0 0 0 1 xx
parameter
Register init - - - 0 0 0 0 0 0 0 1 01
5th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
6th
1 ↑ ↑ 0 0 0 0 0 0 0 1 xx
parameter
Register init - - - 0 0 0 0 0 0 0 1 01
7th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
8th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
9th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
10th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
11th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
12th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
13th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
14th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
15th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
16th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
17th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
18th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
19th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
20th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
Rev.1.01 June 28, 2014 241

・Test Register : EEh

Command 0 1 ↑ 1 1 1 0 1 1 1 0 EE
1st
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
2nd
1 ↑ ↑ 0 0 1 1 0 0 1 0 xx
parameter
Register init - - - 0 0 1 1 0 0 1 0 32
3rd
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
4th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
・Test Register : EFh

Command 0 1 ↑ 1 1 1 0 1 1 1 1 EF
1st
1 ↑ ↑ 0 1 0 0 0 0 0 0 xx
parameter
Register init - - - 0 1 0 0 0 0 0 0 40
2nd
1 ↑ ↑ 0 0 0 1 0 0 0 0 xx
parameter
Register init - - - 0 0 0 1 0 0 0 0 10
Rev.1.01 June 28, 2014 242

・Realtime Scaling Off Control : F1h
Description
This register necessary to set when changing the state Realtime Scaling On to Off.
Function Table
RTSOFC Real Time Scaling off contorol
0 It is impossible to turn off Realtime Scaling function.
1 It is possible to turn off Realtime Scaling function.
Restriction
-
Rev.1.01 June 28, 2014 243

System Interface Configuration (MIPI DSI)

The DSI incorporated in the RSP LCD driver complies with the following standards:
MIPI DSI: Version 1.01.00r11 21-Feb-2008

MIPI D-PHY: Version 1.00.00 14-May-2009
MIPI DCS: Version 1.01.00
(1) Basic DSI Specification
 Command Mode and Video Mode supported

Video data received in video mode is directly output as display data without being written to
internal GRAM.
 One line data must be sent by one packed pixel stream packet.
Note: For the number of lanes and the data rate, see “Block Function” and “Electrical
Characteristics.”
(2) DSI System Configuration
HOST RSP LCD driver

Interface Interface
RESX
Block RESX Block
CSX
CSX
CLKP_A
DSICLKP_A/N_A
CLKN_A
DSID0P_A/N_A DATA0P_A
DATA0N_A
DATA1P_A
DSID1P_A/N_A DATA1N_A
DATA2P_A
DSID2P_A/N_A
DATA2N_A
DATA3P_A
DSID3P_A/N_A
DATA3N_A
CLKP_B
DSICLKP_B/N_B
CLKN_B
DSID0P_B/N_B DATA0P_B
DATA0N_B
DATA1P_B
DSID1P_B/N_B DATA1N_B
DATA2P_B
DSID2P_B/N_B
DATA2N_B
DATA3P_B
DSID3P_B/N_B
DATA3N_B
TE TE
When MIPI DSI is selected, CSX is used only to exit deep standby (DSTB) mode.
When deep standby mode is exited by RESX, CSX is not required. a
Figure 17 Example of DSI
Rev.1.01 June 28, 2014 244

Table 49 Interface Type (IM Setting) – Color Format

RSP LCD driver
Type IM2-0 Data pin Color format MIPI Spec.
support
DSI 110 D0+/-, D1+/- 16bpp Yes No
18bpp Yes Yes
24bpp Yes Yes
Yes: Supported
No: Unsupported
(3) Lane State Definition
Table 50 Lane State Description

State code Line voltage levels High speed Low power
Dp-line Dn-line Burst mode Control mode Escape mode
HS-0 HS Low HS High Differential-0 1 1
HS-1 HS High HS Low Differential-1 1 1
LP-00 LP Low LP Low N/A Bridge Space
LP-01 LP Low LP High N/A HS-Rqst Mark-0
LP-10 LP High LP Low N/A LP-Rqst Mark-1
LP-11 LP High LP High N/A Stop 2
Notes: 1. During high-speed transmission, the low power receivers observe LP-00 on the lines.
2. If LP-11 occurs during Escape mode, the lane returns to stop state (Control mode LP-11).
(4) DSI-CLK Lane
Note: Return to LP11 periodically, when in High Speed Clock Mode

Figure 18 Clock Lane State Diagram
Rev.1.01 June 28, 2014 245

1) Low Power Mode (LP-11: STOP)
Figure 19 Switching the Clock Lane between Clock Transmission and Low Power Mode 1
2) Ultra Low Power Mode (LP-00: ULPM)
Rev.1.01 June 28, 2014 246

3) High Speed Clock Mode
4) High Speed Clock Burst
Clock Lane Disconnect

CLKp/CLKn Terminator
TCLK-POST TEOT
VIH(min)
VIL(max)
TCLK-TRAIL THS-EXIT TLPX TCLK-PREPARE TCLK-ZERO TCLK-PRE
Data Lane Disconnect

TLPX THS-PREPARE
Dp/Dn Terminator
VIH(min)
VIL(max)
Rev.1.01 June 28, 2014 247

(5) DSI-D0 Data Lane
Figure 23 DSI-D0 Data Lane State Diagram
Table 51 Data Lane Operating Modes

No. Description Operation code Note
High Speed Data Transmission
1 LP-11 > L-P01 > LP-00
Burst
2 Escape mode entry LP-11 > LP-10 > LP-00 > LP-01 > LP-00
3 Turnaround LP-11 > LP-10 > LP-00 > LP-10 > LP-00 1
4 Exit Escape mode (Mark-1) L-10
5 Deep Standby Mode DSTB=1 or HWRESET=0 2
6 Exit Deep Standby Mode HWRESET 0->1 3
Note: 1. Before Turnaround operation, DBI Packet must be sent.
2. DSTB must be sent by Escape mode in Sleep mode.
3. After exiting from the Deep Standby Mode, all of commands are reset.
Rev.1.01 June 28, 2014 248

1) Power On, HWRESET  LP-11
The data lanes and clock lane should be in the LP-11 state during power-on, HWRESET, and soft_reset
sequences.
2) Escape Mode
 Escape mode entry

 Mark-1 (exit Escape mode)
Table 52 Escape Entry Code

Entry Command R63419 Note
Escape Mode Command Pattern implementation
No. Symbol
Action Type (first bit transmitted to
LP-RX LP-TX
last bit transmitted)
Low Power Data
1 LPDT Mode 1110_0001 Yes Yes
Transmission
Ultra-Low Power
2 ULPS Mode 0001_1110 Yes No
State
3 UDF1 Undefined-1 Mode 1001_1111 No No
4 UDF2 Undefined-2 Mode 1101_1110 No No
Remote
5 RAR Application Trigger 0110_0010 Yes No Note1.
Reset
6 TER TE-Report Trigger 0101_1101 No Yes Note.2
Unkown-4
7 ACKT (Acknowledge Trigger 0010_0001 No Yes
Trigger)
8 UNK5 Unknown-5 Trigger 1010_0000 No No
Note1: DSI circuit is reset by Remote Application Reset.
Note2: The master port defined by PNSLV pin supports TE-Report.
Rev.1.01 June 28, 2014 249

3) Escape Mode (Host >Client): Low Power Data Transmission (LPDT)
An example of DSI read sequence by LPDT is shown below.
Figure 24
Rev.1.01 June 28, 2014 250

4) Escape Mode (Host>Client): Ultra Low Power State (ULPS)
5) Escape Mode (Host>Client): Remote Application Reset (RAR)
6) Escape Mode (Client>Host): Tearing Report (TER)
R63419 supports TE Report function. Only master port defined by PNSLV pin supports TE Report.
Procedures are as follows:
Host to Client: send set_tear_on of DCS

Host to Client: send BTA
Client to Host: send Acknowledge Trigger
Client to Host: send BTA
Host:check Error Report
Host to Client: send BTA
Client to Host: send TE Report when TE occurred at the line of set_scan_line
Client to Host: send BTA
Host to Client: send image data by HST
Figure 25
7) Escape Mode (Client > Host): Acknowledge Trigger (ACKT)
8) High Speed Data Transmission (HST)
Note: Return to LP11 periodically, when in High Speed Mode.
9) Bus Turnaround (Host>Client) (BTA)
10) Bus Turnaround (Client>Host) (BTA)
Rev.1.01 June 28, 2014 251

(6) Packet Level Communication
1) Short Packet (SPa) Structure
Figure 26 Example of Short Packet (SPa) (DCS WRITE, 1 Parameter)
Rev.1.01 June 28, 2014 252

2) Long Packet (LPa) Structure
Figure 27
3) Multiple Packet Sending
In LP-11 state, multiple Short Packets (SPa) and Long Packets (LPa) can be received between SoT and
EoT.
LP-11  SoT  SPa  SPa  EoT
LP-11  SoT  SPa  LPa  EoT
LP-11  SoT  LPa  LPa  EoT
LP-11  SoT  LPa  SPa  EoT
LP-11  SoT  Combination of the above methods  EoT
Rev.1.01 June 28, 2014 253

(7) Data Identification (DI)
1) Virtual Channel (VC)
The RSP LCD driver supports Virtual Channel(VC). The data of VC is setting by 2bits, and refer data
of DSIVCA[1:0]/DSIVCB[1:0]. The data of DSIVCA[1:0]/DSIVCB[1:0] are stored to NVM.
2) Data Type (DT)
If Data Type undefined in the MIPI DSI specification is received, the subsequent data cannot be
received. Transmit data again after checking that the RSP LCD driver is in LP-11 state by Error Report.
If Data Type unsupported in the RSP LCD driver is received, it is regarded as NOP, and the result is
not reflected on the Error Report.
Table 53
Data Identification (DI)
Virtual Channel (VC) Data Type (DT)
B7 (0) B6 (0) B5 B4 B3 B2 B1 B0
Rev.1.01 June 28, 2014 254

Table 54 RSP LCD Driver Rx Data Type List

Data Packet DBI DPI Command mode Video mode
Description Note
Type size packet packet Implementation Implementation
01h Sync Event, V Sync Start Short Yes No Yes 4

11h Sync Event, V Sync End Short Yes No No 4
21h Sync Event, H Sync Start Short Yes No Yes 4
31h Sync Event, H Sync End Short Yes No No 4
08h End of Transmission packet (EoT) Short Yes Yes
02h Color Mode (CM) Off Command Short Yes No No 4
12h Color Mode (CM) On Command Short Yes No No 4
22h Shut Down Peripheral Command Short Yes No Yes
32h Turn On Peripheral Command Short Yes No Yes
03h Generic Short WRITE, no parameters Short Yes No No 4
13h Generic Short WRITE, 1 parameter Short Yes Yes Yes 1, 2
23h Generic Short WRITE, 2 parameters Short Yes Yes Yes 1, 2
04h Generic READ, no parameters Short Yes No No 1,4
14h Generic READ, 1 parameter Short Yes Yes Yes
24h Generic READ, 2 parameters Short Yes Yes Yes 1, 2
05h DCS WRITE, no parameters Short Yes Yes Yes 1, 2
15h DCS WRITE, 1 parameter Short Yes Yes Yes 1, 2
06h DCS READ, no parameters Short Yes Yes Yes 1, 2
Set Maximum Return Packet Size
37h Short Yes Yes Yes
(default 0001h)
09h Null Packet, no data Long Yes Yes

19h Blanking Packet, no data Long Yes No Yes 4
29h Generic Long Write Long Yes Yes Yes
DCS Long Write/write_LUT
39h Long Yes Yes Yes
Command Packet
Packed Pixel Stream,

0Eh Long Yes No No 3
16-bit RGB, 5-6-5 Format

1Eh Long Yes No No 3
Loosely Packed Pixel Stream,

2Eh Long Yes No Yes 3

3Eh Long Yes No Yes 3
other All unspecified codes are reserved - - - - -
Rev.1.01 June 28, 2014 255

Table 55 RSP LCD Driver LP-Tx Data Type List

RSP LCD driver
Data Packet
Description (LP-Tx) Note
Type size
Implementation
00h-01h Reserved －－
02h Acknowledge with Error Report Short Yes
08h End of Transmission packet (EoT) Short No 5
11h Generic Short READ Response, 1 byte returned Short Yes
12h Generic Short READ Response, 2 bytes returned Short Yes
1Ah Generic Long READ Response Long Yes
1Bh Reserved －－
1Ch DCS Long READ Response Long Yes
1Dh-20h Reserved －－
21h DCS Short READ Response, 1 byte returned Short Yes
22h DCS Short READ Response, 2 bytes returned Short Yes
29h-3Fh Reserved －－
Notes: 1. Generic Command is Manufacturer Command.

DCS Command is User Command.
2. Generic XXX 1 parameter is Manufacturer Command + 1 byte (all “0”).
Generic XXX 2 parameter is Manufacturer Command + 1 parameter.
DCS XXX no parameter is User Command + 1 byte (all “0”).
DCS XXX 1 parameter is User Command + 1 parameter.
3. Line data must be sent by one packet.
4. Any packet with data type that MIPI Specification defines and the RSP LCD driver doesn’t support is
treated as NOP.
5. Defined in MIPI DSI Specification (used for HS transmission).
6. Note that the RSP LCD driver will stop to receive as soon as it detects any packet with data type that the
MIPI Specification doesn’t define.
7. Using DSI Data Type (22h and 32h) with DCS Commands (11h, 10h, 28h, and 29h) is prohibited.
Rev.1.01 June 28, 2014 256

(8) Word Count (WC) on Long Packet (LPa)
Word Count (WC) = 2 bytes: The number of packet data on Long Packet (0 to 65,535 bytes)
(9) Error Correction Code (ECC)
ECC detects 1-bit errors or multiple-bit errors in each Packet Header. ECC is performed on the
following:
 Short Packet: DI, Data0, Data1, and ECC

 Long Packet: DI, WC (2 bytes), and ECC
(10) Command Mode Pixel Data Format (PD)
Figure 28 24bpp Pixel Data Format on the Long Packet (3Ah: set_pixel_format D2-0 = 111)
Rev.1.01 June 28, 2014 257

Figure 29 18bpp Pixel Data Format on the Long Packet (3Ah: set_pixel_format D2-0 = 110)
(11) Packet Footer on Long Packet (LPa)
In the Long Packet, Packet Footer is added after Packet Data. Packet footer includes CRC calculated
from Packet Data as checksum.
 Checksum (2 bytes) = CRC (Packet Data): CRC = X16  X12  X5  X0
Rev.1.01 June 28, 2014 258

(12) Acknowledge with Error Report (AwER)
Table 56
RSP LCD driver
Bit Description Note
Implementation
0 SoT Error No
1 SoT Sync Error No
2 EoT Sync Error No
3 Escape Mode Entry Command Error Yes 1
4 Low-Power Transmit Sync Error Yes 1
5 HS Receive Timeout Error No
6 False Control Error No
7 Reserved -
8 ECC Error, single-bit (detected, and corrected) Yes
9 ECC Error, multi-bit (detected, not corrected) Yes
10 Checksum Error (Long packet only) Yes
11 DSI Data Type Not Recognized Yes
12 DSI VC ID Invalid Yes
13 Invalid Transmission Length No
14 Reserved -
15 DSI Protocol Violation No
Note: Detail error report condition is defined by RSP LCD driver (based on MIPI description).
Rev.1.01 June 28, 2014 259

(13) DCS, MCS, and Data Type List
The following tables show available data type of each command (DCS and MCS).
Table 57 DCS Data Type List

Host to RSP LCD driver Data Type (RX)
W/R Write Type Read Type Other
DCS Data 05’h 15’h 39’h 13’h 23’h 29’h 14’h 24’h 06’h 37’h
Type
Command/Parameter Packet Short Short Long Short Short Long Short Short Short Short
DCS DCS DCS DCS Generic Generic Generic Generic Generic DCS Set
para no 1 1 para 2 para - 1 para 2 para no max.
para para para return
packet
size
00h nop C Yes No Yes No No No No No No -
01h soft_reset C Yes No Yes No No No No No No -
04h read_DDB_start 16 No No No No No No No No Yes 16’h10
05h read_Number_of_the_ 1 No No No No No No No No Yes 16’h1

Errors_on_DSI
06h get_red_channel 1 No No No No No No No No Yes
07h get_green_channel 1 No No No No No No No No Yes
08h get_blue_channel 1 No No No No No No No No Yes
0Ah get_power_mode 1 No No No No No No No No Yes 16’h1
0Bh get_address_mode 1 No No No No No No No No Yes 16’h1
0Ch get_pixel_format 1 No No No No No No No No Yes 16’h1
0Dh get_display_mode 1 No No No No No No No No Yes 16’h1
0Eh get_signal_mode 1 No No No No No No No No Yes 16’h1
0Fh get_diagnostic_result 1 No No No No No No No No Yes 16’h1
10h enter_sleep_mode C Yes No Yes No No No No No No -
11h exit_sleep_mode C Yes No Yes No No No No No No -
12h enter_partial_mode C Yes No Yes No No No No No No -
13h enter_normal_mode C Yes No Yes No No No No No No -
22h set_all_pixels_off C Yes No Yes No No No No No No -
23h set_all_pixels_on C Yes No Yes No No No No No No -
26h set_gamma_curve 1 No Yes Yes No No No No No No -
28h set_display_off C Yes No Yes No No No No No No -
29h set_display_on C Yes No Yes No No No No No No -
2Ah set_column_address 4 No No Yes No No No No No No -
2Bh set_page_address 4 No No Yes No No No No No No -
2Ch write_memory_start N No No Yes No No No No No No -
Rev.1.01 June 28, 2014 260

Table 58 DCS and Data Type List (continued)

DCS Data 05’h 15’h 39’h 13’h 23’h 29’h 14’h 24’h 06’h 37’h
Type
DCS DCS DCS DCS Generic Generic Generic Generic Generic DCS Set
packet
size
30h set_partial_area 4 No No Yes No No No No No No -
34h set_tear_off C Yes No Yes No No No No No No -
35h set_tear_on 1 No Yes Yes No No No No No No -
36h set_address_mode 1 No Yes Yes No No No No No No -
38h exit_idle_mode C Yes No Yes No No No No No No -
39h enter_idle_mode C Yes No Yes No No No No No No -
3Ah set_pixel_format 1 No Yes Yes No No No No No No -
3Ch write_memory_continue N No No Yes No No No No No No -
44h set_tear_scanline 2 No Yes Yes No No No No No No -
51h write_display_brightness 1 No Yes Yes No No No No No No -
52h read_display_brightness 1 No No No No No No No No Yes 16’h1

_value
55h write_content_adaptive_ 1 No Yes Yes No No No No No No -

brightness_control
56h read_content_adaptive_ 1 No No No No No No No No Yes 16’h1

brightness_control
5Eh write_CABC_minimum_ 1 No Yes Yes No No No No No No -

brightness
5Fh read_CABC_minimum_ 1 No No No No No No No No Yes 16’h1

brightness
68h read_automatic_ 1 No No No No No No No No No 16’h1

brightness_control_
self-diagnostic_result
A1h read_DDB_start (Note1) 16 No Yes Yes No No No No No Yes 16’h10
A8h read_DDB_continue N No No No No No No No No Yes 16’h10

(Note1)
DAh Read ID1 1 No No No No No No No No Yes -
DBh Read ID2 1 No No No No No No No No Yes -
DCh Read ID3 1 No No No No No No No No Yes -
E1h idlemode_BL_control 1 No Yes Yes No No No No No No -
E2h read_idlemode_BL_contr 1 No No No No No No No No Yes 16’h1

ol
Note: When each data type packet is sent, it is necessary to write all parameters of each DCS and MCS.
Note1: maximum return packet size ≧ 2
Note2: A1h command is used to write DDB data, too.
Rev.1.01 June 28, 2014 261

Table 59 MCS and Data Type List

MCS Data 05’h 15’h 39’h 13’h 23’h 29’h 14’h 24’h 06’h 37’h
Type
MCS DCS DCS DCS Generic Generic Generic Generic Generic DCS Set
packet
size
MCS 1 No No No No No No Yes No No 16’h1

Read only command
MCS 1 No No No No Yes Yes Yes No No 16’h1

write/read command
MCS 1<n No No No No No Yes Yes No No 16’hn

write/read command
Rev.1.01 June 28, 2014 262

(14) Video Mode
The RSP LCD driver supports Video Mode for moving pictures. There are three formats of
transmission packet sequences. The RSP LCD driver supports two of these formats. See the following
table.
Table 60
Transmission packet sequence in video mode RSP LCD driver implementation
Non-burst mode with sync pulses Not supported
Non-burst mode with sync events Supported
Burst mode Supported
1) Display Timing (Video Mode)
Figure 30
Rev.1.01 June 28, 2014 263

2) Vertical Display Timing (Video Mode)
VSYNC
BP(Command :C2h、4th parameter)

VFP
VFP VS VBP
D[23:0]
VBL Vadr(NL)
DE
VP(1frame)
BP+1 VFP-1
Source Output
HSYNC
V B H B H B H B RGB B H B RGB B H B H B H B V B
S P S P S P S P data P S P data P S P S P S P S P
Key :
VS : Vsync Start(DT=01h),HS : Hsync Start(DT=21h),BP : Blanking Packet(DT=09h)
RGB data : RGB data(DT=3Rh),DT : Data type
Figure 31
Rev.1.01 June 28, 2014 264

3) Horizontal Display Timing (Video Mode)
Figure 32
Table 61 Vertical Display Timing (Video Through Mode, DM = 1h)
Item Symbol Condition Unit Min. Typ. Max. Notes

Vertical cycle VP Line 1286 - -
Vertical low pulse width VS Line 1 - -
Vertical front porch VFP Line 2 - -
Vertical back porch VBP Line 2 - - See Note
Vertical data start point - BP Line 4 - - See Note
Vertical blanking period VBL VFP+BP Line 6 - -
Vertical active area Vadr Line 1280 2560 2560
Note: “BP” is set as back porch by BP register.
Setting of BP is different from VBP if using compression data transfer. Refer to “Compression data transfer”.
1 line : prescribed by HSYNC (when DM = 4’h1)
Table 62 Horizontal Display Timing (Video Through Mode, DM = 1h)

4lane:100+β
Horizontal front porch HFP ByteClock - -
Horizontal data start

- HS+HBP ByteClock 45+α - -
point
Horizontal active area Hadr Pixel 1440 1600
α,β≦12 Byte Clock
Please refer to following restrictions about α,β
Rev.1.01 June 28, 2014 265

Table 63 Vertical Display Timing (Video to RAM Mode, DM = 3h, Method-1)

Vertical back porch VBP Line 2 - -
Vertical data start point - BP Line 4 - - See
Vertical blanking period VBL VFP+BP Line 6 - -
1 line : prescribed by RTN setting (when DM = 4’h3)
Table 64 Vertical Display Timing (Video to RAM Mode, DM = 3h, Method-2)

Vertical back porch VBP Line BP+3 - -
Vertical data start point - BP Line BP+4 - - See
Vertical blanking period VBL VFP+BP Line BP+7 - -
1 line : prescribed by RTN (when DM = 4’h3)
line line
BP FP BP FP
Video data
display
display
Video data
Video data Video data

time time
VS VS VS VS
Method - 1 Method - 2
Rev.1.01 June 28, 2014 266

Table 65 Horizontal Display Timing (Video to RAM Mode , DM = 3h)

4lane:100+β
Horizontal front porch HFP ByteClock - -
Horizontal data start

- HS+HBP ByteClock 45+α - -
point
Horizontal active area Hadr Pixel 1440 1600
α,β≦12 Byte Clock
Please refer to following restrictions about α,β
Rev.1.01 June 28, 2014 267

Timing restrictions in Dual MIPI-DSI ports data transfer

It is necessary to keep the blank spec as below at LCD point, because R63419 has Dual MIPI-DSI ports.
Host Processor needs to add additional blank period (45ByteClock +α, 100ByteClock+β) to keep
above minimum blank period, according to transmission skew between PortA and PortB.
α: Time the pixel data is transferred to PortB precedes time the pixel data is transferred to the PortA.
β: Time the pixel data is transferred to PortB is behind time the pixel data is transferred to the PortA.
45ByteClock(min) 100ByteClock(min)
HSYNC of Master Port
HS+HBP HFP （100ByteClock）
Hadr（RGB Data）
Pixel Data of Master Port 45ByteClock α β （100ByteClock）
（600ByteClock）
45ByteClock
Pixel Data of Slave Port Hadr（RGB Data）

45ByteClock α β （100ByteClock）
（early against Master）（600ByteClock）
α 100ByteClock
Hadr（RGB Data）
Pixel Data of Slave Port 45ByteClock α β （100ByteClock）
（600ByteClock）
（delay against Master）
Figure 33
Below is an Example of R63419 video Mode timing setting (Host Side).
* frame freq. 60 Hz
Vertical Sync
*X 1440 RGB
*Y 2560 line VS
invisible image
* VS+VBP 8 line
8
* VFP 8 line VBP

1440RGB
* HS+HBP 57 byteclock 520 ns Visible image

min. 45 byteclock 411 ns
2560line
2560
α 12 byteclock 110 ns VAdr

Hadr 540 byteclock 4928 ns
* HFP 112 byteclock 1022 ns
min. 100 byteclock 913 ns
β 12 byteclock 110 ns
VFP
8
DSI 877 Mbps/lane

line
Horizontal
Byte clock 9.1 ns
Sync
Note) α and βare set by host side,

according to skew between host and R63319. HS HBP(+α) HAdr HFP(+β)
Note) mark (*) is a parameter to be set in host side generally. 57 540 112 byteclock
(520) (4928) (1022) ns
Figure 34
Rev.1.01 June 28, 2014 268

4) Packed Pixel Stream
1 byte 1 byte 1 byte

012 7 01 2 7 01 2 7
R R G G B B
0 5 0 5 0 5
6b 6b 6b
...
Pixel 1
1 byte 2 bytes 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte
6b 6b 6b 6b 6b 6b 6b 6b 6b
Virtual Channel ID
Data Type
Word Count ECC
Pixel 1 Pixel 2 Pixel 3

Data ID
Packet Header Variable Size Payload (First Three Pixels in Nine Bytes)
1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 bytes
6b 6b 6b 6b 6b 6b 6b 6b 6b
... Checksum
Pixel n-2 Pixel n-1 Pixel n
Variable Size Payload (Last Three Pixels Packed in Nine Bytes) Packet Footer
Figure 35 18-Bit Format Long Packet (loosely packed) Data Type 10 1110 (2Eh)
Rev.1.01 June 28, 2014 269

1 byte 1 byte 1 byte

0 7 0 7 0 7
R RG GB B
0 7 0 7 0 7
8b 8b 8b
...
Pixel 1
1 byte 2 bytes 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte
8b 8b 8b 8b 8b 8b 8b 8b 8b
Virtual Channel ID
Data Type
Word Count ECC
Pixel 1 Pixel 2 Pixel 3

Data ID
Packet Header Variable Size Payload (First Three Pixels in Nine Bytes)
1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 bytes
8b 8b 8b 8b 8b 8b 8b 8b 8b
... Checksum
Pixel n-2 Pixel n-1 Pixel n
Variable Size Payload (Last Three Pixels Packed in Nine Bytes) Packet Footer
Figure 36 24-Bit Format Long Packet Data Type 11 1110 (3Eh)
Rev.1.01 June 28, 2014 270

5) Packet Footer on Long Packet (LPa)
In the Long Packet, Packet Footer is added after Packet Data. Packet footer includes CRC calculated
from Packet Data as checksum.
Checksum (2 bytes) = CRC (Packet Data): CRC = X16  X12  X5  X0
6) Line Contention Detection
The Low-Power receiver and a separate contention detector shall be used in a bi-directional data Lane
to monitor the line voltage on each low-power signal. The low-power receiver shall be used to detect an
LP high fault when the LP transmitter is driving high and the pin voltage is less than V IL. The
contention detector shall be used to detect an LP low fault when the LP transmitter is driving low and
the pin voltage is greater than VIHCD. An LP low fault shall not be detected when the pin voltage is less
than VILCD.
The LP-CD threshold voltages (VILCD and VIHCD) are shown along with the normal signaling voltages
as below.
After contention has been detected, the protocol shall take proper measures to resolve the situation.
Figure 37 Signaling and Contention Voltage Levels
Rev.1.01 June 28, 2014 271

Display Mode
(1) Display mode change in SleepIn
As shown below, input display clock via each interface before issuing exit_sleep_mode.
≧4frame
Figure 38
(2) Display Interface switching flow
RSP LCD driver can switching display interface between Command mode and Video mode using
“Video Through mode” with V2CRM or “Video to RAM mode” without display off. Details are
following.
In case of using RSP compression I/F, V2CRM does not support. If switching display interface
between Command mode and Video mode without display off, use “Video to RAM mode”.
Rev.1.01 June 28, 2014 272

Command Mode　⇔　Video Through Mode with V2CRM=1
Command mode
DM='h0
RM='h0
Mode changes autonmatically from

Video Through mode to Command
mode after 1frame.
Video through mode Video capture at last frame

DM='h1 DM='h0
RM='h0 RM='h0, V2CRM=1
Command Mode　⇔　Video to RAM Mode
Command mode
DM='h0
RM='h0
Video to RAM mode

DM='h3
RM='h1
Figure 39
If switch Video Through mode to Command mode by DM, Continue video input at least 2frames.
DM=1->0
≧2frame
Video Input
Host Frame 1 Frame2 ・・・ Frame N-1 Frame N Frame N+1 Frame N+2
Video Mode(DM=1) Command Mode(DM=0)

LCD Dr
Frame 1 Frame2 ・・・ Frame N-1 Frame N Frame 1 Frame2 ・・・ Frame N-1 Frame N
Figure 40
Rev.1.01 June 28, 2014 273

R63419
Command Mode　⇔　Video Through Mode with V2CRM=1
1frame 1frame 1frame 1frame 1frame 1frame 1frame
Rev.1.01 June 28, 2014

LCD Dr State BP Display FP BP Display FP BP Display FP BP Display FP BP Display FP BP Display FP BP Display FP
Operation
Chart
data write data write data write data write
display display display display display display display
TE
Display mode Command mode Video through mode Video capture mode Command mode
DM='h1 DM='h0
V2CRM=0 V2CRM=1
274
Overlap frame Overlap frame
Figure 41
Host to Driver
Compress 1/3 Capture
Frame Momory
Extract x3 Extract x3 Extract x3 Extract x3
Display
Specification
R63419
Command Mode　⇔　Video to RAM
Rev.1.01 June 28, 2014

Operation
Chart
data write data write data write data write
TE
Display mode Command mode Video to RAM mode Command mode
DM='h3 DM='h0
RM=1 RM=0
Overlap frame
275
Overlap frame
Figure 42
Host to Driver
Compress 1/3 Compress 1/3
Frame Momory
Extract x3 Extract x3 Extract x3 Extract x3 Extract x3 Extract x3 Extract x3
Display
Specification
Frame Memory
The frame memory retains image data obtained from (panel resolution  the number of colors (bpp)).
(Resolution = (Column_Address_Max + 1)  (Row_Address_Max + 1))
Address Mapping from Memory to Display
Normal Display On or Partial Mode On
In this mode, a content of the frame memory within an area where column pointer is 0000h to
(Column_Address_Max)h and page pointer is 0000h to (Row_Address_Max)h is displayed.
Figure 43
Host Processor to Memory Write Direction
The figure below illustrates data stream from the host processor.
Figure 44
Rev.1.01 June 28, 2014 276

The data is written in the order shown in the above figure. The frame memory in this driver employs
an image compression store method. Image is compressed in units of four pixels. To write data to the
frame memory, transfer the image data in units of consecutive addresses. Determine a data transfer start
position settings by set_column_address (2Ah).
Table 66
Condition Column counter Page counter Note

When commands write_memory_start (2Ch) and Back to Start Back to Start
read_memory_start (2Eh) are received. Column Page
Execute Pixel Read/Write Increment by 1 No change
Back to Start
When column counter value is larger than ”End Column” Increment by 1
Column
When column counter value is larger than ”End Column” and page Entry Mode(B3h)
STOP STOP
counter value is larger than “End Page” WEM=0
Back to Start Back to Start Entry Mode(B3h)

Column Page WEM=1
Rev.1.01 June 28, 2014 277

Reference Clock Generating Function

The following figure shows the generation of reference clock (RCLK) used in the RSP LCD driver.
RCLK generated from a divider divides an internal oscillation clock. Then, a divider set by DIV
divides these divided clocks.
Refer “Electrical characteristics about OSC frequency(fOSC).
Set display timing according to use conditions.
DIV
Reference
clock(RCLK）
OSC clock1
Internal (Ex.)(fOSC/4)/DIV Display timing
1/4 Divider
oscillation clock fOSC/4 contorol circuit
(*1) 1/1
OSC clock2
1/2 Step-up circuit
fOSC/2
Figure 45 Internal Reference Clock Generations
If entering 39h(Idle_mode_entry), the setting of DIV is ‘h11. Then, RCLK= (fOSC/4)/4, and if normal
mode frame rate is 60fps, idle mode frame rate is 15fps. Send pixel data to match this slow frame rate.
Output Waveform Mode of Panel Control Signals

For the specifications for panel control signals, see the appendix.
Rev.1.01 June 28, 2014 278

Frame Frequency Adjustment Function

The RSP LCD driver supports a function to adjust frame frequency. The frame frequency for driving
the LCD can be adjusted by setting frame frequency adjustment parameters (RTN0) without changing
the oscillation frequency.
It is possible to set a low frame frequency for saving power consumption when displaying a still picture
and set a high frame frequency when displaying video image.
Relationship between the Liquid Crystal Drive Duty and the Frame Frequency
The relationship between the liquid crystal drive duty and the frame frequency is calculated from the
following equation. The frame frequency can be changed by setting frame frequency adjustment
parameters (the number of clocks per 1 line period (RTN0)).
Equation for calculating frame frequency
RCLK
FrameFrequency  [ Hz]
RTN 0  ( NL  FP 0  BP )
fosc: Internal operation clock frequency

RCLK : Display reference clock (RCLK = fosc/ 4 )
RTN0 : Number of clocks per line
NL : Number of lines to drive the LCD
FP0 : Number of lines for front porch
BP : Number of lines for back porch
Example of Calculation: when Maximum Frame Frequency = 60 Hz
fosc: 65 MHz, RCLK = 14MHz (fosc/4)

Number of lines: 2560 lines (NL = A00h)
Number of clocks per 1 line period: 91 clocks (RTN0=5Bh)
Front porch: FP0=8 lines (FP0=8h)
Back porch: BP=8 lines (BP=8h)
14MHz
 f FRM   60 Hz
91clocks  (2560  8  8)
In the conditions described here, the frame frequency can be changed as follows by setting RTN0.
(NL = 2560 lines, BP = 8 lines, FP = 8 lines, and fosc = 56 MHz (typ.)).
Rev.1.01 June 28, 2014 279

TE Pin Output Signal

Tearing Effect Output signal is turned on/off by set_tear_off (34h) and set_tear_on (35h) commands.
Table 67
TEON
TELOM
(represents status of TE pin output
(35h1st parameter)
35h command)
0 * GND
1 0 TE (Mode1)
1 1 Setting inhibited
Tearing Effect signal mode is defined by TELOM (D0 in parameter of set_tear_on (35h)).
1H(RTN)
Figure 45
Rev.1.01 June 28, 2014 280

Self-Diagnostic Function
The RSP LCD driver supports the self-diagnostic functions. Set get_diagnostic_result (0Fh) 1st
parameter’s D6 bit according to the following flow chart.
Checks VPLVL
voltage level
Figure 46 Functionality Detection
Rev.1.01 June 28, 2014 281

Content Adaptive Brightness Control (Dynamic Backlight Control Function)

The RSP LCD driver supports a CABC (Content Adaptive Brightness Control) function to control
backlight brightness and process image according to image. This function enables to reduce backlight
power.
– Digital Gamma Adjustment for RGB Separate Gamma

– Content Adaptive Brightness Control(CABC)
– Sunlight Readability Enhancement(SRE)
– Backlight Dimming Control
Through histogram analysis of brightness of image data, the brightness of backlight and image
processing coefficient is calculated so that image data is optimized. Backlight power is reduced
without changing display image.
The RSP LCD driver can use Auto Contrast Optimization function and Content Adaptive Brightness
Control function at the same time.
Figure 47 Explanation of CABC
Notes: 1. The CABC and SRE setting are enabled by 55h user command.
(write_content_adaptive_brightness_control).
2. The effects of CABC and SRE function on power efficiency and display quality depend on
image data and the setting. Check display quality on the panel.
Rev.1.01 June 28, 2014 282

System Configuration
The LEDPWM signal connects to the LED driver IC. The LED driver IC is controlled entirely via the
RSP LCD driver.
Figure 48 System Configuration
Rev.1.01 June 28, 2014 283

Color Enhancement Function
Overview
The RSP LCD driver supports a color enhancement function, which enhances saturation by calculating
image data. This function enhances the saturation of the image displayed on the liquid crystal panel and
displays image with color enhanced.
 The function enhances color and makes pixel colors more vivid.
Saturation enhancement
Figure 49
 When the saturation enhancement coefficients of the input image are 1.0 or more, the display
image with color enhanced is generated.
M Y
Input image colors
Display image colors
B G
Figure 50
See the saturation diagram right above. The colors of the input image are enhanced. (The polygon
showing the colors of the input image is enlarged)
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 When the saturation enhancement coefficients of red, yellow, green, cyan, blue, and magenta are
set independently. Here the saturation enhancement coefficients of only red and yellow are set.
M Y
Enhanced colors
B G
Unenhanced colors C
Figure 51
See the saturation diagram right above. Green, cyan, blue, and magenta are not enhanced. The colors
mixed with red or yellow and the mixed colors of red and yellow are enhanced.
Rev.1.01 June 28, 2014 285

- The skin color independent adjustment function displays natural skin color.
Input image Output image: Output image:
No skin color adjustment areas are set. Skin color adjustment areas are set.
- To adjust the skin color after saturation enhancement, this function adjusts the skin hues independently from the
other hues.
Output image: Output image : Output image:

The hues have changed The hues remain unchanged. The hues have changed
from yellowish to reddish. from reddish to yellowish.
Rev.1.01 June 28, 2014 286

Sunlight Readability Enhancement Function

RSP's original Adaptive SRE processing can display readable image in various images under strong
ambient light environment by adjusting image brightness and contrast according to both ambient
light intensity and input image data.
Rev.1.01 June 28, 2014 287

Local Area Auto Contrast Optimze Function

RSP's original Local Area ACO can realize optical contrast compensation for every domain of
display image.
- Local Area ACO is a technology that changes the tone curve for each location.
- Local Area ACO realize beautifule image without losing gradation expression in dark area.
Conventional ACO was generated image on one tone curve in one frame. In this case, bright image can
be more bright, dark image can be darker. So contrast is high, but degradation of bright and dark
gradation occurs. On the other hands, Local Area ACO can change the curve for each location. So
degradation does not occur.
The RSP LCD driver can use Auto Contrast Optimization function and Content Adaptive Brightness
Control function at the same time.
Rev.1.01 June 28, 2014 288

Compression Data Transfer

The RSP LCD driver supports “RSP Compression Data Transfer” function.
The function can reduce the power consumption, EMI noise and space of a system by setting the
amount of data transfer from a host to 1/2 or 1/3.
Compression data transfer function is enabled, and compression rate can be selected by
COMPV_METHOD/COMPC_METHOD registers.
Features:
 Compression rate is selectable. (1/2 or 1/3)
 Both of Command mode and Video mode supported.
Video mode: 1/2 and 1/3 compression
Command mode: 1/3 compression
 The unit of compression is 4pixels x1(1/2), 4pixels x2(1/3).
When the transfer error occurs, the impact of the image changes is small.
Refer to the Application Note for details.
(1)Compression unit size
In 1/2 compression mode, 4pixels (Horizontal 4pixels x Vertical 1pixels) are packed into 1/2 size
compressed block.
Figure 52 Pixel map of 1/2 compression
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In 1/3 compression mode, 8pixels (Horizontal 4pixels x Vertical 2pixels) are packed into 1/3 size
compressed block.
Figure 53 Pixel map of 1/3 compression
(2)Long Packet mapping for compression data
RSP compression data transfer can use existing DSI packet structure. And it is possible to apply both of
Video mode and Command mode.
The following figure describes explanation of each element for compressed data transfer.
Figure 54 Long Packet structure
Rev.1.01 June 28, 2014 290

Figure 55 24bit/Pixel RGB color format(1/2 compression, Video mode)
Figure 56 24bit/Pixel RGB color format(1/3 compression, Video mode)
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Figure 57 24bit/Pixel RGB color format(1/3 compression, Command mode)
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(3)Memory access setting for compression data in Command mode
In setting of Set column address (0x2A) and Set page address (0x2B), please set the address of display
image in conventional way. RSP compression technology can realize Partial / Window update with
only little restrictions of memory access in 1/2 compression mode and 1/3 compression mode.
The restrictions of memory access show in following.
Figure 58 Restriction of memory access
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(4) Compression data transfer in Video mode
The 1/2 compression data is made only from a one-line pixel data, since 1/2 compression unit consists
of horizontal 4 pixels.
It is transferred in an every line period same as Non compression data. (The Non compression data is
transferred in an every line period.)
Figure 59 1/2 compression data transfer in Video mode
The 1/3 compression data is made only from 2-lines pixel data, since 1/3 compression unit consists of
horizontal 4 pixels x vertical 2 pixels.
It is divided into a Left half image data part and a Right half image data part, and they are transferred in
each of an even line period and an odd line period.
Figure 60 1/3 compression data transfer in Video mode
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(5)Data transfer rate
By using compression data transfer, LCM can reduce port number or data transfer rate. The relation of
data transfer rate, port number and compression mode is below. R63419 just support following
combination.
Table 68 Port number and data transfer rate
Compression mode Maximum port number Maximum transfer rate
No compression 4lane 2port 1Gbps/lane

1/2 compression 4lane 2port 500Mbps/lane
4lane 1port 1Gbps/lane
1/3 compression 4lane 2port 333Mbps/lane
4lane 1port 666Mbps/lane
(6)BP setting
By using compression data transfer, setting of BP is different from VBP at each compression rate.
Table 69 BP setting
Compression mode BP setting
No compression VBP = BP
1/2 compression VBP = BP – 1
1/3 compression VBP = BP - 2
Rev.1.01 June 28, 2014 295

Real Time Scaling
The RSP LCD driver supports real time scaling function.
The function can reduce the power consumption of a system by setting the amount of data transfer from
a host to 1/4.
Real time scaling function is enabled by the RTSON, the RTSRAM register.
This function has the following restrictions.
 ON/OFF switching of Real time scaling function is possible in Command mode only.
If change the state Realtime Scaling On to Off, It necessary to set to 20h the 1st parameter of F1h
 Data write must be performed before displaying in Command mode.
 Maximum DSI data transfer rate (tDSIR) of real time scaling is tDSIR/(2 x port number).
Ex) tDSIR=1Gbps
1port : 500Mbps, 2ports : 250Mbps at Command Mode or Video RAM Mode.
1port : 1000Mbps, 2ports : 500Mbps at Video Through Mode.
 In case of switching tDSIR, adjust DSITXDIV and DSI_THSSET.
 BP register needs to set even number. Please set (VS+VBP) to (BP register x 1/2).
 Real time scaling function cannot be used in combination with interlace mode.
 EP – SP > 4lines , and EP – SP = 4n (n=1,2,3,….)
 The odd line inversion cannot use in this mode. (Available mode: 2line, 4line,…. Column)
(1) Real Time Scaling Switching flow
Figure 61 Real Time Scaling Switching Flow
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(2) Real Time Scaling Operation diagram
Figure 62 Real Time Scaling Operation diagram
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(3) Display Interface switching Flow-1
Figure 63 Display Interface switching Flow-1
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R63419
Command Mode　⇔　Video Through Mode
◇Operation diagram【Real Time Scaling=OFF】
Rev.1.01 June 28, 2014

Operation
Chart data write
data write data write data write
TE
(4) Display Interface switching diagram-1
Scaling Mode OFF(RTSON=0, RTSRAM=0)

Display mode Command mode Video through mode Video capture mode Command mode
DM='h1 DM='h0
V2CRM=0 V2CRM=1
299
DSI data
DSI_Bit_Rate
taransfer rate Max. 1000Mbps
Overlap frame Overlap frame
Host to Driver
Compress 1/3 Capture
Frame Momory
Figure 64 Display Interface switching diagram-1A

Extract x3 Extract x3 Extract x3
Extract x3
Display
Specification
Figure 65 Display Interface switching diagram-1B
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(5) Display Interface switching Flow-2
Figure 66 Display Interface switching Flow-2
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(6) Display Interface switching diagram-2
Figure 67 Display Interface switching diagram-2A
Rev.1.01 June 28, 2014 302

Figure 68 Display Interface switching diagram-2B
Rev.1.01 June 28, 2014 303

(7) Real Time Scaling Mode Internal Vsync, Hsync Timing
Figure 69 Internal Vsync, Hsync Timing
Rev.1.01 June 28, 2014 304

(8) Realtime Scaling Video Through Mode Setting
Figure 70 Video Mode H-Timing at Realtime Scaling
Internal HSYNC is extended twice using RTN register at Realtime Scaling Mode.
Internal Data Transmission occurs each line(Internal_H1 and Internal_H2).
So, the following restrictions are needed in order to secure data transfer time.
 Internal_H1
(HS+HBP+Hadr+Hpls1) < (RTN – 4)
RTN ≧80RCLK
※Hpls1 = 57ByteClock (Internal Latency)
 Internal_H2
(HSYNC cycle – RTN) ≧ (Hadr/port * 2/4 + Hpls2)
(HSYNC cycle – RTN) ≧ 80RCLK
※Hpls2 = 44ByteClock (Internal Latency)
Table 69-2 Example of 60Hz display setting at Realtime Scaling and Video Through Mode.
Port HRE1 tDSIR HS+HBP Hadr HFP RTN fFRM
1600RGB 480Mbps 22 800 450 5Ah 60.37Hz
2port 1440RGB 440Mbps 20 720 418 5Ah 60.33Hz
1536RGB 464Mbps 21 768 438 5Ah 60.29Hz
1600RGB 884Mbps 40 1600 782 5Ah 60.34Hz
1port 1440RGB 804Mbps 36 1440 716 5Ah 60.38Hz
1536RGB 852Mbps 38 1536 756 5Ah 60.34Hz
It is possible to shorten HBP according to tDSIR. (tDSIR/1000 * HBP)
The above-mentioned table is calculated as VS+VBP=4 , Vadr = 1280, VFP=4.
Rev.1.01 June 28, 2014 305

Synchronization signal Output for touch panel controller

The RSP LCD driver can output the synchronization signals to capture touch sensing signal for touch
panel controller. To use these signals, touch panel controller can capture touch sensing signal while
avoiding display changing noise.
These signals are consist of vertical synchronization signal: VSOUT and horizontal synchronization
signal: HSOUT. The level of output voltage is IOVCC to GND. Each signal can adjust output timing
for internal synchronization signal. The high level width of VSOUT is 1 line, and the high level width
is adjustable.
Enable/disable of these signals is controlled by TPSYNEN register. VSOUT is outputted always, but
HSOUT is outputted during displaying only.
(1)VSOUT output Timing
VSOUT is outputted that internal VSYNC is starting point. VSOUT output timing can adjust by VSOD
register. Unit is 1H.
(2) HSOUT output Timing
HSOUT is outputted that internal source output timing is starting point. HSOUT output timing can
adjust by HSOD register. And HSOUT high level width can adjust by HSOHW register.
Display off Display on

Ref. Ref.
Ref. 1frame Ref. 1frame
FP BP FP BP
period period period period
Internal VSYNC
1H
Internal HSYNC
Source
SNTx
1H
VSOUT
VSOD=’h1
HSOD
HSOUT
HSOHW
1H
HSOD
HSOHW
Figure 71
Rev.1.01 June 28, 2014 306

State Transition Diagram (Display Mode)
(1)Definition of Display Modes
The state transition of the RSP LCD driver (display modes) compliant with MIPI DCS is as follows:
Figure 72
Notes: 1. A specified sequence is executed during each state transition. For details, see the description
of each sequence.
2. Do not transit to states not defined.
3. Turn on Peripheral Command Packet and Shutdown Peripheral Command Packet is
supported in only DSI Video mode.
Rev.1.01 June 28, 2014 307

Table 70 Operation Mode Transition Sequence

State
Sequence Command
From To
Power On sequence with

(1) - - Sleep mode on
HWRESET
(2-a) HWRESET (RESX=Low) - Sleep mode on
(2-b) HWRESET sequence (RESX= Low ->High) Deep stand by Sleep mode on
Sleep out
(3) exit_sleep_mode sequence 11h:exit_sleep_mode Sleep mode on
Display off
Sleep mode off Sleep mode off
(3-a) 11h:exit_sleep_mode
Display off/on Display off/on
Turn on Peripheral Command
DSI : Data Type=0x32
exit_sleep_mode+ display_on Sleep mode on Sleep mode off

(3-b) 11h:exit_sleep_mode
sequence Display on

(4) set_display_on sequence 29h:set_display_on
Display off Display on
(5) set_display_off sequence 28h:set_display_off
Display on Display off
Sleep mode off
(6) enter_sleep_mode sequence 10h:enter_sleep_mode Sleep mode on
Display off/on
Sleep out
(7) soft_reset sequence 01h:soft_reset Sleep mode on
Display off/on
(7-a) Sleep mode on Sleep mode on
Deep standby mode on

(8) B1h: DSTB Sleep mode on Deep standby on
sequence
Deep standby mode off
(9) (RESX= Low ->High) Deep standby on Sleep mode on
sequence
Turn on Peripheral Command Sleep mode off
(11) Turn on Sequence Sleep mode on
DSI : Data Type=0x32 Display on
Shutdown Peripheral
Sleep mode off
(12) Shutdown Sequence Command Sleep mode on
Display on
DSI : Data Type=0x22
Table 71 Display Mode Transition Sequence

State
Sequence Command
From To
12h:enter_partial_mode previous Display mode target Display mode

(10) Display mode sequence 13h:enter_normal_mode
(Normal/Partial/Idle) (Normal/Partial/Idle)
Rev.1.01 June 28, 2014 308

(2) Power/Display On/Off Sequence
A power/display on/off sequence is shown below.
Power off
Power on
Low = 1ms or more HW Reset

3ms w ait
NVM auto load Automatic User Command (A1h)
Sleep_mode on Manufacture Command
User Command setting XXh
Exit sleep mode 11h

3ms
Note : NVM auto load Automatic User Command (A1h)
VSYNC/HSYNC packet is
needed from immediately Manufacture Command
ater Exit_sleep_mode.
Note : Wait 6 frames Power/display on sequencer operation Automatic
Self diagnostic function D6 Automatic
Sleep_mode off
Set display on 29h
Note : Wait 1 frame(max.)
From start of next frame Display on
Set display off 28h

Note : Wait 1 frame(max.)
From start of next frame Display off
Enter sleep mode 10h

Note : Wait 3 frames(min.)
Power/display off sequencer operation Automatic
Sleep_mode on
Power off
Power off
Note on calculation example of w ait time :

If frame frequency is 60Hz, frame time is 16.6ms(1/60Hz). Secure w ait time described above.
Figure 73
Rev.1.01 June 28, 2014 309

(3) Deep Standby Mode On/Off Sequence
(1) Transit Deep Standby Mode
Sleep mode on This setting is enabled only in Sleep Mode.
Low power mode control Command B1h/1st parameter=01h(DSTB=1)

RESX=L can enter low power mode instead of RESX=L.
Deep standby mode
(2) Exit from Deep Standby Mode
Deep standby mode
HWRESET (RESX=Low)
Wait more than 1ms

HWRESET (RESX=High)
NVM auto load
Wait more than 3ms

Sleep mode on
Figure 74
Rev.1.01 June 28, 2014 310

Gamma Correction Function

The RSP LCD driver supports gamma correction function to make the optimal colors according to the
characteristics of the panel. The RSP LCD driver has registers for positive and negative polarities. The
RSP LCD driver supports digital gamma correction to allow different settings for R, G, and B dots.
Gamma Correction Circuit
The following figure shows a gamma correction circuit. Two ends of the 168-step ladder resistors for
positive grayscale are connected to VPLVL and VGS. Those for negative grayscale are connected to
VGS (GND) and VNLVL.
Vx0, Vx4, Vx8, Vx15, Vx31, Vx55, Vx79, Vx127.5 Vx176, Vx200, Vx224, Vx240, Vx247, Vx251,
and Vx255 are grayscale reference levels. The reference levels can be adjusted by register. Voltage
between VPLVL and VGS (GND), and voltage between VGS (GND) and VNLVL is divided by ladder
resistors. The divided voltage is selected by selectors, and then, grayscale reference levels are output.
For other grayscale levels, see “Grayscale Voltage Calculation Formula.” The amplifiers for the
selectors are divided into three kinds: ones for R dots, ones for G dots, and ones for B dots.
Note: Vx0 to Vx255 mean positive grayscale voltages VP0 to VP255 and negative grayscale voltages
VN0 to VN255
Rev.1.01 June 28, 2014 311

VPLVL
Grayscale reference
level for positive
AMP. polarity
VP0
Positive
polarity VP4
VP8
1R VP15
1R VP31
1R VP55
VP79
Selector
127R 128 to 1
VP127.5
VP176
168R
VP200
VP224
VP240
Selector
1R 127R 128 to 1
VP247
VP251
1R
VP255
VGS（GND）
Negative VN255
polarity
VN251
1R VN247
1R VN240
VN224
VN200
127R Selector VN176

128 to 1
VN127.5
168R VN79
VN55
VN31
VN15
1R Selector
VN8
128 to 1 VN4
1R 127R
VN0
1R
AMP. Grayscale reference
level for negative
polarity
VNLVL
Figure 75
Rev.1.01 June 28, 2014 312

Gamma Correction Registers
A table below shows grayscale reference levels to be adjusted. Each reference level is set by a 7-bit
gamma correction register that generates a grayscale reference level. Each of the gamma correction
registers for positive polarity and negative polarity consists of 7-bit registers (total: 105 bits).
Table 72
Gamma correction register
Grayscale reference level
Positive polarity Negative polarity
Vx0 VGMP0[6:0] VGMN0[6:0]
Vx15 VGMP3[6:0] VGMN3[6:0]
Vx31 VGMP4[6:0] VGMN4[6:0]
Vx55 VGMP5[6:0] VGMN5[6:0]
Vx79 VGMP6[6:0] VGMN6[6:0]
Vx127.5 VGMP7[6:0] VGMN7[6:0]
Vx176 VGMP8[6:0] VGMN8[6:0]
Vx200 VGMP9[6:0] VGMN9[6:0]
Vx224 VGMP10[6:0] VGMN10[6:0]
Vx240 VGMP11[6:0] VGMN11[6:0]
Vx247 VGMP12[6:0] VGMN12[6:0]
Vx251 VGMP13[6:0] VGMN13[6:0]
Vx255 VGMP14[6:0] VGMN14[6:0]
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Relationship between Gamma Correction Register and Voltage
Tables below shows relationships between values set in gamma correction registers and voltage.
Table 73
Register Value Voltage
VGMP0[6:0] 7’h00 V  (1-0/168)
VGMP1[6:0] 7’h01 V  (1-1/168)
VGMP2[6:0] 7’h02 V  (1-2/168)
VGMP3[6:0] 7’h03 V  (1-3/168)
VGMP4[6:0] 7’h04 V  (1-4/168)
VGMP5[6:0] 7’h05 V  (1-5/168)
VGMP6[6:0] 7’h06 V  (1-6/168)

VGMP7[6:0] : :
: :
VGMN0[6:0] : :
VGMN1[6:0] 7’h79 V  (1-121/168)
VGMN2[6:0] 7’h7A V  (1-122/168)
VGMN3[6:0] 7’h7B V  (1-123/168)
VGMN4[6:0] 7’h7C V  (1-124/168)
VGMN5[6:0] 7’h7D V  (1-125/168)
VGMN6[6:0] 7’h7E V  (1-126/168)
VGMN7[6:0]
7’h7F V  (1-127/168)
Note: ‘V’ indicates VPLVL-VGS (positive polarity) or VGS-VNLVL (negative polarity).
Table 74
Register Value Voltage
VGMP8[6:0] 7’h00 V (1- 41/168)
VGMP9[6:0] 7’h01 V  (1-42/168)
VGMP10[6:0] 7’h02 V  (1-43/168)
VGMP11[6:0] 7’h03 V  (1-44/168)
VGMP12[6:0] 7’h04 V  (1-45/168)
VGMP13[6:0] 7’h05 V  (1-46/168)

VGMP14[6:0] 7’h06 V  (1-47/168)
VGMN8[6:0] 7’h79 V  (1-162/168)

VGMN9[6:0] 7’h7A V  (1-163/168)
VGMN10[6:0] 7’h7B V  (1-164/168)
VGMN11[6:0] 7’h7C V  (1-165/168)
VGMN12[6:0] 7’h7D V (1- 166/168)
VGMN13[6:0] 7’h7E V  (1-167/168)
VGMN14[6:0] 7’h7F V  (1-168/168)
Note: ‘V’ indicates VPLVL-VGS (positive polarity) or VGS-VNLVL (negative polarity).
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Grayscale Voltage Calculation Formula
Table 75
Grayscale Grayscale
Calculation formula Calculation formula
voltage voltage
V0 See Table 72 – Table 74. V32 (V31*3+V35)/4
V1 (V0-V4)*18/26+V4 V33 (V31*2+V35*2)/4
V2 (V0-V4)*11/26+V4 V34 (V31+V35*3)/4
V3 (V0-V4)*5/26+V4 V35 (V31-V55)*13.5/16.5+V55
V5 (V4-V8)*10/14+V8 V37 (V35*2+V39*2)/4
V6 (V4-V8)*6/14+V8 V38 (V35+V39*3)/4
V7 (V4-V8)*3/14+V8 V39 (V31-V55)*10.5/16.5+V55
V9 (V8-V15)*13/16+V15 V41 (V39*2+V43*2)/4
V10 (V8-V15)*10/16+V15 V42 (V39+V43*3)/4
V11 (V8-V15)*8/16+V15 V43 (V31-V55)*7.5/16.5+V55
V12 (V8-V15)*6/16+V15 V44 (V43*3+V47)/4
V13 (V8-V15)*4/16+V15 V45 (V43*2+V47*2)/4
V14 (V8-V15)*2/16+V15 V46 (V43+V47*3)/4
V15 See Table 72 – Table 74. V47 (V31-V55)*5/16.5+V55
V16 (V15*3+V19)/4 V48 (V47*3+V51)/4
V17 (V15*2+V19*2)/4 V49 (V47*2+V51*2)/4
V18 (V15+V19*3)/4 V50 (V47+V51*3)/4
V19 (V15-V31)*12/17+V31 V51 (V31-V55)*2.5/16.5+V55
V20 (V19*3+V23)/4 V52 (V51*3+V55)/4
V21 (V19*2+V23*2)/4 V53 (V51*2+V55*2)/4
V22 (V19+V23*3)/4 V54 (V51+V55*3)/4
V23 (V15-V31)*7/17+V31 V55 See Table 72 – Table 74
V24 (V23*3+V27)/4 V56 (V55*3+V59)/4
V25 (V23*2+V27*2)/4 V57 (V55*2+V59*2)/4
V26 (V23+V27*3)/4 V58 (V55+V59*3)/4
V27 (V15-V31)*3/17+V31 V59 (V55-V79)*8.5/10.5+V79
V28 (V27*3+V31)/4 V60 (V59*3+V63)/4
V29 (V27*2+V31*2)/4 V61 (V59*2+V63*2)/4
V30 (V27+V31*3)/4 V62 (V59+V63*3)/4
V31 See Table 72 – Table 74. V63 (V55-V79)*6.5/10.5+V79
Rev.1.01 June 28, 2014 315

Table 76
Grayscale Grayscale
voltage voltage
V64 (V63*3+V67)/4 V96 (V95*3+V99)/4
V65 (V63*2+V67*2)/4 V97 (V95*2+V99*2)/4
V66 (V63+V67*3)/4 V98 (V95+V99*3)/4
V67 (V55-V79)*4.5/10.5+V79 V99 (V79-V127.5)*7.125/12.125+V127.5
V68 (V67*3+V71)/4 V100 (V99*3+V103)/4
V69 (V67*2+V71*2)/4 V101 (V99*2+V103*2)/4
V70 (V67+V71*3)/4 V102 (V99+V103*3)/4
V71 (V55-V79)*3/10.5+V79 V103 (V79-V127.5)*6.125/12.125+V127.5
V72 (V71*3+V75)/4 V104 (V103*3+V107)/4
V73 (V71*2+V75*2)/4 V105 (V103*2+V107*2)/4
V74 (V71+V75*3)/4 V106 (V103+V107*3)/4
V75 (V55-V79)*1.5/10.5+V79 V107 (V79-V127.5)*5.125/12.125+V127.5
V76 (V75*3+V79)/4 V108 (V107*3+V111)/4
V77 (V75*2+V79*2)/4 V109 (V107*2+V111*2)/4
V78 (V75+V79*3)/4 V110 (V107+V111*3)/4
V79 See Table 72 – Table 74. V111 (V79-V127.5)*4.125/12.125+V127.5
V80 (V79*3+V83)/4 V112 (V111*3+V115)/4
V81 (V79*2+V83*2)/4 V113 (V111*2+V115*2)/4
V82 (V79+V83*3)/4 V114 (V111+V115*3)/4
V83 (V79-V127.5)*11.125/12.125+V127.5 V115 (V79-V127.5)*3.125/12.125+V127.5
V84 (V83*3+V87)/4 V116 (V115*3+V119)/4
V85 (V83*2+V87*2)/4 V117 (V115*2+V119*2)/4
V86 (V83+V87*3)/4 V118 (V115+V119*3)/4
V87 (V79-V127.5)*10.125/12.125+V127.5 V119 (V79-V127.5)*2.125/12.125+V127.5
V88 (V87*3+V91)/4 V120 (V119*3+V123)/4
V89 (V87*2+V91*2)/4 V121 (V119*2+V123*2)/4
V90 (V87+V91*3)/4 V122 (V119+V123*3)/4
V91 (V79-V127.5)*9.125/12.125+V127.5 V123 (V79-V127.5)*1.125/12.125+V127.5
V92 (V91*3+V95)/4 V124 (V123*3+V127)/4
V93 (V91*2+V95*2)/4 V125 (V123*2+V127*2)/4
V94 (V91+V95*3)/4 V126 (V123+V127*3)/4
V95 (V79-V127.5)*8.125/12.125+V127.5 V127 (V79-V127.5)*0.125/12.125+V127.5
Rev.1.01 June 28, 2014 316

Table 77
Grayscale Grayscale
voltage voltage
V128 (V127.5-176)*12/12.125+V176 V160 (V127.5-176)*4/12.125+V176
V129 (V128*3+V132)/4 V161 (V160*3+V164)/4
V130 (V128*2+V132*2)/4 V162 (V160*2+V164*2)/4
V131 (V128+V132*3)/4 V163 (V160+V164*3)/4
V132 (V127.5-176)*11/12.125+V176 V164 (V127.5-176)*3/12.125+V176
V133 (V132*3+V136)/4 V165 (V164*3+V168)/4
V134 (V132*2+V136*2)/4 V166 (V164*2+V168*2)/4
V135 (V132+V136*3)/4 V167 (V164+V168*3)/4
V136 (V127.5-176)*10/12.125+V176 V168 (V127.5-176)*2/12.125+V176
V137 (V136*3+V140)/4 V169 (V168*3+V172)/4
V138 (V136*2+V140*2)/4 V170 (V168*2+V172*2)/4
V139 (V136+V140*3)/4 V171 (V168+V172*3)/4
V140 (V127.5-176)*9/12.125+V176 V172 (V127.5-176)*1/12.125+V176
V141 (V140*3+V144)/4 V173 (V172*3+V176)/4
V142 (V140*2+V144*2)/4 V174 (V172*2+V176*2)/4
V143 (V140+V144*3)/4 V175 (V172+V176*3)/4
V144 (V127.5-176)*8/12.125+V176 V176 See Table 72 – Table 74.
V145 (V144*3+V148)/4 V177 (V176*3+V180)/4
V146 (V144*2+V148*2)/4 V178 (V176*2+V180*2)/4
V147 (V144+V148*3)/4 V179 (V176+V180*3)/4
V148 (V127.5-176)*7/12.125+V176 V180 (V176-V200)*9/10.5+V200
V149 (V148*3+V152)/4 V181 (V180*3+V184)/4
V150 (V148*2+V152*2)/4 V182 (V180*2+V184*2)/4
V151 (V148+V152*3)/4 V183 (V180+V184*3)/4
V152 (V127.5-176)*6/12.125+V176 V184 (V176-V200)*7.5/10.5+V200
V153 (V152*3+V156)/4 V185 (V184*3+V188)/4
V154 (V152*2+V156*2)/4 V186 (V184*2+V188*2)/4
V155 (V152+V156*3)/4 V187 (V184+V188*3)/4
V156 (V127.5-176)*5/12.125+V176 V188 (V176-V200)*6/10.5+V200
V157 (V156*3+V160)/4 V189 (V188*3+V192)/4
V158 (V156*2+V160*2)/4 V190 (V188*2+V192*2)/4
V159 (V156+V160*3)/4 V191 (V188+V192*3)/4
Rev.1.01 June 28, 2014 317

Table 78
Grayscale Grayscale
voltage voltage
V192 (V176-V200)*4/10.5+V200 V224 See tables 114 and 115.
V193 (V192*3+V196)/4 V225 (V224*3+V228)/4
V194 (V192*2+V196*2)/4 V226 (V224*2+V228*2)/4
V195 (V192+V196*3)/4 V227 (V224+V228*3)/4
V196 (V176-V200)*2/10.5+V200 V228 (V224-V240)*14/17+V240
V197 (V197*3+V200)/4 V229 (V228*3+V232)/4
V198 (V197*2+V200*2)/4 V230 (V228*2+V232*2)/4
V199 (V197+V200*3)/4 V231 (V228+V232*3)/4
V200 See Table 72 – Table 74 V232 (V224-V240)*10/17+V240
V201 (V200*3+V204)/4 V233 (V232*3+V236)/4
V202 (V200*2+V204*2)/4 V234 (V232*2+V236*2)/4
V203 (V200+V204*3)/4 V235 (V232+V236*3)/4
V204 (V200-V224)*14/16.5+V200 V236 (V224-V240)*5/17+V240
V205 (V204*3+V208)/4 V237 (V236*3+V240)/4
V206 (V204*2+V208*2)/4 V238 (V236*2+V240*2)/4
V207 (V204+V208*3)/4 V239 (V236+V240*3)/4
V208 (V200-V224)*11.5/16.5+V200 V240 See Table 72 – Table 74.
V209 (V208*3+V212)/4 V241 (V240-V247)*14/16+V247
V210 (V208*2+V212*2)/4 V242 (V240-V247)*12/16+V247
V211 (V208+V212*3)/4 V243 (V240-V247)*10/16+V247
V212 (V200-V224)*9/16.5+V200 V244 (V240-V247)*8/16+V247
V213 (V212*3+V216)/4 V245 (V240-V247)*6/16+V247
V214 (V212*2+V216*2)/4 V246 (V240-V247)*3/16+V247
V215 (V212+V216*3)/4 V247 See Table 72 – Table 74.
V216 (V200-V224)*6/16.5+V200 V248 (V247-V251)*11/14+V251
V217 (V216*3+V220)/4 V249 (V247-V251)*8/14+V251
V218 (V216*2+V220*2)/4 V250 (V247-V251)*4/14+V251
V220 (V200-V224)*3/16.5+V200 V252 (V251-V255)*21/26+V255
V221 (V220*3+V224)/4 V253 (V251-V255)*15/26+V255
V222 (V220*2+V224*2)/4 V254 (V251-V255)*8/26+V255
Rev.1.01 June 28, 2014 318

Gamma Correction Register Setting Example
V55P
V127.5P
V200P
V200N
V127.5N
V55N
Figure 76
Notes: 1. Vx0, Vx4, Vx8, Vx15, Vx31, Vx55, Vx79, Vx127.5, Vx176, Vx200, Vx224, Vx240, Vx247,
Vx251, Vx255 are “reference levels” set by gamma correction registers.
2. Set gamma correction registers to satisfy the following relationship: |Vx0| > |Vx4| > |Vx8| >
|Vx15| > |Vx31| > |Vx55| > |Vx79| >|Vx127.5|> |Vx176| > |Vx200| > |Vx224| > |Vx240| >
|Vx247| > |Vx251| > |Vx255|
3. Set gamma correction registers to satisfy the following relationship: V255P  0.2V. V255N 
-0.2V.
Rev.1.01 June 28, 2014 319

Relationship between Display Data and Grayscale Voltage
Table 79 (REV bit function)

REV = 1 REV = 0
Display Data Positive polarity Negative Polarity Positive Polarity Negative Polarity
(PRxPxx) (PRxNxx) (PRxPxx) (PRxNxx)
8’h00 V0 V0 V255 V255

8’h01 V1 V1 V254 V254
8’h02 V2 V2 V253 V253
8’h03 V3 V3 V252 V252
8’h04 V4 V4 V251 V251
8’h05 V5 V5 V250 V250
8’h06 V6 V6 V249 V249
8’h07 V7 V7 V248 V248
8’h08 V8 V8 V247 V247
8’h09 V9 V9 V246 V246
8’h0A V10 V10 V245 V245
8’h0B V11 V11 V244 V244
8’h0C V12 V12 V243 V243
8’h0D V13 V13 V242 V242
8’h0E V14 V14 V241 V241
8’h0F V15 V15 V240 V240
: : : : :
8’hF0 V240 V240 V15 V15
8’hF1 V241 V241 V14 V14
8’hF2 V242 V242 V13 V13
8’hF3 V243 V243 V12 V12
8’hF4 V244 V244 V11 V11
8’hF5 V245 V245 V10 V10
8’hF6 V246 V246 V9 V9
8’hF7 V247 V247 V8 V8
8’hF8 V248 V248 V7 V7
8’hF9 V249 V249 V6 V6
8’hFA V250 V250 V5 V5
8’hFB V251 V251 V4 V4
8’hFC V252 V252 V3 V3
8’hFD V253 V253 V2 V2
8’hFE V254 V254 V1 V1
8’hFF V255 V255 V0 V0
Rev.1.01 June 28, 2014 320

NVM Control
The RSP LCD driver incorporates NVM.
 16 bits are for Supplier ID (read by read_DDB_start command (A1h))
 16 bits are for Supplier Elective Data (read by read_DDB_start command (A1h))
 Manufacturer Command is stored (For the Manufacturer Command stored in NVM, see
“Command Stored in NVM”)
To write, read and erase data from/to the NVM, follow the sequence below. Data on the NVM is
loaded to internal registers automatically when the sequences are performed. NVMLD register
determines whether to update data loaded from NVM to each register.
Power On sequence
HW RESET sequence
exit_sleep_mode command
soft_reset sequence
Deep Standby Mode Off sequence
Data stored in the NVM is retained permanently even if power supply is turned off.
Table 80
Operation Power supply voltage Time Temperature
VSP 5.00 ~ 6.00V
Write/Erase
VSN -5.00 ~ -6.00V 1.7s or more
(External VSP/VSN +10C ~ +40C
DPHYVCC 1.65 ~ 1.95V after NVMFTT = 1
supply)
IOVCC 1.65~ 1.95V
Note: NVM data rewrite (erase-write) operation should be performed up to 40 times per address.
VGHP/VGLP (power supply for panel) and SOUT are GND during NVM data rewrite
operation.
Rev.1.01 June 28, 2014 321

NVM Write Sequence
The register values of User/Manufacturer Commands supposed to be stored in NVM are written to
NVM. When “1” is written to an address, the bit of the address is set to “1”. If the data is erased from
the bit, the bit is returned to ”0”. The bit to which data is not written should be set to “0”.
Note4
Power supply on
VSP,VSN NVM Load Control
IOVCC, DHPYVCC Read Verify Status
Command：D6h
Command: E6h
1st Parameter: 01h NVMVFFLGER
GND 0 : Fail (Note1) 1 : Pass
Exit Sleep mode
NVMVFFLGWR
Command：11h
0 : Fail 1 : Pass
Wait for
TE Output Status (TEM=1)
more than 120ms
The result of verification is outputted from
TE output.
Power on reset VCOM NVM Write Data Set TE = 1 : Pass
(Hard ware reset) Command: D5h TE = 0 : Fail
WCVDC=1, WCVDCB=1
Set_Display_On
Wait for
Command 29h
more than 3ms
Adjust VDC & VDCB value
Sleep in State NVM Access Protect On
Manufacture Command Access Disable Set_Display_Off Command: E6h
(Protect ON) Command 28h NVMAEN=0
NVM Access Disable NVMFTT=0
(Protect ON) Enter Sleep mode TEM=0
Command：10h
Manufacturer Command Access
Protect off Wait more
MCAP=3’b100 than 120ms
NVM Load Control Wait for

Command: D6h more than 120ms
1st Parameter: 81h
DDB data Set Power supply off
Command: E7h
WCDDB=1 VSP, VSN
NVM Load Control
Command: E8h IOVCC, DPHYVCC
Set Parameter: ID1~ID4
Set Parameter: NVMLD
RDID data Set Set Verify output from TE output GND

Command: E7h
WCRDID=1, set_tear_on
Command: 35h
Set Parameter: RDID1~RDID3 1st Parameter: 01h
NVM Write Data Set (initial Setting) NVM Access Protect Off
Verify output Setting and Write Start
Manufacturer Command Command: E6h
NVMAEN=1
NVMFTT=1
TEM=1
Write & Verify operation
Erase & Verify Operation

Before data is written to NVM, the data
stored in the specified address is
automatically erased, an verify
operation is performed.
Write & Verify Operation

After data has been written to NVM, verify
operation is automatically performed.
Wait more than 1.0s
Figure 77
Rev.1.01 June 28, 2014 322

Abnormal Sequence
When the externally applied voltage level drops or the low level of RESX is detected during Sleep
mode off, executes the abnormal sequence and enters Sleep mode on.
・Drop in external input voltage level

When the externally applied voltage is VSP, its voltage level is detected.
The detection level is set by the VBTS register.
・Transition of internally generated voltage

The abnormal sequence is over in about 10 ms.
IOVCC should be 1.65 V or more for 10 ms (during the abnormal sequence).
Abnormal Shutdown sequence

Reset sequence Reset
Display(Normal/Partial/Idle)
during display operation Sequence
1F 2F ・・ (n-1)F nF
Interface
RESX=Low during Display Operation.
RESX
DSP
Internal clock
OSC
Power Supply
IOVCC GND
DPHYVCC GND
VSP GND
VSN GND
(internal detection signal)
Output Voltage
VCI GND
VDD GND
VGH GND
GND
VGL
VCL GND
VPLVL GND
VNLVL GND
GND
VCOMDC
VCOM
* See Appendix for the operation of SOUT.
Notes: 1. If verify operation to verify whether data is erased fails before write operation, write operation is not performed.
2. If power is turned on when data has not been written, data set to “0” is loaded from NVM.
Set the defaults of all the commands at “Initial Setting” after power is turned on. Then, write the data to NVM.
3. To change the number of lanes when data is written to NVM via DSI, execute this sequence after changing the number
of lanes.
4. When VCOM is not adjusted by VDC, this sequence is unnecessary.
Rev.1.01 June 28, 2014 323

Revision Record
Rev. Date Page No Contents of Modification
0.00 2013/08/28 ALL First issue
0.01 2013/10/24 10 Error correction : GVDD-VSS, AGND-VGL -> VGH-AGND, AGND-VGL

11 Error correction of SOUT level : GVDD-GVSS -> VGH-VGL
Error correction : remove GVDD/GVSS
12 Add restriction about EC/SC setting in case of using 2port
14,20,27,28, Error correction : remove GVDD/GVSS
29,32
27 Change serial number : external elements
15 Specification change : remove SELDL, 4lane support only
40 Error correction : remove DC4, change IDST4 condition 6V/-6V -> 5.6V/-5.6V
and revise VC2/3, VLM2/3, DC2/3 setting
40,276 Error correction : fFLM -> fFRM
43 Error correction : remove GVDD/GVSS, VLM1
46 Error correction : remove note.3
48 Error correction : TLPTX2 1 / ( fosc / 2 ) -=> 1 / ( fosc / 4 )
55,56 Change specification : number of parameter of each command
56,61,239, Change specification : Swap register compression method and test register
240
D3h <->Eah, D4h <->Ebh
71-73 Add restriction: If using compression data transfer, this command does not support.
95 Error correction : SC=8n, EC=8m-1 EC-SC≧16pixels
97 Error correction : 1st para/DB3 0->SP[11]
105 Error correction : Description of D1, D0
108 Add description for RCLK
149 Add specification : ENC
150 Change specification : delete SELDL (R63419 is 4lane support only)
154, 276 Change description related OSC frequency
156-161 Change specification : register name and assign for CABC,SRE
17 Add specification : UDS
171 Add specification ABSI=’h2, and change description of explanation of ABSI
172 Error correction : LININVA -> LINEINV
177 Add specification : FP2
178,263,292 Add description of BP setting if using compression data transfer.
182 Error correction : GVDD/GVSS -> VGH/VGL
187 Add specification : RTN2
201 Error correction : GVDD(VGH) -> VGH
202 Error correction : GVSS(VGL) -> VGL
206 Error correction : remove SVDD, and revise restriction
207 Error correction : remove SVSS< and revise restriction
211 Change specification : remove GVDDDRCT, GVSSDRCT
234 Add register : NVMEWCNT (NVM E/W time counter)
276 Add description for Idle mode
Rev.1.01 June 28, 2014 324

277 Error correction : Frame rate calculation example based on fOSC=65MHz

315 Error correction : add Vx127.5 between Vx79 and Vx176
318 Specification change : wait time for NVM write 1.7s -> 1.0S
0.02 2013/12/03 11,14,27, Specification change : add VGHP/VGLP
28,29,32
20 Specification change : add VGHP/VGLP
 VGH\VGL : SOUT level, VGHP/VGLP : Panel power supply
49 Specification change : Note.3 256UI -> 512UI because of using USASPC
50,68,69 Specification change : Number of parameter 16->15
88 Add description about stopping LEDPWM and RGB switch signal except display area.
97, 106 Add specification ;
D7/D0 and D6/D1 flips all display area regardless any window address setting.
141,142 Specification change: IDLE_PWM_EN become ‘1’ if entering idle_mode.
IDLE_MODE_BL_EN not supported
165 Error correction : SOUTTR*/SOUTTF* assignment
180,181 Error correction : delete EQW1,2
181 Error correction : Add description of DIV
227,228 Error correction : Deh -> E5h
233 Specification change : revise NVMLD assignment
293 Error correction : max tDSIR 250Mbps -> tDSIR/(2 x port number)
Add restriction : cannot use odd line inversion
318 Change description about
319 Error correction : revise NVM control command assignment
0.03 2013/12/27 9 Error correction : delete “outline shaping function”
Delete description about DBI and I2C
11 Error correction : move Table.3 from P12 to P11
12 Revise specification: EC/SC value updated.

35-37 Error correction: B1 or B6(36h) →B6(36h)
43,277 Change specification : fOSC 65MHz(typ) -> 56MHz(typ)
69 Error correction : 39h exit_idle_mode -> enter_idle_mode

74 Error correction : add IDMON
95 Change description : EC-SC refer “Restriction in Using R63419”
118 Add description : Local Area ACO on/off register

134 Error correction : delete IFID because of not support I2C
147 Error correction : delete IFIDEN because of not supporting I2C
176 Add restriction : NL : need wait time between data transfer and NL
180 Error correction ; delete EQW1, EQW2
181 Erro correction EQW3,6,8,9 -> EQW3,6,8,16 EQW5,7,9,16 -> EQW5,7,9,17
196 Add description SOUTABSPLx, SOUTABSPLEN
281 Add description : Can use CABC and ACO at same time
287 Add description of Local Area ACO
0.04 2014/01/31 11 Error correction : DPHYVCC voltage range
Rev.1.01 June 28, 2014 325

1.65-3.30V -> 1.65-1.95V

14,25 Error correction : SCL -> WRX/SCL
22 Add specification : PN2PTX
1 = 1 port mode, 0 = 2 port mode
29 Error correction : remove VCOMDC, add range of VCOM
32 Error correction : SOUT level GND -> VSN

39 Error correction :
IOVCC=1.80V, VCI=2.80V → IOVCC=1.80V, Ta= 25℃
40 Change specification to Icin4/5 measurement condition
Add VPL/VNL
Change VC3 : 4’hD→4’hA
Error correction of Idstb5 measurement condition : add Ta= 25℃
43 Specification change : test condition and spec of VGH/VGL

VC3 : 4’h3→4’h0
add APAP=APAN=3’h3
VGH(typ) : 7.85V→7.7V,
VGL(typ/max) : -7.35V/-7.1V→-7.7V/-7.6V
45 Add specification : add APAP/APAN to tDDS measurement condition
46,47,48 Error correction : IOVCC, DPHYVCC voltage range
1.65-3.30V -> 1.65-1.95V
52 Error correction: 0Bh,36h Bit 7/6/3 →Bit7/6/4/3/0

54, 59 Error correction: delete F5h/F6h command
62 Error correction: number of 04h parameter total 16 -> 15
65 Error correction: number of A1h parameter total 16 -> 15
76,77 Error correction: add description for B4, B0.
91 Error correction : set_all_pixels_off -> set_all_pixels_on
99 Error correction : delete following sentence
After pixel data 1 is stored in frame memory at (SC, SP), address counter’s direction
differs depending on Bits 6, 7 of set_address_mode (36h). See “Host Processor to
Memory Write/Read Direction”.
100 Error correction : Add SR[11], ER[11]
104-106 Error correction: delete description of B1

110 Error correction : Add D[2:0]
120 Error correction ; Add LOCAL_ON
134,135 Error correction: number of A1h parameter total 16 -> 15

143 Error correction: delete F5h/F6h command
179 Error correction : delete SNT3*
194 Add description : CE on/off control (CE_ON, PPEN2)

202 Error correction : GVDD(VGH) -> VGH
203 Error correction : GVSS(VGL) -> VGL
209 Specification change : APA*/50% -> setting inihibit

Add description in case of changing APN* register setting
218-221 Error correction : VDC -> VDCB
Rev.1.01 June 28, 2014 326

0.1 2014.04.19 9 Add description of Direct data input mode

Video mode -> Video through mode
10 Add description : Note3 for Direct data input mode
20 Add description : VGHP/VGLP connet to LCD panel and stabilizing capacitor
25 Error correction :VDDTEST,VREFC GND -> Open or GND
29 Error correction : delete “Regulator (0.2V step)” for VGH
Add descripotion : (VSP – VCI2) ≧ 0.2V(VSP – VCI3) ≧ 0.2V
32 Error correction : VPLVL/VNLVL level GND -> HiZ
32 Specification change : SOUTn , VGLP = VSN -> GND
39 Error correction : Iopn test condition DM[2:0]=3’h1, -> 3’h0
39 Add value to IOPN(max), IDST(max)

40 Error correction : VPN/VNL setting to tDDS test condition 25h->2Bh
40 Add value to IDST4(max), IDST5(min)
43 Add description : VSP/VSN voltage to VGH/VGL test condition

45 Add description : VSP/VSN voltage to tDDS test condition
Error correction : VPN/VNL setting to tDDS test condition 25h->2Bh
68,69 Error correction : delete description of IFID
78 Error correction : DB[2:0] 000->111
91 Error correction : set_all_pixels_on -> set_all_pixels_off
134,135,320 Error correction : delete description of IFID
144 Add restriction : not support DSTB command in case of BFh/5th para = 00h
194 Error correction : CE on/off setting Disable <-> Enable
202 Add specification :
Recommended voltage: (voltage set by BT2) – (voltage set by VLM2) ≦ 2V
203 Add specification :

Recommended voltage: (voltage set by BT3) － (voltage set by VLM3) ≧ -2V
210 Specification change of VBTS value 00h:3.01->4.74, 01h:3.49->5.10
223 Specification change : D7h/1st initial value 82h->Fah
227 Error correction : add description of TP[11] 2Pixel V-Stripe

228 Error correction : “Case of TIGON(Command Deh 1st parameter” : Deh→E5h
228,229 Error correction : Command B3h/1st=04h (DM=0h) → 00h（DM=0h）
247 Error correction: Delete “CS x6” because CSX is test pin.
260 Error correction : A1h’s write type 15h, 39h= yes (because of using this command to
write data and read data)
306 Error correction : CS x6 -> (RESX= Low ->High)

308 Change description : Enter DSTB DSTB command -> RESX=L
Error correction : Exit DSTB CS x6 -> RESX= Low->High
0.2 2014.06.03 37 Error correction : rigih side figure Top -> Bottom
39,40,41 Specification change : remove “TBD”
40 Add specification : Icin4/5 1600RGB(HRE1=3’h0)
Rev.1.01 June 28, 2014 327

43 Add specification : VGH VLM2=14h, VGL VLM3=14h

78 Error correction
Bits D[2:1] – DBI Pixel Format (Control Interface and DSI Command Mode
ColorFormat Selection)
152 Error correction : ‘b11 fTXCLK: 20.83->15.63, Bit rate : 10.42->7.81
163 Error correction: remove description ALMID4, because this register is for RSP
test use.
227 Error correction : TIP[10:0] -> TIP[15:0]
228,229 Add specification “ In case of Bport master, set C1h/3rd parameter = 0xC0.”
239 Error correction : COMPC_METHOD 1/2 compression not supported
243 Add description : F1h register for Realtime scaling

281 Error correction : checking voltage VSP->VPLVL
296 Change specification : Restriction for Real time scaling
298 Change specification : Transfer rate for Video mode

305 Add description of Real time scaling Video through mode setting
1.0 2014.06.11 296 Error correction : even line -> odd line
1.01 2014.06.28 141 Error correction : D5 reserved.
195 Error correction : CBh/13para =C0h->E0h
226 Asdd description : Setting of PNSLV=1
234 Error correction : E8h 00h,00h -> 28h,01h

238 Add description about COMP_ENTRY_NUM
Rev.1.01 June 28, 2014 328

Rev.1.01 June 28, 2014 329

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Specification

Power Supply Specification ................................................................................ 11

Term Definition .................................................................................................. 12

Restriction in using R63419................................................................................ 12

Block Diagram .................................................................................................... 14

Block Function .................................................................................................... 15

Pin Function ........................................................................................................ 18

Alignment Mark .................................................................................................. 26

Power Supply Generating Circuit ....................................................................... 27

Specifications of External Elements Connected to the Power Supply Circuit ... 28

Voltage Setting Pattern Diagram ........................................................................ 29

Rev.1.01 June 28, 2014 1

System Configuration for Dual MIPI-DSI Ports ................................................ 33

Absolute Maximum Rating ................................................................................. 38

Electrical Characteristics .................................................................................... 39

Command List ..................................................................................................... 52

Command Accessibility ...................................................................................... 57

Default Modes and Values .................................................................................. 62

User Command ................................................................................................... 66

Rev.1.01 June 28, 2014 2

set_tear_off: 34h........................................................................................................................................................ 102

Manufacturer Command ..................................................................................... 143

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・Interface ID setting : B4h ...................................................................................................................................... 149

Rev.1.01 June 28, 2014 4

DIV ..................................................................................................................................................................... 180

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・Test Register : D9h ................................................................................................................................................ 225

System Interface Configuration (MIPI DSI)....................................................... 244

Rev.1.01 June 28, 2014 6

2) Long Packet (LPa) Structure ........................................................................................................................... 253

Display Mode ...................................................................................................... 272

Frame Memory.................................................................................................... 276

Reference Clock Generating Function ................................................................ 278

Output Waveform Mode of Panel Control Signals ............................................. 278

Frame Frequency Adjustment Function.............................................................. 279

TE Pin Output Signal .......................................................................................... 280

Self-Diagnostic Function .................................................................................... 281

Content Adaptive Brightness Control (Dynamic Backlight Control Function) .. 282

Color Enhancement Function ............................................................................. 284

Sunlight Readability Enhancement Function ...................................................... 287

Local Area Auto Contrast Optimze Function ..................................................... 288

Compression Data Transfer ................................................................................ 289

Rev.1.01 June 28, 2014 7

(2)Long Packet mapping for compression data ......................................................................................................... 290

Real Time Scaling ............................................................................................... 296

Synchronization signal Output for touch panel controller .................................. 306

State Transition Diagram (Display Mode) .......................................................... 307

Gamma Correction Function............................................................................... 311

NVM Control ...................................................................................................... 321

Abnormal Sequence ............................................................................................ 323

Revision Record .................................................................................................. 324

Rev.1.01 June 28, 2014 8

*MIPI: Mobile Industry Processor Interface, *DSI: Display Serial Interface

 Real time scaling function

Rev.1.01 June 28, 2014 9

 Internal liquid crystal drive power supply circuit

MIPI: Mobile Industry Processor Interface, DSI: Display Serial Interface