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Strong Fet™ Irfb7446Pbf: Application V 40V R Typ. 2.6M Max 3.3M I 123A I 120A
Strong Fet™ Irfb7446Pbf: Application V 40V R Typ. 2.6M Max 3.3M I 123A I 120A
IRFB7446PbF
Application HEXFET® Power MOSFET
Brushed Motor drive applications
VDSS 40V
BLDC Motor drive applications D
Benefits S
Improved Gate, Avalanche and Dynamic dV/dt Ruggedness G
D
Fully Characterized Capacitance and Avalanche SOA
TO-220AB
Enhanced body diode dV/dt and dI/dt Capability
IRFB7446PbF
Lead-Free*
RoHS Compliant, Halogen-Free*
G D S
Gate Drain Source
Base part number Package Type Standard Pack Orderable Part Number
Form Quantity
IRFB7446PbF TO-220 Tube 50 IRFB7446PbF
8
RDS(on), Drain-to -Source On Resistance (m )
125
ID = 70A
6 100
ID, Drain Current (A)
T J = 125°C
75
4
50
2
T J = 25°C 25
0
0
2 4 6 8 10 12 14 16 18 20
25 50 75 100 125 150 175
VGS, Gate -to -Source Voltage (V) TC , Case Temperature (°C)
Fig 1. Typical On-Resistance vs. Gate Voltage Fig 2. Maximum Drain Current vs. Case Temperature
Notes:
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 120A. Note that current
limitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.046mH,RG = 50, IAS = 70A, VGS =10V.
ISD 70A, di/dt 1174A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400µs; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
R is measured at TJ approximately 90°C.
This value determined from sample failure population, starting TJ = 25°C, L= 1mH, RG = 50, IAS = 22A, VGS =10V.
* Halogen -Free since April 30, 2014
10
4.5V
10
1 4.5V
T J = 175°C
100 1.8
(Normalized)
10 1.4
T J = 25°C
1 1.0
VDS = 10V
60µs PULSE WIDTH
0.1 0.6
2 4 6 8 10
-60 -20 20 60 100 140 180
VGS, Gate-to-Source Voltage (V) T J , Junction Temperature (°C)
VDS = 32V
Coss = Cds + Cgd
10.0 VDS = 20V
C, Capacitance (pF)
10000
8.0
Ciss
6.0
Coss
1000
Crss 4.0
2.0
100 0.0
0.1 1 10 100 0 10 20 30 40 50 60 70 80
VDS , Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)
T J = 175°C
100
100µsec
100
T J = 25°C 1msec
10 DC
Package Limited
10
10msec
1
1 Tc = 25°C
Tj = 175°C
VGS = 0V Single Pulse
0.1 0.1
0.0 0.5 1.0 1.5 2.0 0.1 1 10 100
VSD, Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V)
Fig 9. Typical Source-Drain Diode Forward Voltage Fig 10. Maximum Safe Operating Area
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
50 0.6
Id = 5.0mA VDS = 0V to 32V
49
0.5
48
47 0.4
Energy (µJ)
46
45 0.3
44
0.2
43
42
0.1
41
40 0.0
-60 -20 20 60 100 140 180 0 5 10 15 20 25 30 35 40 45
T J , Temperature ( °C ) VDS, Drain-to-Source Voltage (V)
Fig 11. Drain-to-Source Breakdown Voltage Fig 12. Typical Coss Stored Energy
20.0
RDS(on), Drain-to -Source On Resistance ( m)
VGS = 5.5V
VGS = 6.0V
15.0 VGS = 7.0V
VGS = 8.0V
VGS = 10V
10.0
5.0
0.0
0 100 200 300 400 500
ID, Drain Current (A)
1000
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C.
0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
5 V R = 34V
3.5 TJ = 25°C
TJ = 125°C
4
IRRM (A)
2.5 3
ID = 100µA
ID = 250µA 2
1.5 ID = 1.0mA
ID = 1.0A
1
0.5 0
-75 -25 25 75 125 175 225 0 200 400 600 800 1000
T J , Temperature ( °C ) diF /dt (A/µs)
Fig 17. Threshold Voltage vs. Temperature Fig 18. Typical Recovery Current vs. dif/dt
5 70
IF = 70A IF = 46A
V R = 34V 60 V R = 34V
4
TJ = 25°C TJ = 25°C
TJ = 125°C 50 TJ = 125°C
3
QRR (nC)
IRRM (A)
40
30
2
20
1
10
0 0
0 200 400 600 800 1000 0 200 400 600 800 1000
diF /dt (A/µs) diF /dt (A/µs)
Fig 19. Typical Recovery Current vs. dif/dt Fig 20. Typical Stored Charge vs. dif/dt
60
IF = 70A
50 V R = 34V
TJ = 25°C
TJ = 125°C
40
QRR (nC)
30
20
10
0
0 200 400 600 800 1000
diF /dt (A/µs)
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
15V
tp
L DRIVER
VDS
RG D.U.T +
V
- DD
IAS A
20V
tp 0.01 I AS
Fig 23a. Unclamped Inductive Test Circuit Fig 23b. Unclamped Inductive Waveforms
Fig 24a. Switching Time Test Circuit Fig 24b. Switching Time Waveforms
Id
Vds
Vgs
VDD
Vgs(th)
Fig 25a. Gate Charge Test Circuit Fig 25b. Gate Charge Waveform
EXAM PLE: T H IS IS A N IR F 1 0 1 0
LO T C O D E 1789 IN T E R N A T IO N A L PART NUM BER
ASSEM BLED O N W W 19, 2000 R E C T IF IE R
IN T H E A S S E M B L Y L IN E "C " LO G O
D ATE C O D E
YEA R 0 = 2000
N o t e : "P " in a s s e m b ly lin e p o s it io n ASSEM BLY
in d ic a t e s "L e a d - F r e e " LO T C O D E W EEK 19
L IN E C
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Qualification Information†
Industrial
Qualification Level (per JEDEC JESD47F) ††
Revision History
Date Comment
9/11/2012 Added Package limit and updated Fig2 & Fig10 on page 1, 2 & page 5.