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Clase 12 - Adc
Clase 12 - Adc
Clase 12 - Adc
UNIVERSIDAD
MANUELA BELTRÁN
Analog to Digital
Converter
Motivation
The ADC converts an analog signal into a digital number, so that the
microcontroller can interpret the information.
*http://www.electronicwings.com/pic/pic18f4550-adc
What is an ADC?
𝐶𝑃𝑈
Optional but
it is useful
Basics of A/D Conversion
Nyquist Theorem
for a given sample rate fs, perfect reconstruction of the sampled
signal is guaranteed possible for a signal bandlimit B < fs/2.
Basics of A/D Conversion
Nyquist Theorem
for a given sample rate fs,
perfect reconstruction of the
sampled signal is
guaranteed possible for a
signal bandlimit B < fs/2.
Basics of A/D Conversion
Ideal ADC
- Digital code increases Linearly with input voltage
- Needs infinite quantized levels (bits) to encode the infinite possible voltages
- Unachievable and impractical
0V 5V
There are infinite numbers in between
Basics of A/D Conversion
Real Practical ADC
The real practical A/D converter has a transfer function with a uniform
staircase formation
A/D Module
A/D Module
An ADC compares the analog input voltage with fractions of a
voltage reference (𝑽𝑹𝑬𝑭 = 𝑽𝑹𝑬𝑭+ − 𝑽𝑹𝑬𝑭− )
𝑽𝒎𝒂𝒙
𝑽𝒎𝒊𝒏
𝑽𝑹𝑬𝑭
A/D Module – Basic Definitions
Voltage Range=𝑽𝑹𝑬𝑭+ − 𝑽𝑹𝑬𝑭−
The voltage range is divided
into 2𝑛 levels. The size of
𝑽𝑹𝑬𝑭
the level is given by: 𝒏
𝟐
𝑽𝑹𝑬𝑭 𝑽𝑹𝑬𝑭+ − 𝑽𝑹𝑬𝑭−
𝑸 = 𝟏 𝑳𝑺𝑩 = 𝒏 =
𝟐 𝟐𝒏
Quantization
Level 1 LSB corresponds to the
minimum voltage change
the system can convert
𝑽𝑭𝑺
Full Scale Voltage: sets
digital output at max level
𝑽𝑭𝑺 = 𝑽𝑹𝑬𝑭 − 𝟏𝑳𝑺𝑩
A/D Module – Basic Definitions
𝑉𝑅𝐸𝐹 = 4𝑉
𝑛=3
4𝑉
𝐿𝑆𝐵 = 3 = 0.5 𝑉
2
A/D Module – Basic Definitions
ADC RESOLUTION
The Resolution of an A/D converter is the number
of output bits it has (3 bits, in this example).
𝑽𝑹𝑬𝑭
𝑸 = 𝟏 𝑳𝑺𝑩 = 𝒏
𝟐
ADC RESOLUTION
The more bits the output word has, the better the resolution!!.
ADC RESOLUTION
The value of an LSB depends upon the ADC Reference Voltage and Resolution
𝑽𝑹𝑬𝑭
𝑸 = 𝟏 𝑳𝑺𝑩 = 𝒏
𝟐
A/D Module – Basic Definitions
Solution:
Voltage Range=200x0.5=100 mV
𝟏𝟎𝟎
With n bits, this voltage will be divided into mV steps.
𝟐𝒏
𝟏𝟎𝟎𝒎𝑽
𝟎. 𝟐𝟓𝒎𝑽 = → 𝒏 = 𝟖. 𝟔 thus 9 bit word length is required
𝟐𝒏
ADC RESOLUTION IMPROVEMENT
Better resolution (accuracy) can be realized if we did either (or both) of two
things:
The problem with higher resolution (more bits) is the cost. Also, the smaller
LSB means it is difficult to find a really small signal as it becomes lost in the
noise.
The problem with reducing the reference voltage is a loss of input dynamic
range.
Quantization Error
𝑽𝑹𝑬𝑭 𝟐𝒏 − 𝟏
𝑽𝑭𝑺 = 𝑽𝑹𝑬𝑭 − 𝟏𝑳𝑺𝑩 𝑽𝑭𝑺 = 𝑽𝑹𝑬𝑭 − 𝒏 = 𝑽𝑹𝑬𝑭 = 𝑽𝑭𝑺
𝟐 𝟐𝒏
(𝑉𝑖𝑛 − 𝑉𝑅𝐸𝐹− )
𝑛
𝐷 = 𝑒𝑛𝑡 2 ⋅
𝑉𝑅𝐸𝐹+ − 𝑉𝑅𝐸𝐹−
Quantization
Level
𝑉𝑖𝑛
𝐷 = 𝑒𝑛𝑡 2𝑛 ⋅
𝑉𝐷𝐷
0 ≤ 𝑉𝑖𝑛 < 𝑉𝐷𝐷
𝑽𝑭𝑺
1 1 2
So the first digital level will span from [0 ), the second [ ),
2𝑛 2𝑛 2𝑛
2 3
the third [ ), and so...
2𝑛 2𝑛
1) Digital Value Calculation
Ejercicio:
Se dispone de un ADC de 8 bits de resolución, con voltajes de referencia
Vref+ = +10V y Vref- a tierra. Determine:
Weight:
Number of LSB that
each bit represents
𝑉𝑅𝐸𝐹 𝑉𝐹𝑆
𝑉𝑂𝑈𝑇,𝐴𝐷𝐶 = 𝐷 ⋅ 𝐿𝑆𝐵 = 𝐷 ⋅ 𝑛 = 𝐷 ⋅ 𝑛
2 2 −1
*D is the digital word converted to decimal
2) Converted Voltage Calculation
𝑉𝑅𝐸𝐹 = 5𝑉
5
𝑉𝑂𝑈𝑇,𝐴𝐷𝐶 = 𝐷 ⋅ 𝐿𝑆𝐵 = 44 ∗ 8 = 0.8593
2
2) Converted Voltage Calculation
Types of Analog to
Digital Converter
Flash ADC
The flash ADC is the fastest type available.
𝑁𝑏𝑖𝑡𝑠
𝑡𝑐𝑜𝑛𝑣𝑒𝑟𝑠𝑖𝑜𝑛 =
𝐹𝑐𝑙𝑜𝑐𝑘
1) Check if the input is greater than half the reference voltage. If it is, the
MSB of the output is set.
2) This value is then subtracted from the input, and the result is checked for
one quarter of the reference voltage.
3) This process continues until all the output bits have been set or reset.
https://www.youtube.com/watch?v=TYCn33udOac
Successive Approximation
Algorithm Flowchart:
https://www.youtube.com/watch?v=TYCn33udOac
Sigma-Delta ADC
In a perfect world, the hold capacitor would have no leakage and the buffer
amplifier would have infinite input impedance, so the output would remain
stable forever.
1) The hold capacitor will leak and the buffer amplifier input impedance is
finite, so the output level will slowly drift down toward ground as the
capacitor discharges.
3) Some of the input signal appears at the output, even in hold mode. This
is called feedthrough effect.
Common ADC Errors
PIC ADC
Programming
Analog to Digital Converter
Result:
ADCON2 REGISTER - ACQT
ADC Conversion Time: Time required to obtain the digital result, i.e., the
time it takes to complete a single conversion. Conversion time does not
include the acquisition time. The conversion time is usually specified in
analog-to-digital clock cycles and the minimum period for the clock is
specified to obtain the specified accuracy for the ADC.
ADCON2 REGISTER - ADCS
ADCON2 REGISTER
𝒇𝑻𝑨𝑫 = 𝑭𝑶𝑺𝑪/𝑫𝑰𝑽
𝑻𝑨𝑫 = 𝑫𝑰𝑽/𝑭𝑶𝑺𝑪
𝑇𝐴𝐷𝑚𝑖𝑛 = 0.8𝑢𝑠
ADCON2 REGISTER
Programming ADC
Initialization:
1. Set analog input port as input (TRIS)
2. Configure ADCON1 to select Vref (VCFG1: VCFG0), and to select port pins
required as an analog input (PCFG3: PCFG0)
3. Configure ADCON2 to select A/D result format, A/D clock and acquisition time.
4. Configure ADCON0 to select channel (CHS) and enable ADC module.
5. Flush ADC output register
OJO
Verificar!
Programming ADC
A/D conversion and Read digital values
1. Flush ADC output register
2. Start A/D conversion (Go/done’=1)
3. Wait for G0/done’ bit which is cleared when the conversion is completed.
4. Then copy conversion stored in ADRESH and ADRESL to a desired register.
Programming ADC