IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO.

7, JULY 1998 613

Machine Learning-Based VLSI

Cells Shape Function Estimation

Xiao Quan Li and Marwan Anwar Jabri

Abstract— We describe in this paper a novel approach based upon

machine learning for estimating layout shape functions of full-custom
integrated circuit cells. A neural network is trained to estimate one
dimension of cell layout from circuit netlist, a desired packing density, and
prescribed values of the complementary dimension. The neural network Fig. 1. A view of an integrated circuit hierarchy.
is then combined with a linear function generator and a neural network
that predicts the number of contacts (vias) to produce estimates of cell
layout shape functions. We have experimented with this approach on an
independent test set of circuits and the results are very encouraging. The
resulting estimation system is very fast and can be easily incorporated into
exiting floorplanning systems. An additional benefit of the the machine
learning aspect is the simplicity and systematicity in incorporating into
the estimation system new circuits and technology information as they
become available.
Index Terms— Dimension estimation, floorplanning, layout aspect ra-
tios, neural networks, number of contacts, shape functions.

I. INTRODUCTION
In full-custom very large scale integration (VLSI) design, a cell
refers to the lowest level circuit in the design hierarchy as shown
in Fig. 1. For a given circuit context, the masks of the cell can be
designed in various ways. We show in Fig. 2 the circuit schematic
of an inverter cell designed using an nMOS technology and an asso-
ciated mask layout. Different layouts of the same circuit are called
“realizations.” We show in Fig. 3 some possible layout realizations of
the inverter in Fig. 2(a). The width and height of different realizations
can be used to define a discrete shape function as shown in Fig. 4.
Features that characterize and differentiate full custom cell layout
(FCCL) realizations are (Fig. 2):
1) Circuit Specific: schematics of the circuit—transistors/gates
count and their area, number of netlists (Fig. 5), and
2) Contextual: floorplan information—how the cell layout fits with
its surrounding interconnection port positions.
Different realizations can be produced by varying items in 2)
above. A continuous shape function represents a continuous rela-
tionship between the width and the height (Fig. 4).
Shape functions are useful in automated and manual design tasks.
In automated design, they are used in chip level area optimization
and floorplanning [1]–[3]. Shape functions of lower level modules
are assumed to exist and are used to generate the minimal area
of overall floorplan by optimally selecting the realization for each
module as to minimize a chip level cost function. The assumption
of the existence of FCCL shape functions (discrete or continuous) is
valid in the case of library based design systems. In this case, several
layout realizations of a circuit may exist and the layout dimensions
of these different realizations can be used to define a discrete shape
function. For standard cell based designs, the shape functions of cells
and modules can be estimated accurately using empirical [4] and
constructive techniques [5].
Manuscript received July 17, 1996. This paper was recommended by
Associate Editor M. Sarrafzdeh.
The authors are with the Computer Engineering Laboratory, Department of
Electrical Engineering, The University of Sydney, NSW 2006 Australia.
Publisher Item Identifier S 0278-0070(98)05195-1.
(a) (b)
Fig. 2. (a) Schematic of a circuit, with T1 and T2 being depletion and
enhancement mode nMOS transistors, respectively. (b) Mask layout of the
circuit.
In manual design tasks, the existence of shape function estimators
allow designers to explore layout dimension options and manual floor-
planning. For example, the availability of cell dimension estimates
can assist in the determination of wiring delays and clock skews.
This paper is concerned with the automatic estimation of FCCL
shape functions from circuit schematics. In other words, we are
concerned with the task of “predicting” the width and height of
unknown realizations given some features that can be extracted from
the circuit schematic and contextual descriptions without knowledge
of the layout.
The automatic prediction of cell shape functions in a full-custom
design methodology is a complex process because of the large number
of practical layout options. The creation of a shape function prediction
model is further complicated by the nonlinear relationships that exist
between cell features and possible layouts [6].
This paper presents a novel machine learning-based technique for
the generation of shape function prediction models. The technique is
based on multilayer neural networks trained using gradient descent
to predict the width or height of FCCL’s and the number of contacts
required by a circuit. To the best of our knowledge, it is the first time
that the estimation of shape functions of full-custom layouts from
schematics has been attempted. The technique has been evaluated on
a database of real cells, and it shows great potential for its practical
exploitation in CAD systems.
II. SHAPE FUNCTION MODELING
The modeling of shape functions can be treated as a nonparametric
prediction problem. To achieve this, one has to define features or
the “predictor variables,” collect data or observations, and use the
collected data to build an estimation model.

0278–0070/98$10.00  1998 IEEE

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 614 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 7, JULY 1998
(a) (b)
Fig. 3. Possible layouts for the inverter of Fig. 2. Note the layouts have been scaled to fit. (b) A rotated version of (a). (c) A different position for
Vin : (d) An up-down flip of (a).
Fig. 4. The filed circles represent a discrete shape function. The continuous
curve represents a continuous shape function. The continuous shape function
defines the minimal area required for the layout of the block. Realizations
with corresponding width and height points above the curve (dotted lines) are
possible but will not be minimal in terms of area.
Fig. 5. Netlists of the circuit in Fig. 2. Note the circuit has four netlists.
Before we describe the features that we have used in our modeling,
we will review those used in the modeling of FCCL dimensions and
which have been reported in [6].
A. Features Characterizing FCCL Dimensions
The width and height of an FCCL depend on a number of
features of the circuit at hand. Previous research has shown that the
relationship between these features and the actual dimensions of the
FCCL is too complex to be modeled using handcrafted formula [6] but
are amenable to automatic modeling. These features can be divided
into two groups: circuit specific and context (floorplan) oriented.
1) Circuit-Specific Features: The circuit specific features that
have commonly been considered are:
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(c) (d)
Ntrans number of transistors or transistors equivalent of gates;
Tav average area of these transistors;
Nnetlists number of interconnection netlists in the circuit.
All these features influence the area of the FCCL in a relatively
easily predictable manner. Their influence on the aspect ratio of an
FCCL is significantly more difficult to predict. This is especially the
case for interconnection netlists where wiring directions (which are
considered to be unknown in the dimension prediction process) affect
the aspect ratio more directly than the number of netlists.
2) Context-Specific Features: The contextual (floorplan) feature
group consists of the information about the number of interconnection
ports on each side of the block’s enclosing rectangle. For these
features, we introduce the index side defined as
side 2 ftop, bottom, left, rightg:
The floorplan-based features are:
Dataside number of data ports on side;
C tlside number of control ports on side;
C lkside number of clock ports on side;
P owerside number of power and ground ports on side;
P ack the packing density as discussed in Fig. 8.
The numbers of data, control, clock, and power ports have been
treated as separate features because in practice they occupy varying
mask layers. This is not suggesting that these ports should occupy
different layers, but that degrees of freedom should be provided to
accommodate the cases where they do. We show in Fig. 3 how the
position of ports affects layout organization and dimensions.
B. Features Characterizing Shape Functions
The discussion above was aimed at briefly reviewing the important
features that characterize dimensions of FCCL’s. The question now is
which of these features would influence the shape function of a cell?
More specifically, does shape function modeling require floorplan-
based features?
As mentioned in Section I, different layout realizations of a circuit
are obtained by varying the contextual features of the cell. The
variation of these features translates into possible movements of ports
along a side of the FCCL enclosing rectangle, or from one side to
another. Such movements are not necessarily linear, that is, ports may
have to be moved in groups as to maintain their practical distribution.
For example, if a group of ports represents a data bus, then it is
unlikely that the movement of one port (representing one bit of the
bus), from one side of the circuit enclosing rectangle to another side,
would lead to a layout realization that meets practical floorplans. This
complex relationship between floorplans (port positions) and shape
functions leads to difficulties in selecting the number of ports and their
type on a side, as predictor variables in shape function modeling.
 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 7, JULY 1998 615

(a) (b)
Fig. 6. The packing density of mask layout. It reflects the amount of “dead space” in the layout. The packing density of the layout in (a) is higher than that
of (b). The dead space is any wasted space in the layout that may be due to layout pitch matching. Of course design rules based spacing is excluded.

TABLE I
FEATURES USED IN SHAPE FUNCTION MODELING EXPERIMENTS
1) Prescribed Input Dimension: The contextual information can
be represented in a simpler but indirect fashion. This is possible
in shape function modeling because we can aim at estimating one
dimension given the cell features and given prescribed values of the
second dimension. For example, we can develop a model that can
estimate the width of a FCCL given the cell specific features, the
aggregate numbers of ports for each type, and prescribed values
of the height. In this case, the height of the cell becomes what
we call a prescribed input dimension (PID). As the height of the
FCCL is specified and the aggregate number of ports for each type
is also provided, the shape function prediction model generation
technique could extract a relationship that represents the floorplan-
based features. As we will see later in the paper, the provision of a
PID is simply and conveniently implemented using a linear function
generator.
Therefore, our modeling experiments have used the ten features
(predictor variables) shown in Table I. We have not included in
this table the PID as it is automatically generated. The modeling
experiments we describe later evaluate the impact of including the
aggregate number of ports for each type as well.
C. Prediction Model Construction Techniques
Many automatic data modeling techniques have been developed
over the last few decades. Traditional techniques make use of “fitting”
(or regression) algorithms to fit some observation data using a set
of basis functions. Polynomial, splines fitting, and simple linear
regression are the most widely used. Depending on the prediction
problem, some modeling techniques are more suitable than others. For
instance, multivariate adaptive regression splines [7] (or MARS) is a
technique that is more suitable to problems where the input variables
(features) need not be highly combined in a linear or nonlinear fashion
to produce accurate models [8]. From the experiments we have done,
it is shown that there are some complex combinations of the input
feature variables in the modeling of FCCL dimensions and shape
functions, and it also confirmed that modeling techniques such as
MARS do not lead to as accurate predictions as multilayer perceptron
do.
Multilayer perceptrons can provide effective prediction models.
It has been shown that a three-layer multilayer perceptron (MLP)
network is a universal approximator [9]. A typical MLP architecture
is shown in Fig. 7. The input layer has a size N +1 (counting the bias
input) pin neurons. These pin neurons have a unity transfer function.
Their outputs are fed through weights to the next layer that contains
nonlinear neurons. Each pin in the input layer is connected to every
neuron in the first layer. Each neuron of the first layer feeds its output
through weights to all nonlinear neurons of the second layer. And so
on, until the output layer.
The weight connecting neuron i to neuron j is denoted wij :
Neurons are indexed from zero (bias pin neuron) to N
L01
N =1+ Nl
l=0
where Nl is the number of neurons in layer l: When pattern n is
applied, the output of neuron i in layer l is
yi (n) = f (neti (n)) (1)
where
N 01
neti (n) = wij yj (n):
j =1
The function f ( ) is usually a squashing function such as the sigmoid
function
1
fs () =
1 + e0
(2)
or the hyperbolic tangent function
ft () = tanh(): (3)

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 616 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 7, JULY 1998
Fig. 7. Typical MLP architecture.
Both hyperbolic and sigmoid functions are used in the networks
described in this paper.
In the case of estimation, the inputs to the MLP are the features
and its outputs are the variables that need to be estimated. An MLP
is trained to estimate by the means of an optimization algorithm. The
most commonly used algorithm is backpropagation [13]. Backpropa-
gation performs training by minimizing the network output error. We
define the error for the output neuron k when pattern n is applied
ek (n) = dk (n) 0 yk (n)
where yk (n) is the output of neuron k and dk (n) is its desired output,
for pattern n: The pattern mean-squared error for n is defined as
ek2 (n)
"(n) = 12
k2 
where  is the set of all output neurons. The training algorithm
will determine the values of the weights as to minimize a total
mean-squared error
"Total = "(n):
n
The training will stop when "Total reaches a small prescribed value.
Once the weights have been determined, the MLP is evaluated on
an independent set of patterns (called the testing set) to assess
its generalization capability. The quantification of the generation
capability is problem dependent. In the case of shape function
modeling, an error margin "m is defined and the output of the MLP
for pattern n is said to be correct if
"(n)  "m :
The error margin "m is also often used in the training algorithm to
instruct it to neglect corrections to the weights when (7) holds for
a particular pattern. The value of "m could be critical. If it is too
small, an over-training effect can take place where, when training
completes, the MLP would have memorized well the patterns in
the training but its generalization performance (on the testing set)
degrades compared to its performance when larger values of "m
are used. Techniques such as cross-validation [10] can be used to
avoid over-training. A third set of pattern, called the cross-validation
dataset (CVD), is created (patterns are removed from the training
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and/or testing set). During training the CVD is applied through the
MLP and the corresponding total mean-squared error is recorded.
Training is halted when this error shows some significant increase.
However, in applications where data is limited, the strength of cross-
validation is diminished because the training and testing data may
suffer in size, and the size of the CVD may not be sufficiently large to
confidently detect good stopping conditions. In this case, determining
the best stopping criteria can be identified by running a large number
of experiments using various stopping criteria and values for "m :
(4)
III. SHAPE FUNCTION MODELING ARCHITECTURE
The shape function modeling architecture proposed in this paper
(5)
consists of two subsystems: a complementary dimension estimation
module and a linear function generator. The complementary dimen-
sion estimation module estimates a dimension of the FCCL given
input features from Table I and a PID. To produce a shape function,
the linear function generator produces a monotonically increasing
(6) series of numbers between zero and one at a predefined step size.
In the experiments we report below, step sizes of 0.1 and 0.01 are
used. Although the shape functions produced by this architecture are
discrete, the actual underlying model is continuous. Because the MLP
is in effect trained to predict a dimension given the complementary
dimension (PID), we call such configurations of MLP’s dimension-
dependent prediction (DDP).
A. Cells and Layout Database
(7) Our database was collected from two sources. The first source
is the VLSI designer’s library [11] which was used in full-custom
dimension estimation experiments in [12] and [6]. The layouts from
the second source are full-custom cells developed in our laboratory in
the 1980’s. Altogether, 53 layouts have been collected. They are all
of digital circuits, nMOS-based, and represent a variety of functions.
The layouts are lambda based with some mapping to a 5-m and
others to a 3-m fabrication processes. Note that the database does not
include regular arrays of structures such as PLA, RAM, and ROM.
Such blocks are commonly produced by “module generators” and
their organizations are predefined and highly accurate estimates of
their dimensions and shape functions can be produced.
 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 7, JULY 1998 617

Fig. 8. The rotation of a pattern has the effect of introducing a new and important point of the shape function.

Although our database is based on nMOS circuits, the shape
function modeling method described in this paper can be applied to
other technologies where layouts can be collected. The collection of
data for such a task is not easy as circuits and associated full-custom
layouts are generally treated with secrecy. Hence, we did not have a
choice in selecting the data as only nMOS circuits and layouts were
available.
For each circuit in the database, the features shown in Table I and
the corresponding dimensions of the layout are extracted and stored to
form a pattern. Because the features are independent of the orientation
of the cell, the number of the patterns was doubled by rotating the
cells (swapping the width and height for each cell) to produce a total
number of patterns of 106. As the database does not contain patterns
of equal width and height, no pattern redundancy is introduced.
The rotation of the original 53 patterns yields a very convenient
effect beside the increase of the amount of training and testing data.
This effect is illustrated in Fig. 8. For each pattern a new symmetrical
point of the circuit shape function is introduced by the rotation.
The patterns in the database are then normalized by dividing each
feature value by a number that represents the maximum of that feature
in the database. The resulting patterns are then bound between zero
and one. Other normalization methods were also assessed but did not
yield better results.
The fact that each FCCL in the database exists in its original and
rotated form ensures that the trained MLP is not biased toward a
particular dimension. Hence, where a width- or a height-dimension
estimation MLP was used, proper training should yield on average
similar behavior for each MLP.
1) the average and standard deviation of the relative error of the
model on an independent test dataset;
2) an error tolerance  .
An experiment is repeated 20 times with different initial conditions,
training, and independent testing datasets to yield an experiment set.
The average and standard deviation of the two measures above are
then computed.
The details of the experimental procedure are shown below.
1) A set of predictor variables are defined (input features).
2) A Muscle file (MUME’s neural network configuration file [14])
is created. Parameters such as training convergence criteria and
training output error margin "m are set.
3) A program is used to randomly generate from the master layout
database training and testing sets containing Ntr and Nte
patterns, respectively.
4) The MUME neural-network simulation program is executed to
train the neural networks.
5) When training is completed (either convergence criteria or
maximum number of iterations is reached) the generalization
performance of the resulting neural-network shape function
model is evaluated on the test set to produce the estimates
of the complementary dimension for each test pattern.
6) The predicted and expected values of the dimension D being
modeled are used by a number of postprocessing programs to
compute:
a) the relative dimension error for a pattern in the test set

"e;p =
jD 0 D j
e;p a;p
(8)
IV. EXPERIMENTS AND RESULTS De;p
The investigation of MPL architectures capable of performing a
mapping/estimation task is an iterative design process. Determining a b) the average of the relative dimension errors
suitable architecture requires understanding of the learning algorithm,
N
the relationship between the dimensions of the input and output 1
"e = "e;i (9)
spaces, the architecture of the network (number and sizes of hidden Nte i=1
layers, neuron transfer functions) and the amount of data. A detailed
account of MLP exploration procedures is beyond the scope of this
c) the standard deviation of the relative dimension errors
paper. In brief, for a given feature set and data, essential elements
in the interpretation of MLP performance include an experimental 2
procedure, a concise performance measure, and variation of number
of free parameters (weights) through the variation of the number of
Nte "2 e;i
0 "e;i
e = e e

Nte (Nte 0 1)
hidden layers and their sizes. (10)

A. Experimental Procedures d) the tolerance specific performance Ce;m (percentage of

We distinguish here experiments and experiment sets. In an exper- pattern for which the target dimension is predicted to
iment, a modeling architecture is constructed and evaluated using: within  ):

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 618 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 7, JULY 1998

7) Steps 3)–6) above are repeated Ne times (number of trials)

with a different random selection of the training and testing
sets to produce an experiment set for which we compute the
following measures:

a) the experiment set relative error average

N
1
"= "e (11)
Ne e=1
b) the associated standard deviation
2
Fig. 9. Shape function modeling using a four-feature DDP.
Ne "2e 0 "e
e e
=
Ne (Ne 0 1)
(12) TABLE II
TRAINING AND GENERALIZATION PERFORMANCE OF
c) the tolerance specific average performance FOUR-FEATURE DDP’s FOR SHAPE FUNCTION MODELING
N
1
Cr = Ce; (13)
Ne e=1
d) the associated standard deviation
2
Ne 2 0
Ce; Ce;
e e
C
Ne (Ne 0 1)
= (14)

which are then used to assess and compare shape function

estimation architectures.
Note that for each experiment, and unless otherwise specified, 76
patterns were selected at random from the data to form a training set
(Ntr = 76) and the remaining 30 patterns were used for independent
testing (Nte = 30):
TABLE III
B. Further Assessments of Shape Function Prediction Performance PERFORMANCE OF THE FOUR-FEATURE SHAPE FUNCTION MODEL
(DDP 4-8-5-1) ON THE TRAINING AND TESTING SETS
The evaluation of the quality of the shape functions predicted by
our proposed method is not a straightforward process. The reason is
that a “direct” assessment of a shape function model would require
more than two layout patterns of the same circuit, which is very
difficult to assemble. To overcome this, we introduce two additional
“checks” to the evaluation of (13) and (14).
Check 1: The output of the shape function estimator should al-
ways decrease or remain unchanged when the PID increases as
illustrated in Fig. 4. Deviations of this desired behavior would
indicate significant problems in the modeling architecture, its training
and/or its input feature representation.
Check 2: The response of the model to features of “similar”
circuits has to be “similar.” Consider a circuit C1 in the test set. C1’s
features will be used to produce a prediction for its shape function.
The “closest” circuit C2 to C1 will be found by scanning the test set
for the circuit with the smallest Euclidean distance to the predictor
variables of C1. The model used to predict the shape function of C1
should produce a dimension estimate for C2 (given the PID of C2
from the database) which should be “close” to the predicted shape
function curve of C1.

C. Shape Function Modeling Using Four Features

A shape function prediction system using a four-feature DDP is
shown in Fig. 9. Note, port and packing density information is not
used. The output of the DDP MLP represents the complementary
dimension to the PID input. So if the PID represents the width, the
output of the DDP MLP represents the height.
We show in Table II the training and generalization performance
for a number of MLP DDP architectures. We show under the
“training performance” column the percentage of patterns in the
training sets for which the complementary dimension has been
estimated to within the specified tolerance : Note that the four layers
network achieves better training performance. The table shows under
the “generalization performance” column the average and standard
deviation [according to (11) and (12)] of the estimated complementary
dimension errors over the 20 runs and for the best of these runs. The
standard deviation of the generalization error is a useful indication of
how consistent is the complementary dimension prediction. It is also

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 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 7, JULY 1998 619

Fig. 10. Shape functions produced by a four-feature DDP-based model.

Fig. 11. Shape functions produced by a ten-feature DDP-based model.

a useful measure to compare networks with different architectures and TABLE IV

the effects of input features on the performance. Note the error margin TRAINING AND GENERALIZATION PERFORMANCE OF
"m is not used in the evaluation of the generalization performance TEN-FEATURE DDP’s FOR SHAPE FUNCTION MODELING
(i.e., any error counts). The four-layer networks also achieve better
generalization performance on average. The best performance is
achieved by the 4-8-5-1 architecture.
Table III shows the performance of this architecture on the training
and testing sets when the tolerance  is swept from 0.05 (5% of target)
to 0.5 (50% of target). The average and the standard deviation of the
number of patterns that the trained 4-8-5-1 MLP DDP has correctly
estimated within  is shown as a percentage in the third column for
the training set and in the fourth for the testing set. Note in the case
of the training set, this is different from the training performance (that
is, it is not the same as training the net at varying error margin).
The numbers in Table III basically say that not only the network
has a poor generalization performance, but it also has difficulties
learning the training set. This is not surprising given that we are
trying to create a model that is too complex to be constructed from
the information conveyed by the four input features. This is also
illustrated in the poor quality shape functions produced by the model
aggregate number of ports per type as predictor variables. Note no
and of which we show two examples in Fig. 10. A simple inspection
is sufficient to see that the number of transistors, netlists, the average port-per-side information is used (that is no context information).
transistor area, and the PID do not convey sufficient information for Again, the output of the DDP MLP represents the complementary
accurate dimension dependent estimation. dimension to the PID input. So if the PID represents the width, the
output represents the height.
D. Shape Function Modeling Using Ten Features We show in Table IV the training and generalization performance
Given the poor results obtained with the four features of the of a number of MLP DDP architectures. What we see in this table
previous section, an obvious improvement is to incorporate the is an improvement over the four-feature modeling architecture. The

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 620 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 7, JULY 1998

average generalization performance has improved by two percentage

points.
We show in Fig. 11 shape functions produced by this model for
the same patterns in our previous illustration. Clearly there are some
improvements, but they are not significant. For a large number of
circuit patterns in the testing sets, the shape functions produced by the
ten feature models have behavior similar to those shown in Fig. 11.
The dimension estimated by the DDP decreases as the complementary
input dimension increases, up to point, and then both dimensions seem
to unexpectedly develop a monotonically increasing relationship. This
suggests that like the four feature-based DDP, the ten feature-based
Fig. 12. Including the number of contacts to a ten-feature DDP.
DDP is failing to capture the essence of the shape function model.
Because all possible direct features have been explored, there
are three possible reasons that could be responsible for the poor
estimation performance: TABLE V
TRAINING AND GENERALIZATION PERFORMANCE OF
1) inadequate (DDP) modeling architecture; ELEVEN-FEATURE DDP’s FOR SHAPE FUNCTION MODELING
2) insufficient training data;
3) insufficient information in the input representation (features).
We have investigated many potential architectures, and we could not
detect a change in the DDP estimation performance. As the data are
scarce, the only option we had was to increase the size of the training
set at the expense of the size of the testing set. This was tried and
no noticeable improvement was observed. As for the adequacy of
the input representation, the only option available to us (as all the
features have been assessed) was to explore the impact of “hidden
features.” The obvious choice was to target the use of the number
of contacts as a feature, assuming that it could be itself estimated
accurately from the features of Table I.

E. Including Number of Contacts in Shape Function Modeling

We argue here that the number of contacts is a valuable hidden fea-
ture in shape function prediction and we will later in the paper support
this argument by experimental results that support this argument. TABLE VI
It is known that the number of contacts or vias [6] can affect PERFORMANCE OF THE 11 FEATURE DDP
dimension prediction when contextual information is used as predictor (11-6-1) ON THE TRAINING AND TESTING SETS
variables. In shape function prediction no contextual information can
be used in a simple fashion. Because the number of contacts directly
affects area and a prescribed input dimension is used as a predictor
variable, we can expect the extraction of a relationship between the
number of contacts, the PID, and the complementary dimension to
be predicted, can be achieved by our modeling technique. We have
performed a number of experiments where the number of contacts
was used as an additional input to the implementations described in
the previous two sections. We discuss these experiments and their
results in the next few sections. Following these experiments we will
describe how the number of contacts can be accurately estimated
using features from Table I.

F. Including the Number of Contacts as an

Input to a Ten-Feature DDP
The modeling architecture is shown in Fig. 12. Again, for com-
parison purposes, the training and testing sets used here are those
used in the previous experiments. The training and generalization
performance of this architecture for various DDP MLP’s is shown
in Table V. Clearly, the number of contacts feature is yielding a
significant improvement in modeling accuracy compared to all models The shape functions for the same patterns illustrated previously are
described so far. shown in Fig. 13. Note the significant improvement in the shape
The best performance is achieved by an 11-6-1 DDP MLP. We of these functions, in particular, with respect to Check 1 and the
show in Table VI the performance of this DDP on the training and performance of the ten feature-based model. Before we look at how
testing sets when the tolerance is swept from 0.05 to 0.5. Note the this architecture performs with regard to Check 2, we look at the
significant improvement on the testing set in particular. For an error estimation of the number of contacts and it integration in an overall
margin of 20, over 81 of the testing patterns are correctly estimated. shape function estimation system.

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 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 7, JULY 1998 621

Fig. 13. Shape functions produced by an 11-feature DDP with the number of contact feature provided from the database.

Fig. 14. Shape functions produced by the 11-feature DDP with the number of contact feature predicted by the NCP.

TABLE VIII
GENERALIZATION PERFORMANCE OF THE
CASCADED 11-6-1 DDP AND 9-11-5-1 NCP
TABLE VII
TRAINING AND GENERALIZATION PERFORMANCE OF THE NCP’s

G. Number of Contact Prediction for Shape Function DDP

The number of contact prediction (NCP) systems we have in-
vestigated have built on the experience described [6]. Note that in
comparison to the work reported in [6] (on the prediction of actual

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 622 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 7, JULY 1998

Fig. 15. Comparison of shape functions generated with 11-feature-based DDP with the number of contacts provided from the database and from the NCP.

dimensions of FCCL), the input feature representation in our present
context are different and are restricted to the features of Table I.
Because the NCP will be connected to a DDP, the data used for the
evaluation of the NCP and the DDP should be consistent. That is,
no training data of the NCP should be part of the testing sets of
the DDP and vice-versa. The easiest way to maintain consistency is
to use the 11-feature DDP experiment datasets for the training and
evaluation of the NCP.
Our investigations of the NCP explored various combinations of
circuit features and multilayer perceptron architectures. We have
grouped the investigated architectures according to their input rep-
resentations (features):
three-features NCP architectures: Ntrans ; Taverage-area ; Nnodes ;
four-feature NCP architectures: Ntrans ; Taverage-area ; Nnodes ;
P ack;
five-feature NCP architectures: Ntrans ; Taverage -area ; Nnodes ;
P ack; P orttotal ;
nine-feature NCP architectures: Ntrans ; Taverage -area ; Nnodes ;
P ack; P orttotal ; Datatotal ; C tltotal ; C lktotal ; P owertotal :
We show in Table VII the training and generalization performance
the best performing architecture for each of these groups. The best
performing architecture in each group is shown in italic and the
overall best performing architecture is shown in bold (9-11-5-1)
which has an average error of 9.21% with a very small standard
deviation.
H. Incorporating the NCP in Shape Function Modeling
The DDP (11-6-1) and NCP (9-11-5-1) are now cascaded to form
an 11-feature shape function prediction system (with the PID input of
the DDP supplied by the linear function). The generalization perfor-
mance of the cascaded scheme is shown in Table VIII. Obviously the
performance is slightly degraded compared to the 11-feature shape
function estimation where the number of contacts was supplied from
the database.
We show in Fig. 14 the estimated shape functions for patterns 4
and 12. Obviously the improvements introduced by the number of
contacts are maintained when this number is estimated. This result
is very pleasing.

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 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 7, JULY 1998
Fig. 16. The shape functions of pattern 4 and pattern 10, the closest to pattern
4 according to an Euclidean distance based on the 11 input features and the
prescribed input dimension.
We show in Fig. 15 shape functions produced by the 11-6-1
DDP for four different patterns (representative) when the number
of contacts is sourced from the database and when it is estimated.
Overall, the differences are not significant.
As an implementation of Check 2, we show in Fig. 16 the shape
functions for patterns 4 and 10. Pattern 10 is the closest to pattern
4 in terms of Euclidean distance (smallest but nonzero Euclidean
distance). Although the circuits associated with patterns 4 and 10
are slightly different, the similarity in the estimated shape functions
provides further evidence that the modeling reflects important aspects
of the desired dimensions relationship.
I. Operation Speed
The operation speed of the overall prediction system is independent
of the circuit at hand and is directly proportional to the size of
the MLP’s. The speed can be computed by counting the number
of multiply/accumulate and neuron transfer functions according to
(1)–(3). For either of the neural networks, the number of operation
for a feedforward evaluation is approximated to
L L
l l01
N N + Nl :
i=1 l=1
Multiply and accumulate Neuron functions [(2) or (3)]
On a Sparc workstation Ultra 1, the speed for a single feedforward
through the whole system is less than 200 ms.
V. CONCLUSIONS
This paper has presented a novel technique for custom cell layout
shape function estimation based upon machine learning. Our results
show that a dimension can be predicted to within 11.52% average
error and that estimate accuracy is improved when the aggregate
number of ports for each of data, control, clock, and power, are
provided.
The accuracy and speed efficiency makes our proposed method
ideal for use in fast design exploration during floorplanning, timing,
and skew analysis by CAD systems.
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623
The proposed shape function generation system was evaluated on
nMOS circuits and layouts and the method is applicable to any
technology for which a database of layouts can be gathered.
The results of the experiments demonstrate the importance of port
information in shape function modeling. The results also demonstrate
that machine learning in the context of neural computing can take
advantage of the port information in conjunction with the PID to
yield improvements.
The presence of three- and five-micron nMOS circuits in our
database, shows a fabrication process independence in our shape
function modeling approach. The question as to whether constructed
models can be used to generate shape functions of CMOS circuits
is open to debate and requires further research. As the model-
input variables (features) are all lambda-based, one can expect that
generated models would apply to other lambda based technologies.
This is not necessarily true because although no nMOS specific
measures are used in our database, the layout dimensions used in the
MLP training reflect inherently nMOS organization of layout. CMOS
layouts are organized differently as they take advantage of different
design rules (e.g., well spacing). Based on our modeling experience
however, we anticipate improved performance when CMOS-based
layout shape function estimation is targeted.
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