ISSCC 2005 / SESSION 21 / TD: RF TRENDS: ABOVE-IC INTEGRATION AND MM-WAVE / 21.
21.7 A 70GHz Cascaded Multi-Stage Distributed
Amplifier in 90nm CMOS Technology
Ming-Da Tsai1, Huei Wang1, Jui-Feng Kuan2, Chih-Sheng Chang2
1 mission lines, which also drive the output line through M3-6. The
National Taiwan University, Taipei, Taiwan
2 gates of cascode devices (M5, M6) are bypassed using 1pF capaci-
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, Taiwan
A broadband cascaded multi-stage distributed amplifier
(CMSDA) is proposed and implemented in a standard 90nm
CMOS technology. The standard CMOS technology can offer gain,
bandwidth, and power performances comparable to advanced
compound semiconductor technologies [1]-[4]. The CMOS
CMSDA can achieve better than 7dB gain with a bandwidth of
70GHz. The measured 1dB compression point (P1dB) is 10dBm at
30GHz, the input IP3 (IIP3) is 9.3dBm at 40GHz, and the aver-
age noise figure (NF) is 6.4dB from 1 to 25GHz.
The distributed amplifier (DA) architecture is well-known and
widely used in instruments, electronic warfare, optical communi-
cations, and broadband commercial/military radio systems. The
state-of-the-art DAs in III-V and SiGe technologies have already
been demonstrated [1-4]. A record DA in SOI CMOS process is
demonstrated in [5] with high GBW using devices with fT and fmax
of 196 and 230GHz. Recently, high-performance DAs using stan-
dard CMOS technology have been demonstrated; the DA in [6]
shows a bandwidth of 22GHz with a 7dB gain, and the DA in [7]
has the highest frequency of 39GHz with a gain of 4dB. The chal-
lenges of CMOS DA design at high frequency include conductive
Si-substrate and topology limitations. In this paper, a new circuit
topology with coplanar waveguides (CPWs) to reduce substrate
loss is demonstrated using a standard 90nm 1P9M CMOS tech-
nology, with a fT of 160GHz and an fmax of 142GHz. This circuit
indicates that standard CMOS technology is also promising for
broadband applications up to 70GHz with good output power per-
formance.
In general, the travelling-wave architectures can be classified
into conventional distributed amplifier (DA) and cascaded single-
stage distributed amplifier (CSSDA) [8]. The architecture and
simplified equivalent circuit of DA and CSSDA are shown in Fig.
21.7.1. In order to improve the gain-bandwidth performance, a
CSSDA is investigated in hybrid circuit [8] and another CMOS
CSSDA with relatively low output power of –0.5dBm is present-
ed in [9]. The architecture, equivalent circuit, and equation for
available power gain of ideal lossless DA and CSSDA are shown
in Fig. 21.7.1 and 21.7.2, respectively [8].
Although CSSDA has a potential of higher gain-bandwidth per-
formance than DA, its output power is limited by the device size
of the last stage. Using larger devices, the output power can be
increased, however, larger devices have larger parasitic capaci-
tance and thus this approach limits the bandwidth. In order to
overcome this bottleneck, a new design concept to improve
CSSDA performance is proposed. The single cells of CSSDA are
replaced by distributed cells to construct a broadband CMSDA.
As in CSSDA, the CMSDA can have the following features: (i) the
characteristic impedance of the input and output artificial trans-
mission lines are matched to the 50Ω environment; (ii) the inter-
stage impedance can be optimized to boost the overall gain per-
formance [8]. Figure 21.7.3 shows the schematics of the proposed
CMOS CMSDA, which is a cascaded two-stage distributed ampli-
fier, and each stage is composed of two gain cells. Each gain cell
of the first stage is a common-source transistor connected with
CPW lines, and the second (output) stage consists of two broad-
band cascode architectures, providing high gain-bandwidth per-
formance. The input and output CPWs are terminated by 50Ω
402 • 2005 IEEE International Solid-State Circuits Conference
polysilicon resistors Rog and Rod in series with bypass capacitors
Cb1 and Cb2, respectively. These capacitors with the inductance of
supply line introduce a low-frequency pole, and hence, the resis-
tor Rx is used to prevent low-frequency instability. The output
parasitics of M1 and M2 are coupled into the inter-stage trans-
tors (Cm5, Cm6) and for stability consideration are biased sepa-
rately through high-resistivity polysilicon resistors. The induc-
tances of the artificial transmission lines are all realized by CPW
with suppression of coupled-slot-line mode using underground
passes.
S-parameters are measured via on-wafer probing, as shown in
Fig. 21.7.4. The measured gain is better than 7dB and the 3dB
cut-off frequency is at 74GHz with input and output return loss-
es of better than 7dB and 10dB. Reverse power gain (S12) is lower
than –40dB due to the good isolation of the circuit architecture
and the cascode gain cells. The total power consumption is
122mW. Figure 21.7.5 shows the measured results of the P1dB and
IMD3. The P1dB is measured at 20 and 30GHz with a 10dBm out-
put power. The IMD3 is measured at 40GHz. For a –16.2dBm
input, IMD3 is 51dB below the carrier which is equivalent to a
+9.3dBm IIP3. This MMIC features an average NF of 6.4dB
between 1 to 25GHz. The measured performances and compari-
son with recently reported DAs implemented other advanced
process technologies are summarized in Fig. 21.7.6. The die
micrograph of the fabricated chip is shown in Fig. 21.7.7. The die
size is 0.9×0.8mm2 including all testing pads and dummy metal.
The proposed miniature MMIC can provide good output power at
millimeter-wave frequency, high linearity and gain-bandwidth
performance, and represents the state-of-the-art broadband
amplifier in standard CMOS technology.
Acknowledgement:
This work is supported in part by NTU-TSMC Joint-Development Project
and National Science Council (NSC 93-2752-E-002-001-PAE and NSC-92-
2213-E-002-033). We thank Hong-Yeh Chang, Pei-Si Wu, Kun-You Lin, and
Ming-Fong Lei of NTU for their valuable discussions.
References:
[1] K. Kobayashi et al., “A 2-50 GHz InAlAs/InGaAs-InP HBT Distributed
Amplifier,” IEEE GaAs IC Symp., pp. 207-210, Nov., 1996.
[2] S. Masuda et al., “An Over-110-GHz InP HEMT Flip-Chip Distributed
Baseband Amplifier with Inverted Microstripline Structure for Optical
Transmission Systems,” IEEE J. Solid-State Circuits, vol. 38, no. 9, pp.
1479-1484, Sept., 2003.
[3] J. Carroll et al., “0.25µm pHEMT 40Gb/s E/O Modulator Drivers,” IEEE
International Mircowave Sym., vol. 1, pp. 489-492, June, 2002.
[4] O. Wohlgemuth, et.al., “SiGe Broadband Amplifiers with up to 80GHz
Bandwidth for Optical Applications at 43Gbit/s and Beyond,” in IEEE 33rd
European Microwave Conf. Dig., vol. 3, pp. 1087-1090, Oct., 2003.
[5] J. Kim et al., “A 12dBm 320GHz GBW Distributed Amplifier in a
0.12µm SOI CMOS,” ISSCC Dig. Tech. Papers, pp. 479-479, Feb., 2004.
[6] R. C. Liu et al., “Design and Analysis of DC-to-14-GHz and 22-GHz
CMOS Cascode Distributed Amplifiers,” IEEE J. Solid-State Circuits, vol.
39, no. 8, pp.1370-1374, Aug., 2004.
[7] H. Shigematsu et al., “40Gb/s CMOS Distributed Amplifier for Fiber-
Optic Communication Systems,” ISSCC Dig. Tech. Papers, pp. 476-477,
Feb., 2004.
[8] B. Y. Banyamin et al., “Analysis of the Performance of Four-Cascaded
Single-Stage Distributed Amplifiers,” IEEE Trans. Microwave Theory and
Tech., vol. 48, no. 12, pp. 2657-2663, Dec., 2000.
[9]M. D. Tsai et al., “A Miniature 25-GHz 9-dB CMOS Cascaded Single-
Stage Distributed Amplifier,” to appear in IEEE Microwave and Wireless
Components Lett.
0-7803-8904-2/05/$20.00 ©2005 IEEE.
 ISSCC 2005 / February 9, 2005 / Salon 7 / 11:15 AM

Zod OUT
M1 M2 Mn

IN Zog Conventional
Distributed Amplifier
(DA)
Zod
gmVgs
OUT n 2 g m 2 Z od Z og (1)
Gav ≅ 2 ( n −1)
g m 2 n Z o int Z od Z og
IN 4 Gav ≅
Ri Zog 4
+
Vgs Cgs
-

Zog , Zod : Characteristic impedance of gate and drain line, respectively

Figure 21.7.1: Architecture and equivalent circuit of DA. Figure 21.7.2: Architecture and equivalent circuit of CSSDA.

20

0
S-parameters (dB)

-20
S21
S11
-40 S22
S12

-60

10 20 30 40 50 60 70 80
Frequency (GHz)

Figure 21.7.3: Schematic of the CMOS CMSDA. Figure 21.7.4: Measured S-parameters. 21

10
20GHz
S21 S11/S22 BW GBW NF P1dB IIP3 PDC Die Size
0 30GHz Technology
(dB) (dB) (GHz) (GHz) (dB) (dBm) (dBm) (mW) (mm2)
Ref.

8.0-9.0
InAlAs HBT 5 <-5/<-5 50 89 - - 89 2.52 [1]
-10 <25GHz
Output (dBm)

InP HEMT 14 <-9/<-10 90 451 - - - - 2.75 [2]

-20 -10
GaAs HEMT 6 <-13/<-4 50 100 -
22
- 1900 2.4 [3]
-20 @25GHz
-30
SiGe HBT 7 <-5/- 81 181 - - - 495 1.17 [4]
-30 -40
IMD3
4.8-6.2 12
Output (dBm)

-50 SOI CMOS 11 <-7/<-3 90 319 4.5 210 1.28 [5]

<18GHz @20GHz
-60
-40 -70 0.18 µm CMOS 7.3 <-8/<-9 22 51
4.3-6.1
- - 52 1.35 [6]
<18GHz
-80

-90 0.18 µm CMOS 4 <-10/<-10 39 62 - - - 140 3.3 [7]

-50 -100
39.998 39.999 40.000 40.001 40.002 40.003 6.0-6.9 10 This
90nm CMOS >7 <-7/<-12 70 157 9.3 122 0.72
work
Frequency (GHz) <25GHz @30GHz
-60
-60 -50 -40 -30 -20 -10 0 10
Input (dBm)
Figure 21.7.6: Summary of measured performances and comparison with
Figure 21.7.5: Measured P1dB and IMD3. recently reported DAs in other advanced process technologies.
Continued on Page 606

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OUT

IN

Figure 21.7.7: Chip micrograph (0.9 x 0.8 mm2).

606 • 2005 IEEE International Solid-State Circuits Conference 0-7803-8904-2/05/$20.00 ©2005 IEEE.