Paqno Ypehaj RU-20 (Collins PRC-515) Texunuko YnytTcTBo (3a wramnare Ha A4 dopmaty) Yugoslav RU-20 (Collins PRC-515) Radio Set Instruction Book (for printing on 8.5x11 in. letter size format)523-0769144-001211 1 duly 1978 Rockwell International instruction book COLLINS AN/PRC-515 RADIO SET Collins Telecommunications Product: Division Electronic Systems Group Rockwell Internaticnal Cedar Rapids, lowa 52406 Printed m ine Untied Stes of AmericaSection INTRODUCTION .... ‘TABLE OF CON 1 DESCRIPTION Purpose... 20... Equipment Supplied 2.222: squipment Specifi Equipment Description... Reeei ter Group OR-SUU7/URC™ age Ballery BI-706. Tio Set Hlarniesx MT=S1G7PRC-SIS Antenna AS-5093/PRC-515 ..... Handset 1 S017/GR 2... Ueadset- Microphone 1-016/PRC-515 lectrical Power Cable Assembly CX- Battery Charger PP=5267/U Direet Current Generator ¢ eleyrraph Key KY -5033/PRC-5 Auten Antent Op I: Standard Con Spare Battery Option ... Generator Option Cold Weather Configuration... 1 Antenna Options . . P nsmilter Group OR-5007/URC Detailed ‘theory ...... er Treiman vers Reeciver ‘Theor Broadband Ampliti Miser AIA2 ITA AVASAI AM Rey 6c USK Reecive | Transmitter ‘Th AIASAZ TO/IRC 5U47/URC idetone and Law Voltage input” ALG PageSection. i ie 1 1.4.2.2. 7.4.2.2. 1.4.2.2. HOF CONTENTS (Cont) Mixer AIA2 oo. 00.0005 band Amplifier AYA... vathesizer AIAG MU AIAGAIAL soc e cece ee aee cy Divider AIAGAIA2. .. Lf Phase-Lock Loop AIAGAIAS 6.0.0. quency Converter AIAGAIAG . ose. se “back Loop ATAGAZA3, able Frequency Divider ALAGA2A2, and Voltage Regulator AIAGAZAT oo... eee ees Power $i pply AIA... musmitter Chassis ATAT .. Coupler AB, AM-52HO/URE Amplit Tratismit plifier ASAT... ch AYAS oe... eee itor AIAG vee cee J Part of ASAGAT and A3AGA2 - + ABAGA3 and part of ABAGAL 2.5 jor, Part of A3AGA Land ABAGAZ ninator, Part of A3AGAL and Reflected Pow ABAGA2 . ALG Detee ng Network sformer AIAS apacitor ASAT ing Co Control Logic A3A2 "| Frequency DecodingTAULE OF CONTENTS (Cont) MAINTENANCE Second-Tin Proventive WM: ent Required publesboating « ‘Testing/Troubleshooting |. ont Required... lexhooting . upply AZAG, Testing ‘Troubleshooting ......... net Amplifier ATA: ‘Testing: ‘Troubleshooting Discriminator A3AG, Testing ‘Troubleshooting Tuning Capacitor A3AT, Testing /Troubleshooting ..... Tuning Coil ASAK, Texting/Troubleshooting Autotransformer A3A9, Testing /Troubleshooting . Control Logie A3A2, ‘Testing /Troubleshooting Servo Amplifier ASAL, ‘Testing /Troubleshoot I/AT ALASAL, ‘Testing/Troubleshooting: ..... Bands ABAS. ‘Testing Troubleshoot Control A2, Testing/Troubleshooting ..........5 Frequeney Synthesizer A1AG ‘Testhye/Troubleshooting Mixer AIA2. ‘Testing/Troubleshoot Logie/Tx ATASA2. Testi Receiver: ‘Trannnitter € Troubleshooting... ier Coupler Ch: Amplifier Power AmptitieTABLE OF CONTEN' Power Amplifier ASAT Disassembly oo... eee eee ins /Control ABATA2 Removal for Ace ussemblios: Her ABARAT Removal © ABASAIFL Removal. ABA2 Removal Receiver-Transmitter Al Disassembly Dust Cover Removal. . Lorie ls ATAS IIAT AMASAT 8 Mixer AIA2 Remo Rroadband Amplifier ATA: Power Supply ATA Remon : nthesizer AIAG Removal. Gener Disassembly, Sover Removal... .ee ees ahassembly AT Removal. 2 Generator Removal... . Receiver~Transmitter Group Rea : Reeeiver-Transmitter AT Reassembly ... Vower Supply AIA Replacement... 0. Frequency Synthesizer AIAG Replacement ¢ AVA2 Replacement . thane Amplifi UVAE AIASAL Repl Logie? MASA? Repl Dust Cover Replicement . Amplifier Coupler issembly 1 ARIAL Replacement... 2 JA2 Replacement. . 3 IAA Re ent... 4 ASAT Roplicement . 2. 5 A3A2 Replacement 6 coment 1 a Page 2-234 2-234 2-234 2-234 2-234 2-234 2-234 2-237 2-237 2-237 2-237 2-237 2-238 2-238 2-238 2-238 2-238 2-240 2-240 2-240 2-240 2-240 2-240 2-240 2-240 2-242 2-242 2-242 2-242 2-242 2-242 2-242 2-242 2-243 2-243 2-243 2-243 2-243 2-243 2-243 2-244 2244 2-244 2-244 2-244 2-244mm Iv TABLE OF CO! 8 (Cont) 1.9 Autotransfor 1.10 Raneswit LM Amplifier Co Cover Repia Receiver: Tra Adjustment... 1 General. 2 Receiver 3 Amplifier: Coupler : of Solid-State Devices tion of Reference Designation Columns. eee... SCHEMATICS 41 Zoneral . Page 2-245 2-245 2-246 2-246 2-246 2-246 2-246 2-246 2-246 2-247 2-247 2-247 2-247 2-250 a(Missing page)(Missing page) vii+23 24 325 vill LIST OF ILLUSTRATIONS (Continued) ‘rile Chassis Part of ATAT plifier Coupler AN 5 ntvol Layrie ARA2 C2 Sheets) "vo Amplifier ABAT Cl Sheets) Bins /Control A3A4 oe eeeeteee RE Civenit Card. Part of ARAGAT Bandswiteh AIA Cr Sheets) Mer No. 1 AANS Filter No. 2 A: Tuning Co Eleetrieal Pow Storage Rattery R-TUG/U tenn AS -5008/0 eleygraph Key WY Direet Current Component. Axsew Chassis AIAL, Mixer AIA2, S Broadband Amplific Power Supply ATAT ACIAT ALASAT, Set Diagram |... tic Dingra Frequency Voltage Rett tie Diagram SehematiFigure at 22 +23 24 25 4-26 «27 “38 LIST OF ILLUSTRATIONS le Discriminator A2AG. 8 tie Dingram Tuning Capacitor A3A7. Schematic Dingram - oil ABAX, Schematic Diagram ~ ASAS. Sehemtie: Dinggr Headset-Micruphon al Power C: Sehematie Diagram ...... Direct Current Generator Diagram , Page 4-51 4-53 455 4-57 4-59 4-61 4-63 4-65Table LIST OF TALES: Equipment Accessory uipment: Kequi pend Litn Receiver-Transmitter Al, Testing /Troubleshooting Amplifier-Coupler A3. ‘Testing/Troubleshooting - Generator Second-Line Replaceable Hems ....66..0.. Generator Mii ‘Third-Line Mainte Powor Supply AIA. Broadband Anpt ‘quipnient Require ing/Troubleshooting ....... AIA3. bieshooting . ‘esting/Troubleshooting ‘Testing/Troubleshooting «2.1 1e/ Troubleshooting ting/Troubleshooting . ting/Troubleshooting . Discriminator ‘Tuning Capacitor AXA ‘tuning Coil A3A8, ‘Tes Autotransformer A3A: Control Logie AIA2, Servo Amplifier A3A1 IS/AL AIASAL. Randswiteh ARAS. ‘Testing! Power Amplifier A3A4. ‘Testing /Troubleshooting Control A2, ‘Testing/Troubleshooting «. Frequency Synthesizer AIAG, ‘Testing /Troubleshooting ... Mixer AIA2, ‘Testing /Troubleshooting . Togie/Tx A1ASA2. Testing/Troubleshooting.... Reveiver-Transn is AIA1, Continuity Amplifier: C is ABA, Continuity ...0022. Page 4 4 1-48 a2 m4 2-6 2-7 2-26 2-48, 2-62 2-63 2-68 2-70 2-78 2-86 2-96 2-108 2-117 2-126 2-136 2-156 2-174 2-181 2-188 2-194 2-202 2-214 2-226 2-230INTRODUCTION line equip manual contains seconel and { 615. It includes a description of th Ist, and schematic: ttems of Radio Set AN/PRC-515 and sever pames are: ICLATUR: NOM Recelver~Transmitter Group OR-5007/URC Radio Receiver-Transmitter 1 Receiver-Transmitter Control C- ‘Amplifier-Coupler AN-5280/URC Storage Baltery 183-706/U Radio Set Harness M''-5167/1"R Antenna AS-5093/PRC-515 Handset H-5017/GR. Headset-Microphone I-5016/PRC- ~229/PRC-515 Electrical Power Cable Assembly CX Battery Charger PP-5267/11 Direct Current Generator G-5002/ PI Telegraph Key KY-503:1/PRO-515 Antenna AS-5094/PRC-515 Antenna Counterpoise AS-5095/ 1 ‘Additional ma nuals tat support [ts Radio Set AN/PRt 15 Operator's Nn Radio Test Set AN/PRM- 01 Radio Test Set AN/PIM 7/0 MI intentnee Manustl Battery Charger P1-! wtintenance instructions for Radio Set AN/PRC- it, maintenance procedures, illustrated parts ‘Throughout the manual, common names are used for nonmenclatured ll nomenclatured accessory'items. The common COMMON NAME recelver-transmitter group recelver-transmitter control amplifier-coupler battery pack frame whip antenna handset headset battery cable battery charger generator telegraph key dipole antenna ntenna counterpoise lio Set AN/PRC~515 inelude: ‘xi/(xii blank)SECTION 1 DESCRIPTION 1,1 PURPOSE Set AN/PRC-515 (figure 1-1) Is a backpack, single-sideband, high-frequency receiver- ganomitter that provides tactical voice and CW communications in the 2, 0000- to 29, 9999- MBs frequency range with a channel spacing of 100 Hz. 1,2 EQUIPMENT SUPPLIED Equipment supplied as part of Radio Sct AN/PRC-515, is shown in figure 1-2, and is listed in table 1-1. 1,3 ACCESSORY EQUIPMENT Accessory equipment available for use with Radio Set AN/PIC-515 {8 shown in figure 1-3 and Js listed in table 1-2, Figure 1-1. Radio Set AN/PRC-515 1-1Cin ie 1. RECEIVER-THANSMITTER CONTHOL cs3ta/URE. 2. naDIOnceeveR TRANSMITTER RT S0477UNC 2. AMPLITIEN.COUPLER ‘ANsz00/URe 4. nauin ser nanness. Mrsierencsis 5. STONAGE BATTERY 88.706 8. ANTENNA AS Sonam 515, ICANSET ANCROPHONE Migtemnesis A. HANDSET 8017/68 9. CLECTRICAL POWER CABLE ASSEMBLY CX-5229 PRESS igure 1-2, waorr017 Equipment SuppliedAT TEnY CHANGER Prs26z/U 2 OMKECT CUNMENT GEWEHATOR Gsoo2mne IS TeLccnarxey Kvsausenesis ANTENNA AS-SOO4/PRCSIS, Antrnna counTEnPOIse ASeooumests. racze017 Accessory Equipment 1-3qry NOMENCLATURE COLLINS, PART NUMBER [a Radio Receiver-Transmitter RT-5047/URC 622-2148-002 "1 Receiver-Transmilter Control C-5310/URC 622-253-003 41 Amplifier-Coupler AM-5280/URC 622-214-001 2 Storage Battery BB-706/0 629-6703-001 1 Radio Set Harness MT-5167/PRC-515 629-345-002 1 Antenna AS~6093/PRC-515 629-5702-001 1 Mandset 11-5017/6R 637-1952-001 1 Meadset-Microphone 11-5016/PRC-515 635-6148-001 1 Electrical Power Cable Assembly CX-5229/PRC-515, 629-3428-001 *These items make up Receiver-Transmitter Group OR-5007/URC (Collins part number 622-1407-002). ‘Yable 1-1, Equipment Supplied NOMENCLATURE COLLINS. PART NUMBER Battery Charger PP: 629-3416-003 Direct Current Generator G-5002/PRC-515 629-3415-001 ‘Telegraph Key KY-5033/PRE-515 Antenna AS-5094/PRC-515 Antenna Counterpoise AS-5095/PRE-515 622-073-001 629-5896-001 14 ‘Table 1-2. Accessory Hi1.4 BQUIPMENT SPECIFICATIONS preuency TANBE eee eee eee eee Woe verve eee ee power output oes sees eeeeeee pay cycle - + Recelver sensitivity ‘Audio cutpul 2+ - eee eee eee Total woight . . ‘Temperature range Operating +s eee eeeeeeee eee Operating altitude . . Operating humidity .......6. 2 to 29,9999 All In 0, L-kilz Increments, Upper sideband (USB), amplitude modulation equivalent (AM), and continuous wave (CW), 20 watts (high power) or 2 watts (low power) noml- nal peak envelope or average power into 50 ohms with 1,3:1 vawr. Continuous for 12-hour period at 1:9 transmit voice/receive ratio using one Storage Battery BB-706/0 4 seconds nominal and 7 seconds maximum (after frequency selection is made). -113 dB mW, 50-ohm rf input for a signal + noise/noise ratio of not less than 10 dB, -102 dB mW, 30% modulated, 50-ohm rf input for a signal + noise/noise ratio of not less than 10 dB. -56 to -26 dB mW into 600 ohms to develop rated rf output, 10 mW into G00 ohms, adjustable with volume + control, 22 to 30 V de (25.2 V de nominal), 60 watts nomi- nal on transmit CW and 1.5 watts nominal on receive (provided by Storage Battery BB-706/U). 12,7 key (28 Ib). -54 to 465°C (-65,2 to +149°F). ~60 to +75°C (-76 to +167°F). 3,048 metres (10, 000 feet). 95 percent relative humidity, 1-61,5 EQUIPMENT DESCRIPTION 1.5.1 Recelv. nsmitter Group OR-5007/UNC Receiver-Transmitter Group OR-5007/URC consisting of three units: Radio Reece Control C-5310/UNC, and Ampli together, these units are cleet controls ‘are located under « hin a compact lightweight receiver-transmitter 1047/URC, Receiver-Transmitte . When mechanically latched connected through mating counectore, All operating cover on the control, 1.5.2 Storage Battery 1706/0 Storage Battery RN-706/0 is a rechargeable nickel-cadmiui 1,8-Ah battery that latches beneath the receiver-transmiller group. It supplies de power for 12 hours of operation at 1:9 transmit volve/receive duly eyele. 1.5.3 Radio Sct Harness MY-5167/PRC-515, Radlo Set Harness AIY-5167/0RC-515 ix axed pack frame with adjustable straps, It can hold, simultancously. 2 recelver-transmitter group, a battery, and elther a Direct ‘Current Generator G 515 or a spare battery. The field pack, part of the pack frame, has compartments to store all the accessory items except the battery charger, 1.5.4 Antenna AS-5093/PRC-515 Antenna AS-5093/PRC-515 is 0 2.4-meLre (8-fool) whip antenna that can be easily folded for Storage. :It has a shock slsorhing mount aud detent positioning device capable of 90° front~ to-back movement in 45° increments. 1,5.5 Handset 11-5017/GR Handset H-5017/GR has an earpiece, a microphone, a push-to-talk (ptt) switch, and con- nects to the control by menns of a coiled cord, 1,5.6 Headset-Microphone II-S016/PRC-515 Headset-Microphone 11-6016/PRC-515 has two earpieces, a boon migrophone, a ptt switch, @ headband, and conncets to the control by means of a coiled cord, 1,5,7 Electrical Power Cable Assembly CX-5229/PRC-515 The CX-5229/PRC-515 isa 1. fool) cable and a canvas bag with an adjustable shoulder strap. It allows the Laltery to be carried under the operator's outer clothing during very cold weather. Battery Charger PP-5267/U is a portable battery charger that will discharge and charge six batteries simultancously. It operates [rom either 28-V de or 110-V ac power source. 1.5.9 Direct Current Generator G-5002/PRC-515 '002/PRC-515 is a hand-operated generator that can be latched up and the batlery to extend operating time indefinitely. Direct Current Generator ( between the receiver-transmitterrates are indicated hy lamps; green for normal operation and red for high rate. OSA PRG BG 4.5.10 Telegraph Key . sph Key KY~5033/PRC-515 is adjustable in te fol by means of 2 0 1) Mextble e feattached to the operator's thigh with a strap, ion and gap and connects to the con- land connector. ‘The telegraph key can 1.6.11 Antenna AS-5094/PRC-815 AS-5094/PRC-515 is a dipole antenna that consists of two 35, 67-metre (117-foot) jed wires, wrapped on individust! plastic bobbins, and allows long-range communica . Each wire has a 30, 18-metre (100-foot) throwing line attached. ‘The two wires are ected toa center junction, which is connected to the receiver-transmitter with a 1, 25~ metre (60-foot) coaxial feeder line. 1.5.12 Antenna Counterpoise AS-5095/PRC-515, ‘The AS-5095/PRC-515 provides a ground plane in low electrical conductivity areas. It con- sists of four 10-metre (32. 8-fool) braided wires and a 1.8-metre (6-foot) feeder cable eomected toa center junction. ‘The wires and feeder cable are wrapped on a plastic bobbin for storage. 1,6 OPERATING CONFIGURATIONS AND OPTIONS 1,6,1 Standard Configuration ‘The standard configuration consists of the receiver-transmitter group and the battery in- stalled in the pack frame, ‘The whip antenna is connected to the antenna connector on the amplifier-coupler, and the handset or the headset is connected to one of the audio con- nectors on the control, For CW operation, the telegraph key is connected to one of the audio connectors. This configuration is uscd for missions of up to 12 hours operating time and communications distances up to 25 kilometres (15.5 miles). 1, Spare Battery Option When missions of up to 24 hours operating time are required, a spare battery fs latched to the bottom of the operational Inittery. ‘The spare buttery is not electrically connected to the system, When the operating lattery is discharged, il 8 interchanged with the spare, 1.6.3 Generator Option For cases of isolated or extencled missions, a generator ean be used to maintain battery charge. The fencrator conneels between the recelver-transmitter group and the battery. A olip on the pack frame secures the generator erank, 1.6.4 Cold Weather Configuration ler, the battery must he kept warm to obtain sul- ry cable allows the batlery to be removed from the recelver- ried in a battery bag under the operator's outer clothing. During cold weather of 0°C (1 tent mission time, ‘The ltl tranamitter group and to be ¢1.6.8 Antenna Options th In dry oe: rocky ground plane for the whip ante laid out on the ground, and the fcedline con on the anaplifier-coupler. counterpoive provides a es of the antenna counterpoise are eclor is plugyed into the coaxial BNC connector For extended communication . the whip antenna is replaced with the dipole antenna, ‘The dipele antenna can be crected using available structures such as buildings or trees. Each end of the dipole ina habbin that allows adjustment of the length. Marking on the braided wire faeiliGites selection of the proper length for the desired operating frequeney. ‘The antenna fecdline is plugged into the coaxial BNC conncetor on the amplifier -coupter. 1,7 PIONCIP LES OF OPERATION Figure 1-4 is Set AN/PRC and figure: 1-5 is « bloc! eeviver=tra . including optional accessory item nsmitter group. 1.7.1 Receive Functional Theory The receiwer-transmitter group is in the receive mode whenever the push-to-talk (ptt) or CW key line is open. In the receive mode, the receive-transmit relays in power amplifier A3A4 and broadband amplifier ALA: bypass these amplifiers and connect the antenna rf signal to mixer A1A2 where il is converted to a 5-Mllz if signal, Mixer AlA2 consists of two mixer circuits and a 115-Milx filter. ‘The first mixer eireuit mixes the rf signal with a variable injection signal (117 to 145 MHz) from frequency syn- thesizer A1AG, The variable injection frequency is controlled by frequency selectors on the contra. ‘The output of the first mixer ix pasted Chrowh a 115-Nllz, bandpass filter to the sccond mixer. In the second mixer the L15-Nllz if signal 18 mixed with a 110-Mllz in- Jection signal to produce a §-Mily if signal, ‘The 5-Mllz if signal is fed to if/af amplifier ‘ALAS where it is converted to an audio signal, I/af, ampéitter ALAS performs USI or ABI detection depending on the position of the MODE selector @ the control. ‘The «detection circuits receive a 5-Mllz injection signal from fre- quency sythesizer AIAG. ‘The volume control on the control sets the audio input level of AIAG, ‘The receive audio ALAS ix coupled through a filler in the control and is parallel con nected to fre two audio connectors on the control, 1.7.2 ‘Trausmit Functional ‘theory The recelverr-transmitter roup is in the transmit mode whenever the plt or CW key line is closed. Dering CW operation, delay circuit in ALAS maintains the transmit mode during normal CW key open periods (1 second maximum). nal is passed through a filter in the control to if/ ter. In A1A5, the voice signal ia amplifiet On voice operation, the transmit 4 af amplifier A1AS in the radio receiv and applied to a balanced modul:tor, from frequency synthesizer ALAG to produce at 5-Mlz double-sideband signal, which ts passed thraugh a SSB filter to produce a single-sileband (SSB) signal. In AM, the 5-MHz carrier is reinserted alter the SSI} filter to produce an equivalent AM signal consisting of the SSB signal and a 5-Milz carrier, 1-8TRANSMIT AUDIO HANDSET Weso\7/GR OF. HANDSET MICROPHONE H-SOV6/PRC-S15 RECEIVE AUDIO RECEWER- TRANSMITTER, ‘anour ‘OR-B007/URC ' 1 1 ' ' 1 ‘ | reteqnani Key ! ' | fersourencsis 1 1 1 | | 1 1 1 | I L-—--—J t ! { ' potas 1 i | I ccc 7 omnect cunnent t | Generator ty it | G-soozrncsts | 1 antenna, 1 1 1 Lo4 sssosrncsis | L--{---4 ! ' 252 voc Ah 1 femal sronsce sarrene ! ‘orewa 4 | seme esis 1 ! aS Nore: ‘BROKEN LINES INDICATE OPTIONAL ACCESSORY ITEMS. vrs2609019 Figure 1-4, Radio Set AN/PRC-515, Block Diagram 1-9RECEIVER TRANSMIT CONTROL, a — er’ ‘URC [awe iFTER-COUPLER JAM-S2B0/URC. AS [RADIO JRECEIVER-TRANSMITTER RT-5047/URC. al | | | | Figure 1-5. Recelver-Transmitter Group or OR -5007/URC, Block Diagram ‘On CW operation, the CW key line is filtered in the control and applied to if/af amplifier ALAS in the radio recelver-transmitter. A CW keying circuit in A1AS applies a keyed 2-kB signal to the input of the balanced modulator. The 2-kHz signal is obtained from frequency synthesizer ALAG, Mixer ALA2 converts the 5-MIlz. voice or CW if signal to an rf signal of the desired frequex Mixer ALA2 consists of two mixers snd a 115-Mllz, bandpass Gilter. In the first mixer cir- cult, the 5-MIlz if sigmal is mixed with a 110-Millz injection signal from frequency syn- thesizer A1AG, ‘The output of this mixer is fed through a 115-MHz bandpass filter to the second mixer. In the second mixer, the 115-Mllz if signal is mixed with a variable injectis frequency (117 to 145 Mll7) from frequency synthesizer ALAG to produce the desired rf signal frequency. ‘The variable injection (requency Is controlled by frequency selectors on the control. 2-10ho output of mixer A1AZ is amplified to approximately 250 mW by broadband amplifier AS and applied to power amplifier AAT. Power amplifier AIAG amplifies the output to watts or 20 walls depending upon the selling of the POWER/PUISSANCE switch on the con= Gel. The output of power amplitier A3Ad is fed through bandswitch ASAS, discriminator , tuning capacitor AJA, tuning coil ATAB, and autotransformer A3AS to the antenna. ‘connected, the whip antenna is used. When the whip antenna is disconnected, a switch fa the amplifier-coupler selects he dipole antenna, 4.7,3 Tuning Functional ‘theory red on oF 2 new Erequeney i selceted, the control applies @ rechannel e to if/al amplifier ALAS. It/at the rechannel pulse and applies ff to frequency synthesizer A1AG and control logic A342, Frequency synthesizer ALAG erates 0 new variable injection frequency based on hinary coded decimal (bed) information feceived from the frequency selectors on the control, Control logic A3A2 also receives bed ey information from the selector switches and provides band-switching information to pandswitch ASAS. During synthesizer frequency changing and band switching, the transmit circuit is disabled, When hand switching is complete, control logic A3A2 advances to a standby condition. In this condition, frequency synthesizer ALAG and bandswitch A3AS are tuned to the new frequency, Init tuning capacitor A3A7 «ind tuning coll A3A8 are tuned to the old frequency. The receive cireuits are operational, but the transmit circuits are disabled. er power’ Final tuning is initiated by momentarily pressing the ptt switch or the CW key. Control logic ‘ASA2 now advances to the tune state and (1) a 2-kItz audio tone is applied to the operator’ headset; (2) a transmit siznal at the selected frequency fs supplied to the amplifier-coupler andl (1) tuning capacitor A3AT and tuning coll cy using the output of discriminator AIAG. PpLoximately 1.3:1 for 30 milliseconds, control logic ASA2 and the (ransmitter is unkeyed, Tuning Is now complete, When vawr remains below advances to the operate st Daring transmit operation, the vswr is continuously monitored and if It goes above 1.3:1 for more than 2 seconds, a retune cycle is initiated. In retune, the servo amplifiers ar eabled and the servo motors are driven hy discriminator phasing and loading Inputs, de~ rived from the transmitter volee envelope, until the vawr is below 1.3:1 for more than 300 milliseconds, ‘Transnut operation is checked hy 1 Lune incomplete monitor ciroult in control logte ASA2. A fault condition occurs if (1) the tune or retune cycle is not completed or (2) the rf voltage at the Junction of the tuning coil and tuning capacitor exceeds 850 volts peak. When a fault condition occurs, tuning stops, the transmit circuit 1s disabled, and an interrupted 2-kHz tone (beeping) is ‘applied to the operator's headset. A tune incomplete condition 1s reset by Feohanneling the frequency selectors on the control, 1.2.4 Recelver-Transmitter Group OR-5007/URC Detailed Theory '-5310/URC 1.7.4.1 Receiver—Transmitter Control A2, Refer to figure 4-14, schematics section of this manual, When Recelver-Transmitter Control C-5310/URC (control) is mec! ully latched to Radio Receiver-Transmitter RT- 5047/URC (receiver-transmitter), connector A2P1 is mated with A1A1J1 (as shown on figure 4-1, schenmitics section). ‘Connectors J1 and 32 of A2 are connected in parallel to Simultaneously accommodate any (wo of three audio 1/O devices: Handset I1-5017/GR, Meadset-Microphone 11-5016/PRO-5 h Key KY-5033/PRC-515, ‘The signals. of the audio 1/0 device(s), CW KE KRCV/XMYT AUDIO, are filtered by the LC filter qnnetwork connected to cach of the signal lines. ‘The control provides OFF control for the recelver-transmitter group (hire ical Linkage of x switch contact to the wiper arm, of potentiometer AZIL, When AzIti is rotated lo the maximum ebunterelockwise (cow) position, detent occurs (switch contact opens) and the +25.2-V de (SW) voltage is removed from A2P1-36 and -49, Rotating A2ii clockwise (ew) from the detent, closes the switch and applies ¥25,2 V de from A2D1-24 and ~30 to AZP1-3G and ~49. Further rotation of A2KI toward maximum ew increases the audio tin (AF GAIN HGH) of the af ampliter 8 of the receiver-transmitter. Rotating A2R1 cow decreases af gain, When +25.2V de is switched to A2P1-36 and ~19, the voltage is also applied to the lamp circuits of frequency elector switches AISI through ASG, ‘The switehes are then {lluminated when lamp teat switch A287 Is depressed and ground fs applicd, ‘This illuminates switches A281 through A2S6'when the operator needs light to read the frequency or wants to make a lamp check, Frequency selection is made by actuating the appropriate switches until the desired freque is read in the window adjacent to cach switch, ‘The Irequency switches provide binary coded decimal (bed) signals. representing the sclected frequency, to which the recelver- transmitter and Ampliticr-Coupler AM-5280/URC (amplifier-coupler) automatically time, Operating modes, USB or AM, are selected by switch A2S8. An open circuit at AZP1-23 selects the AM (USH) function, wh xround al AZP1-23 aclects AM. Operating power level, Ii PWR or 10 PWR, is selected hy swilch A289. A ground at A2P1-27 places the radio in LOW POWER (2 watts) operation, An open at A2P1-27 selects LOW POWER (22 watts) operation, A rechannel signal (ground) is applied to AZP1-38 (RCP) whenever one or more of ewitches A2Si through AZSG are actuated, 1.7.4.2 Radio Receive ‘Yransmitter Al, RT-5047/URC Refer to Cure 1-6. ‘The radio reeviver-tranamilier performs frequency translation and amplification of af to rf (transmit function) and rf to af (receive function) with five sub assemblies: if/af amplificr (A1A5), mixer (A1A2), broadband amplifier (A1A3), frequency synthesizer (AIAG), and power supply (A1A4)._ If/af amplifier ALAS provides af/If ampli- fication, modulation/demodulstion, if selectivity, «ind logic processing of control functions. Mixer A1A2 provides up snd down conversion for the received or transmitted signals, Broadband amplifier A1A3 amplifies the transmit rf to approximately 250 mW to drive the power amplifier circuits of amplificr-coupler A3, Frequency synthesizer ALAG generates and supplies injection frequencies to the mixer for up and down conversion, and carrier nj ection frequency and tone frequency to the I{/al amplifier. Power supply ALA4 converts +25, 2 volts de (SW) into regulated +13-volt and -5.2-volt de outputs for distribution to the other subassemblics. 1.7.4.2, Receiver Theory Refer to figure 4-14, schematics section, At control A2 the operator selects elther the USB or AM mode and the operating (requency. When AZ Is turned on, tuning 1s complete, the radiods unkeyed, and receive operation of Radio Set AN/PRC-51S 18 in effect, 1.7.4.2.1.1 Broadband Amplifier ALAS Refer to figure 1-1 in this scction and (igure 4-3 of the schematic section, ‘The received signal is coupled from amplifier-coupler A3 through chassis ALA1 to connector A1A1J3/ AIALP1-12 and on to relay ALA3KI-A2. With the radio unkeyed, relay A1A3K1 Is de~ energized and relay contacts A2/A3 and 82/183 are closed. ‘This routes the received rf from Pl-12 through the limiter and LC filter network to ALA1J3/A1A3P1-2, 4-12ad MIXER Ataz AMPLIFIER ALAS ius gi fet ne prurincansn Figure 1-6. Radio Receiver-Transmitter RT-3047/CRC, Block Diagram 1-13/1-14 (Blank)iaKER Aaa tealas amv fe Fes.t1.02 sesavoccm| 3 q q| al omy moueon. Figure 1-7. Broadband Amplifier (Keceive or Transmit), Simplified Schematic Diagram 1,7.4,2,1,2 Mixer ALAZ Refer to figure 1-8 of this section and figures 4-1 and 4-2 of the schematic section, The receive rf (AM or USB) is routed hy chassis wiring from broadband amplifier A1A3 to AlA1J2/A1A2P1-14, The control inputs supplicd to A1A2 arc XMT and RCV logic, and the AGC/ALC DRIVE from A1A5, During receive mode, RCV (XMT) logic at ALA2P1-5 is high and the XMT (TCV) Joyie at A1A2P1-6 Is low. ‘The RCV logic 1s applied to injection amplificr transistors Q® and QU, which in turn switches on diodes CR2, CR3, CRG, and CRE, The fixed and variable injection frequencies are now applied to the recelve up con- version mixer Qi and (2 and the receive down conversion mixer Q11 and Q12, The XMT logic awitches Q10 and Q14 ate off, which disables both transmit mixers. The receive rf (2-29. 9999 Mllz) (rom P1-14 passes through the low-pass LC filter, switching diode CR2, transformer ‘T'1, and on to the gates of the up conversion mixer FET's Q FET's Q3 and (4 neutralize the gate-to-drain capacity of QL and Q2, The re- celve rf is mixed with the variable injeetion frequency (117-114, 9999 MHz) to obtain 115- ‘MHz if, which is applicd to the 115-MIlx filler through diode CR3, ‘The 115-MIlz if out of the filter passes through diode CNG and transformer ‘TS to the hase of down conversion Rxor transistors (QUI and QI2. ‘The L15-Mllz if is mixed with fixed injection (LL0-MIlz) to Produce a S-Milz if, ‘The S-Mllz if (with upper and lower sidelainds reversed) is coupled by Wansformer T6 through diode CRS to P1-2 (iE OUT), 1-15wcrc ome fo = . ane + LOM ns ny ‘Sanit? Mdleewe Er mous Figure 1-8. Mixer (lteceive or Transmit), Simplified Schematic Diagram When the receive rf input signals are below AGC threshold, the electron flow is through i ductors L3 and L1G, bypassing diodes CR1 and CR7. As the rf Input signal increases, th: AGC/ALC DRIVE voltage at Pi-9 decreases, permitting conduction by diodes CR1 and Cl: ‘As the current of diodes CII and C7 increases, the rf and if signals are shunted to ground, reducing the signal gain, 1.7. 4.2.1.3 M/ALALASAL AM Recelve, Refer to figure 1-9 of this section and figures 4-1 and 4-5 of the schematic section. The IF IN signal is applied from A1A2P1/A1A1J2-2 to ALA1J5/ ALASAIP1-2. When in AM made, the 5-Milz if signal 1s coupled from ALABALP1-2 FIN), to the hase of amplificr switch transistor Q2, With the radio in AM mode, REVIAW togie (ground) st 12-0 ta upplied to the buse of transtotor Q2, biasing It ¢ and allowing the AM receive if to be applied to filter AM [ter FL and then on to a: plifier switch transistor QI, which is also biased on by +5, 2-volt logic (RCV. AM) P2-13, ‘Transistors Qt and QO are binsed off during AM mode. The receive if output of through if amplifier transistors Q21 through Q24 on to AGC/AM (cclor transistor Q25, ‘The detected af output 0 transistor Q25 is applied to the input of AN switch U3I} and to the AGC hang elreuit transistors Q29 through (232. As the collector current of transistor Q92 Increases transistor Q8 of the AIC/AGC DRIVE circuit, the output voltage of transistor Q6 ¢ creases. This deer s 11, L2, and L3 permits diodes CR CRT, and CRE to conduct, wh watin of transistors Q19, Q21, and Q stor QI prisses lied 1-16AIASAL jas | oF cam nian momen Figure 1-9, f/Al_ (ALASA1) Receive, Functional Block Diagram Proportionate to the received signal level. ‘The de vollage output of transistor Q6 Is also supplied to A1A2 from 1-13 (AGC DRIVE). The presence of RCV-AM lozic at the control element of switch USB switches the AM reveive audio to the oulput clement of the switch, ‘This audio is then coupled by capacitor C55 to the first audio amplifier U2A. The output of audio amplifier U2A is ap- plied to R134, and to P1-40 (AF GAIN IGM), which connects to variable resistor R1 (@L gain) of control AZ. ‘The audio level at the input to audio 0 switch U3A, is controlled by A2K1 and voice/dita gate, switch USD, Switch USA is gated by ROV MUTE logic. With the radio in normal receive operation, no tuning occurring, the RCV MUTE logic enables switch U3A and the audio is coupled by capacitor C61 to the second af am- plifier U2B, The receive audio ix amplified and coupled to ALASP1/A1A1J5-34 on to ALALJ1/A2P1-43 (CV AUDIL) for routing to the audio 1/0 device(s) connected to the control. b, USB Receive. Refer to figures 4-1 and 4-5, schenmatics section, and figure 1-9 of this section. ‘The 5: velve If is applica to ALAGAL on the Same signal Line that AM receive if i ive if ix coupled to switch transistors Q1 and Q2, With Q1 gated on by REVAN logic (P2-23), when the radio is in USB mode, the recelve Af output of Q1 is di pled to lower sidelaud filler FL2 (the sidebands are inverted In ALA2 80 lower sidelend ix the upper sidelamd), ‘Then the receive if passes through transistor Q20 when RCV. AM yiting logic is present. This couples the 5-MIlz If to if amplifiers, transistors Q21 through Q24. ‘The gtin of transistors Q20 through Q22 is controlled by AGC/ALG DIVE in the same manner ag noted in AM receive mode of 1-7operation, The if output of transistor (24 1s sent to AGC/AM audio detector, transistor Q25, Also, the if signal at the emitter of Q24 ix coupled to transistor Q28 of the SSB detector, which is comprised of transistors (26, Q27, «nd Q28, ‘The SSB detector 1s awitched on during USB mode by RCV"AN logic (I'2-12) which Is applied to the base of transistor Q27. ‘The 5-MHz injection signal (rom P1-21 is coupled to the base of Q2G, Mixing the injection frequency with the receive If produces the resultant USB af output from Q27 which Is then coupled ty enpacitor O54 to awitel UIC, Uuiring USI racelve mode, ewitsh USC te closed by RCV-AM logic and the audio output of USC is coupled to the audio amplifiers by capacitor C55, The USB audio amplifiers are the same ones that are used for AM operation. 1.7.4.2,2 Transmitter Theory The receiver-transmitter group is rcady to transmit after power is turned on, frequency and mode are selected at control A2, and tuning is complete. To transmit, enable the recelver- transmitter group keyline by (1) pressing the ptt switch on the headset or handset, or (2) by keying the telegraph key. Refer to figures 4-1, 4-6, and 4-14 schematic section, For voice operation, the PTT signal is supplied to ALASAZ (rom control A2 through the following route; A2P1/A1A1J1-39, through chassis A1A1 wiring to ALAIJS/ALASA1?1-23, and through ALASAL board wiring to ALASA1P2/A1ASA2P1-26, For CW keying operation, the CW KEY signal is supplicd to ALASA2 from control A2 through the following route; AZP1/AIA1J1-19, through ALAL chassis wiring to ALA1J5/ALASALP1-17 and through ALASAL board wiring to ALASA1P2/A1A5A2P1-20, For xmit audio (voice), the xmit audio signal is supplied to A1A5A2 from control A2 through the following route; AZPI/ATALI1-20, through chassis ALAL wiring to ALALJS/ALASALP1~15, and through AIASAI:-bourd wiring to ALASALP2/A1ASA2D1-29, 1,1,4,2,2,1 Logie/Tx ALASA2 Refer to figure 1-12 of this section and figure 4-6, schematics section, XMT AUDIO from P1-29 is coupled through FET Q12 to af amplifier U8B, Transistor Q14 and FET Q13 serve as a voice/data gain change stage (data is not uscd). The af output from amplifier UBB is ‘applied to P1-9 and to af amplifier U8A, ‘The audio to U8A is amplified and applied to AGC detector, transistor Q11. The AGC detector output voltage is applied to attenuators (FET's Q12 and Q15) to maintain the audio output at P1-9 at a constant level. Figure 1-10 of this section provides 2 logic. table for the various transnilt-recelve functions. In CW mode, the 2-KIlz audio (rom P1-10 passes through gate/tilter stage, FET's Q5, Q6, and Q16, and through af amplifier UBL with attenuators Q12 and Q15 at full attenuation. RC network C1 and 1X4 provides a delay to hold the radio in transmit mode for approximately one second after CW key is released, The rechannel pulse siymal at 1-24, which is momentary ground, causes capacitors C4 and C24 to be discharged by transistors (3 and Q4, respectively. ‘The output pulse at P1-3 (CP STRETCH is delayed hy the Lime constand of C4 and 18 and the pulse width is deter- mined by C24 and RG 1,7,4.2,2.2 I/AC ALASAL wsmit turns on balanced modu- ransislor (2: ‘he XMT AUDIO from P2-9 is. vith §-Nflz from P1~21 to produce a js vulpul signal from Ul is sent Refer to figure 1-10 and 1-11 ator Ul and transistor 3, applied to balanced modulato double sideland, suppressed through transistor Q5, diode ¢ ‘The lox 1-18PL pw NOTE: WHEN CW KEY IS DISABLED THE OUTPUT STAYS AT. ZENO AT PI FON APPROX, 1 SECOND, X +MORE THAN +45 O-SLESSTHAN OSV wrors er | ow PL PIN EY ‘2 x x ° x x ° x ° Figure 1-10, Logie/x ALAGA2, Logie Tables 1-9AIASAL " FS 35 | ax m0 Ee oe en taj ey DIO oemen | «| pee 4 —__| x nee phe mouse Figure 1-11, I{/Af ALASA1 (Transmit), Simplified Schematic Diagram ‘The if output from FL2 is amplified by transistor (3 and coupled to P1-2 (IF OUT). If AM ta selected at control A2, carrier reinsert gate, transistor Q4 and diode CR1, are gated on by logic from P2-27. This allows the 5-Mllz. carrier to be added to the SSB output of If amplifier Q3, producing an AM equivalent (AM) signal to P1-2. . Sidetone and Low Voltage Input. During transmit, the sidetone transmit audio is supplied to the headsct or the handact via the reccive audio circuits previously discussed, Refer to figures 1-12 and 1-13 of this scetion and figures 4-5 and 4-6, schematics section, There are three conditions when the sidetone gate (FET A1ASA1Q37) is biased on: When () tuning is tn progeces (TIP) a 2-kitz tone is heard; when (2) 2 coupler fault occurs, a. pulsating 2-kllz, tone is heard; or, when @) there Is forward power output from amplifier coupler (A3), audio is heard, ‘In USB mode FET A1A5A1Q37 remains on for the time constant of capacitor ALA5A2C3 and resistor ALAGA2R14 (approximately 1 second) after the absence of volee audlie. ‘The low voltage input (IAN) indieation occurs when +25,2 V de (SW) at ALASA2P1-25 becomes less than +22. 5 volts, allowing transistor ALASAZQI to conduct, This causes square-wave generator ALASA2UAA and AYAGAZUSA to oscillate. output is coupled throujzh R:I7 to ALASAZP1/ A ASALL2 of ALASAL to produce a low [requency clicking sound, If a coupler fault ocours during this time, a pulsating 2-kilz tone is heard, 1-20Figure 1-12, Logic/Tx ALA3A2, Simplified ‘Schematic Diagram and Logic Tables 1-21/1-22 (Blank)AIASAL \| Remsen ‘AIASAZ poe care | ausupva are any >t ese Figure 1-13, If/Af Amplifier ALAS (Prins. "+ Functional Block Diagram 1-23/1-24 (Blank)AIASAL ‘AIRS AR,b, ALC. Refer to figure 1-14 of this section and figure 4-5 of the schematic section, During transmit operation, the ALC stages of ALAGAL are enabled by XMT logic from P2-32 to switch transistor Ql1. When transmitting, noyative ALC voltage from ‘amplificr-coupler A3 is applied {rom P1-31 to the cmitter of transistor Q17._If broad- band amplifier A1A3 excccds approximately 300 mW, it develops a negative ALC voltage which is applied to the cmitter of transistor Q1G through P1-36, ‘The output of Q16 or Q17 causes transistor Q13 to start discharging capacitor C22, which causes transistor Q9 to begin conduction. As the conduction of Q9 increases, the output of transistor Q6 (ALC/AGC DRIVE to mixer A1A2) decreases, permitting diodes ALA2CRi and ALAZCR7 fo conduct. ‘This decreases the rf output from A1A2 to amplifier-coupler A3 until AS has the proper output level and is not overdriven, 1,7,4,2,2.3 Mixer ALAZ Refer to figure 1-8 of this section and figure 4-2 of the schematic section. During transmit, the switching logic at P1-5 and P1-6 switches the transmit mixers on and the recelve mixers off, The IF IN (5-MIlz, AME or SSB) signal is coupled by diode CR10 and transformer T8 to the up conversion mixer, transistors QUG and QIG, ‘The sum of 110- and 5-MHs frequencies (115 MHz) is coupled through transformer 7 and diode CRO to the 115-MHz filter, The filtered output is coupled! to the down conversion mixer, FET's Q5 and Q8, by diode CRS and transformer T4, cre the 115-Mllz signal is mixed with 117- to 144,9999-MHz variable injection signal from P2 to oblain the 2- to 29, 9999-Milz output, FET's Q7 and Q8 neutralize avasar a mevuar | m Fae Figure 1-14, AGG/AIC, Simplified Schematic Diagram 1-25the gate-to-drain capacity of FET's (5 and QG, The rf output of the down cosversion mixer is coupled through low-pase filter Inductors 1.1 and 1.2 and capacitors C1 and C2, to P1-14 (KMT RF) by transformer 3, diode Cl4, and capacitor C4. If the rf output {8 too high (as noted in ALC discussion), the ALt/ AGC DRIVE at P1-9 decreases, permitting diodes CR1 and CR7 to conduct, reducing the rf output, 1,7,4,2,2.4 Broadband Amplifier ALAS Refer to figure 1-7 of this section and figures 4-1 and 4-3 of the schematic section. The transmit rf output of A1A2 is applicd to A1A3 vin ALA2P1/A1A132-14 and ALA1S3/A1A3P1-2, With the radio turned on at the control, 125.2 V de (SW) Is applied to A1A3, and with the key line enabled by the ptt switch, keying relay Ki is energized and the +25.2 V do (SW) is ‘switched to the amplifier circuits by Q4. The incoming rf at P1~2 is passed through the LC filter network, a limiter circuit and on to the emitter follower stage, Ql, through the closed relay contacts, B1 and BZ. The emitter follower couples the rf to rf amplifiers Q2, Q3, and Q5. The 250-mW rf output of Q5 is transformer coupled by T1 through the closed relay contacts Al and A2 to Pl-12, The ALC detector, VR2 and CR8, provide a protective ALC bias to ALAS AIC elrcults that limits the rf output to approximately 300 mW if amplifier- ler A3 ALC should fall. ‘This Al OUT signal at 1-9 Is routed through A1ALI3-9 to ALA1J5/ALASALP1-36, The transmit rf output from A1A3 Is supplied to amplifier-coupler ‘A3 through A1A3P1/A1A1J3-12 of A1A3 and ALAIP1/A3J1-36. 1,7,4,2,2;5 Frequency Synthesizer ALAG Refer to figure 1-6. Frequency synthesizer A1AG provides a variable injection frequency and a fixed injection frequency to A1A2 plus two fixed frequencies to ALAS during both receive and transmit periods of operation, ‘The variahle injection frequency is a frequency in the 117 Mliz to 144, 9999-Milz range, varinble in 100-Iiz. increments, the specific frequency being proportionate to the operating frequency selected at the control. ‘The fixed injection frequency to the mixcr module ix 110 Alllz, ‘Two fixed frequencies are supplied to A1AS. One is the 5-Milz fixed injection frequency and the other one is the 2-Kllz tone signal, ALA6 also supplies the transmit inhibit logic output (XAT INIl) in response to the power on or frequency change logic (RECIIANNEI,) from control AZ, Control A2 also provides the bed frequency selection logic and the USI logic inputs to AIAG. To process the above logic inputs and to generate the above output signals, the frequency synthesizer uses the seven sulmssemblics shown on figure 1-6. For frequency generation functions, four phase-lock loops are used, Refer to figure 1-15. One phase-lock loop is used to gonerate the fixed! Injection frequency (110 Mllz). The eemaining phaso-lock loops, the low frequency, the converter, and the high frequency phase-lock loops, are used to generate the 117-144, 9999-Millz \ariable injection frequency. The low frequency phase-lock loop (LFPLL) uses the bed logic from the control and provides the bed selected frequency within the 1.0 to 1,0999-Milz. range (o the converter for translation to a higher frequency within the 111 to 111, 0999-Nllz range. This translated output from the converter is applied to the high frequency phase-ock loop (HEPLL) for (ranslation fo a higher Lrequeney. During locked conditions, the TIEPLL ts controlled ly the sample cul hell pha. ar setae, ‘The output frequency of the HEPLL mixer (variable from 6-23.9 Milz), the resultant frequency of mixing the output frequency of the converter (L11-111, 00 AIT) with the IEPLI. veo frequency (117-144. 9999 MHz), Ie sampled by the sample intin the correet veo frequency. But, when a new frequency acquisition hy ( quired (initiated by frequeney change at control A2), control of the IFPI. veo is switched to the frequency/phase diseriminator of the variable divider to acquire d phase tock an the new frequency. As shown in figure 1-15, the variable divider is controtled by bed logie from the control, thus, a frequency 1-26GENERATOR AIAGAI FREQUENCY CONVERTER LF PHASE LOCK LOOP Figure 1-15, Frequency Synthesizer A1A6, Block Diagram 1-27/1-28 (Blank)HF GENERATOR AIA6AZ LF GENERATOR AU HF PHASE LOCK LOOP a ‘CONVERTER Aa | [aie [| sss | | ]veRiABLE FREQUENCY 1 || [ower a2 ee LL [=shange at the control causes the bed logic change to switch on the variable divider. This {nitintes the loop action necessary to achieve digital phase lock on the new frequency by the frequency/phase discriminator ant inhibit the transmit (XAIT INI!) functions during frequency acquisition (rechannel cycle). When digital phase-lock occurs, voo control is transferred back to the sample and hold phase detector and the variable divider 1s switched off, This puts the hf phase-lock loop Imiek in 1 locked (normal) condition ‘The fixed divider operates in conjunction with the frequency standard and supplies the follow- ing frequencies to the radio receiver-transmitter. ‘The 5-Mlls is supplied to ALAS during all modes of operation execpt AM receive when the 5-Mllz. signal is switched off, The 2-kHz tone signal is supplied to ALAS during all modes of operation. The 100-kils frequency ts supplied to the HFPLL. ‘The 25-kilz Crequency is applied to the variable divider, and the 100-Hz frequency is supplicd to the LFPLL, a, Froquoncy Standard ALAGALAI, Refer to figures 1-6 and 1-15 of this soction, and figure 4-7, schomatics section. ‘The frequency standard subassembly circuits are com! prised of the frequency standard gonerator (10 Alllz), which Is a temperature-compen- sated, crysinl controlled oxcillator (texo), and a fixed injection frequency generator, whieh is a veo with a xample and hold stage. The texo consists of crystal Y1, transis tors QI and Q2, varactor C2 and temperature compensating networks RT1, RT2, and RT, The trinimor capacitor is provided to compensate for the aging of the crystal and the selectable componenta (ux noted by schematic note 3) are to be selected at final test, When the ralio power is turned on, the texo is energized and supplics a stable reference frequency of 10 Millz from the impedance matching output network of Q1 and Q2 through the buffer-driver stage (23 and Q4 to the sample and hold reference pulse shaper Q5. ‘The 10-Milz reference frequency output from the impedance matching network {s supplied to frequency converter ALAGALA4 and the 10-Nillx, output (rom the buffer-driver is applied to ALAGALA2. ‘The veo circuit consists of the oscillator, FET Q9, varactor CRI, and switch transistor 8, With the radio power on, the USB logic input from ALAS switches transistor Q8 on to provide the correct de voltage Level for the oscillator to operate at 110 Milx.. ‘The 110-Killy output of the veo is applied to the sample and hold clreuit, CR7 and Ch, throuh buffer Wb and Q7, ‘The rectifier diodes CR7 and CR8, provide a nogative de voltage (ecdlack to the vco that corrects the frequency compared to the 10-Mllz reference frequency al the primary of TL. The 110-Mllz output from the veo, 110 Alllz INJ, is applied to ALAZ xs an output from buffer-deiver Q10 and connector ALAGAIAIPA, The 45.2 V de fe supplied to freauency standard ALAGALAL from power supply ALA4 via AMAL and ALAGAIA2, ‘The 111.5 V de ty supplied by voltage regulator ALAGAZAL via ALAGALAZ, (Refer to fijgire 1-11, schematics section.) b, Fixed Frequency Divider ATAGAIA2, Refer to figures 1-6 and 1-15 of this section and figure 4-8, schemation section, ‘The Cixed frequency divider consists of a notwork of frequency dividers and a gited transistor emitter-follower circuit that applies the 5-Mits Injection frequency outpul to AAS. The 10-Allz. reference frequency is supplied by ALAGAIAI to transistor driver Q2. ‘The output of the driver is a 10-Mlllz square-wave clocking signal tha 2:1 frequency divider, UIA, ‘The outputs of the divider are two is useal lo elock the 8:1 divider stage, ULB and U2, and the other is coupled lo emitter-follower Qt, which is controlted by the RCV logic from 11-6. (Ql in turmeaton hy the REVEAR logic thurimyg all modes of operation QU in turned off and the §-MIlz output is cut ULB, UZA and U2, is divided by 5, to 1 MHz, iz, hy. UA. One 100-Kilz output is applied to HEDLL, ATAGAZA3, ‘The divider U3B ix con nd 5, providing S0-Kllz oulput and a 20-Kllz except the AAI receiv off. ‘The S-Mllz input to th and further divided by 10, to 100- divider USB and one ix supplied figured to divide the 1-29output. The 50-kllx: output is divided hy 2 by UAA to provide a 25-kHs frequency to the variable divider sulmascmbly. ‘The 20-kilz output [8 applicd to divider USB and divided by 10:to produce a 2-klix output, ‘This is coupled by capacitor C2 to P1-6, ‘The 2-kllz output from divider USI Is also applicd to 2:1 divider U¢B and to 10:1 divider USA, and converted to 100 Iz for application to LFPLL A1AGALAS. ‘The +5,2 V de Is supplied hy ALA4 und the +11,6 V de 1s provided by ALAGARA1 (figure 4-11, schematics scction). Lf Phase-Lock Loop ALAGAIAS, Wefer to figures 1-6 and 1-15 of this section and figure 4-9, schomatics section. ‘The LFPL1, supplics to the frequency converter ALAGALA4 a frequency that can be varied from 1.0 MHz to 1.0999 MHz in 100-Hz increments, The specific frequency within the 1,0- to 1, 0999-MHz range 1s determined by the bed logic input to connector P1 from control A2. ‘To generate the 1. 0- to 1, 09999 Mz frequency, ALAGALA3 cmploys a veo stage, a (requency/phase detector stage, ‘a sample and hold phase detector stage referenced to 100-Hz from the fixed frequency divider. The output frequency of the veo is controlled over the above range by the de voltage applied to varactor Cit2, Therefore, when a frequency is selected at control A2, the bed logic 1s applied to the frequency discriminator variable dividers U6-U9, They establish the proper logic Input to the sample and hold switch, Ul, to adjust the de voltage to CRZ for an oscillator output (requency equivalent to the binary coding from control A2, ‘To mainlain veo frequency rlability, the output of the vco ts looped back to the phase detector, UIA, through (cedinck driver Q7. The output of the fre- quency discriminator 1s applicd from NOR gate USA to the phase detector U4A. The output of U4A Is a logic output with a variable duty cycle that controls the duty cycle of the output from UG to the sample and hold phase detector, U1. Also applied to U1 is the ramp vollage supplied by the ramp generator, transistors Q1 and Q2. The ramp gener- ator is driven by the 100-lIz reference signal from ALAGALA2, When Q2 is on (the input 1s high), capacitors C1 and C2 are held at zero. When the Input 18 low Ql is turned off, allowing C1 to charge toward 14 V de at a constant rate until Q2 is turned on by the 100-11 inpul. ‘The ramp voltage Is sampled by the #1 and $2 signals at the duty cycle rate which is a function of the phase difference between the frequencies applicd to the phase detector, U4A. The fl signal gates (samples) the ramp voltage through the (Irst petrt of switch Ui. ‘The §2 signal follows and gates the ‘sampled ramp voltage through the second sevtion of switch Ul for filtering. The sampled ramp voltage, alter filtering, becomes the vco control voltage and 1s coupled to varactor C2 by source followers @3 and (4. Increasing the veo control voltage, Increases the veo Frequeneys decreasing the contrat voltage, decrenses the veo fre- quency. ‘Therefore, the veo control voltage, heing a function of the frequency difference between the compared (requencics, increuses or decreases the oscillator frequency to correct the output freques ‘The +13 V de voltaxe ts supplied! hy ALAd and the +11.5 and 414 V de voltage ts provided by ALAGAZAL (figure 4-11, schematics section). Frequency or AIAGAIAL, Itefer to figures 1-6 and 1-15 of this section and figure 4-10, schematics section. ‘The trequeney converter generates a frequency within the 111.0 £0 111, 0999-Aillx range, The trequency is supplied lo ALAGAZA3 for genera~ in} ‘that In supplied to AIA2. ‘The specific output frequency of the conv ea! hy the outpat of frequeney/phase detector (F/6 DET) UL and U2. An output tresquency between 111, 0-111, 0999 Miz Is generated by the veo, 2. ‘The veo control voltage (0 CRI from the F/f detector is a function of the phase difference etween the output frequenes of the oscillator and the input fre~ quency from ALAGATAS, boll of which are applied to the F/fideteotor, UL, The input frequency to the E/# deivetor from ALAGATAS, 8 previously noted, ie determined by the bed logic from the control. ‘The olher inpuit Frequency to the F/B detector 1-30(1.0-1, 0999 Mil2), representing the vco frequency, is developed in the following manner. The 111, 0-111. 0909-Rillr. vco output is applied to buffer Q6 and coupled by C36 to gate G2 of mixer Q5, ‘The 10-Alllx. input from the frequency standard is applied to amplifter- buffer Q3 and coupled by C26 to XJ1 mulliplicr Q4 which provides the 110-MHz input to gate G1 of mixer Q5. ‘Ihe resultant output frequency, 1, 0-1,0909 MHz, ts supplied to squaring amplifier Ql. ‘The 1,0-1,0999-Milz square-wave output of QI is applied to the input of F/8 detector UIA.” ‘The two frequencies are compared by the F/# detec- tor to develop a square wave pulse train at the output of U2 with a duty cyole that is a function of the phase difference between the compared frequencies. The output of U2C is applied to the low-pass filter network where the ac component is filtered out and the de voltage becomes the veo control voltage. This 1s applied to varactor CRI to vary the veo frequency as necessary to decrease the phase difference to achieve lock-on, ‘The +13 and +5, 2 volts de voltage is supplied by ALA4 and the +11, 5 volts de comes from A1AGA2A1 (figure 4-11, schematics section). HE Phase-Lock Loop ALAGA2A3, Variable Frequency Divider ALAGAZA2, and Voltage Regulator ALAGAZA1, Refer to {igures 1-G and 1-15 of this section, and figures 4-11, 4-12, and 4-13, schematics section. ‘The purpose of the HFPLL is'to generate a variable injection frequency within the 117 to 144, 9999-MIlz range for application to mixer ALA2 (Cigure 1-6). ‘To accomplish this, ALAGAZA3 requires the 111.0 to 111, 0999- ‘Mis input from A1AGA1M, the 100-kllz signal from ALAGALA2, and the phase/lock control signals from A1AGA2A2, During locked operations (normal operating conditions with power on and all Luninys complete), the frequency generating ciroults of ALAGAZAS. operate independently of ALAGA2ZA2 and ALAGA2A1, ‘The IIFPLL (figure 4-13, schema- tes section ) consists of the vco, Q104 and varactors CR101 and CR102; the sample and hold detoctor, Q3; the mixer, 7; and the associated buffer stages for the veo and mixer output signals. ‘The output frequency of the veo is actively controlled by the de control voltage applied by the sample and hold phase detector to the varactors. This detector de output is a result of the sampled output frequency of mixer Zi. Two fre- quencies are applic! to ZI, the 111-111, 0909-Nllz reference frequency from ALAGALAG and the 117-144, 9999 Alllz, output frequency of veo Q104, to develop an if within the 6-33, 9 Miz range (4--Millz. above the 2-29, 9999-NIllz. operating frequency selected at control A2). ‘The output of the mixer i® passed through the low-pass LC filler network to the aquaring amplifier cireuils of QG and Q7 for application to the sample and hold detector stage. ‘The 6-3.1-Nillx signal is mixed with the 100-kllx input from ALAGALAZ in the secondary of transformer Tl. ‘The resultant 6-33. 9-Mllx signal is rectified and filtered by the ciruits of C13 and C4 and QS of A1AGAZA3. This becomes the veo de negative feodinck vollage that ix applied to varactore CII and CI102 of ALAGAZAS, The de voliage varies the eaptcitance of the varactors, raising or lowering the veo frequency as necessary to kecp the phase error in the hold-in range. ‘The if output from 7:1 Is also applied from if amplifier Q7 to squaring amplifier Q5, the output of which is routed to ALAGAZAZP2-2 (figure 4-12, schematics section ). During the locked condition deseribed above, the variable divider is inoperative, therefore, the if input has no effect, However, when the radio is first turned on or a Rew frequency is selected! at the control a rechannel logic signal is initinted by control AZ, This starts a tun cle within the radio thal ineludes switching (on or of of logic 1 and #5 V de to various circuits of ALAGAZA2, ‘The rechannel logic (RCP Ti) is supplied (rom ALASAZMI~33 to ALAGAZAIP 1-3 via ALASAL and chassis ALAL, When the J xin in enabled al ALAGAZA1PI-3, 2 ground {8 applied to Pulse stretcher circuit U2 of ALAGAZAL resulting in conduction ‘of squaring amplifier Q7. Conduction of Q7 establishes the following events; (1) Q4 Lo conduct, (2) QS to conduct, (8) +14V de potential fell at switch function of ALAGA2A3, (4) Q8 ceases conduction, (6) Q6 to conduct. ‘The conduction of Q6 applies 2°ground poten= pin ALAGAZALI2/ALAGAZA2N2-5 (5 V de CUNTROL line), A ground 1-31on this pin forward biases scrics control switch Q2 of ALAGAZA2 therely enabling the logic 1 and +5 V de function. These two functions are enabled as long ax control transis- tor Q2 is held on by the 5 Vae CONTROL signal from ALAGAZA1, Wheaa LOCK (LOCK-0) pulse occurs on connector pin ALAGAZAIP2-3, the § V de CONTROL line ts disabled and Q2 ceases conduction, ‘This disables logic 1 and +5 V de om A1AGAZA3, Refer to figure 4-12, schematics section. ALAGAZA2 performs the frequemay/phase dis- ‘crimination and vco contro! functions for the hf phase-lock loop in a manner aimilar to those functions previously covered for ALAGA1A4. When logic 1 and +5 V deis enabled as a result of a rechanncl pulse, the variable dividers, U2-US of ALAGA2A2, reseive the bod Jogic signals from the control. ‘The hed logic, representing the aclected freqency, 1s processed for compirison with the logic output of divider U1 (6-33.9 MHz), representing the HFPLL voo output {roquency, to determine the frequency and phase differenes with reference to the 25-Kiz signal from ALAGALA2 via ALAGAZA1, The phase difference oxtput from the frequency/phase discriminator, U1O through U12 of ALAGAZA2, is applied tothe PHASE. signal line, ALAGA2A2P2-4, the duty cycle of which is a function of the phasedifference between the compared frequencies, Refer to figures 4-11, 4-12, and 4-13, achematics soction. ‘The PHASE sigmal at ALAGAZA2P2/A1AGA2A11'2-4 in applied to the pulse shaper transistor, AIAGAZAIQ3. The ‘output of ALAGAZA1Q3 is applied to FET ALAGAZA3Q8 for filtering and conversion to a de veo control voltage. ‘The de level, proportionate to the phase difference, 18 applied to the varactors to retune the wo to revlice the phase difference until lock-in { acikeved. When lock-in occurs, the frequency phase discriminator of the variable divider (Cigtre 4-12, ‘schematics section) provides a 1OCK signal at ALAGAZAZP2-3 from NOR gue ALAGAZA2UGB, which is routed to Inverter ALAGAZA1UZA and coupled to the pulse shaper anglifier atage, Q7, Q4, Q8, and G9, of vollaze regulator ALAGAZAT. One output from A1AGA2A1Q4 Is supplicd to ALAGAZA3 (SWI'TCII signal) to turn off FET ALAGAZASQS, ‘This transfers the control of voo ALAGAZA3QL04 (rom ALAGA2A2 to the sample and hold circuits of ALAGA2A3, ‘The other output from ALAGA2A1( is amplified hy ALAGA2A1Q9 und applied as a cut off signal to switch transistor ALAGAZAIQ6 as previously discussed In this subsestion (e). When a frequency change is initiated at the control, the bed logic is processed by ALAGAZAZ to provide a transmit Inhibit signal (SIT INIIBIT to ALASA2PI~22 (o prevers transmission during the tune cycle of the 5.2 volts de at ALAGAZA2-11 18 supplied by ALA4, Refer to figure 4-11, schematics section. In addition to the circuits already @scussed, AIAGA2A1 provides remulating clreuits for the +11.5 and 434 volts de voltngeas well as signal Interface between the various aynthesizer subarwembltes as shown on gure 4-11, The +14-volt de regulator consists of serics regulator transistor Qi, reference voltage regulator Vi, and comparator U111, whlch is connected to the output voltage divider 1t3, R4, and R12, and the reference voltage divider, VII, R10, and R11, The collector of series regulator QI is connecter to 125,2 V de (aw and ft). A change in the +14-volt de output appears asx voltage change aeross voltage divider K3, R4, and R12, This change ts compared with the reference voltage by the comparator ULB and reflected aa a bias change at the luse of series regulator ase In bins reflects an increase in the output voltage. Consequentty, the reduces conduction of QI which reduces the output voltage until 11 V de ce manner, a decrease in bias reflects a decrease in the output voll: he eutput voltage until the +14-volt output level is r The 111, 5-volt voltage regulator, 2, V3, and BIA, are connected to the reference vallage divider VIUL, 110, and RL, and 411, 5-volls de divider R7, R8, and RY. “The cx connected to +13 volis de, and the con- trol circuiis operate in the sa as QI to provide a regulated +11.5 velts de output. 1-32‘The +14~ and +11, -volt de outputs are distributed to the various frequency synthesizer sub- assemblies as shown on the voltage regulator schematle diagram, figure 4-11, 1.1,4.2.2,0 Power Supply A1A4 Refer to figure 1-16 and 1-33 of this section and figure 4-4, schematics section. Power supply A1A4 provider related! 113 volta and 15.2 volts de outpuls from a +25, 2-volt de source (battery). ‘The routing of source voltage 1s shown on the power distribution diagram, figure 1-33 of this section. The 113 V de switching rogulator circuits consist of series switch transistor QL, fly-inck diode CRI, control transistors Q3, Q4, QS, comparator transistors Q6 and Q7, sand reference vollage regulator VR4, Transistor Qi conducts in 14- to $5-usec intervals in response to bias changes effected by the comparator, Q6 and Q7. If the sampled output voltage applied to Q6 is high compared to the reference voltage applied to Q6, the series switch transistor Is saturated for roduced periods of time during ita operating intorval by the reduced on-LUme of the control transistor @3, ‘The on-time of QS is reduced by the increased bias voltage [rom the Darlington pair of transistors, Q¢ and QS, which reflects the voltage error (high voltage) determined by the comparator Q6, During the conduction cycle-of series awich QI, the reduced current flow causes the output voltage to decrease toward the reference level unlil the correct output (+13 V de) is reached. Con- vereely, if the output voliage decreases, the effective bins reverses to Increase the conduc tlon time of Qi and raise the output voltage to the normal lovel. Transistor Q2 provides overcurrent protcetion for the 113 V de regulator network. = mee Figure 1-16, Power Supply ALAA Simplified Schematic Diagram Las‘The +5. 2-volt de regulator network is comprised of series ewitch Qs, contraletreuits Q9 and Q10, comparator Q11 and Q12, and reference voltage regulator VR4. ‘Th.soperation of the 45.2 V de rogulator 48 sivutlar to the operation of the +13 °V de regulator. ‘Transistors Q13 and Q14 provide overcurrent protection for the regulator. 1.7.4-2.2.7 Receiver-Transmiticr Chassis ALAL Refer to figure 4-1, schemutics section. The receiver-transmitter chassis ‘as elght connec- tors, Ji through J7 and P1, and a number of filtering capacitors. The eight: wnectors pro- ‘vide interconnection hetween modules ALAZ through ALAG, control A2 and amglifier-coupler A3. A de filter clroult for +25.2 V de (SW) Is also provided. The filter ctrealt, Qi, capaci- tore C1 and C2, and resistors Iti through R3 are energized when 425.2 V do #W) is awitohed on at control A2, The 125.2 V de (SW) turns on Qi. This results in 2 +25, 2¥ de (SW and FLTR) output from the filter network, Cl, C2, and Ri through R3, to connectr J6 of ALAL, ‘When the +25, 2 V de (SW) is switched off at control A2, transistor Qi is turmad off, cutting off the +25.2 V do (SW and FLTR) to JG. 1.7.4.3 Amplifior-Coupler A, AM-~5280/URC 1,7.4.3.1 Transmit Theory Rofor to figure 1-17. Hower amplifier A3A4 of the amplifler-coupler ts a thuve stage push-pull class AB broadixind amplifier with a minimum power gain of 23.5 «i, ‘The ampli- fier is designed for a maximum required drive of 100 milliwatts, and 22-wats output, An ‘output of 22 watts allows for antenna coupler losses, and guarantees full 20-watts output ‘when fhe antenna coupler is tuned to a 50-ohm load,” ‘The power amplifier cambe operated at ‘either 20- or 2-watts output. ‘The output level is selected by a switch on contol A2, A thermal switch In the power amplifior monitors the temperature of a heat sink. In the ‘event a safe operating temperature is exceeded, such as by over extending thu duty cycle, the ALC ciroult automatically limits the output at 2 watts, ‘The fully automatic antenna coupler is capable of tuning an 8-foot whip and St-ohm antennas over the 2- to 30-Milz frequency race. ‘The coupler will also tune long wireand other whip antennas at selected frequencies. ‘Tuning time is 4 seconds typical and 7 secmds maximum. ‘Tuning elements include servo~iriven clements (A3A7 and A3A8) that providetine tuning and frequency hand awitched clements (AIA), Elements within A3AS are used to translate ‘antenna impedances to within the tuning range of the servo-driven elements, 3A7 and ASB, 1.7.4.3.1.1 Power Amplifier ARA4 Refer to figures 4-18 and 4-19, seh transmit modo, rf is applied (1 Since the PA KEY is low and matics section, and figure 1-17 of this sestion, In radio receiver-transmittor Al to rf sulzs.sembly ASA4A1. 5.2 V dle (KEYED) Is enabled in transmit mocie, rf is passed ‘AMAIAIRI (0 transformer AIMAIT1. The fis amplified by a three at plied fo oulpul core AIMALPL, Each of Une three amplifier stages of ASMAL is transformer coupled to the next stage. The predriver stage consists of transistor palr (21 and G2, the driv consists of Q5 and (6. The 76 to bias/control ABAIAZ, the proper de bins levels to ‘AB amplifier operation. Thi ‘A3AS. 134iar ep outie ‘Avrornansr omen = = SEE] Sue ee = | F Ld 4 t ' 1 L t ' t t H I ! qu Figure 1-17, URC, Block Diagram, Her-Coupler A’, AML 1-35Power amplifier ALC (automatle level control) Is derived by sampling the rf drive supplied to discriminator AAG. ‘The resulting dc signal from the ale detector on the discriminator is fed to an op-amp on servo amplifier A3A1. ‘The op-amp produces 0 VIC when the output of the rf amplifier Is 1/2 dit or less below 20 walts and approximately -8 V de with an rf output +1/2 dB above 20 watts. 1,7,4.3,1,2 Bandswitch ASA Refer to figure 1-17 this scction and figure 4-20, schematics section. ‘The bandawitch ‘automatically selects the proper frequency Ixind filler upon recelpt of Information from control logic A2A2, ‘The Land swilchex! {liters are used to provide harmonic rejection in the transmit mode. The filters arc low pass filters and are selected approximately every 1/2 octave for each of the eight bands. The Lilter element values for each band are selected to give the best possible harmonic suppression for that band. The number of filter elements in some bands is higher than actually needed for harmonic suppression, this reduces the bandpass ripple to keep the vswr low at the higher (requencles and maintains optimum efficiency. Frequency and logic {rom control logic A3A2 applics a logic high to the appro- priate servp Land contact of awitch 1. ‘This logic high enables transistor switch A1Q2 which actuates relay A1K1 and applies 125.2 V de to bandswitch motor Bl. ‘The motor runs and rotates switches Si, S2A, and 83 unlil S1 switches off of the logic high contact and opens the motor elrcuit, This dcencrgizes AIK1 and stops the motor. Simultaneously, SZA and 83 have rotated to contact positions corresponding with the activated frequency band. This connects the appropriate handjass filler (1 of 8) to the rf signal path, ‘The amplified rf from the power amplifier is now able to pass through S3 to the proper bandpass filter and through S2A to discriminator A3AG. The bandswitch also drives xwitch S21) which applies a ground to the center tap of the variable tuning coil (A3A8) if the frequency is greater than 12 Milz, Bandswitch motor Bl is mechani- cally coupled to the wafer switch in nsformer AJAY, While the motor is running the band logic sclects the correct qu(put network in A3A9, When the motor stops running (relay AIKI deenergizce), ground is removed from the Land switch complete output (ASASP1-14), ‘This logic output tells contro! loxic extrdl ABAZ that the Land switching process is completed. During the amplifier-coupler tun ogie low from the tune in progress (TIP) ciroult aetuates relay ALK2, ‘This 1 Istor across the output (rf line) until all tuning Is completed. ‘The TIP resistor is located on Ad. 1,7,4.3,1.3 Dis Refer to figure 4-21, schematics section. ‘The discriminator is 2 device that amples input rf power, voltage and current to the amplifier-coupler and develops de error signals that are related to the Impexkince of the luad and the power to the load. ‘The loading discrimina- tor develops a de error voltage that Is proportional to the magnitude of the impedance with respect to the normal $0-ohm impedines. ‘The phasing discriminator develops a de error signal that 1s proportional (o the pluise angte between the renetive and resistive portions of the load imped lected power detectors are wsed to determine the start and completion respectively of the tuning sequence, xilor AZAG a. Loading Discriminator, 1 ing discriminator compares th comparison creates an sig the impedance of the rf cireuit snd of ABAGAL and AXAGAZ, Refer to figure 1-18, The load- le of the rf current with the rf voltage. ‘This ‘output Ual is proportional to the difference between ohms. aasecegrovee seeing rontie vo ea secure vee mason Figure 1-18. Loading Discriminator, Part of ASAGA1 and ASAGA2, Simplified Schematic Diagram When the impetanee of the rf circuit is 50 ohms, there is no error signal developed. When the rf elreuil impedance ix greater stn 50 ohms, the error signal is positive. ‘When the rf circuit impedance is less than 60 ohms, the error signal is negative. RE Line current (i1) Induces 2 voltage (cg) across transformer T2, When diode CR3 is forward biased, the current through resistor 2, diode CR3, and transformer T2 _ develops a voltage (¢3) across 1R2 that Is proportional to the rf line current, Line voltage is sampted by a voltae divider consisting of C15 and C4. When diode CR1 is reverse biased, the current through RI develops a voltage (eq) across Ri that is proportional to the Ff Line voltage. C15 is factory adjusted so that the volkyze avross R2 is equal to the voltage across RI when the impedance of the rf cireuit is 50 ohms. When the rf etreuit Impesta ine voltage tends to dec the increased current {lo} it Is proportional to the is lens than 80 ohms, the line current increases and the cise. ‘This causes the vollage across R2 to increase due to '2, ‘The vollage aeross Iti tends to decrease since The voltage difference across RZ and Ri develops 1-37‘a negative error signal output. Wh the inverse Is true, and a positive error signal is developed. b, Phasing Discriminitor, AJAGA: aul part of AJAGAL, Refer to figure 1-19. The phasing discriminator in amplifier-coupler A3 develops a de error signal that is pro- portional to the phase shift between the rf voltage and the rf current, When the antenna ia resistive, the line current and the line voltage are in phase, and the error signal ts zero. When the antenn ix expacitive, the line current leads the line voltage, and the error signal is negative. When the antenna is inductive, the line current lags the line voltage, and the error signal is positive. Is divided into two circuits. Potentiometer RS ts adjusted Celreuit number 1 (0, C, E, and ¥) and ciroult number 2 ine vollage ¢1, 1s sampled, with no phase shift, by voltage divider C12 and G13, ‘The induced voltage in the secondary of the transformer 12 90 dearees out of sinc wth line current jig, The vector addition of the induced voltage, 42 and the sampled vollze cg in elreuit Humber 1 ereites a resultant voltage ¢, vector addition of Induced vollage cg and the snmpled voltage eg in elrowlt number = creates a resultant voltage o7. Voltages eq and es are rectified by CR6 and CRS and filtered by C10 and C9, ‘The hlgebratc sunt 6f Vee and Ved Is the error oatput. en the rf circuit impedange is greater than 50 ohms, om Cine watt Xd 1-38When the antenna is resistive, line current fy, and line voltage ey, are in phase, The of the resultant volinge across circuit number 1 (e4) is equal to the magnitude of the resultant vollage across circuit numbor 2 (og); therefore, the error algnal is zero (vector diagram (1) of figure 1-19). ‘When the antenna is capacitive, the veotor addition of induced voltage ¢, and sampled voltage eg causes resultant voltage e4 to increase in magnitude. The vector addition of induced voltage ey and sampled voltage og causes resultant voltage e, to decrease in magnitude, The algebraic sum of resultant voltages e4 and e; creates a negative error signal output (vector diagram (2) of figure 1-19), Whon the antonna is inductive, the vector addition of induced voltage eg and sampled voltage eg causes resultant voltage ¢, to decrease in magnitude, ‘The vector addition of foduced voltage es and sampled voltage eg causes resultant voltage e, to increase in magnitude, The algebraic sum of resultant voltages e4 and ¢, creates « positive error aignal output (vector diagram (8) of figure 1-19). Resultant voltage eg is rectified by diode CRG and then filtered by C5, LS, and C10. Resultant voltage og is rectified by diode CRS and thea filtered by L4, and C9, ‘The algebraic differences of the resultant voltages create a dc error signal output propor - tional to the phase difference betwen the rf voltage and the rf current. Forward Power Discriminator, Part of A3AGA1 and A3AGA2, Refer to figure 1-20, ‘The forward power discriminator yenerates a de output proportional to the rf power traveling toward the antenna, oH ati Figure 1-20, ANAGA: i Simplifted Schems tor, Part of ASAGAL and te Dingram 139‘The secondary of transformer ‘T2 is loaded with a low value of resistance, R7, to result ina secondary voltage (cg) 180° out of phase with primary current. The line tex! hy the voltage divider C15 and C1 and appears at the Junction of he sampled portion of the line voltage is 180° out of phase with the secondary voltage across TZ. Un one-half of the rf cycle the Inluced voltage 1s greater In magnitude than the sampled voltage; therefore, diode CR2 ts forward biased to produce a positive oulput when forward power Is present, 4. Reflected Power Discriminator, Part of A3AGAL and ASAGA2, Itefer to figure 1-21, The reflected power discriminator develops 2 de output proportional to the deviation of the vawr from 1.0 to 1, ‘The vswr deviates from 1.0 to 1 when (he antenna impedance is not 50 ohms and resistive; therefore, a reflected power output is developed when the ‘antenna circuit is not resonant with a resistance of 50 ohms. tor, Part wf ASAGAL Reflected Power Diserimt tic bingy Hed See Figure 1 1-40‘The secondary of transformer ‘T1 is loaded with a low value resistor, R8, to result in a secondary voltage (ca) In phase with the Une current iy, ‘The line voltage is sampled, with no phage shift, hy vollage divider C14 and C6, Cis factory adjusted to create a sampled vollage (at junction of Clt4 and 1a) equal to the Induced voltage on TL when the vewr is 1.0 to 1; therefore, Clt4 1s cut off, and there is no output. When the antenna circuit is resonant with a resistance less than 50 ohms, the rf. current increases and the rf vollage tonds to decrease, The induced voltage in the secondary of Tl is greater in magnitude than the sampled voltage. ‘Therefore, on the positive half of the rf eycle, diode ClX4 Is forward biased. The conduction of CR4 de- velops a positive oulput proportional to the relected power. When the antenna circuit is resonant with a resistance more than 50 ohms, the rf current decreases and the rf voltage tends to increase. The Induced voltage e2 is less than sampled voltage ¢3. Therefore, on the negative half of the rf cycle, diode CR4 is forward biased, ‘The conduction of Clt4 develops 2 positive output proportional to the reflected power. ‘When the antenna circuit is reactive (nonresonant), the rf line voltage 1s out of phast with the rf line current. During portion of cach eyele, the induced voltage 1s more positive than the sampled vollage, and diode CIt4 is forward biased. ‘The conduction of RA develops a positive output proportional to the reflected power. fe. ALC Detector. ‘The AL detector develops a de oulput proportional to the rf voltage, ‘The rf is rectified by CI7 and referenced by zener diode VII, The ALC detector voltage controls the oulput of the power amplitier during tune and low power (2 watts) modes, 1,.7.4.3.1.4 RCTuning Network Refer to figure 1-22 Tuning eapacitor eloments that provide extet impedance nnttching to the 50-ohm output of Uh power amplifier. Autotransformer A3AY contains capacitive and inductive components which are frequency bandswitched clements that translate antenna impedances to within the tuning range of C1 and Li. ‘The inductive component, autotransformer (A3AST1), is used ex- elusively for tuning the 8-foot whip antenna (rom 2 to 8 Mllz, The antenna switch located on 3 is a mechanically interlocked switch that selects the proper tuning element in autotrans- former A3A9, The switeh Ix activated hy the whip antenna, When the whip antenna Is not connected, the eaysteilive companents (ARAMCE through C5 and C7) are automatically con- nocted to the dipole antenna TING connector, Autotransformer A3A9, Refer to figure 4-24, achomatice section,‘ ‘ovides two frequency sclective networks, one for use with a dipole antenna (enpacitors C1 through CS and C7) and one for use with a whip antenna (autotransformer Tl and eapacitor C6), ‘The required value of ¢ nee (CL through G5 and C7) is selected by bandswitch ASAS, ‘The capaci 1s the dipole antenna impedances to within the tuning range of variable elements 141 and Cl. ‘The same is true for selecting autotransformer taps when using the whip antenna, Once antenna impedances are inside the tuning range, loading and phasing error signals run [1 and C1 to obtain the 50-ohm input impedance to the antenna, section and to figures 4-16 and natFigure 1-22. IC Tuning Network, Simplified Schematic Diagram Figure 1-23 shows how U1, C1, and capacitance (A3A9C1 through C5 wai C7) are used to tune the antenna at one example freyuoney. Figure 1-24 shows the tming procedure using the 8-foot whip antenna below 8.0 Mllz, ‘The auto transformer 1s switched out above 8.0 Mllz. When a whip antenna is connected, the amuplitier-coupler anton switelis mechanically switched to the normally open position, ‘The rf is applied to switch wal'ers SLA and S13 Of ASAD, Switch $1 is driven hy Iandswitch motor ASA5B1. At tuned Grequencies from 2 to 7.9999 Alllz, the rf is coupled through S11 to autotransformer T1.. ‘The autotrans- former passes the rf through SIA to Lhe whip antenna connector. Fronn8 to 23, 9099 Miz, the rf is applied dircetly to SLA, From 24 lo 29.9999 Miz, capaeitor C6 pro- vides capacitance for tuning the whip antenna, When using thi ‘The vf is lipole antenna, th plied to a contact on switeh te the in the normally closed posi- pacitors -A3A9 C1 through the tuning range of Gland Li. ‘The dipole antenna BNC connector. b, Tuning Capacitor ASAT, Refer (o figure 4-22, schematics seetion. ‘Te tuning eapaci~ tor is controlled by vollages (C1 max run and C1 min run) from servo amplifier A3A1, When a positive voltage is applied to AZA7P1-9 (CL max run) and 2 geoand to A3A7P1-10, . oF STA to motor 11, Under this cxndition when BL ically adjusted Loward maximunt eapaeltance, wanS1A is mechanically connectest to BL. SLA may rotate until the contact going to CRA becomes ape mum capacitance. When the contact opens, the voltage to B1 is removed and BI stops. Switch SIM rotates while BI is running. A ground established through S113 from AZA7P1-2, applies a ground at A3A7PL-5 to tell control logic A3AZ when C1 is maximum, When a positive voltage is applies! to ARA7P1-10 (CL min run); current flows through B1 (red dot side) to the wiper arm of SLA and out through CR3, C1 max run (A3A7P1-9) 4s ground, B1 now runs to force Cl towards minimum and also rotates witches SLA and S1B, ‘Switch S1A may continue to rotate until the contact going to CR3 becomes: ‘open, disabling B1, Switch StI! applies « ground to ASA7P1-6 to tell control logic ASA2 when C1 reaches a capacitance of 145 to 275 pf or less, ‘When logic conditions on control logic ASA2 arc such that there is no forcing of the ‘capacitor to max or min positions, the phasing voltage sample from the discriminator controls C1 position, Operation of the tuning capacitor 18 as discussed above, except that C1 1s adjusted (foward max or min) only whon a phasing voltage exists. ©. Tuning Coll ASA8. Refer lo figure 4-23, schematics section. ‘The tuning coll is post tioned by LA max run and 11 niin run control voltages from servo amplifier ASAL. When a positive voltage is syplicd to ASABT'L-10 (1 mix run) current flows through CRI and $1 to motor 11, (A3A8P1-4) is ground, This condition forces Bi to run to maxinum, nee, Uke follower arm plnecs a ground on ASASP1-2 (LI MAX) and pulls switch St down to Cit2, ‘The ground at ASABPI-2 tells control logic A3A2 that 1.1 is at maximum, When 81 ie actuated, the current path 1a broken and the motor stops runnin When 2 positive voltage is applied to ASA8P1-4 (LI min run), current flows through servo IL, switch 82, and diode CR3, L1 max run (ASASPL710) ts ground, “This forees xen nuin, At minimum, inductance, the follower ‘ound on ABASPI-9 (LL MIN) and pulls witch 1-0 tells control ASA2 that Li ia at minimum. motor stops running. When logic conditions on control logic A3A2 are such that there is no foreing of the inductor to max or min positions, the loading voltage sample {rom discriminator ASAG controls the tuning of 1.1. Operation of the tuning coll Is as discussed above, except that Li is adjusted (oward max or min) only when a loading voltage exists. ‘The positive or negative voltage sample will cause Ll to run only until proper loading cccurs (rf eircult impedance returns to SU ohms). A tab above the tuning cait ix counceted te the TT PaRTT@n output of A3A8, When a froquency 12 Mllz.or greater ix selected «ground [3 applied by bandswitch ASAS to the Center-lap on the tuning coil 1.1. Should the roller make contact with the tab above 12 MHz, the ground is transferred to the [i FesitTon output and applied to control logic ASA2, Logie from A2A2 then disables the loading servo amplifier and the coll stops. 1,7,4.3.1,5 Control Logie A3A2 Refer to figure 4-17 (bed) frequency infor: radio receiver: capacitor posi signals for the . Control logic ARAZ receives binary coded decimal 1 pulse (RCP STRETCH) and key tine control from 1 enable from servo amplifier AYAL, and tuning coil/ TARAS, antral xupplies control logic frequency bend logie andl servo command logic, a, Frequency Decoding, Refer to tiga Into frequeney had intoretion, see tablet module A3A5, level logic is al logic: ABA: ‘The hed input from control A2 is decoded Wl logic controls IM on bandswiteh ropelate fresqueney line/lines on pplied to various logic yates whereame (0 Fen tO FROM COMME, = 2.8 Figure 1-26, Frequency Hand Lagie, Simplified Schematic Diagram 147FREQ FREQ 7 CONN BAND RANGE PIN 1A 2,0 to 2,39 Milz. 2-13 1B 2.4 to 2.9 Miz P2-9 2 3,0to 3.9 Miz P2-10 3 4.0 to 5,9 Mille 4 6,0 to 7,9 Mitz Pell 5 8.0 to 11,9 MHz 2-28 6 12,0 to 15,9 MHz 2-26 7 16,0 to 23,9 Miz 2-20 8 24,0 to 29.9 Mllz 2-27 ‘Table 1-3, Frequency Bands it lo decoded and a logic 1 is applied to the proper connector pin on P2, ‘This in turn enables B1 on bandswitch module A3A5. For example; assume an operating frequency of 2.8 liz, Refer to figure 1-26, A logic 1 Is applied to the 2,0 Mitz and 0,8 MHz input (P1-3/5), all other frequency inputs are logic 0. ‘The bed frequency logic, us shown in figure 1-26 is applied directly or indirectly through logic gates to the output gales for cach frequency band, Note that output gate USA, figure 1-26, 1s the only output. rite with all logic O inputs to connector Pl. Refer to the truth table in figure 1-26, A logic Foutyait from USA enables the 2.4 to 2,9 Mts fre- quency band (11). All other outputs are logic 0 and the frequency bands (LA and 2 through 8) are disabled. Operation for decoding any (requency (2 to 29,9 Mila) 18 similar to the above example except the logic flow will change and the proper band for the selected frequency will be enabled, At frequencies above 12 Mllz, a high level logte Is applied to the forcing circuits of the variable tuning elements (C1/1.1) where it is used under certain conditions, This is covered in later paragraphs, b, Tune Logic. Refer to figure 1-27. Coupler tuning is accomplished by four tuning steps (bandswitch, standby, tune, and operate) that control the logic to the servo amplifiers and ALC eireuits, Initial turn-on of primary power oF the selection of a different frequency generates a rechannel pulse. net pulse sets the awplitier-coupler to tune step 1, band switch. ‘The tuning sequence ix illustrated in figure 1-27, A bandswitch complete sig- nal plus coil (1) position siggrt allows the loxie lo wdvance to step 2, standby. ‘The sequence logic waits in standby lor a key (key interlock) from the operator. ‘The tuning elements are atill positioned in the tuned condition for the last frequency. Upon receipt of a key (key Interlock) the loxie sequence goes to step 3, Lune, When the tuning se ‘quence fs not fn Tanbswitel and afl Teundsiitehing is conmplel a key interlock 1 148a Se» snes wr] | <> sear, Tas me Figure 1-27. * on ‘Tune Sequence Flow Diagram 149present, transistor switch Q2 applies a ground to ASAZP1-11. ‘This ground actuates Keylino rolays in power amplifier A3M to pass the rf to bandawitch A3AS, In tune, the following signals are used to control the tune cycle: Servo amplificr enable enables servos and allows elements C1 and Li to tune ‘Tune-in-progress (TIP) places power amplifier in a tune mode signal to power amplifier TIP to radio receiver- places radio receiver-transmitter Al in a tune mode, transmitter AL ‘which supplies a CW tone for tuning Sidetone control to radio rf present in recelver-transmitter Al sidetone con~ recelver-transmitter Al trol circuits, which in turn generates a sidetone in the operators headset. Forward rf power and low viwr (VSWN) logte from servo amplifier ASAL indicates that rf is present and the transmission line to the power amplifier is tuned to 60+ JO ohms. to within 1.3:1 vswr. Approximately 1 second after the amplifier-coupler is tuned to 1,3:1 vewr with forward power present, the tuning sequence advances to step 4, operate. In operate, anytime the vawr indicstles mismatch of greater than approximately 2:1. for more than the allotted time delay, the serve amplifiers are enabled. The amplifier- coupler retunes until the vswr is low and the fixed delay expires, then it returns to normal operate, The vswr logic to enable the servos is delayed each time the vawr Increases or decreases to provide nolse Immunity and allow the serves to pull-in as accurately as possible, ‘The tune cycle is timed by « fault circuit, see figure 1-27. If the tune cycle exceeds 15 to 36 scconds the system will fault, If a fault occurs, the tuning sequence must be re~ set with a tune slart (rechannel) pulse. 1, Bandswitch Step. Hefer to figure 1-28, ‘The rechannel pulse (HCP STRETCH) applies 2.50 ms ground (logic 0) to U20D, ‘This scts the bandswitch Mip-flop (U20D and U2iC), This same low level pulse Is applied to U201 and resets the fault flip-flop (U20A and U20B). Simultancously a logic 0 is gnted through U14D and USE and re~ sets the standby, tune, and operate flip-flops. When the bandswiteh flip-flop is set, the logic 1 output of U200 is applied to wervo enable UDB. ‘The output of UBB drives the olreult to cnorgize relay ASASAIKL. ‘This enables +25. 2 V de (KEYED). Gate ‘U20D also supplics 2 logic 1 to U2ZLA. ‘The logic 0 output of U21C is applied to the input of ULLD.. If the frequency is higher than 12 MHz. and the roller on the tuning coil is contacting the 141 porition tah, a logic 0 from UL3D is applied to the other input of ULLD, ‘the logic 1 out of ULLD onables the servo and forces the roller toward ‘MIN until it breaks contact with the tab, at approximately mid-coll. The output of U13D changes to a logic 1 and is applied to the input of U21A. The logic 0 output of U2IC is also applied to USC to hold the power amplifier in an unkeyed condition. When bandswiteh motor Ht on A3A5 stops running, ground is removed from the band~ switch complete eireuil and a logic 1 1s applied to the input of U2LA. When the band- switch flip-top is s switch is complete, and the roller on the tuning coil is not making contact with the 14 position tab (if over 12 Mllz) all inputs to U21A are logic 1. When all inputs to U21A are at logic 1, the Luning sequence advances to standby. 2, Standby Slep. ‘The logic O output of U2LA sets standby ‘The logic 0 output of U20C iss applied fo the input of UL7 flop (U20C and U21B), ‘The logic 0 output ofoot = oo =H sy “S_—-FEBERTEL wo wos cone: ETRE oa Figure 1-28, Control Logic A3A2, Simplified Schematic Diagram 1-51 /1-52 (Blank)U2LB Is fed back to UZIC to reset the bandswitch flip-flop. In standby the radio may receive but transmission is inhibited, ‘The tuning elements are atill in thelr pre- viously tuned positions unless the radio is in the RCV only mode. In the RCV only mode the tuning coll and capacitor are homed to maximum, however, the RCV only mode is used only during testing with Radio Test Sct AN/PRM-501. When the standby flip-flop is set and the radio keyed (key interlock) both inputs to ULTC are logic 1, When Loth inputs to U17C are at logic 1 the tuning sequence ad- vances to tune, When a ground is applied to the keyline, logic 0 is gated through U1SF and U14C to set key Interlock flip-flop U14B and ULBB. ‘The logic 1 output of U14B te applied back to the input of U17C and also to U18C to remove the power amplifier key inhibit, Tune Step. When both inputs to U17C are at logic 1, the logic 0 output sets tune fip- flop U17B and U18A. ‘The logic 1 output of U17} is applied through CR30 to enable the servos and applied through R20 to the input of U14A. The logic 0 output of U18A supplies the feedback to resct the standby Mip-flop and also applies a logic 0 to U7F. ‘The logic ia inverted hy U7H, amplified by Q1, and awitched by Q3, placing a ground on the keyline and spp! logic low to radio recciver-transmitter Al, The radio receiver-transmitter turns on the rf and allowa the amplifier-coupler tuning elements to tune. Discriminator A3AG samples the rf and provides phasing and load~ ing information to servo amplifier A3A1, A3A1 determines when the vawr is 13:1. When the vawr is correct «ul forward power is present, an advance to operate signal (logic 1) is applied to the input of U14A. When the tune flip-flop is set and an advance to operate logic 1 is supplied by ASAL both inputs to UL4A are at logic 1, When both inputs to U14A are at logic 1 the tuning Sequence advances to step 4, operate. Operate Step. ‘The logic 0 output of U1AA sets the operate flip-flop, U17D and U17A. The logic 1 output of UI7D (operate or Tune) is applied through U11B to the L1/C1 forcing circults. ‘The logic 0 output from UL7A Is fed back to U18 Lf Phase-Lock Loop A1AGALA3, Sckematic Diagram 10 Frequency Converter A1AGA1A4, Schematic Diagram +n Voltage Regulator A1AGA2Al, Schematic Diagram en Variable Frequency Divider ALAGA2A2, Schematic Diagram G13 if Phase-Lock Loop A1AGA2A3, Schematic Diagram ou Receiver~Transmitter Control A2, C-5310/URC, Schematic Diagram 15 Amplifier-Coupler A3, AM-5280/URC, Schematic Diagram 16 Servo Amplifier A3AL, Schematic Diagram 417 Control Logic ASA, Schematic Dingram 48 RF Subassembly AIAIAL, Schematic Diagram 19 Bias/Control Schematic DiagramFIGURE TITLE 4-20 Bandswitch A3AS, Schematic Diagram 4-21 Discriminator A3AG, Schematic Diagram 4-22 ‘Tuning Capacitor A3A7, Schematic Diagram 4-23 Tuning Coll A3A8, Schematic Diagram 44 Autotransformer AJA9, Schematic Diagram 4-25 Handset H-5017/PRC-515, Schematic Diagram 4-26 Headset-Microphone H-5016/PRC-515, Schematic Diagram 4-27 Electrical Power Cable Assembly CX-5229/PRC-515, Schematic Diagram 4-28 Direct Current Generator G-S0U2/PRC-515, Schematiis Diagram«® © ‘susispems ey aessyre mas ne © sete are euealeg @ Cine te wear as Figure 4-1. Chassis A1A1, Schematic Diagram 4-3/4-4 Biank)so BREEN 333 /PPp}3 | sue. commen | Porsiaty Srteeros lay I Ae =| AC cw UE Bee come Pare ry2 Figure 4-2. M Schematic Diagrai 4-5/4-6 (Blank)‘eeave oewe = . ti yoOF a . +s2s2vocism =a Figure 4-3. Broadband Amplifier A1A3. Schematic Diagraim 4-7/4-8 (Blank)—— Figure 4-4. Power S Sehemati 19 (Blank)Figure 4-5. If/Af A1A5A1, Schematic Diagram (Sheet 1 of 2) 4-11/4-12 (Blank)2 frase Hazan Figure 4-5. If/Af A1ASA1, Schematic Diagram (Sheet 2) 4-13/4-14 Blank)fom ates worn ausar2) 6 | vom {i Figure 4-6. 14 Schemat:Fe 2“ SAMPLE, AND HOLO |p w Ua hesiaer Figure 4-7. Frequency Standard AIASA141. Schematic Diagram 4174-18 (Blank)Pe UMLess OTHEEWISE SPECINED: RESISTANCE VALUES ARE I OOS 0 rire 9 ROFARADS. oes /oR ASSEMBLY DESIGNATION ® ®@ © ®Ee ae wes ctf SBS Ne = —— rs : ea, (7 ausasey Pe {ro wsamsess Figure 4-8. Fixed Frequency Divider ALAGAIA2 Schematic Diagram 4-19/4-20 (Blank)ros nnsasnrm9) vans cust te @ ne: ie @ om 2p Ro arasarare2) enor snomg gre, sumnes wuts we moe, werruet Ong WILGES tne ICROFAMOS Hoe OSCE LES a CADETS © rari mrmes cau we voy, FN conure 28 940, Once hesvenere stead Pie pane ao 33 vote map 7 1s ome © ron vas os scereo we rs. © 1g at sens ry Sg rer oe © voxares oF arsesSOSESS TREE Srey AL serene ysts AME On, AL CARCTANCE VALE ARE mw rss, UNLESS GOMMECTION TO POWER AO CRODND ARE sO P45 IY AND Pm TIS GROUND EXCEPT me] 7 Sea —_ Pe ba fir ds Pas pe tate ba © awe sevecreo wrest © vozareo om ane Figure 4-9. Lf Phase-Lock Loop ALA6A1A3 Schematic Diagram 4-21/4-22 (Biank)PRs Figure 4-10, Frequency Converter ‘ALAGAIA4, Schematic Diagram 4-23/4-24 (Blank)£70 ET sors. OB era ele eS SF as 5 Houtstee vais ae tm nnaoons @ nan rerpoce xsiourios we 0m Sbetite'Sereatign marie tim unt we oF Soe Seearis © wusss cosecriass 19 roee wo crate we Sens Rocce. vss @ wares o wasn @ sarin re maeas ron s0484couronenBST mans: 1 oe aoe Ouse: © Our SpeeEee nine fs |e vr corn, Wann 4 | ase mm resenves loo yee a z 20 |usnase cise! ® ei SheMeecmce lies oe no ® ges ees Zo", gS TE ase © yap arenes ogee oom, 2 sre sie ee Blin wore © wise ser etn in 1 Figure 4-11. Voltage Regulator AIAGA2A1 Schematic Diagram 4-25/4-26 (Blank)PLL HIGH FREQ ss2ver AIAGA2RS AXED FREO DIVIDER ‘AIRGAIA, fae Sux Tuo Ys Tons [es Tose Tome Gos E05 « $ N20 $800 & $ to a faa 4 a0 4 0 « ieues gms SAFE, eee aa ® GS, CAPACITANCE VALLES ARE IN MICROFARADS, AND DICOES parr MOONE e194 ME SOM: oH eDRETE ® ‘DESIGMATION, PREFIX WITH UNIT AND/OR ASSEMBLY QESIGNATION. © RES ENT Tte OTE 2 Sas Hn ts cose Bar zu. Pivtoc nes av wo tows YAU 15 1000 oF 61-3T5-001 WO 51 OF © gia “ us 1 wicmocneuit TES sn a esr sane care lenoe [SE Figure 4-12. Variable Frequency Divider ‘AIA6A2A2, Schematic Diagram 4-27/4-28 (Blank)sear) Fate ave [5 ora gars aa ave ooo wszvor Bain we e a a auates wr nara es: ® cro, @ fr © capacttance auc ‘eoranans, x0 ALL ROUETANCE VALUES PART REFERENCE DESIENATIONS ARE SHOWN, FOR COMPLETE OESIGRATIN baer itn un AND/0NASSEMRLY CSEMATIN Figure 4-13, HE Phase-Lo Schematic Diagr: Loop ALABATA3, 4-28/4-30 (Blanss-e-éle ge laren . Sn) Sor Me sn faa FR agezsron a, 1ou 00 me era, Brees, ese voctem ar case ac a came ame Joe vor are exes aeE> a> +f a Te wes otMeRMS,SPCCIED, CAPACITANCE VALUES ARE MMEROPARADS, SmotSéa Saher taaies ae w increas TS A 2 PARTUL REFERENCE DESIGNATIONS ARE SHOWN, FOR COMPLETE OCS ‘ation crx wet On ANO‘ON ABSCuBLY BESONATION. Figure 4-14, Receiver-Transmitter Control ‘Az C-5310/URC, Schematic Diagram 4-31/4-32 (Blank)Reborn ffs" © RETIRE id Ramla Te as ® fre W DOUNC & Ws KSOMY. © pene ve sa 380. 6 a HoH OL © sess mem ec msstwge mes © swe nse Figure 4-15. Amplifier-Ci AM-3280/URC, Schematic 4-23/4—84 (Blank)FILTER BOARD A3AI “=eer VOLTAGE DETECTOR ASA2ur anroee Sie ty oin 2 28.24 seme, paszvorveres) 10 Jerse‘sesevor weven, Fee Ln ry = UNLESS OTHENVNSE SPECIES RESISTANCE VALUES ARE BOS, (APACTTANGE WALUES ARE Dk MCROFAPADS, MOUCTANCE VALUES ARC ae MMLLOMENRYS, aMO DIODES ARE TYPE nee 2. PARTI. REFERENCE OCSEATIONS ARE SHOML: FOR COMPLETE OESENATION, cecroworm —__ PREED WITH OTT AND/OR ASSEMBLY BCSEAATIN 13. UNLESS CDWNECTION To PoweR AMO ROUND ARE” SHOW: AMCROCROAT POL W014 15 +506 MND Pte AG. 7 ts ca. few wo ou 7G jo vernasazes) Jsvocsw Figure 4-16. Servo Amplifier A3A1, ‘Schematic Diagram (Sheet 2) 4-37/4-38 (lank)feszvocwn . Tate = 2320 oy Ss eeszvewen | +252 V¢ (YEO AN FLTR) zi Be eeavoe 18} rave Be ONES! REFERENCE BESKOUTORS USED CRE, YAEL, AT. 027, U7SEEN SSS, a = a 10 | SESESRE re _ DLE f a ee F TH ; HoH st i oo : Fas - Fs, + ayes ay BOF reg eno? a = | MENS Tf 10 amr, ue, am |S " sree le, si oI “ate ee i ze kt RESISTANCE VALUES ARE OMS, .¥ eeseNATION. ‘No CAGUND AME sho POL TA IS #57 0€ Nore meat PHT TK SSVC AND #3 81S C0. TI woes Figure 4-17. Control Logic A3A2, Schematic Diagram (Sheet 1 of 3) 4-39/4-40 (Blank252 vocieerea) a0 It UWLESS OTHERMSE SPECIFIED; AL RESISTANCE VALUES ILL CAPACITANCE VALUES ARE DU MICROEARADS, 20 Panta REFERENCE DESENATDNS. ARE SHO}, FOR C2 [PREFDE WH AATTANG/OR ASSEWBLY DESICNATION UALESS COMMECTION TO POWER AND GROUND ARE. SH Ivo PD 7 15 G12, XCEPT TYPE 4048 WHERE PE menocincur TW9es roar [weet [aers [aor Pee TR aor [eens [sees s+ie. use cxas ante ase? + 4 +4 — fuel crs ze Fone cme savor Se bs, cm mera leeeee ze b ‘Raa orenare wey rem Epon cal _ s i = .hrtr—ee—eE Sasa i ‘ R = fe] ee ra toe SEE, wou nog Shain Figure 4-17. Control Logic A3A2, ‘Schematic Diagram (Sheet 2) 4-41/4-42 Blank)es = ce fee a eee & [ere te 4 ben PT ER, ome ge aes Toa -eeownnwn] "edad tar ze a + —~ | us wan once Ee “ ome st oo Be ecee corer) Skrwannse ew oe Figure 4-17. Control Logic A3A2 Schematic Diagram Sheet 3) 4-13/4-44 Blank)FINAL os eC © yess gmenmse secre, eesmaace ts stm ons, ete WERE, A Woden Ais ‘cm crore 2 © pera nerenence oesiourions sat swomy FoR comucTe DESLOMATION, PEELE WET ONT AND/OR ASSEMBLY OESGUATICN. ena Figure 4-18. RF Subassembly ASA4A1, Schematic Diagram 4-45/4~46 (Blank)x Stauton wor sto of eatace o¢siaurion 3 wae coPREREGULATOR UR (home a payor 9 ad Fin as pares nine aun Fett ns ovecs us ovoces © yy mente rain, msziner wus ae ons wo © rane mn tsa eet one sow. @ ra is atest scr, my OC 0, 3.3 OF 4.7 OF. Son Figure 4-19. Bias/Control A3A4A2, jematic Diagram 4-47/4-48 Blank)FILTER BOARD NO. 1, AZ = suo 1 > | Soe on 3 PH Ze G wets wie sere a 2 2 en By) Stee te iL Fe Ta Bi Fe Ly, . [i tse 2 = =. tano 7 = @ (caesar Sra ear a ry he ue par eortnkoe sso movetoner waves an Ly Fe Ts © RE rs euros ae nee i & o SSE “as OH 4 HH" a OH a ‘pecan Figure 4-20. Bandswitch A3A5, Schematic Diagram 4~49/4-50 (Blank)atin" wrucie [5 ‘Ate ocrecron| ‘© "ones otras stort srusaae ats ae ments, escnact @ res seceer sounae ise Shown Se on-as Treanor Figure Diseriminator A3A6, atic Diagram, 4-51/4-62 @Slank)ro 5 wore, STA COMTAET OBC TO CRS 1S OPEM AT waMMAN. 5A CONTACT Om TO EHC TS OMTW AT MASDAI. AMROW SWITCH MONEATES Figure 4-22, Tuning Capacitor A3A7, Sehematte Diaygesun Fon 4-53/4-64 (Blank)Bre asares somes ag $8 sepntar idee 3S, 1. WUES3 CTIERWSE NOTED, NO0ES ANE M4003. 2. Te Foulowen ama waxtS covtacy Amo (Ghoutos THe PestTONNG CONTACT OVER ant oF Tie con Lt. 3. UMLESS oneenwe SPECINED RERITANCE SALLE ane mova, cAMMCTIANCE WLS [ANC W1 MACROFARADS, AND OUETANCE LCS. ine m wearers & Puipeen hme ACTUATES 81 mo 43 190, PAGE A oun On Actua (rw Eom a Sraceeet-o1e Figure 4-23, Tuning Coil A3A8, Schematic Diagram 4-55/4-56 (Blank)== = ae ae anoowiten SF ee hss ‘gran is ace rao Figure 4-24, Autotransformer A3A9, tic m 4-67/4-68 (Blank)| oe a Figure 4-25. Iandset 11-5017/PRC-515, ichomatic Diagram 4-59/4-60 (Blank)| 4-26 427 4-28