ANALOG SIGNAL PROCESSING

by

Peter B. Aronhime
University of Louisville

F. W. Stephenson
Virginia Polytechnic Institute
& State University

A Special Issue of
ANALOG INTEGRATED CIRCUITS
AND SIGNAL PROCESSING
An International Journal
Vol. 6, No. 3 (1994)

SPRINGER SCIENCE+BUSINESS MEDIA. LLC

 Contents

Special Issue: Analog Signal Processing

Guest Editors' Introduction ....................................... P. B. Aronhime and F. W. Stephenson

Statistical Design
Global Design of Analog Cells Using Statistical Optimization Techniques ............................. .
. . . . . . . • . . . . . .F. Medeiro, R. Rodrfguez-Macfas, F. V. Fernandez, R. Dominguez-Castro, J. L. Huertas and
A. Rodrfguez-Vdzquez 3

DDA·Based Circuits
A Multiple Input Differential Amplifier Based on Charge Sharing on a Floating-Gate MOSFET .......... .
. . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .K. Yang and A. G. Andreou 21

Design and Applications of a CMOS Analog Multiplier Cell Using the Differential Difference Amplifier ...
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S.-C. Huang and M. Ismail 33

Optimization Techniques
On the Optimal Design of Switched-Capacitor Filter Circuits for Analog and Mixed-Signal Integrated Circuit
Realization ......................................................... N. C. Gustard and R. E. Massara 43

Optimal Gain Overdesign in Analog Filters .........•.............. A. C. M. de Queiroz and L. P. CaMba SS

Filter Design
A 7.2 GHz Bipolar Operational Transconductance Amplifier for Fully Integrated OTA-C Filters .......... .
. . . . . . . . . . . . . . . . . . . . . . . . . • . . • • . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M. Atarodi and J. Choma, Jr. 67

Current-Mode Synthesis Using Node Expansion Techniques ................... M. Desai and P. Aronhime 19

Macromodeling
Nonlinear Macromodeling with AWE ...................................... R. J. Trihy and R. A. Rohrer 89
ISBN 978-1-4419-5147-2 ISBN 978-1-4757-4503-0 (eBook)
DOI 10.1007/978-1-4757-4503-0

Llbrary of Congress Cataloglng-in-Publlcation Data

A C.I.P. Catalogue record for this book is available

from the Library of Congress.

Copyright © 1994 by Springer Science+Business Media New York

Originally published by Kluwer Academic Publishers. Second Printing in 1998
AII rights rescrved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted in any form or by any means, mechanical, photo-
copying, recording, or otherwise, without the prior written permission of the
publisher, Springer Science+Business Media, LLC

Printed an acid-free paper.

 Analog Integrated Circuits and Signal Processing, 6, 177-178 (1994)
C1 1994 Kluwer Academic Publishers, Boston.

Editorial

This special issue was conceived in Detroit during the 36th Midwest Symposium on Circuits and Systems. We
were asked by Editor-in-Chief Mohammed Ismail to select a collection of analog papers from those presented at
the conference and seek to have the authors develop them further for publication in this special issue.
It seemed to us quite appropriate that we undertake this task as a technical challenge as well as a means of
recognizing the unique role which the Midwest Symposium has played for the past thirty-nine years. It is the oldest
conference devoted to circuits and systems and affords a convenient form for the presentation of papers by graduate
students as well as by faculty and engineers from the non-academic arena. Furthermore, despite its somewhat
restrictive title, the Symposium has been held in many locations outside its original Midwest home. In recent years,
conferences have been held in Puebla (Mexico), Calgary (Canada), Monterey (California), Louisville (Kentucky),
Lafayette (Louisiana) and Washington, D.C. Future venues include Rio de Janeiro (Brazil) and Davis (California).
Of course, all of these conferences were, or will be, located in the midwest section of the town or city I
We carefully reviewed many papers presented in Detroit and decided that we must restrict our pool to those of an
analog nature. Furthermore, the papers needed to address something broader in scope and on a topic lending itself
to a full length journal paper. Our final selection loosely falls within our chosen title of Analog Signal Processing,
but we ask the reader's indulgence on this issue. More important to us has been the need to select a solid group of
analog-related papers which represent the breadth of topics covered in a variety of sessions in Detroit.
Several papers address the questions of cell design for CMOS applications. Medeiro et al. describe statistical
optimization for the design of complex analog cells while Yang and Andreou develop the lossless property of an
MOS floating gate into circuits having potential use as analog signal processing building blocks. By contrast, Huang
and Ismail discuss the design of a differential difference amplifier with application as a basic block in a simple
four-quadrant multiplier. In a further paper on analog design, Gustard and Massara use a switched-capacitor case
study to illustrate the usefulness of numerical optimization techniques in the generation of silicon-level layout for
analog functional modules from high-level specifications.
Filter design is featured in three of the contributions, but in distinctly different ways. de Queiroz and CaiOba discuss
an optimal approach to the overdesign of gain-shaping filters, while Atarodi and Choma present a transconductaJtce
amplifier for use in active integrated filters operating at cut-off frequencies greater than 200 MHz. Finally, Desai
and Aronhime propose a method for the node expansion of passive prototypes from which may be derived a series
of oscillators and active filters.
The paper by Trihy and Rohrer is quite general and offers an approach for the simulation of nonlinear (linearized)
circuits. Using an asymptotic waveform evaluation, the paper offers strategies for macromodeling nonlinear circuits.
In conclusion, we wish to acknowledge the assistance of Dr. Jatindar Bedi, ECE Department, Wayne State
University, who served as Publications Chairman of the 36th Midwest Symposium. Dr. Bedi was extremely helpful
in providing us with pre-publication copies of several papers. In addition, we acknowledge the work of Dr. Michael
Polis (currently Dean of Engineering at Oakland University), General Chairman of the 36th Midwest Symposium
and other Operating Committee members, Dr. Harpeet Singh and Dr. Feng Lin(both at Wayne State University), Ben
Behera (Aero Service Corp.), Dr. Majid Ahmadi (University of Windsor), Dr. Nader Boustany (General Motors),
and Dr. Magdy Bayoumi (University of Southwestern Louisiana) for their efforts in organizing the Symposium.

Peter B. Aronhime
F. W. Stephenson
178 Aronhime and Stephenson
~ ;)~'J\11',
,~,. i
t~
t.
Peter Aronhlme received the B.E.E. degree from the Uni-
versity of Louisville in 1962 and M.S. and Ph.D. degrees
from the Colorado State University in 1964 and 1971. He has
held engineering positions with Bell Laboratories in Winston-
Salem, NC, and Hughes Aircraft in Fullerton, CA, and he has
held academic positions with Tri-State University In Angola,
IN, and Jllinois Institute of Technology in Chicago. In 1976
he joined the University of Louisville, where he is Professor
of Electrical Engineering and Coordinator of the Computer
Science and Engineering Ph.D. Program. In 19g7 he was a
visiting professor at Colorado State University. His research
interests include network theory, computer-aided circuit anal-
ysis/design/testing, modeling and instrumentation. Dr. Aron-
hirne is a member of Eta Kappa Nu, Sigma Xi, Phi Kappa
Phi, and Omicron Delta Kappa.
F. William Stephenson is a native of Newcastle upon Tyne,
England, earned a B.Sc. in Electrical Engineering, 1961, at
2
the University of Durham {UK) and a Ph.D. in Electrical En-
gineering, 1965, at the University of Newcastle upon Tyne
{UK). Dr. Stephenson has been Dean of the College of Engi-
neering at Virginia Tech since June 1994. From 1990-1994
he was Professor and Head of The Bradley Department of
Electrical Engineering at the same school. Previously, from
1986-1990, he was Associate Dean for Research and Gradu-
ate Studies in the College ofEnglneering. In addition, he was
the founding Director of the Virginia Tech Hybrid Micro-
electronics Laboratory and co-founder of the Virginia Tech
Student Chapter of ISHM, the largest in the nation with 140
members: He has held industrial appointments with Welwyn
Electric and the Microelectronics Division ofElectrosil, both
in England. While with Electrosil, he worked on the applica-
tions of both monolithic and hybrid integrated circuits. His
main research interests are in the areas of hybrid microelec-
tronics, RC active and switched-capacitor filter design. Prior
to joining Virginia Tech In 1978, he taught at the Universities
of Hull {UK) and Rochester, NY, where he was the RT French
Visiting Professor in 1976-77. He Is the co-author of Lin-
ear Microelectronic Systems, Macmillan, 1973, and Active
Filters for Communications and Instrumentation, McGraw
Hill {UK), 1979, and the editor of RC Active Filter Design
Handbook, John Wiley & Sons, 1985. He has published re-
search results in such journals as IEEE Transactions (CHMT
and CAS), Tnt. Journal of Circuit Theory and Applications,
Microelectronics, and others. Dr. Stephenson is a member
of HKN, Tau Beta Pi, ODK, a Fellow of the Institution of
Electrical Engineers (lEE), and a Fellow of the Institute of
Electrical and Electronic Engineers (IEEE).
 Analog Integrated Circuits and Signal Processing, 6, 179--195 (1994)
0 1994 Kluwer Academic Publishers, Boston.

Global Design of Analog Cells Using Statistical Optimization Techniques

F. MEDEIRO, R. RODRfGUEZ-MACiAS, F. V. FERNANDEZ, R. DOMiNGUEZ-CASTRO,

J. L. HUERTAS AND A. RODRfGUEZ-VAZQUEZ
Dtpl. ofAnalog Circuit Dtslgn, Ctntro NaciDnal tk Mlc,.ltctrdnlu, Edlftclo CNM, Avda. Rtlna Mtrr:tdts ••..
41012-Sml/a, SPAIN, FAX 34' 4624,06, Plumt 34 '4239923

angelllcnm.us.e~

Abstract. We present a methodology for automated sizing of analog cells using statistical optimization in a simula-
tion based approach. This methodology enables us to design complex analog cells from scratch within reasonable
CPU time. Three different specification types are covered: strong constraints on the electrical performance of the
cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a
bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique
is also presented to yield designs with reduced variability in the performance parameters, under random variations
of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors
are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed
methodology.

1. Introduction connection of sub-blocks (differential pairs, current

The design of analog VLSI building blocks, and in
general the design of any integrated circuit, comprises
three major steps. First, a suitable schematic must be
selected. Then this schematic must be sized to com-
ply with required performance specifications on gain,
bandwidth, slew-rate, etc., as well as to meet design
objectives regarding area, power consumption, etc. Fi-
nally, a layout must be generated for the sized schemat-
ics. Of these three major steps, this paper focuses on
the problem of analog sizing.
Analog sizing is a very complicated, time-con-
suming task whose automation has drawn strong atten-
tion in recent years, where several tools and method-
ologies have evolved [1-8]. Two basic reasons lie be-
hind these developments: a) market pressure to reduce
the design cost of the analog components of modem
analog-digital ASICs and b) the need for custom ana-
log design to be available to ASIC system designers.
Most previously reported approaches for automated
analog cell design are closed systems covering only
a limited number (though not necessarily small, see
for instance [1]) of schematics. Some tools work on
a flat schematic library where topologies are defined
at the device-level [1, 6, 8, 9]. In others [3, 5, 7, 10]
architectures are defined at the conceptual level as a
mirrors, etc.), each of which can be expanded hier-
archically down to the device-level. Tools also dif-
fer among themselves depending on the sizing strategy
used. In some approaches, the sizing process is re-
duced to a constrained optimization problem [6, 8]; in
others, sizing is performed by following specific de-
sign plans for each topology, previously developed by
expert designers and stored in the tool database [1, 3,
s. 7, 10].
Closed sizing systems are all equation based; that
is, the knowledge about the available topologies is pro-
vided as analytical design equations. The associated
design equations for new topologies must be generated
- a task for only real analog design experts to tackle.
Another drawback relating to closed systems is that
they do not allow the exploration oftopology enhance-
ments as conceived by designers with some expertise.
Some of the drawbacks of closed systems are over-
come by the approaches in [9, 11 ], which are also equa-
tion based. The distinctive feature is that some of the
design equations for new topologies are automatically
generated via auxiliary symbolic analysis tools [9, 12].
Expert concourse is not further required to that end.
Unfortunately, symbolic analysis tools provide equa-
tions for neither DC nor large signal transient charac-
teristics, whose associated design equations must still

3
180 Medeiro, Rodrfguez-Macfas, Fernandez. Dom(nguez-Castro, Huertas and Rodrfguez-Vazquez

be manually provided. Hence, the methodology is only analog output buffer, which were sized using the pro-
partially open. Furthermore, the level of complexity for posed methodology, fabricated in different CMOS
AC automatic modeling is limited by the capabilities technologies, and whose performance was corrobo-
of symbolic analysis tools (currently, about 15 MOS rated from actual silicon prototypes. The proposed
transistors using high-frequency MOST models and technique is also extended to design for low variability
workstation standard configurations). Consequently, incorporating mismatching information in the design
this approach is not the most suitable for the auto- procedure. This is illustrated in the design of a CMOS
mated sizing of complex analog building blocks (for folded-cascode operational amplifier.
instance, fully-differential opamps), or for applications
where large signal specifications play a major role, for 2. Some Generalities on Optimization-Based
instance, oversampled modulators for high resolution Sizing
AID converters [ 13].
Whether closed or open, equation-based systems Analog sizing is a constructive procedure to map cell
have a common drawback in that sizing is carried out specifications into design parameter values. Design
using simplified analytical descriptions of the blocks. specifications are given a broad meaning here which
Hence, manual fine-tuning using an electrical sim- includes constraints on the electrical performance pa-
ulator and detailed MOS transistor models may be rameters of the cell as well as design objectives. Let us
necessary once rough automated sizing is completed. consider for illustration purposes the output buffer of
This drawback is overcome in the so-called simulation- figure 1, one of the examples covered in this paper. A
based systems [14], which also reduce sizing to a con- possible specification set for this circuit could include
strained optimization problem, and aim to solve it by constraints on its DC gain (Ao > target), input capaci-
following an iterative procedure built around an elec- tance (C;n <target), 3-dB frequency (f3 d 8 >target),
trical simulator. No design equations are required in and output voltage range (target < OS < target), in
addition to the design objective of minimum possible
these approaches; the design parameters are updated
power consumption. With regards to the design param-
at each iteration based on the results provided by sim-
eters, these include transistor dimensions and passive
ulations with detailed transistor models. Thus, they
component values.
are intrinsically open. A representative example of
In a generic circuit, the design parameters can
this methodology is DELIGHT. SPICE [14] where DE-
be viewed as components of a vector xT
LIGHT (a general algorithmic optimization tool) and
{x 1, x 2 , ... , x N} defining a multidimensional de-
SPICE are combined. Also, advanced electrical simu-
sign space. Thus, performance parameters and the
lators, like HSPICE [ 15], incorporate optimization rou-
tines. However, the optimization routines in both tools
search for a local solution, and consequently are typ-
ically used to redesign cells whose performance spec-
ifications are close to the design goals (for instance,
technology updating of a cell library), but are inappro-
priate to size analog cells from scratch. This is a real
challenge in analog design automation and requires the
development of other techniques.
This paper presents a simulation-based approach for
global sizing of arbitrary topology analog cells us-
ing statistical optimization. We demonstrate that by
combining proper cost function formulation and in-
novative optimization heuristics complex cells are de-
signed starting from arbitrary initial points, within rea-
sonable CPU times and with no designer interaction
required - a very appealing feature for ASIC appli-
cations. We present results obtained for two fully-
differential CMOS opamps, a comparator and an Fig. 1. A CMOS output buffer.

4
 Global Design of Analog Cells using Statistical Optimization Techniques
features involved in design objectives are given as
functions of x; referring again to the example
of figure I: A0 (x),C;n(x).fadB(x),OS(x), and
Power(x). Then the problem of sizing is formulated as
a constrained optimization problem; in particular, for
the case of the buffer of figure I ,
minimize Power (x)
A0 (x) > target
subjected to C1n(x) < target (I)
!adn(x) > target
target < OS(x) < target
Unfortunately, even for elementary analog cells like
that shown in figure I, the analytical solution to the
sizing problem is not possible due, among other fac-
tors, to the following:
• Design equations, i.e., functional relationships
among performance parameters and design objec-
tives on one hand, and design parameters on the
other, are very difficult to obtain accurately.
• These relationships are typically highly nonlinear
and, consequently, unsolvable analytically. A fur-
ther complication arises due to the large dimensions
of the design and the specification spaces.
• The need to minimize some functions forces the cal-
culation of first and second derivatives and hence
@! YF.S:
(a) =···o;;~·g;;p.;x.c;s·~ianagen;cn.················
manual managemcr·u
~~ au1oma1ed management
•non••••••••••••••••,.,.•••••• •••••••
(b ) PARAMETER UJ"'ATINC
Fig. 2. Iterative analog cell sizing: (a) general concept; (b) manual
and automated design updating management.
181
introduces additional complications to the analyti-
cal solution process.
Due to these difficulties, analog circuits are most
conveniently sized by using an iterative, dynamic pro-
cess. This concept is illustrated in figure 2: starting
from an initial design parameter estimate, x 0 , a dis-
crete sequence of movements (represented generically
as ~xn) is performed through the design parameter
space until an equilibrium solution point x• is found.
A key component of this iterative loop is process
management: the calculation of the direction and mag-
nitude of the movement ~Xn to be made at each itera-
tion. In manual design, ~Xn is chosen by the designer
based on his/her knowledge of the circuit structure be-
ing sized - a difficult and time-consuming task even
for experienced analog designers. In automated de-
sign, the selection of ~Xn must be performed by the
computer based on the evaluation of some critical cir-
cuit performance indicators. A convenient approach to
do this is to recast the problem formulation as a cost
function 4i(x) which quantifies the degree of achieve-
ment of the design goals and their relation to the design
parameters. Thus, the parameter updating to be done
for the subsequent iteration ~Xn is selected at each
iteration using functional analysis data of 4i(x). This
approach also provides simple and accurate criteria to
finish the sizing process at points where the cost func-
tion is either maximized or minimized.
In the simplest case, ~Xn is calculated by using
pieces of information calculated only at Xn · However,
as demonstrated in this paper, the use of additional in-
formation from previous points, at time instances n- 1,
n - 2, etc., may produce more robust solutions of the
sizing problem, in the sense of yielding cells whose
specifications have lower variability when statistical
variations of the technological parameters are taken
into account. In this more general case, the updating
process is described as a high-order nonlinear discrete-
time system,
As stated in the introduction, we will assume that
performance evaluations in figure 2 (equivalently, the
calculation of performance specification values and the
values of the features involved in the design equations
as functions of x) are made using electrical simulation
and detailed transistor models to guarantee accuracy
of the sizing process. Many different alternative im-
plementations of figure 2 are possible depending on:
5
182 Medeiro, Rodrfguez-Macfas, Fernandez. Domfnguez-Castro, Huertas and Rodrfguez-Vdzquez
a) formulation ofthecost function itself, b) the updating
procedure. Two major alternatives can be roughly iden-
tified, depending of the functional structure of S[ •)
in (2):
• Deterministic, incremental techniques where .6x,.
calculation uses information about the derivatives
of the cost function. This is an important draw-
back since analytical expressions for the cost func-
tion and its derivatives as functions of the design
parameters are not commonly available, so that the
derivatives must be calculated by numerical interpo-
lation. Another major drawback is that only .6x,.
values which lower the cost function are considered.
Hence, the optimization process is easily trapped in
local minima, rendering it very suitable only for fine
adjustment of the design.
• Statistical techniques, where .6xn is calculated at
random and hence requires no information about the
cost function derivatives.
Parameter updating in deterministic techniques is
done only in the direction which lowers the cost func-
tion. This makes them very sensitive to the starting
point and hence inadequate for global circuit sizing.
This is overcome using statistical optimization tech-
niques where movements in the design space are done
heuristically, following statistical optimization princi-
ples [16]. The price to pay for an independent initial
point is a larger number of iterations and hence longer
CPU times. However, as shown here, proper formu-
lation of the cost function, the movement generator,
and the cooling schedule, adapted to the nature of ana-
log synthesis, palliates the high computational cost and
thus provides a convenient methodology for global de-
sign of analog cells.
3. Cost Function Formulation
A first step towards devising a tool for automated sizing
of analog cells using statistical optimization is to for-
malize the setting of performance specifications. In a
more general case, three different specification classes
must be considered:
• Strong restrictions: These are specifications
whose fulfillment is considered essential by the
designer; for instance, the phase margin of an
opamp must be larger than 0 (PM > 0} for sta-
bility [17]. No relaxation of the specified value is
6
allowed. Hence, if any setting of the design parame-
ters (equivalently, any point of the design parameter
space) does not satisfy one strong restriction, it must
be rejected immediately.
• Weak restrictions: These are the typical perfor-
mance specifications required of analog building
blocks, i.e., A 0 > 80dB. Unlike strong restrictions,
weak restrictions allow some relaxation of the tar-
get parameters, making such circuit sizings which
do not meet such specifications acceptable.
• Design objectives: Stated as the minimi7.ation
(maximization reduces to this case by either chang-
ing the sign or using the inverse of the function to
maximize) of some performance features,
minimize Y>~~, (x) 1 ::; i ::; P (3)
for instance, minimize -GB of an opamp (equiva-
lently, maximize GB), where GB denotes the gain-
bandwidth product; or minimize the occupied area
of the circuit.
Mathematically, the fulfillment of these specifi-
cations can be formulated as a multi-objective con-
strained optimization problem,
!
minimize Y>~~, (x}, 1 ::; i ::; P
y.;(x) ;::: Y.; or Ya;(x) ::; Y..;,
1 ::;j::; Q
subjected to
Ywk(x) 2:: Ywk or Ywk(x) ::; Ywk•
1 ::;k::; R
(4)
where Y>~~; denotes the value of the i-th design objec-
tive; Y•i and Ywk denote values of the circuit speci-
fications (subscripts s and w denote strong and weak
specifications, respectively); and Y.; and Ywk are the
corresponding targets (for instance, A 0 ;::: 80dB, set-
tling time ::; O.lJ.!s).
The cost function is defined in the minimax sense as
follows,
minimize ~(x)
(5)
= max{ F>~~(Y>~~;), F.;(Y.;), Fwk(Ywk)}
where the partial cost functions F>~~( • ),F.j( • ),
 Global Design of Analog Cells using Statistical Optimization Techniques 183

and Fwlc( •) are defined as vector, .1.x.,, is randomly generated at each iteration.
The value of the cost function is calculated at the new
- L w; log(IY>~o;/), parameter space point and compared to the previous
one. The new point is accepted if the cost function has
i
F.i(Y.J) K.J(Y•J• Ysi) (6) a lower value. Unlike deterministic techniques, it may
also be accepted if the cost function increases, accord-
Fwlc(Ywk) -Kwk(Ywk> Ywk) log ( f::) ing to a probability function,

(8)
where w; (called weight parameters for the design ob-
jectives) is a positive (alternatively negative) real num- depending on a control parameter, T. The random
ber if Y>~oi is positive (alternatively negative), and for character of movements and the statistical acceptance
K,j( •) and Kwk( •) we have of those which increase the cost function enable es-
caping from local minima and hence wide exploration
-oo, if strong of the design space. This probability of acceptance
{ restriction holds changes during the optimization process, being high at
oo, otherwise the beginning (for large T) and decreasing as the system
cools (decreasing T). This is the general concept lying
if weak behind simulated annealing optimization techniques-
restriction holds a process whose name is justified by its analogies to the
otherwise physical annealing in solids [ 16]. The tool proposed
(7) herein incorporates new heuristics relating to both pa-
rameter updating and the cooling schedule itself, as
where k~c (weight parameters assigned to weak restric- explained below.
tions) is a positive (alternatively negative) real num-
ber if the weak specification is of ~ (alternatively :::;) 4.1. Cooling Schedule
type. Weight parameters are used to give priority to the
associated design objectives and weak specifications. Cooling schedule refers to the strategy used to mod-
As shown in the cost function formulation, only rela- ify the temperature while the process evolves. Unlike
tive magnitude of the weight parameters of the same
type makes sense. In (7) weak specifications are as-
sumed positive. Sign criteria is reversed for negative
specifications.
Strong restrictions are checked first at each itera-
tion. If any of them are not met, the corresponding
movement must be rejected. Otherwise, weak restric-
tions are examined. Weak restrictions have priority
over design objectives. If some weak restriction is not
fulfilled, the cost function is built only with their con-
tribution. Hence, if no circuit sizing is able to cover all
weak specifications, the optimization process will pro-
vide results as close as possible. Once all of them are
met, the design objectives are evaluated and their in-
fluence in the cost function guides their maximization
or minimization.

4. Parameter Updating and Process Management

Figure 3 shows a block diagram illustrating the opera-

tion flow in the proposed methodology. The updating Fig. 3. Operation flow in the proposed methodology.

7
184 Medeiro, Rodrfguez-Madas, Fernandez, Dom(nguez-Castro, Huertas and Rodrfguez- Vazquez
classical simulated annealing algorithms [ 16], where T
in (8) decreases monotonically during the process, our
tool uses a composed temperature parameter,
T = a(x)T (n) 0 (9)
where n denotes the iteration count, T 0 ( n) (the nor-
malized temperature) is a function of n, and a(x) (the
temperature scale) is a function of the position in the de-
sign parameter space. Our tool incorporates heuristics
to choose T0 and a for increased convergence speed,
namely:
• Non-monotonic and adaptive normalized tempera-
ture.
• Use of a nonlinear scale, with different expressions
for different regions of the design parameter space.
4.1.1 Normalized Temperature. Instead of a conven-
tional slow monotonically decreasing temperature [ 18],
a sequence of fast coolings and re-heatings is used. In
circuits with not very demanding specifications, this
enables to obtain feasible designs for low iteration
counts. Also, for those cases where demanding speci-
fications are asked for, we have found that this strategy
reduces iteration count by, on the average, a factor of
6. l\vo different evolutionary Jaws for the normalized
temperature are incorporated in the tool: exponential
decreasing, and linear decreasing. For illustration pur-
poses figure 4(a) shows an exponential schedule with
eight re-heatings. Initial and final temperatures, num-
ber of coolings, decreasing law and rate, etc., are com-
pletely controlled by the user. An alternative cooling
schedule makes To to change as a function of the per-
centage of accepted movements,
T 0 (n) =T 0 (n- 1) + ,6 ( 1- p,~n)) (10)
where p is calculated as
number of accepted movements
p= ( 11)
during the last M iterations, where M is an heuris-
tic variable whose typical value is around 25; f3 in (10)
controls the rate of temperature change and has a typical
value around 0.1; and p, ( n) is a prescribed acceptance
ratio, which can be fixed or vary with some given law.
This schedule provides very good results for practi-
cal circuits, rendering the outcome of the optimization
process somewhat independent of the specified values
8
of the initial and final temperature. Figure 4(b) illus-
trates this type of cooling schedule.
4.1.2 Temperature Scale. As (9) shows, the temper-
ature scale parameter is a function of the position in
the design parameter space. More specifically, the
scale depends on which region of the parameter space
is reached after each movement. This is so done to
compensate the large differences that may eventually
appear in the increments of the cost function in the dif-
ferent regions. Thus, no temperature definition is used
for those regions where strong restrictions do not hold,
due to the fact that any design entering this region is
automatically rejected. On the other hand, in regions
where some weak specifications are violated, temper-
ature is given as
T =To lkmaxl ==* a(x) = kmax (12)
where kmax is the weight associated to the maximum
among the Fw( • )'sin (6), and T 0 is the normalized
temperature at the current iteration. Finally, if both
strong and weak restrictions hold, temperature is given
as
where wi is the weight associated to the i-th design
objective.
4.2. Parameter Updating
Concerning the updating of design parameters three
kinds of heuristics have been adopted:
• Changes in the amplitude of the movement Axn as
a function of the temperature. In particular, at high
T, large amplitude movements are allowed as they
are likely to be accepted and favor wide exploration
of the design parameter space. On the contrary, at
low T, acceptance probability decreases and, hence,
only small movements are performed (equivalent to
fine-tuning the design).
• The possibility of defining logarithmic scales for
independent variables. This has been done be-
cause many design parameters, i.e., transistor sizes,
bias currents, etc., may vary over several decades.
For instance, a change of 2J.LA in a bias current
does not have the same significance if the previ-
ous bias current value is 5J.LA as if it is 100J.LA;
 Global Design of Analog Cells using Statistical Optimization Techniques 185

1.0 ~-~--.-----~--.---------,.-------,

0.8

ae o.6
!:!
8.
E
~ 0.4

0.2

0.00
(a)

0 · 0 o~-----::csoo~-~-__,I_.,.ooo.,.__~-....,.t-='so,...,o,..._.~--..J
(b) #iterations
Fig. 4. Cooling schedules: (a) exponential decreasing with re-heatings; (b) adapt;ve temperature with given acceptance mtio.

hence, linear movement of this variable would un-
derexplore the low bias current range - a draw-
back which is overcome by using logarithmic scales.
• Discretization of the design parameter space. Many
design parameters are already discrete in nature, i.e.,
in many microelectronic technologies transistor di-
mensions can only vary over integer multiples of
the technology grid. Our discretization consists in
making discrete those variables which are contin-
uous, and define a larger size grid for those vari-
ables which are already discrete in nature. Then, the
parameter space can be viewed as a collection of
hypercubes. Only movements over vertices of this
multidimensional grid are allowed, being marked
when they are visited. Thus, if during the optimiza-
tion process one vertex is re-visited the correspond-
ing simulation need not be performed. Hence, an
important number of simulations is saved. When
this optimization process ends, a local optimization
is started inside a multidimensional cube around
the optimum vertex for fine tuning of the design.

9
186 Medeiro, Rodrlguez-Madas, Fernandez, Dominguez-Castro, Huertas and Rodriguez-Vazquez

6.0

c:: 2.0
-~
c::;
§ 0.0
u..
~-2.0
E-
-4.0
- 6.0

(b) -10.0 -5.0 0.0 10.0

X

Fig. 5. (a) Test function with two variables for optimization heuristics comparison; (b) cross section.

In this local optimization, design variables recover heuristics. Its mathematical structure for an N-
their continuous nature or their original grid size. dimensional case is
Together with these heuristics, large efficiency en-
II cos(xk- d) ,
N N
hancements are also achieved by proper control of the f(x) = K · min{-e-eE._,<x•-dl'
DC electrical simulator routines. For this purpose a k=l
dynamic, adaptive, DC initialization schedule is im-
plemented which uses operating point information of
N
- e-eE•=•'"'•-d)
•
II cos(x~; +d)+ 'Y}
N

previous iterations to increase convergence speed of the k= l

simulator. This yields significant CPU time, especially (14)
at low temperatures.
where K,~, d and 'Yare constants. This function has
one absolute minimum (of value -K) and many lo-
4.3. Heuristics Comparison cal minima, and exhibits the interesting feature that the
number of minima increases linearly with the number
A multi minima analytical function is used in what fol- of variables. This means that the complexity of the
lows to demonstrate the advantages of the proposed optimization process is determined exclusively by the

10
 Global Design of Analog Cells using Statistical Optimization Techniques 187

II

Achieved minimum I
(a)

100
90
~ 80
"'c
.8
~
~

Achieved minimum
(b)

Fig. 6. Cooling schedule heuristics comparison.

number of variables, and not by structural changes in
the cost function. Figure 5(a) shows this function for
two independent variables. A cross-section is shown
in figure 5(b).
The heuristics described in Section 4.1 and 4.2 have
been tested using the test function in (14) with differ-
ent number of independent variables. The test proce-
dure consisted in the repeated execution of the different
heuristics on the test function, starting from random
points of the parameter space and with a fixed iteration
count. For each of these executions the best achieved
minimum was stored. Experimental results arising
from these tests are shown in the three-dimensional
plots in figure 6. In order to get better insight into the
test results, the plot of the test function is allowed to
take only integer values. Hence, the minimum achieved
at each test execution is represented by its closest in-
teger value. The X -axis in figure 6 represents the
magnitude of the achieved minimum (its closest in-
teger value). TheY-axis corresponds to the number
of independent variables in the test function /( • ),
and the Z -axis represents the percentage of iterations
that achieved that minimum. Figure 6(a) corresponds
to a conventional cooling schedule. It had a single

11
188 Medeiro, Rodrfguez-Mac£as, Fernandez, Dom(nguez-Castro, Huertas and Rodrfguez-Vazquez
cooling with fixed scale in variable movements and
variable Markov chain length [ 16]. For a function with
a small number of variables most iterations provided
the global minimum of the function but this percentage
decreased rapidly when the number of variables was
increased. Figure 6(b) corresponds to our improved
cooling schedule with the same number of iterations.
The cooling schedule used had four successive coolings
and re-heatings, variable scale, and a Markov chain
length equal to 1. Most iterations provided the global
minimum of the function, even when the number of
independent variables was increased.
5. Extension to Low-Variability Sizing
All heuristics mentioned above assume that devices
of the same type (i.e., NMOS transistor, PMOS tran-
sistors, etc.) have identical technological parameters
(i.e., threshold voltages, intrinsic transconductance,
etc.) and that these parameters remain constant for a
given technology. However, this does not hold in prac-
tice; technological parameters are subjected to large
random variations which may degrade significantly the
performance of analog cells, specially when small de-
vices are used [ 19, 20, 21].
Although statistical process variations can not be
annulled, they can be measured, captured into mod-
els [ 19, 20, 21] and incorporated to the circuit design
process. However, the conventional approach to mea-
sure performance variations by Monte Carlo simula-
tions is very costly in CPU time and, consequently,
not well suited to be used in an iterative optimization
loop. Since dispersion of the transistor parameter val-
ues is inversely proportional to the device's area, and to
the distance among nominally identical devices [21], a
strategy to reduce variability of the cells is to put ad-
ditional constraints on the design variables. However,
this strategy drastically reduces the search space, limit-
ing the achievement of demanding performances. The
heuristics described below provides a more convenient
approach that takes advantage of the large amount of
data generated during the statistical optimization pro-
cess. It encompasses a modification of the cost func-
tion structure and a new comparison methodology, in
combination to the nonmonotonic cooling schedule.
First of all, design specifications, and, hence, the
cost function is made to depend not only on the vector
of design parameters x, but also on a vector of transistor
model parameters e. These model parameters change
12
during the optimization process as a consequence of
the dependance of their statistical variability with de-
vice area and distances between devices [21]. At each
iteration, design parameters are updated according to
the heuristics in Section 4.2 and device model parame-
ters are changed according to the statistical distribution
of the technological independent parameters [20]. In
addition to enlarging the number of parameters, a new
addend is incorporated to the cost function to evaluate
the sensitivity of performance specifications to device
model parameter variations. Such addend is
LPt=l IY•P•'• (Xn,en)-Yopao, (Xn-t,en-d I
_.!._ L
M {
1/epoci(Xn.,en)
M n=l I:J=l iej,n- ej,n-d
•WJ •W2}
(15)
which incorporates information from the last M iter-
ations, where M corresponds typically to the number
of iterations performed in one cooling. Each addend
in (15) contains the ratio of the relative increase in the
specifications (either weak specifications or design ob-
jectives) to the increase in the L device model param-
eters with respect to previous iteration. The numera-
tor evaluates relative variations of the P performance
specifications with respect to previous iteration due to
variations in the design parameters x, and the device
model parameters e.
The amplitude of design parameter variations de-
creases along each cooling. Therefore, the variability
of performance specifications is evaluated with higher
precision as the optimization process evolves. This fact
is reflected in (15) by the weight parameter w~o which
is given by
(16)
where r in an heuristic parameter larger than 1. Hence,
w1 increases along a cooling, giving more importance
in {15) to the addends corresponding to the last itera-
tions within each cooling.
A similar weighting between different coolings is
done with parameter w2, which is given by
(17)
where r' is a heuristically chosen constant parameter
which must be smaller than 1 and l is the ordinal of the
current re-heating within the cooling schedule.
 Global Design of Analog Cells using Statistical Optimization Techniques
The cost function at some given iteration must be
compared with some previous iteration in order to ac-
cept or reject the current design parameter movement.
A new comparison methodology is introduced adapted
to the new cost function formulation. Each iteration in
a given cooling is compared with the iteration of equal
ordinal from the best of previous coolings, for accep-
tance or rejection, following the statistical optimization
principles of Section 2. If rejected, the design point of
the best cooling is adopted as new point in the current
iteration and the optimization process continues. Since
(15) is added to the cost function, the optimization pro-
cess tends to minimize it. That implies small specifi-
cation increases in the last M iterations and, hence,
reduced performance statistical deviations.
A mathematical test function has also been used here
to prove the method's capability and as a benchmark
for heuristics refinements. Its analytical struture for an
N -dimensional case is
f(x) = K + K' ~ Isin c~Xk) I
c1T6Xk) I)
+h (dist 2 (X,Xmtn) + ~ lsin
(18)
The first addend in (18), sets the mean value off( •)
and the second one creates variations around that mean
value. Statistical deviations are simulated at the third
addend by means of a random variable, h. The global
minimum of dispersion is located in X min· Sinusoidal
variations set local dispersion minima. A method to
reduce variance will be acceptable, if the final solution
is close to X min·
For a test example with eight independent variables
comprised in the interval Xn E [-0.7, 0.7], a mean
value K = I 00 and sinusoidal variations with an am-
plitude K' = 10, the new heuristics provides a solution
to a distance of 1. 75 from the global minimum, where
standard deviation is u = 0.25. A conventional statis-
tical optimization technique ends in distances around
12 from X min• where standard deviation is u = 12.
6. Practical Results
Proposed techniques have been applied to a wide vari-
ety of analog building blocks. Results are shown for the
design of two fully-differential opamps, a comparator
and an output buffer. Simulated results and measure-
189
ment of silicon prototypes of the circuits demonstrate
the feasibility of the approach.
6.1. Fully Differential Class-AB Opamp with
Dynamic Biasing
Let us first consider the fully differential opamp of fig-
ure 7 [22), intended for a 16bit@16-KHz second order
I:..:l modulator. This class-AB opamp includes dy-
namic biasing of the output branches to obtain large
output swing and high slew-rate, and uses a dynamic
common-mode feedback network. These advanced cir-
cuit strategies, and the complexity of the circuit itself
(it contains 48 transistors) renders its sizing a diffi-
cult task, hard to handle for system level designers.
However, the herein proposed methodology was able
to automatically size the circuit for the intended appli-
cation after 1 hour CPU time on a 1OOmips sparcstation,
starting from scratch and with no designer interaction
required. Table 2 shows the sizing obtained.
The first column in table 1 contains the design goals,
which includes a design objective on the power con-
sumption and weak restrictions on the gain-bandwidth
product (GBW), phase margin (PM), input white noise
and output swing (OS). Figure 8 shows the evolution of
the cost function during the optimization process. Note
that the vertical axis contains two regions, separated by
a dashed line. The weak region corresponds to the case
where any of the weak restrictions is violated, while
the objective region corresponds to the case where all
weak restrictions are fulfilled; inside this region the
optimization process focuses on the design objectives.
Note that a good design (meaning one that fulfills all
the weak restrictions) is obtained after 750 iterations.
Simulated results corresponding to the obtained sizing
are shown in the second column of table 1.
Figure 9 is a microphotograph of a CMOS 1.2J.tm
double poly n-well prototype of the fully differential
opamp. Measured results from the silicon prototype
are also shown in table 1. The I:..:l modulator CMOS
prototype, which was built using this opamp, displayed
a measured resolution of 15.7bits@l6KHz.
6.2. Fully-Differential Folded-Cascode Opamp
As a second example, let us consider the folded-
cascade fully-differential opamp of figure 10, which
displays the sizes provided by the tool. These sizes
13
190 Medeiro, Rodrfguez-Macfas, Ferndndez, Domfnguez-Castro, Huertas and Rodrfguez-Vdzquez

Fig. 7. Fully-differential opamp.

Table I. Simulated and measured resulls for the class-AB opamp.

Specifications Simulated Measured Units

Ao ~ 70 74.9 74.6 dB
GBW ~ 20 19.7 19.4 MHz
PM ~ 60 63.3 6S 0

Input white noise ~50 44.7 nVIVHz

OS ~7 8.0 8.2 v
Offset 3.3S mV
Power minimize 4.3 4.3 mW

Table 2. Sizing for the opamp of figure 7. of CPU time on a 100mips sparcstation. Simulation
results for the sized circuit are shown in the second
Mt,2 149.2/2.2 J.&m M21,22 48.2/2.2 pm column of table 3. The opamp has been integrated in
M3,4 22.0/2.2 M23,24 42.8/2.2 a CMOS 1.2mm double poly n-well technology. Ex-
M5,0 80.4/2.2 M2s,20 6.2/2.2
perimental results are given in the third column of ta-
MT,B 11.8/2.2 M21,2s 5.4/2.2
Mg,to 149.8/2.2 M29,30 78.8/2.2 ble 3. The final Et.. modulator prototype displayed
Mu,12 65/2.2 M3t,32 34.2/2.2 16.8bit@40KHz [23].
Mta,tt 78.8/2.2 M33-48 5.0/1.2
Mts,to 34.2/2.2 Mblaa 378.0/5
MtT,t6 121.8/2.2 Ct-4 0.4 pF
Mt9,20 142.8/2.2 lblaa 74 ItA 6.3. Regenerative Comparator

were obtained for the specifications needed in a
17bit@40KHz fourth order Et!. modulator. The spec-
ifications are given in the first column of table 3. Once
again only the power consumption was a design objec-
tive. The optimization process started from scratch on a
10-dimension design space and required about 45mins.
The comparator used in the same 17bits Et.. modu-
lator was designed using the high-frequency regen-
erative latch of figure 11 to meet the specifications
of table 4. The simulated and measured results of
the sized schematics provided by the design tool are
also shown in table 4. As for the previous opamp,

14
 Global Design of Analog Cells using Statistical Optimization Techniques 191

3.5

c 2.5
.S!
....
u
c
~
.... 1.5
"'0
u
0.5

0 # iterations
Fig. 8. Cost function evolution for the optimization of figure 7.

Fig. 9. Microphotograph of the fully-differential opamp of figure 7.

measurements correspond to a prototype built in a the measured resolution time and have found that they
CMOS 1.2Jlm double poly n-well technology. We have can be fully explained by taking into account the dy-
analyzed the origin of the slight deviations observed in namics of the measurement set-up.

15
192 Medeiro, Rodrfguez-Macfas, Fernandez, Domfnguez-Castro, Huertas and Rodrfguez- Vdzquez

Fig. 10. Fully-differential folded-cascode opamp.

Table 3. Simulated and measured results for the folded-cascode opamp.

Specifications Simulated Measured Units

Ao ~ 70 78.52 76.01 dB
GBW(lpF) 2: 30 34.88 MHz
GBW (12pF,IM!l) 4.17 4.21 MHz
PM(IpF) 2:60 66.28
PM(I2pF, IM!l) 87.2 86.8
Input white noise ~12 13.53 nV/.JHz
SR ~70 74.81 70.5 V/IJ.S
OS ~ ±3 ±3.2 ±3.0 v
Offset 3.35 mV
Power minimlze 1.95 1.93 mW

6.4. High-Frequency Analog Buffer
The analog buffer of figure 1 was designed for very low
input capacitance. The sizing obtained after 30mins
CPU time is shown in table 5. Table 6 shows the spec-
ifications, where the DC gain (A 0 ), output range (OS),
and power consumption are design objectives; the 3-dB
frequency is a weak restriction, and the input capaci-
tance is included as a constrained design objective. As
Table 4. Simulated and measured results for the comparator.

Specifications Simulated Measured Units

TPHL < 20 8.0 12.0 ns

TPLII <20 10.0 14.0 ns
Resolution < 60 40 36.4 mV
Offset 77 22.5 mV

Table 5. Tmnsistor sizes for the analog buffer of figure I.

M 1 ,2 4812.2 Ms,a 20.812.2 M8 403.212.2 I'm

Fig. II. Regenerative latch. MJ,4 167.212.2 M7 148.813 Cc 4.7 pP

16
 Global Design of Analog Cells using Statistical Optimization Techniques 193

shown in the third column of table 6 the tool was able results shown in table 3 for the same example. This is
to obtain a solution with input capacitance as low as due to the change in technological parameters. A tech-
0.07pF and /3dB of 34.35MHz. nology with available data about electrical parameter
correlations was necessary to apply the reduced vari-
Table 6. Simulated results for the analog buffer (output load ance technique. Hence, it was reasonable to compare
IOpP@IMU). the results with the memory-less technique using the
same technological parameters.
Specifications Simulated Units

f-adB > 30MHz 34.35 MHz

minimize C;n, with C;n < O.lpP 0.07
maximize Ao -0.169
maximize OS [-2.2,0.6]
minimize Power 3.726
6.5. An Example of Low Variability Sizing
The reduced variability technique has been applied to
practical topologies with good results. Table 7 gives the
results of the application to the folded-cascode opamp
of figure I 0. Electrical parameters were correlated ac-
cording to [ 16], and their variations are proportional
to transistor area and the distances between them [21 ].
Comparative Monte Carlo analyses are shown for the
design obtained with the statistical optimization tech-
nique described in Section 3 and 4, and that described
in this section. In particular, we have focused on those
specifications which are more sensitive to technologi-
cal variations: offset, DC gain, common-mode rejec-
tion ratio, and power supply rejection ratio. Probability
distributions resulting from Monte Carlo analysis for
the latter two are very asymmetric. Hence, it is more
interesting to show their possible minimum value in
said probability distribution.
Experimental results with the memory-less tech-
nique of Section 3 and 4 are seen to differ with the
Table 7. Simulation results for the folded-cascade opamp.
pP
6.6. Discussion of Results
dB
v
mW Summarizing, previous results demonstrate the possi-
bility to size complex analog cells in fully automatic
way, starting from scratch and without designer in-
teraction required - features that render the proposed
methodology very appealing for system designers. As
a matter of fact, resorting to the concourse of this
methodology, and using it also at the functional and
system levels has enabled to design full-custom Ell
modulators with reduced manpower in short time cy-
cles [23].
References
I. Degrauwe, M. G. R. et ol., "IDAC: An interactive design tool
for analog CMOS circuits," IEEE Journal of Solid-Stale Cir-
cuits, Vol. 22, pp. 1106-1114, December 1987.
2. Meixenberger, C., Henderson, R., Astler, L. and Degrauwe,
M., "Tools for analog design,'' Proc. Workshop on Advances
in Analog Circuit Design. pp. 357-368, Scheveningen, The
Netherlands, 1992.
3. EI-Thrky, P. and Perry, E. E., "BLADES: An artificial intel-
ligence approach to analog circuits design," IEEE Trans. on
Computer-Aided Design, Vol. 8, pp. 680-691, June 1989.
4. Gielen, G. and San ,;en, W., Symbolic Analysis for Automated
Design of Analog Integrated Circuits. Kluwer, Boston, 1991.

Memory·less technique Reduced variance technique

min. min.
Specs nominal mean variance value mean variance value Units

SR> 70 80.8 109.8 vt,...

offset 2.0 1.7 1.5 1.0 mV
power 1.73 1.1 mW
DC gain> 70 80.9 71.4 13.5 72 7 dB
GB >30 35 31 MHz
PM>60 65 62.9
noise< 12 13.4 II n
OS> 3 3.89 4.1 v
CMRR 75.12 45.3 82.5 49 dB
PSRR 150.0 94.4 165.0 105.5 dB

17
194 Medeiro, Rodrfguez-Macfas, Fernandez, Domfnguez-Castro, Huertas and Rodrfguez-Vazquez

S. Hwjani, R., Rutenbar, R. and Carley, L. R., "OASYS: A frame-

work for analog circuits synthesis," IEEE Trans. on Computtr-
Aided Design, Vol. 8, pp. 1247-1265, December 1989.
6. Onodera, H. et al., "Operational-amplifier compilation with
performance optimization," IEEE Journal of Solid-State Cir-
cuits, Vol. 25, pp. 466-4 73, April 1990.
7. Sheu, B. J., Lee, J. C. and Fung, A. H., "Flexible architec-
ture approach to knowledge-based analogue IC design," lEE
Proceedings, Vol. 137, Pl. G, pp. 266-274, Augustl990.
8. Young Koh, H., Sequin, C. H. and Gray, P. R., "OPASYN: A
compiler for CMOS operational amplifier," IEEE Trans. on
Fernando Mede1ro received the Licenciado en Ffsica degree
Computer-Aided Design, Vol. 9. pp. 113-125. Feb. 1990.
in 1990 from the University of Seville, Spain. He is currently
9. Gielen, G. E., Walshans, H. and Sansen, W., "Analog circuits
working towards the Ph.D. degree in the field of modeling
design optimization based on symbolic simulation and simu-
lated annealing,"IEEEJouriUll ofSolid-State Circuits, Vol. 25, and automated design of Ell. converters. Since 1991 he has
pp. 707-713, June 1990. been working at the Department of Analog Circuit Design of
10. Makris, C. and Toumazou, C., "ISAID: Qualitative reasoning the Centro Nacional de Microelectronica. His research inter-
and trade-off analysis in analog IC design automation," Proc. ests include mixed-mode integrated circuit design and design
IEEE Int. Symp. on CircuitsandSystems,pp. 2364-2367, 1992. automation.
II. Jongsma, J. et al., "An open design tool for analog circuits,"
Proc.lnt. Symp. 011 CircuitsandSystems,pp. 2000-2003, 1991.
12. Fern~ndez, F. V., Rodrlguez-Vbquez, A. and Huenas, J. L.,
"Interactive AC modeling and characterization of analog cir-
cuits via symbolic analysis," Analog Integrated Circuit and
SigMI Processing, Vol. I, pp. 183-208, Kluwer, Nov. 1991.
13. Boser, B. E. and Wooley, B. A., "The design of sigma-della
modulation analog-to-digital conveners," IEEE Journal of
Solid-State Circuits, Vol. 23, pp. 1298-1308, December 1988.
14. Nyc, W. etal., "DELIGHT.SPICE: An optimization-based sys-
tem for the design of integrated circuits," IEEE Trans. on
Computer-Aided De.rign, Vol. 7, pp. 501-519, April1988.
Rafael Rodrfguez·Macfas received the Physics degree in
IS . Campbell, C. A., HSPICE User Manual. Meta Sofiware Inc.,
Electronics in 1991 from the University of Seville, Spain.
1988.
He is currently working towards the Ph.D. degree in the field
16. van Laarhoven, P. J. M. and Aans, E. H. L., Simulated Anneal-
of statistical modeling and optimization of analog integrated
ing: TMory and Applications. Kluwer Academic Publishers,
Boston, 1987. circuits. Since 199 I he has been working at the Department
of Analog Circuit Design of the Centro Nacional de Micro-
17. Roberge, J. K., Operational Amplifier.<: Theory and Practice.
John Wiley & Sons Inc., New York, 1975. electr6nica. His research interests include analog integrated
circuit design and CAD methodologies.
18. Rutenbar, R. A., "Simulated annealing algorithms: An
overview," IEEE Circuits and Devices Magazine, Vol. 5, pp.
19-26, January 1989.
19. Director, S., Maly, W. and Strojwa<, A., VLSI De.rignfor Man -
ufacturing: Yield Enhancement. Kluwer Academic Publishers,
Boston, 1990.
20. Michael, C. and Ismail. M., "Statistical modeling of device
mismatch for analog MOS integrated circuits," IEEE Journal
of Solid-State Circuits, Vol. 27, pp. 154-166, Feb. 1992.
21 . Pelgrom, M., Duinmaijer, A. and Welbers, A., "Matching prop-
enies of MOS transistors," IEEE Journal of Solid-Slate Cir-
cuits, Vol. 24, pp. 1433-1440, Oct 1989.
22. Wang, C., Castello, R. and Gray, P. R., "A scalable high-
Francisco V. Fernandez received the Physics degree in Elec-
performance switched-capacitor filter," IEEE Journal ofSolid-
Stale Circuit.<, Vol. 21, pp. 57-64, February 19R6. tronics in 1988 and the Ph .D. degree in 1992, both from the
University of Seville, Spain. In 1988 he joined the Depart-
23. Medeiro, F., Perez Verdu, B., Rodriguez- V~zquez, Y. and
Huena<, J. L., "A tool for automated design of sigma-della ment of Electronics and Electromagnetism at the University
modulators using statistical optimization," Proc. of IS CAS '93, of Seville, where he is a teaching assistant. He is also at the
pp. 1373-1376. Chicago, May, 1993. Department of Analog Circuit Design of the Centro Nacional

18
 Global Design of Analog Cells using Statistical Optimization Techniques
de Microelectr6nica. During 1993 he stayed at the Katholieke
Universiteit Leuven, Belgium, as a senior researcher. His
research interests include design and modeling of analog in·
tegrated circuits and analog design automation.
Rafael Domfnguez-Castro received a five-year degree in
electronic physics (Licenciado en Ffsica Electr6nica) in 1987,
the M.S. equivalent in microelectronics in 1989 and the Doc-
tor en Ciencias Ffsicas degree in 1993, both from the Univer-
sity of Seville, Spain. Since 1987 he has been In the Depart-
ment of Electronics and Electromagnetism at the University
of Seville, where he is currently a teaching assistant. He is
also with the Department of Analog Circuit Design of the
Spanish Microelectronics Center (Centro Nacfona1 de Mi-
croelectr6nica). His research interests are fn analog/digital
Integrated circuit design, Including neural and fuzzy circuits,
and computer-aided design and modeling of analog integrated
circuits.
Jose L. Huertas received the Licenciado en Ffsica degree in
1969 and the Doctor en Ciencias Ffsicas degree in 1973, both
195
from the University of Seville, Spain. From 1970 to 1971 he
was with the Philips International Institute, Eindhoven, The
Netherlands, as a postgraduate student. Since 1971, he has
been with the Department of Electronics and Electromag-
netism at the University of Seville, where he is a professor.
He is also the Director of the Department of Analog Circuit
Design of the Centro Nacional de Microelectr6nica. His re-
search interests are in the field of multivalued logic, sequen-
tial machines, analog circuit design, and nonlinear network
analysis and synthesis.
Angel Rodrfguez-Vnquez received the Licenciado en
Ffsica degree in 1977 and the Doctor en Ciencias Ffsica de·
gree in 1983, both from the University of Seville, Spain.
Since 1978 he has been with the Department of Electron·
ics and Electromagnetism at the University of Seville, where
he is an Associate Professor. He is also at the Department
of Analog Circuit Design of the Centro Naclonal de Micro-
electr6nica. His research interests are in analog VLSI, in·
eluding neural, fuzzy and chaotic circuits, mixed-mode IC
design, and computer-aided design and modeling of analog
integrated circuits. He has published 45 journal papers, about
90 conference papers and several book chapters. Since June
1993, Dr. Rodrfguez-V,zquez has been an Associate Editor
of IEEE Transactions on Circuits and Systems.
19
 Analog Integrated Circuits and Signal Processing, 6, 197-208 (1994)
Q 1994 Kluwer Academic Publishers, B06ton.

A Multiple Input Differential Amplifier Based on

Charge Sharing on a Floating-Gate MOSFET*

KEWEI YANG AND ANDREAS G. ANDREOU

lHJHJrtml!lll of El•ctrlcal and Coii1{"Uer Engllle•rlng, Tire Johns Hopkins Unlverdty. Baltimore, MD 21218

iewel@olympUI.•u.Jhu.•dM; andrroo@olympiU.•c•Jiut.•d•

Abstract. The loseless property of an MOS floating gate is exploited to implement exact summing operations in
the charge domain. Loseless charge sharing in such structures yields circuits with potential applications as building
blocks for analog signal processing. Large signal as well as small signal models of floating-gate transistors are
presented for both above-threshold and subthreshold regions. Experimental data from fabricated devices in a 2
micron double poly, n-well process are in good agreement with the models. A canonical structure, the Multiple
Input Floating-gate Differential Amplifier is proposed and its use in different circuit configurations demonstrated.
Experimental data from a multiple differential input operational amplifier are presented. Limitations of the proposed
circuits are also discussed.

1. Introduction

Analog VLSI systems or subsystems, and their design

methodologies rely on computable functions that ex- • •• • ••
ploit underlying device physics [1, 2]. It is this, that V1~ 0 mt Vi~ Omi Vn~ Omn

-- f Ii
makes analog computing methods advantageous over

---
discrete time and digital algorithmic techniques forcer-
tain class of problems. It In
A basic operation in all electrical circuits is that
of current addition. Kirchoff's Current Law (nothing
lout
but conservation of charge) makes this operation exact.
Weighted summation, of some input signals X 1 (a)

vt
ct _i_

where Y; is the result and w,

are the weights is useful
operation in analog integrated systems and can be im-
plemented in two different ways. Figure 1 shows two
methods to implement weighted summation.
To compare their relative merits we make both of
them have voltage inputs and current outputs. In a the
first circuit, analog information is processed through
current sums. Bach input is a voltage-controlled cur-
rent source with transconductance Gm1 as a weight
(b)

• This work was partially supported by a NSF Research Initiation Fig. I. Weighted summation using (a) currents and transconduc-
Award (MIP-9010364). tances and (h) charges and capacitances.

21
198 Yang and Andreou
factor. The output of the circuit is given by
lout = L:: Gmt Vl
In the charge based circuit, first introduced as a
model of a neuron by Shibata and Ohmi [6] (see fig-
ure l(b)), exact summing is implemented by direct
conservation of charge on the floating node. A fixed
amount of charge is shared by input voltages through
coupling capacitors. C'P and G1 are parasitic capaci-
tance and leakage conductance, respectively. For an
ideal system these components have to be minimized.
The transfer function of such a system is given by
w1 is determined by capacitive coupling, which will be
addressed in a later section.
The Floating-Gate MOSFET is suitable for charge-
domain signal processing systems because its very
small parasitic capacitance and leakage conductance.
Charge-sharing circuits benefit from easy implementa-
tion and system expansion, and good matching among
input signals. Capacitors are better matched than tran-
sistors [3].
Analog computation and signal processing often re-
quires manipulation of analog signals with basic oper-
ations beyond the weighted additions. The Differential
Difference Amplifier (DDA) introduced by Siickinger
in 1987 employed current summing and is canonical
structure that can implement a wide range of analog
signal processing functions [4 ]. It has two pairs of
differential inputs which couple together in a current
summation. The output of the DDA is therefore the
comparison of the two differential pairs. However,
the mismatch among input transistors and bias current
sources causes nonlinearity in the circuits. This lim-
its further increase in the number of differential input
pairs. In addition, each input pair of the DDA has its
own operating range which also limits the function of
a DDA. Some improved designs ofDDAs and applica-
tions in signal processing have been reported in [5].
In this paper, we introduce a new charge-mode cir-
cuit called the Multiple Input Floating-gate MOS Dif-
ferential Amplifier, or MIFDA [11]. The operation
of the MIFDA is based on the idea of charge shar-
ing of a multiple control gate Floating-Gate MOSFET,
instead of current sums of currents in a DDA. The
implementation of Floating-Gate MOSFETs does not
require a special process. It can be realized in a
22
standard double-poly CMOS process. By replacing
the two input transistors with multiple control gate
Floating-Gate MOSFETs, we realize multiple differ-
ential input pairs. Since there are no extra transistors
introduced, problems caused by transistor mismatch
are no worse than a single input pair MOS differential
amplifier.
In Section 2 we discuss the physics of the multiple
control gate Floating-Gate MOSFET, which is the core
of a MIFDA. Designs of MIFDAs will be presented
in Section 3 along with measurements on a fabricated
MIFDA operational amplifier and analysis of its lima-
lions. Finally in Section 4, we show some potential
applications of MIFDAs as analog signal processing
building blocks.
2. The Multiple Control Gate Floating-Gate
MOSFET
Floating-Gate MOSFETs we present in this paper
are designed in standard double-poly CMOS process.
A multiple control gate Floating-Gate MOSFET, as
shown in figure 2, employs the first polysilicon layer
as a floating node. Three control gates made from the
second polysilicon layer couple with the floating-gate
in parallel through capacitors. Figure 2(a) is an ide-
alized layout of a multiple control gate Floating-Gate
MOSFET with minimum parasitic capacitance since
the control gates are stacked above the channel area.
However, this design limits the capability of changing
the channel dimension and the coupling capacitance.
The actual layout shown in figure 2(b) brings the dou-
ble poly coupling capacitance outside the channel re-
gion. The parasitic capacitance of the field oxide is
very small due to the thickness of the field oxide. In
contrast to a regular MOSFET, the floating gate voltage
governs the transistor operation. However, the floating
gate voltage is determined by the charge on the floating
gate and thus affected by all of the terminal voltages
associated with the floating gate through coupling ca-
pacitors.
The expression of the floating-gate voltage is the
key to modeling Floating-Gate MOSFETs. The ca-
pacitor model shown in figure 3 is used to calculate
the floating-gate voltage. The floating-gate voltage is
given by:
VFGB = [Cjc(wl V1 + · · · + Wn Vn) + Cj, VsB
+CJdVDB + Coxt/1 + QJg] /C,um
(I)
 A Multiple Input Differential Amplifier Based on Charge Sharing on a Floating-Gate MOSFET 199

(a)

Fig. 3. Capacitor model for a multiple control gate Floating-Gate

MOSFET.
Poly2
in both subthreshold and above threshold, we present

D
Polyl
models for both regimes.

~
Me tall
2.1. Subthreshold

In the subthreshold region, where the substrate sur-

D
Active
face is in weak inversion or even depletion, the surface
potential is a quasi-linear function of the control gate
voltages. We view a MOSFET as symmetrical device
(b) with interchangeable source and drain. The current
equation generally takes the form [2]:

Ivs = g(VaB)(?-l(VvB) -1-l(VvB)) (2)

v1 v
..L ooo .L/ Floating Gate Based on existing subthreshold MOSFET models [1,
Source~ Drain
7, 8, 9], we developed a subthreshold Floating-Gate
Substrate MOSFET model [10]. The current-to-voltage relation
for multiple control gate transistor is given by
(c) W (q(wtVt+· .. +wnVn)
Iv = - I0 e u,
L
Fig. 2. Multiple control gate Hosting-gate MOSFET. {a) Ideal struc-
ture; (b) actual layout; (c) symbol. (sVsa+CoVas ~ ~
e u, (e-u;-- e-ut)
where: (3)
c....m = (wt + ... + Wn)C/c + c,. where (c = K.Cfc/C;...m• (s =
K.C,.jc;,.m, (v =
+Cfd + Cfb +Co., K.Cfd/C;,.m. c;. .
m = c....
m - K.Coz· K. is the gate
efficiency. W and L are channel width and length re-
and l/J is the surface potential of the substrate. All volt-
ages in {1) are defined to be relative to the substrate
spectively. ! 0 is the current factor. Ut =
kT/q is the
thermal voltage. The saturation condition for a sub-
"B." w is the weight of each control gate defined by the
threshold transistor is approximately Vvs > 4Ut. The
relative value of its coupling capacitance with the float-
saturation region transconductance with respect to the
ing gate. Q/9 is the charge on the floating gate. This
sum of the control gate voltages is given by
charge is often not zero after fabrication and affects the
current voltage characteristics of the transistor. Since (clv
MOS transistors in a differential amplifier can work 9m = fJ;- (4)

23
200 Yang and Andreou

-7 of the multiple control gate Floating-Gate MOSFET in

I. 10
the saturation region is
-9
'I. 10 • (vlv
9d =gd+-- (6)
3: I. 10
-II Ut
..Y -13 - - - Measured
I. 10 Model 2.2. Above-Threshold
-15
I. 10
0.2 0.4 0.6 0.8 When a transistor operates in the above-threshold re-
gion, where the substrate surface in strongly inverted,
the surface potential no longer linearly depends on the
gate voltage. It remains a constant near 2</>F + VsB·
(a) We can substitute 1/1 in (1) with 2<PF + V88 for the
above-threshold operation. The floating-gate voltage
is now
VFGB = [(Cjc(WtVt+···+wnVn)+CJ•VSB
+CJdVDB + Co.,(24>F + Vss)
I. 10
+Qjg] /C.um
3: I. (7)
..Y I. 10 To maintain consistency in the model, we use the sym-
-12 - - - Measured metric formulation first introduced by Meyer [12] for
I. 10 the above-threshold region. The channel current in lin-
---Model
ear region is given by
-1 -0.8 -0.6 -0.4 -0.2
Vds(V) (8)

(b) where
F(VFGB, V) (VFGB - VrH - V) 2
Fig. 4. Output characterisllcs of single control gate Floating-Gate
MOSFETs. (a) N-channel; (b) P-channel. (9)
+ ~~(V + 2</Jp)!
For a regular MOSFET

(5)

and VrH is the threshold voltage, t 0 ., is the gate ox-

The nominal value V0 has the unit of volts and is pro-
ide thickness, and N B is the substrate doping concen-
portional to L. This voltage is analogous to the Early
tration. In properly operating differential amplifiers,
voltage in bipolar transistors and is determined exper-
transistors work in saturation region. When a transis-
imently. For Floating-Gate MOSFETs, the 9 function
tor saturates, VvB 2': v.ato VvB in (8) is replaced by
in (2) is not only an exponential function of control gate
V.at· Since F(VFGB, V.at) ~ 0, the saturation chan-
voltage but also a an exponential function of the source
nel current is given by
and drain voltages. The output characteristics of a sin-
gle control gate Floating-Gate MOSFET in figure 4 Iv = KF(VFGB• VsB) (10)
shows exponential increase of the drain current with
the drain voltage. Therefore the output conductance The saturation region transconductance with respect to

24
 A Multiple Input Differential Amplifier Based on Charge Sharing on a Floating-Gate MOSFET 201

........ ·········~···· .. ·· ..

1 o·7 ················r·················i.................·t···· ......

~.,
-
"d 1 o·9

1 o_,,

1 o·13
-2 -1 0 2 3 4 5

Fig. 5. Id• vs. V1 and V2 of an N-Channel two control gate Floating-Gate MOSI'ET, W
the weighted sum of control gate voltages is given by
2Cfc lj(TJ (II)
m c....
9m=--y.tHD
The output conductance is also different from that of a
regular MOSFET,
Yd = 9d + c2Cfd y'Ki; (12)
aum
where 9d = >.ID· >.is the Early effect parameter asso-
ciated with the channel length modulation.
In general, a multiple control gate Floating-Gate
MOSFET operating in either the subthreshold or
above-threshold region has a transfer characteristic as
following:
i = 9m(W!V! + W2V2 + · · · + WnVn) (13)
where 9m is given by (4) for the subthreshold and (11)
the above-threshold. One thing we shall mention here
is that the models described above are only good for
the first order analysis of the circuit operation, a better
complete Floating-Gate MOSFET model suitable for
circuit simulator has been developed here and will be
addressed elsewhere. The charge sharing on the float-
ing gate causes every control gate to have a weighted
influence on the output current. Measurement results
of a two control gate Floating-Gate MOSFET shown
= L = 4p.m, and control gate areas are 3 X 4 p.m2 •
in figure 5 gives the inside how the transistor works.
Both control gates have equal influence on the tran-
sistor's transfer function. If one view Vi as the gate
voltage of the transistor, v2
then governs the threshold
voltage of the transistor.
To control the floating gate charge, we can use UV
light which temporarily increases the conductance of
the oxide associated with the floating gate. The change
in conductance allows the charge and discharge of the
floating gate while maintaining the minimal leakage
current under normal operations. There are other tech-
niques reported to use a switch transistor connected
to the floating gate to change the floating gate charge.
However, we believe that in an analog system espe-
cially where Floating-Gate MOSFETs are used in dif-
ferential mode, even a small leakage current from the
floating gate will greatly affect the circuit performance.
The UV light method shows clear advantage over the
switch transistor method.
3. The Circuit Implementation: MIFDA Design
MIFDA circuit design follows the same principle of
regular Opamp or arA design except that the two in-
put MOSFETs are replaced by multiple control gate
Floating-Gate MOSFETs. Figure 6 shows a simple
two-stage multiple input Opamp. This circuit is de-
signed to work in the above-threshold region. Input

25
202 Yang and Andreou

bandwidth of 360KHz and a slew rate of 2V/J.LS. The

close loop follower has a linear range of-3.9V to 4.5V.
A large capacitance Cfc associated with each input is
responsible for the low frequency response of the am-
plifier. In a later section, it will be shown that C 1c
is also related to the input offset. Therefore, a com-
promise has to be made in order to achieve a desired
performance of the amplifier.

Vss -5V

=lb-
--< A
--<
--< -
--<

Fig. 6. 'Three ditreren!ial inputs two stage operational amplifier.

weights are designed to be I for all inputs. Using the

transistor model described in Section 2, the transfer
function of this Opamp can be given by

Vo = A[(V!+- vn + . .. +Wn+- vn-) +Vol/]

where A is the voltage gain, and Vaf 1 is the input
offset voltage. Transistor sizes are shown in table I.
Table I. Transistor dimensions of the circuits in figure 6. All
transistors have the same channel length L = lOJlm.
Device Tl,2 T3.4 T5,6 T7 T8
Type N p N N p p
60 25 64 330
W(1Jm) 80
The control gate to floating-gate coupling area AJc is
20x8011m2 • Rb is the bias resistor setting the bias cur-
rents for the two stages. A test chip was designed and
fabricated in a double polysilicon CMOS process. The
capacitor Cc and resistor Rc are designed for inter-
nal frequency compensation. In the actual circuit, Rc
is replaced by a P-type MOSFET (T9) to save space.
Figure 7 is a photograph of the actual chip. On the left
side there are two input transistors with three differ-
ential pairs. A large bias resistor and a compensation
capacitor are seen on the picture. The power supply
for the circuit is VDD = 5V and Vss = - 5V. Ibia•
is 40J1A. The amplifier has a open loop gain of 72dB
with one differential input pair while other two pairs
are grounded. It has a common mode rejection ra-
tio CMRR = 52dB. The amplifier has an unity gain
(14)
Fig. 7. Photograph of a two-stage three-input operational amplifier
implemented in a standard 2 Jlffi n-well double polysilicon CMOS
process.
3.1. Input Offsets
T9 The input offset of a MIFDA is an important issue in
10
designing the circuit. The offset can come from two
sources other than transistor mismatch. Let us assume
that the two input transistors are perfectly matched.
The input offset of a MIFDA can be derived from the
transistor model described in Section 2.
_c,d(v+ -v- )+Qjg-Qjg
TT
C (15)
Voff - C DB DB
fc fc
The second term on the right side of (15) is the floating
gate charge. When a chip is fabricated, there is usu-
ally random amounts of charge on the floating gates.
A non zero Qj9 - Q/9 results in a large random input
offset of the MIFDA. The method to erase the charge
on the floating gate is to shine UV light on the chip
while connecting all terminals of the circuit to ground.
The UV light excites some electrons to energy states
above the conduction band of the oxide layer, which
will increase the conductance of the oxide layer [13].

26
 A Multiple Input Differential Amplifier Based on Charge Sharing on a Floating-Gate MOSFET 203

Table 2. Input offsets In m V of the Opamp before and after the UV

treatment.

chip I chip2 chlp3

Before UV - 60 + 200 + 25
AfterUV -8 -8 -7

This conductance of the oxide allows the discharge of

the floating gate until the floating gate potential is the
same as ground. Table 2 shows a comparison of offset
voltages before and after the UV illumination of three
MIFDAs. The offset voltages range from -60mv to
+200mv before the UV illumination. The offset volt-
ages settle to -8mv after 5 minute UV illumination.
The first term of ( 15) is the second source of input
offset which is caused by the feedback of drain voltages
to floating gates through the coupling capacitors. From
( 1) and (7) one can clearly see that the floating gate volt-
age is not only a linear function of control gate voltages,
but also a linear function of drain and source voltages.
When the transistors biased at different drain voltages,
the floating gate voltages can be different even though
the control gate voltages are the same. The method to
reduce the drain feedback effect is to reduce the output
conductance by: increasing the control gate to floating
gate capacitance Ctc· Another benefit of doing this is
that the offset caused by the floating gate charge is also
reduced (see (15)). However, as we mentioned ear-
lier, increasing C1c would result in a decrease in the Fig. 8. A symmetrical design of mulliple Input operational trans-
frequency response. A trade-off is needed. conductance ampllller.
In subthreshold MOS analog circuits, OTAs are ma-
jor building blocks. Similar to the above Opamp de-
sign, a multiple input OTA has the following transfer
function. 3.2. Input Range
Io = Gm[(Vi+- vn + ··· + (Vn+- vn-) +Van) A current-mode DDA has a limited input range for each
(16) input pair. Alternative input stage designs have been
suggested to solve the problem [5]. For a differential
where Gm is the overall transconductance of the OTA. amplifier to work properly, the input stage should have
Voff has the same expression as in (15). Since the drain a good linear differential transconductance. The in-
current is more sensitive to the drain voltage feedback put differential pair shown in figure 9(a) must have a
effect in the subthreshold region than in the above- non-saturation differential current output !l.J for a dif-
threshold region because of the exponential current-
to-voltage relation, a simple OTA design will have a
ferential voltage input A V, in other words, 9U # 0.
In the above-threshold region, this requires both input
large input offset. A wide range OTA design as shown transistors working in the saturation region. In a DDA
in figure 8 is proposed to solve the problem. Cascade circuits, each input differential voltage is limited in op-
current mirrors improve the voltage gain and reduce the erating range as follows
offset. The symmetrical current mirrors at the top of
the input differential pair keep the same drain voltages
for the two input transistors VJ'B - VDB = 0, (17)

27
204 Yang and Andreou

I+ I·
I+ I.
In the subthreshold region, the transfer function is
given by [1]:
t t
v+-i~~v- !:!.I
,.;,/:iV
= Ibia.tanh-2- (18)

.
vbtas _j
I
t !bias
The input range is defined such that the tanh function
-::- (a} is in the quasi-linear region. For ,.;, = 0.6, the input
Fig. 9. A comparison of input stages. (a} DDA; (b) MIFDA. range is approximately l!:i VI ~ lOOmV.

(a) (b)

(c) (d)

(e)

Fig. 10. Examples of applications or MIFOAs in analog computational systems.

28
 A Multiple Input Differential Amplifier Based on Charge Sharing on a Floating-Gate MOSFET 205

For a MIFDA input stage shown in figure 9(b ), the
above limitation applies only to the differential float-
ing gate voltage, l1 V19 , instead of each differential pair.
This means that there is only a range limit for the sum
of input differential voltages.
(19)
Here we assume uniform wei~hts for all inputs. From
the device model, we know 0: > n. In the worst
case when all differential inputs are the same in both
amplitude and phase, the input range is still slightly bet-
ter than that of a current-mode DDA. A small amplitude
of one differential signal will help increase the ranges
of other input signals. Furthermore, phase difference
among signals will also help improving the operating
range of input signals.
Figure 13 shows a self-compensating sample-and-
hold circuit using a MIFDA. The leakage current
through the switch transistor causes a decrease in
the holding time of a regular sample-and-hold circuit.
However, the follower made of a MIFDA responds only
to the differential input. A similar leakage at the neg-
ative node v- virtually compensate fot the leakage at
the positive node v+. In the sample period, the gates
of the two switch transistors aresetto V8 s. v-is con-
nected to ground while v+ is connected to the sample
signal. In the hold period, the gates of the switch tran-
sistors are changed to Vvv . The leakages of the v-
node and the v+ node cancel each other to maintain
a longer holding time. We shall point out that for this
circuit to work, the two leakage currents have to be
very similar.

4. Applications of MIFDAs In Analog

Computation

There are many examples of analog computational cir-

cuits in which a single MIFDA can replace one or more
differential amplifiers and many external passive com-
ponents. All of the analog circuits using DDAs can be
implemented with MIFDAs directly without additional
modification. To simplify the following expressions,
we assume the MIFDA has a infinite gain.
Figure 10 shows some examples of analog sig-
nal processing circuits which employ MIFDA. Fig-
ure IO(a) is a level shifting follower with V2 connect-
ing to a DC voltage source. The output signal fol-
lows the input signal with a DC shift of V2 • The
experimental results are shown in Figure 11. Fig-
ure lO(b) is a differential-to-single-ended voltage con-
verter. It is useful for detecting an internal voltage
drop in a circuit without affecting the circuit operation.
It can also be used differential transconductor, where
! 0 = Gm(V- V0 ) . Figure IO(c) is a simple analog
Fig. II. Experimental result• of 5etup (a) in figure 10.
voltage inverter with a gain of -1. Figure 10(d) is a wide
range linear transconductor with high input impedance
and low output impedance. Our design of MIFDAs has MIFDAs can also be used in <iynamic analog signal
three pairs of differential inputs. Figure 10(e) shows processing circuits. Figure 14(a) shows a differential
an instrumentation amplifier with programmable gain integrator where the output only responds to the change
of (Rl + R2)/ Rl. Figure IO(f) shows how to use the in input differential voltage not the absolute value. It
third differential pair to compensate the input offset. has a transfer function
Figure 12 is the implementation of a 4-bit D/A con- 1 ( V + -V)
-
V0 = - - (20)
verter using a weighted input MIFDA. ST +1

29
206 Yang and Andreou

w0 =1/8
Wt=l/4
W2=1/2
wa=l

Fig. 12. A 4-bit D/A converter using weighted input MIFDA.

Hold

Fig. 13. A self-compensating sample-and-hold circuit using a MIFDA.

where r = C/Gm. Figure 14(b) shows a differential lower circuit complexity and better input transistor
differentiator. The transfer function is matching. The input range of a MIFDA is improved
V, = Asr (V+ _ v-) over its DDA counterpart. This provides more flex-
(21)
ST +1 ibility in the use of MIFDAs. The input offset prob-
lem associated with the floating-gate MOSFETs is well
studied. UV light is used for after-fabrication treat-
5. Conclusions
ment of offset caused by the random distribution of
Multiple control gate floating-gate MOSFETs are floating-gate charge. A symmetrical input stage de-
proven to be effective in realizing multiple input dif- sign is also effective in eliminating offsets caused by
ferential amplifiers, which function like regular CMOS the drain feedback effect. It should be pointed out here
DDAs and have some unique advantages including that the circuits we designed for testing are simple and

30
 A Multiple Input Differential Amplifier Based on Charge Sharing on a Floating-Gate MOSFET 200

c
T
(a)

(b)
Fig. /4. Dynamic analog signal processing circuits. (a) Differential Integrator; (b) differential Differentiator.

not fully optimized; however, the same design princi-
ples could yield practical amplifier designs. The use of
MIFDAs in analog computational systems are not lim-
ited to the examples we show in the last section. We
believe that MIFDAs have the potential to be the center
of many future analog signal processing systems.
6. Acknowledgments
We thank Paul Furth for his suggestions on improved
circuit design. We also thank Mark Martin and peo-
ple in Analog VLSI group at Johns Hopkins for proof
reading the manuscript
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Systems, Vol. 40, pp. 289-301, May 1993.
6. Shibata, T., Ohml, T., "A functional MOS transistor featuring
gate-level weighted sum and threshold operations," IEEE Tran.
Electron Devices, Vol. 39, pp. 1444-1455, June 1992.
7. Vittoz, B. A. and Pellrath, J ., "CMOS analog Integrated circuits
based on wealc Inversion operation,'' IEEE J. of So/id...State
Clrr:uits, Vol. SC-12, pp. 224-231, June 1971.

31
208 Yang and Andreou
8. Vittoz, E. A., "The design of high-performance analog cir-
cuits on digital CMOS chips,"IEEE J. of Solid-State Circuits,
Vol. SC-20, pp. 657-665, June 1985.
9. Fichtner, W. and Piltz!, H. W., "MOS modeling by analytical
appro~imations," Int. J. Electronics, Vol. 46, 1979.
10. Yang, K. and Andreou, A. G., "Subthreshold Analysis of
Floating-Gale MOSFETs,'' in Proc. Tenth Biennial UGlM
Symposium, pp. 141-144, Research Triangle Park, NC. May
1993.
II. Yang, K. and Andreou. A. G., "Multiple Input floating-gate
MOS differential amplifiers and applications for analog com·
putalion,'' Proc. 36th Midwest Symposium on Circuits and Sys·
tems, IEEE, August 1993.
12. Meyer, J. E., "MOS models and circuit simulation,'' RCA Re·
view, Vol. 32, March 1971.
13. Glasser, L. A.," A UV write-enabled PROM,'' 1985 Chapel
Hill Conference on VLSI, pp. 61-65. Computer Science Press,
1985.
Kewel Yang received the B.S. degree in electronic engi-
neering from Tsinghua University, Beijing, China, in 1986
32
and the M.S. E. degree in electrical and computer engineer-
ing in 1991 from The Johns Hopkins University, where he
is currently working toward the Ph.D. degree. From 1986 to
1989, as a research engineer in Microelectronics R&D Cen-
ter at Chinese Academy of Sciences, he worked on gate array
ASIC design tools including logic, transistor and physical
layout cell libraries. He is now a research assistant in the Mi-
croelectronics Laboratory at The Johns Hopkins University,
working on device modeling, floating-gate analog memory
and subthreshold MOS analog VLSI.
Andreas G. Andreou received the M.S.E. and Ph.D. de-
grees in electrical engineering and computer science from
the Johns Hopkins University, Baltimore, in 1983 and 1986,
respectively. From 1987 to 1989 he was a postdoctoral fel·
low and associate research scientist at Johns Hopkins, where
he became Assistant Professor in 1989 and Associate Profes-
sor in 1993. His research interests are in the areas of device
physics, integrated circuits/systems and neural computation.
Dr. Andreou is a member of Tau Beta Pi.
 Analog Integrated Circuits and Signal Processing, 6, 209-217 {1994)
Q 1994 Kluwer Academic Publishers, Boston.

Design and Applications of a CMOS Analog Multiplier Cell

Using the Differential Difference Amplifier•

SHU-CHUAN HUANG 1 AND MOHAMMED ISMAIL

Department of Electrical Eng/Me ring, 'I'M Ohio State University, Columbus, Ohio 43210-1272
1 Now l.r an Associate Professor at the Dept. of Electrical Eng .. Tatwng lii.Stltwtt of Technology. Talpe~ 1blwan, ROC

Abstract. This paper presents design techniques for a wide input range CMOS differential difference amplifier
(DDA) and discusses its application as a basic block in the implementation of a simple four-quadrant multiplier celL
The cell can be configured as an amplitude modulator or a one-over circuit, which are widely used in many analog
signal processing applications. The DDA can also be reconfigured as an opamp, and hence can be used to design
many of the opamp-based multiplier circuits. The DDA amplitude modulator (AM) uses a transistor and a resistor
as the only components external to the DDA. A DDA one-over circuit, which provides an output proportional to the
inverse of the input, is also achieved with the same level of simplicity. High-frequency effects due to the DDA's
finite gain-bandwidth (GB) and MOS parasitic capacitances are investigated. Experimental results obtained from a
2 ~tm CMOS MOSIS chip are given.

1. Introduction
The Differential Difference Amplifier (DDA) is a novel
Vpn ---1
analog building block, whose symbol is shown in fig-
ure l(a). The concept of operation is similar to that of Vpp ---1
an opamp with the output given as Vnn ---1
Vnp ---1
Vo = Ao[(Vpp- Vpn)- (Vnp- Vnn)] Ao-+ 00

(I) (a)

tY :
where A 0 is the DC gain of the DDA and (V,p- Vpn)
and (Vnp- Vnn) are the two differential voltage inputs.

~~~
Therefore, if a negative feedback is introduced through Vo
nodes Vpn and/or Vnp• the following design equation
is obtained. Vnn
-Vo
Vnp
Vw- Vpn = Vnp- Vnn (2)
(b)
A fully-differential DDA (FDDA), shown in fig-
ure 1(b), can be designed in a manner similar to a Fig.l. Symbolsof(a)DDAand(b)PDDA.
fully-differential opamp [1]. Furtherm(>re, A DDA can
be reconfigured as an opamp as shown in figure 2 [2], As a result, the DDA can be used to develop opamp-
so that based building blocks. Figure 3 shows examples of
opamp-based multipliers [3, 4]. The output of circuit
(3) (a) is given by

• Parts of this work have been presented at the I Oth Norchip Sem- (.lf) 1 (Xl- X2)y
(4)
inar, Helsinki, Finland, November 3-4, 1992 and Included In the
Seminar's proceedings, pp. 9-14. This work was supported In part (.lf) 2 (Zl- Z2)
by the NSF grant MIP-88%244 and by the Semiconductor Research
Corporation contracts 90-DJ-066 and 91-DJ-066, and In part by the where C!f .lf
)I and ( )2 represent the sizes of tran-
Norwegian NTNF, SINTEP and Nordic VLSI. sistors in the input and feedback sides of the opamp

33
 210 Huang and Ismail

Z2
_L

(a) y Vo

-Y
Yo

-Yo

(b)
T
Z2
(a)
Fig. 2. (a) Single-ended and (b) fully-differential opamps.

respectively. The output of circuit (b) is

v, _ (f)dXl- X2)(Yl- Y2) (5)

o - (f) 2 {Zl-Z2)

In addition, the DDA can be used to develop its own set

of basic analog cells, such as an adder/subtractor, dif- Y2
ferential integrators and multipliers/dividers [5, 6]. In
Yl
this paper, we will focus on the design of DDA-based
multipliers, which are widely used in analog signal
and information processing applications such as mod-
. ulation, demodulation, mixing and neural computation
[7]. In the next section, we will discuss the design of
DDA-based circuits such as an amplitude modulator, a
Zl
four-quadrant multiplier and a one-over circuit. Sim- (b)
ulation results will be provided to verify the operation
of the proposed circuits. The design of a DDA with Fig. 3. Opamp-based multiplier/divider using (a) fully-differential
a wide input range will be presented in Section 3. In and (b) single-ended opamp.
Section 4, high-frequency nonideal effects in the AM
circuit are investigated. Experimental results of the
DDA modulator will be given in Section 5.

2. Design of DDA-Based Multipliers/Modulators Vin~-Vin

Before discussing the design of a DDA-based multi-
plier, we first consider a MOS transistor operating in
the linear region with its drain and source nodes biased
out of phase as shown in figure 4. As a result, the drain
current is given by
(6)
ID
Fig. 4. MOS transistor with its drain and source biased out of phase.
where K = J.LC0 .,W/L and Vr is the threshold volt·
age of the transistor. This configuration results in the
cancellation of the second-order term ('IIi;) such that
the input voltage (V.n) and the drain current has lin-
ear relationship. The transistor is therefore equiva-
lent to a grounded resistor with a resistance equal to

34
 Design and Applications of a CMOS Analog Multiplier Cell Using the Differential Difference Amplifier 211

VM+vm
vM~sv­
4
VM=4V
3 VM=3V
Vc VM•2V ·-···

Vo
0
-I
-2
(a) -3
-4

VM+vm I R -sL_~~-~~~~~~-~~~
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8

y,~
Vc(V)

:Vo
Fig. 6. Output transfer curves of tbe multiplier with various VM.

~
where A is a DC signal and fm(t) and cos wet are the
-Vo modulating and carrier signals respectively. m is the
modulation index, where m ~ 1 is required for demod-
(b) ulation using an envelope detector [8]. According to
(7) and (8), one can see that Vm operates as the modu-
Fig. 5. DDA-based multiplicationlrnoduiation cell (a) single-ended lating signal and V., as the carrier signal. The DC signal
and (b) fully-differential.
A is
1/2K (VG- Vr). The inverting bias of drain and source A=- [1 + 2KR(VM- Vr)] (9)
nodes can be achieved by a DDA with Vnp = Vin•
and the modulating index m is
Vpp = Vnn = 0 and a negative feedback through node
Vpn• which can be verified easily using design equation 2KR
(2). The output voltage of a multiplier is obtained by m = 1 + 2KR(VM- Vr) (lO)
converting the resulting current into a voltage through
a resistor as shown in figure 5. The output is obtained To satisfy the condition m ~ 1, we must have
as
R ~
2K(VM - Vr- 1)
Vo -Vc- 2KR(VM + Vm- Vr)Vc
for VM- Vr >1 (II)
-[1 + 2KR(VM- Vr)]
(7)
1
[ 2KR ] R ~
1 + 1 + 2K R{VM - Vr) Vm Vc 2K(VM- Vr- 1)
for VM- Vr <1 (12)
where VM + Vm ~IV.: I+ Vr for an NMOS transistor. On the other hand, the amplitude of Vo is limited by
Note that the above expression results in a multiplica- the output swing of the DDA used. If the maximum
tion of Vm and V.,. SPICE DC simulation results of output amplitude is assumed to be Vvv(= -Vss),
Vo versus V., with various VM (vm = 0) are shown in V., = Vcp cos wet and Vm has amplitude VMP. we
figure 6. To be more specific, the multiplier functions have
as an amplitude modulator. Recall that an amplitude
modulated (AM) waveform with a sinusoidal carrier is
[1 + 2KR(VM- Vi)]
given by
2KRVMP ]
x [ 1 + 1 + 2KR(VM- Vr) Vcp ~ Vvv
¢AM(t) = A(l + mfm(t))coswct (8) (13)

35
212 Huang and Ismail

Therefore,

(14)

Combining (1 1), (12) and (14), we have

Vc
VDD/Vcp -1 Vo
2K(VM- VT + VMP) +
for VM- VT >1

. [-
mm 1
-::-::-::-:=-:----::c:--,..,.
2K(VM- VT -1)'
Fig. 8. Threshold-voltage-independent DDA-based multiplier.
VDD/Vcp -1 ]
2K(VM- VT + VMP) Since R is inversely proportional to K, a small value of
R can be used by choosing a large K value (large W)
for VM- VT <1 for the transistor. Figures 7(a) and (b) show the SPICE
(15) simulation outputs of the modulator with R =
500 n
and 800 n respectively, where W / L = 50 JLmi3JLm
andVT = 0.975VfortheNMOStransistorandVM =
4 4 V. vm is given as a sinusoidal wave (amplitude IV)
with frequency 1 KHz and V, is a square wave (ampli-
tude 1V) with frequency 20 KHz.
A straightforward way to implement a threshold-
0
voltage-independent multiplier is to use two modula-
tion cells as shown in figure 8. The output is given
-2
as
-4
(16)
0 0.0005 0.001 0.0015 0.002
t(sec)
where transistors M 1 and M2 are assumed matched.
One of the inputs, Vm = Vml - Vm2• and the output
(a) are differential. If a single-ended output is desired, a
differential-to-single-ended converter is easily realized
by a DDA difference amplifier [5]. However, a sim-
pler implementation can be obtained using the opamp
architecture shown in figure 3(a).
Using the same concept, a one-over circuit, which
provides an output proportional to the inverse of the
0
input, can be achieved by the circuit shown in figure 9,
where Va and VB are bias voltages and v;n is the input
-2
of the circuit. This circuit finds many applications, e.g.,
-4
a tracking system where the target velocity is inversely
proportional to an integrated pulse width [9). Note
0.0003 0.001
t(sec)
0.0015 that the FDDA is connected as a differential unity gain
buffer [ 10]. As a result, the outputs are directly con-
nected to the inputs of the FDDA (high input impedance
(b) nodes), and therefore the buffer stage in the FDDA can
Fig. 7. Simulation results of the DDA modulator with (a) R = SOOn
be eliminated. From (2) we have VI-Vo = v2- (- Vo)
and (b) R = soon. which gives VI - v2 = 2Vo. Since VI = VB -1 Rand

36
 Design and Applications of a CMOS Analog Multiplier Cell Using the Differential Difference Amplifier
Fig. 9. Simple one-over circuit.
V2 =-VB+ IR, then V1 = -V2 and hence V1
and V2 = - V0 • According to (6),
And since V0 = VB- I R, the resulting output function
is proportional to the inverse of v1n and is given by
Vo = [1 + 2KR(Va ~~T)] + 2KRv;n
This circuit could also perform voltage division.
SPICE simulation results are given in figure I 0 with the
same NMOS transistors used in the modulator, Va =
4 V and R = 800 n. One can observe that one-over
the output is linearly proportional to the input.
The useful voltage range of the circuits discussed
is limited by the input range of the DDA. This is due
to the fact that there is no virtual short between the
single-ended voltages Vw and Vpn Wnp and Vnn) [5].
In the following section, the design of a wide input
range DDA will be discussed.
Ql Ql Ql M Q6 Ql
~
Vln(V)
~
Fig. 10. Simulation results of the simple one-over circuit.
213
3. Design of a Wide Input Range DDA
The simplest way to implement a DDA is to make use
of an opamp design concept with an additional two-
transistor differential pair as the added input port [ 11].
However, the input operating range is limited by the
nonlinear I-V property of the differential pair. To cir-
cumvent this problem, one can replace the differential
pairs with wide-range linear V-I converters. The lin-
= Vo ear V-1 converter used in this paper is shown in fig-
ure 11 [5]. The overall DDA circuit is shown in fig-
ure 12, where M 1-M 10 form a cascode gain stage, and
(17)
(1 8 )
v,
Fig. 11. A linear CMOS V-1 converter.
Vi.1 and Vb2 are the bias voltages. The input operating
range of the DDA is therefore widened by the linear V-
I converter. A fully-differential DDA is implemented
by a DDA with a common-mode feedback circuit [1].
The opamp reconfigured from a wide input range DDA
should exhibit a good performance at high frequencies,
due to its linear transconductances at the input stages.
4. High-Frequency Nonldeal Effects
In this section, high-frequency nonideal effects such
as the finite gain-bandwidth (GB) of the DDA and the
MOS parasitic capacitances will be investigated for the
AM circuit. To reduce the complexity of calculation,
09
these two effects will be dealt with separately in a man-
ner similar to that discussed in [12] for opamp MOS
circuits.
37
214 Huang and Ismail
Vdd

Vss

Fig. 12. A CMOS wide input range DDA circuit.

Finite GB Effect
Vo = Vpn-IR
If the finite GB effect of the DDA is taken into ac-
count in the AM circuit, nonlinearities are introduced
in the transistor current I, since the DDA inverter is now
frequency-dependent. Assume the open-loop gain of
the DDA is modeled by A(8) = GB/8. According to
(2), we have + (VG- VT +\'c) 2;B Vo] (22)

which gives
(19)
V0 = -[1 + 2KR(Va- VT)]\'c x €GB(8) (23)
i.e.,
where fG 8 ( s) is an error function resulting from the
GB effect and is given by
(20)
1
(24)
Note that Vpn is no longer equal to - Vc. The current fGB( 8 ) = 1 + crn[1 + KR(VG- VT + Vc)]
I is therefore given by
It results in a phase lag, (),written as
w
() = tan- 1 GB[1 + KR(VG- VT + Vc)] (25)

which may degrade the high-frequency performance.

Magnitude errors lt:aB{jw)l <~ 1- [1 + KR(Va-
VT + Vc) ]2 2 (5~2) are of second-order and can be ne-
glected.
(21)

where VG = VM + Vm. The 8 and s 2 terms in the MOS Parasitic Effects

above equation result from the GB effect. Moreover,
V02 in s 2 term would introduce second-order harmonic At high frequencies, aMOS transistor operating in the
component in I. Fortunately, since the frequency range triode region can be modeled as shown in figure 13,
of interest is much smaller than GB, the 8 2 term can where Ra is the small signal MOS resistance given by
be neglected in the calculation. The output voltage is 1
written as RG = K(VG - VT) ( 26 )

38
 Design and Applications of a CMOS Analog Multiplier Cell Using the Differential Difference Amplifier 215

Therefore, the equivalent resistance Req is

1 1 Rc
Req = y II 8C, = 2 X ET(8) (30)

where the error function ET (8) is given by

:r.8 +1
Fig. 13. Small-signal high-frequency model of a MOS transistor
operating in the triode region.
ET(8) = &Q..r.82 +
12
(&Q..
2
+ .!.)8 + 1
4
(31)

Again, the 8 2 term in the denominator is practically

small and is negligible, and ET(8) is approximated by
.!.8 + 1
E (8) - ......,.---;o:"-6 - - - (32)
T - (R'{• +f)8+1
Vo
whose magnitude and phase are obtained as

Fig. 14. AM circuit with aMOS small-signal high-frequency model. 1 + (Ra2C, + f)2w2
Cd and C, are extrinsic capacitances and Cp represents tan-
l WT -tan- l w -
'6 (ReG, + 'T)4
2-
the distributed capacitances in the channel, which are
modeled as a uniform RC transmission line. The first (33)
order y parameters of the transmission line are given
The distributed effect reduces the equivalent resistance
by [12]
of the transistor slightly, and introduces small phase
lag. The output voltage is written as
IT+ 1
Y11 ~ ---2"'=-...,.-
Y22 ~ Rc("f + 1) -V.,- IR
(27)
-1 -Vc[1 + 2KR(Va- VT)/ET(8)] (34)
Y12 = Y21 ~ Rc(1f + 1)

5. Experimental Results
where T = RaCp and Cp = C 0 ., W L. Using the
model, the AM circuit is redrawn in figure 14. Note The DDA proposed in Section 3 was fabricated in a
that the extrinsic capacitance cd is eliminated in the 2 1-lm P-well MOSIS CMOS process. A common cen-
figure, since it is driven by a voltage source Vc. Using troid layout technique was used to improve the match-
the admittance parameters, we may write the following ing of the devices incorporated in the input stages, Fig-
equation. ure 15 shows the measurement of V0 with Vm (100Hz
and amplitude I V), v;, (not shown with I KHz and
amplitude I V) and R = 220 !1. The transistor in the
circuit is built by a series combination of2 SK9160 de-
pletion transistors (which have their sources connected
The equivalent admittance, Y, is therefore given by to the bulks) with their gates and sources connected
respectively and their drains being the new drain and
y Ir /2 source of the composite transistor. This implementa-
Vc = -'V;, tion reduces the body effect of the transistors. The
depletion mode transistors were chosen to simplify the
Y11- Y12 = Y22- Y21 experiments since they are normally on (no DC com-
ponent, VM, is required). It can be seen from figure 15
(29) that the envelope of the output is proportional to the
Rc(~ + 1) modulating signal Vm.

39
216 Huang and Ismail

h,P running
· · · ..........,. . . . . . . . . . . ,.................... ,................. , 1 500 IV I d i v

. J. . . ..
!

..... . ......
V., Joffset:-35.00 mv
.. •····~ . .. .. .. . .... .... . . ~ 1 ' 000 1 cc

:/ ··~ [\
\
J\ v; :, \
[\ r; \
i ·\ .... ... ···~. . ··+ . ·~

..
4 500 W:V/dlV
·~ offset•-35.00 mv
.r··
1 . 0()0 1 cc
....... i
-10.0000 ms 0. 000(10 s 10.0000 ms
2.00 ms/dill
Fig. 15. Experimental results of the DDA modulation cell.

6. Conclusions
The design of a wide input range DDA and a simple
DDA-bascd multiplier cell have been discussed, and
experimental results are given. A DDA can be recon-
figured as an opamp to make use of opamp-based build-
ing cells. In addition, simple AM and one-over circuits
are developed by reconfiguring the basic multiplier cell
and taking advantage of the differential input prop-
erty of the DDA. This demonstrates that the DDA is
a competitive building block to opamps in many signal
processing applications. AII-MOS implementations of
the circuits discussed in this paper are easily achieved
by replacing resistors with aii-MOS voltage-controlled
floating resistors, e.g. see [13]. The voltage-controlled
resistors will provide electronic programmability of the
output voltage.
References
I. Huang, S.-C. and Ismail, M., "A CMOS differential differ-
ence amplifier with rail-to-rail fully-differential outputs" (to
be published).
2. Zarabadi, S. R., Larsen, F. and Ismail, M., "A configurable
op-ampfDDA CMOS amplifier architecture," IEEE Tran•. Cir-
cuits Sy•t., Vol. 39, pp. 484-487, June 1992.
3. Khachab, N. I. and Ismail, M., "MOS multiplier/divider cell
for analogue VLSJ," Electron. Lett., Vol. 25, pp. 1550-1551,
Nov. 1989.
4. Khachab, N.J. and Ismail, M., "A nonlinear CMOS analog cell
for VLSI signal and information processing," IEEE J. Solid-
State Circuits, Vol. 26, pp. 1689-1699, Nov. 1991.
5. Huang, S.-C., Ismail, M. and Zarabadi, S. R., "A wide range dif-
ferential difference amplifier: A basic block for analog signal
procerssingln MOS technology," IEEE Trans. Circuits Sy!l.-
II, Vol. 40, pp. 289-301, May 1993.
6. Ismail, M., Huang, S.-C. and Sakurai, S., "Continuous-lime
signal processing," in Analog VLSI: Signal and lnfornuuion
Procusing, edited by M. Ismail and T. Piez, ch. 3, McGraw-
Hill, 1994.
7. Mead, C. and Ismail, M., Analog Vl.SIImplementation of Neu-
ral Systems. Kluwer, 1989.
8. Stremler, F. G., Introduction to Communication Systems.
Addison-Wesley, 1982.
9. Etienne-Cumrnings, R., Hathaway, R. and Van der Spiegel,
J., "Accurate and simple CMOS 'one-over' circuit," Electron.
Lett., Vol. 29, pp. 1618-1620, Sept. 1993.
10. de Ia Plaza, A. and Morlan, P., "Power-supply rejection in dif-
ferential switched-capacitor filters," IEEE J. Solid-State Cir-
cuits, Vol. SC-19, pp. 912-918, Dec. 1984.
II. Sackinger, E. and Guggenbuhl, W., "A versaUle building block:
the CMOS differential difference amplifier," IEEE J. Solid-
State Circuits, Vol. SC-22, pp. 287-294, Aprill987.
12. Khachab, N. I. and Ismail, M., "Linearization techniques for
nth-order sensor models in MOS VLS! technology," IEEE
'fran Circuits Syst., Vol. 38, pp. 1439-1450, Dec. 1991.
13. Sakurai, S. and Ismail, M., "A CMOS square-law pro-
grammable floating resistor independent of the threshold volt-
age,'' IEEE Trans. Circuits Syst., Vol. 39, pp. 565-574, Aug.
1992.

40
 Design and Applications of a CMOS Analog Multiplier Cell Using the Differential Difference Amplifier
Shu-Chuan Huang was born in Taipei, Taiwan, in 1965.
She received the B.S. degree from National Central Univer-
sity, Taiwan, in 1987 and the M.S. degree from the Ohio State
University, Columbus, In 1990, both in electrical engineer-
ing. She is currently a Ph.D. student of electrical engineer-
Ing and a Research Assistant at the Ohio State University,
Columbus. Her research interests are in the area of analog
integrated circuit analysis and design. She was employed by
Tatung Institute of Technology, Taiwan, as a teaching assis-
tant, 1987-1988, and received a scholarship from the institute
while at the Ohio State University.
Mohammed Ismail is a professor in the Department of Elec-
trical engineering nt The Ohio State University (OSU). Previ-
217
ousiy, he held several positions in both Industry and academia
and has served as a corporate consultant to nearly 20 compa·
nies in the U.S. and abroad. In 1985, Dr. Ismail received the
NSF Presidential Young Investigator Award, and in 1993, the
OSU Lumley Research Award in recognition of outstanding
research accomplishments. In 1984, he received the IEEE
Outstanding Teacher Award at the University of Nebraska.
Dr. Ismail is the founder of the Int. J. Analog Integrated Cir-
cuits and Signal Processing and currently serves as the Jour-
nal's Editor-in-Chief (N. America). He has been the Circuits
and Systems Society Editor of the IEEE Circuits and De-
vices Magazine since I 991 and was the Chairman of the So-
ciety's Tech. Committee on Analog Signal Processing from
1987-1990. He also served as Associate Editor of the IEEE
Transactions on Circuits and Systems ( 1989-1991) and of the
IEEE Transactions on Neural Networks (1992-1994). He Is
the author of about I 00 publications on VLSI circuit design
and signal processing and was awarded several patents In the
area of analog VLSI. He co-edited and co-authored Analog
VLSI Implementation of Neural Systems (1989), Introduc-
tion to Analog VLSI Design Automation (1990), Statistical
Modeling for Computer-Aided Design ofMOS VLSI Circuits
( 1993) and Analog VLSI: Signal and Information Processing
(1994). He received his Ph.D. in electrical engineering from
the University of Manitoba in 1983.
41
 Analog Integrated Circuits and Signal Processing, 6, 219-229 (1994)
0 1994 Kluwer Academic Publishers, Boston.

On the Optimal Design of Switched-Capacitor Filter Circuits

for Analog and Mixed-Signal Integrated Circuit Realization

N.C. CUSTARD AND R. E. MASSARA

El1ctronlc Sysrtms EnBin.,,.,, Unlv•nlty of Essu. Co/ch1111r, Essa C04 35Q, En11Dnd

Abstract. This contribution describes developments in the use of numerical optimization techniques as part of a
package whose function is to generate silicon-level layout for general analog functional modules from high-level
specifications. The investigation is using switched-capacitor filters as a case study that is representative, in terms
of its associated physical layout problems, of many classes of analog circuits.

1. Introduction constraint-driven than is the case in digital IC design.

Examples of distinctively analog- and mixed-signal
This study describes the development of a switched-
layout constraints include: the need to trade area com-
capacitor filter (SCF) circuit-level design system util-
paction against the risk of crosstalk between near-by
ising numerical optimization as part of a larger system:
signal nets; the potentially serious problem of noisy
an automatic knowledge-based analog circuit compiler.
digital clock and signal paths; interconnection length
The front end of the compiler consists of a
and the associated introduction of parasitic circuit el-
knowledge-bast!d Flexible Expandable Expert Design
ements; the need to ensure matching and temperature-
System FEEDS [1], illustrated structurally in figure 1
tracking of groups of active devices; and many others
which, based on user input, decides on the choice of a
[2, 3].
suitable analog filter structure and calls the appropriate
Many of the existing analog compilers utilize digital
system design tool. FEEDS calls on a variety of cir-
layout tools which may not cope adequately with these
cuit compilers providing analog functionality such as
restrictions, thus, a custom analog layout tool is in-
operational amplifiers (op-amps), phase-locked loops
(PLLs) and switched-capacitor filters (SCFs). The sil- cluded in the system to overcome these problems. This
paper will focus on two major issues. The first concerns
icon layout of an analog circuit is very much more
the circuit design strategy adopted in producing one
of these analog module design experts. The example
DESIGN chosen is the SCF module. Practical simulation results
EXI'ERTS
r- --- are shown which provide helpful insight into the ap-

H OP-AMP ~ proach which, in the authors' view, should be adopted

in incorporating SCF synthesis into an analog compi-
lation system. The second area of interest concerns the
H_ SCF
~ way in which optimization has been used within this
CADENCE design scheme. Results are presented to demonstrate

H ~
an efficient technique for the use of an optimization
EDGE
FEEDS PLL
LAYOUT
algorithm in the context of a circuit-simulation-based

H,
ENVIRONMENT
design scheme necessarily involving very CPU-time-
LIN/LOG . ~
MULTIPLIER intensive design objective function evaluations. It is
suggested that these latter results have significance and
1 OTHERS ~ application considerably beyond the immediate area of
this study since numerical optimization based design
------
strategies are commonly used in engineering design
Fig. I. Overview of knowledge-based analog compiler system. where system simulation is expensive but constitutes

43
220 Gustard and Massara
the only practicable way of characterising system per-
formance.
2. Choice of SCF Structures
The realization of analog filters in silicon integrated
circuits encompasses a number of design problems
which limit the choice of circuit structure. Compo-
nents are nonideal, op-amps have limited gain, finite
output impedance and parasitic poles. Switches have
finite on-resistance, capacitors have many stray com-
ponents associated with them [4] and significant toler-
ances [2, 5]. A further consideration is that of structure
size; silicon area is expensive, hence any reduction in
physical circuit size is advantageous. All these factors
have stimulated the development of SCF designs.
3. Blquad SCFs
Since the 1970s many novel structures have been re-
ported for the realization of switched capacitor filters.
Each structure has particular advantages. Biquadratic
blocks (blquads) have low sensitivity to the stray capac-
itance inherent in silicon layout, are easy to cascade and
simple to design. However, they are restricted by an
inability to produce high Q values, limiting their use
in high-order filters. There have been many biquad
circuits reported, each with various advantages (rep-
resentative examples include [6-11] and [2]). Biquad
circuits of the type reported by Gregorian and Ternes
[2] were chosen for use in this system because of their
low component count and versatility of application to
common filter functions.
Vin
Cl"
Fig. 2. SCF biquad section.
44
Biquad structures do however have disadvantages.
Often a single component defines a filter pole, result-
ing in high sensitivity to component tolerance. Given
any reasonably demanding or high-order filter specifi-
cation, one or more of the biquad sections will be in-
volved in realizing high-Q pole-pairs. Very high sensi-
tivities to component error are likely to result and, since
component tolerances are inevitable in silicon realiza-
tion, the frequency response produced by the filter may
deviate unacceptably from that required by the speci-
fication.
Figures available for capacitance tolerance vary
widely, Gregorian and Ternes [2] quote figures of
± 15% for absolute accuracy and a range of 0.1 - 1%
for ratio accuracy. Geiger, Allen and Strader [5] quote
± 20% for absolute accuracy and ± 0.06% for ratio ac-
curacy.
To illustrate the sensitivity of a biquad filter to com-
ponent tolerances, a series of simulations were carried
out where the netlisting routine introduced a variation
in component values. Given the above figures, a ran-
dom error of ± 1%, the extreme of the quoted ratio
ranges, was introduced in steps of 0.1% across all the
passive circuit components. These tests where used
rather than the "classical" sensitivity analysis as sen-
sitivity plots are rather open to interpretation. With a
series of tolerance plots worst case situations can be
more easily seen.
The specification chosen for this example was that
of a 7th-order Chebyshev filter with 1dB passband rip-
ple. Passband cut-off frequency was 5kHz and the
capacitor clock rate was 60kHz. This specification
required three biquad sections of the form of figure 2,
Vout
 Optimal Design of SC Filters for Analog/Mixed-Signal ICs 221

Table2.
CD
Unit Capacitor Values for Pirst..Qrder Section
..-----II~~
C!>/2 CE ~'
cs CS/2 CD CB

-0t· t·
2.000000 1.000000 1.968542 17.955232

together with a first-order SC section, Figure 3. As the

Vln
Vout biquad is used in a low-pass circuit Cl' and C1 11 are
omitted. All components at this stage of simulation
- were ideal, section Qs were 10.898676 3.1558645 and
1.2969355.
Fig. 3. SCP first-order section. The values for the passive components of the filter
were as shown in table 1 for the biquad sections and
table 2 for the first-order section. It must be noted
Table 1. that the precision of these figures would be restricted
by the limitations of the fabrication process leading to
Unit Capacitor Values for Biquad Sections
additional tolerance effects.
Low-Q Mid-Q High-Q Figure 4 illustrates the effect of this ± 1% tolerance
C1 4.2140239 2.0315589 5.2445388 range on the biquad-based design. The results show a
C2 4.1516958 2.0178707 5.3046117 marked deviation, particularly in the vicinity of the high
C3 1.0000000 1.0000000 25.1007282 frequency (high-Q) pole. This strongly suggests that
C4 3.2630614 6.3406843 1.0000000 the biquad structures cannot be relied upon to realize
CA 5.0650780 6.0627376 22.7081311
CB 5.0650780 6.0627376 22.7081311 high order filter circuits without undesirable distortion
occurring.

1.5 I I

1 :·.-

0.5
,•. . ..
......... ......
0
Gain '/..·'{:·.= .= _...;~·~.. .~.~~.:~_.:_:.:_:_·!_,, :::·;~,:
dB '~...'~'·.·,,
~~~:~~~ ·. :~-!) .:.f.t: ~
•• .'•"•":·. • • r ::• ,,._
-0.5
..• t- ... .
. ..~'.·.·:::: ·. ·"'.';
0

•.,·_j(-" ··.~.~>.....
-1 ,~~,;i!·I · . .~ ~.::·:':::·r·
., ' v· -.·~·.·-: · · ·.·.:.·: ·.·.•::_..·;,
.....·•._...
. . :: i=
·.·· ..
0 ...

'..
-1.5 ....
·:.··
-2~--~--~--~--~--~--~--~--~--~--~
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Frequency (Hz)
Fig. 4. 7th-order biquad filter with a ± 191> random component tolerance.

45
222 Gustard and Massara

4. Ladder SCFs Realistic values of finite switch resistance and typical

stray capacitances have been added to the circuit sim-
Analog ladder filters are well known for their low sen- ulation, together with nonideal op-amp models based
sitivity to component tolerance and this applies also to on the use of a commercial op-amp from the MffiTEC
SCF implementations [2]. Ladder structures have been foundry [16].
widely used [12-14] in SCF design with advantages
of low component count and a capability of realizing
high-order filter structures. The low sensitivity of the
structure is attributable to the response function being
distributed throughout the circuit components such that
no single component alone defines the filter poles. This
results in a structure which is inherently insensitive to
component tolerance.
To illustrate the comparative insensitivity of the lad-
der structure, an SCF 7th-order ladder implementation
[12] was designed to the same specification as the hi-
quad example. The structure was as shown in figure 5.
The component values are shown in table 3. ,T-$;
TableJ.
I~
Ideal Ladder Filter Component Values (Unit)
Cu 1.000000
Cc1 4.995378
01 2.004174
Cc2 5.92536S
Cl2 2.291852
Cc3 6.078894
03 2.280120
Cc4 4.397739

This ladder filter was subjected to the same tolerance

tests applied to the biquad. We see from figure 6 that
variation in component value has a very much reduced
effect compared with the biquad.
Despite the superior performance of the ladder
structure in this test, and the sound theoretical basis on
which these excellent sensitivity properties are founded
[15], biquad structures remain a popular choice in in-
dustrial SCF implementations. One reason for this is
the emphasis which is placed in the literature on stray-
insensitive designs - a feature associated with many
SC biquads. It should be noted that stray-insensitivity
depends on ideal op-amp behaviour; the practical non-
ideality ofiC op-amps is a source of error in both biquad
and ladder SCFs as well as a factor which devalues the
effectiveness of stray-insensitive design.
The difficulties that these sources of error can pro-
duce is shown in figure 7 where ideal and practical
responses are illustrated for a 5th-oder Chebyshev SC
ladder filter. The structure used was of the same for-
mat as that shown in figure 5, but using only 5 sections. Fig. 5. 7th·order SC ladder filter.

46
 Optimal Design of SC Filters for Analog/Mixed-Signal ICs 223

I .\ ,. .
0.2 ,------,.---.,..--.--.---,----,----.---,--.,.----.,
0 h-----------------~~------------~
-~. -t·..... .I
~·r-----~.. .5?
I
~~~
,,
..
"1/ ·::: .. r

-0.2 -~ ?: ·t ..~-
·lj
-0.4 ·v':'i; ?·'.' ·•;.
·;~.
:g
.,
-0.6 .• . ~.... ~
~.·
~~- ·:::~
·::,. l• ·:r· : 'i
Gain _ 0 8
• •~
, ·::;. )),' ·f; ·: •'\.:?
dB l 1
·•I
... ,.
)•
)•. ·,:t:. ·:Jt
''!,!'t. .·:"'!(·...
-1
•, /,1,1,'•,
":·:·· ?;;}
. ... -.

-1.2 ....

-1.4
-1.6
-1.8 ._____._ __.__ __.__ _.__ _,__ _..___..___..__--J'------1
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Frequency (Hz)
Fig. 6. 7th-order ladder filter with a ± 19& random component tolerance.

-0.2

Gain _ 0 4
dB .

-0.6

-0.8

-1 ~---'--~~~--~--~~-----'------~
0 1000 2000 3000 4000 5000 6000
Frequency (Hz)
Fig. 7. Distortion of passband response of a 5th-order chebyshev ladder filter.

The macromodels used for this are shown in figure 8.
Bottom-plate stray-capacitance was calculated as the
typical process value for polyl to substrate, plus an
approximate interconnection capacitance, caleulated
from process value for metall to substrate of mini-
mum width and length equal to the capacitor perimeter.
Top-plate stray-capacitance was approximated by the
interconnection value.
The netlister calculates the value of capacitor for the
given clock frequency to model finite switch resistance
with a value of lOkfl, the simulated impedance of a sin-
gle minimum size MOSFET for the design process.

47
224 Gustard and Massara
c
Cbot yr~ Ctop ~:~r­
~~Cr
a) Capacitor b) Switch
hs = high speed clock
Rg. 8. Macromodels for nonideal componenls.
Op-arnp macromodels introduce a dominant-pole-
frequency, input capcitance and output impedance.
Gain of the op-amp is a capability of SWITCAP II
and was given a value suitable for the op-amp model.
All the above model values can be adjusted for a given
process.
Where biquads are used to achieve a commercial
design, a common response to the difficulties of high
sensitivity and the problems added by non idealities and
strays is to over-design. Thus extra circuit sections will
be added to ensure that a response template is met de-
spite the high cost in silicon area. For relatively un-
demanding specifications this may be acceptable but
precision requirements could well involve considerable
additional circuit complexity.
The SCF Expert produced in this study will provide
either biquad or ladder realizations, selected according
to the demands of the specification. For both classes
of structure, we have explored the effectiveness of us-
ing numerical optimization to compensate for realistic
models of the imperfections that will necessarily re-
sult from IC reali7.ation. These imperfections include
stray capacitance; switch resistance; and op-amp non-
idealities. The result is a system that produces accurate
designs with no additional silicon area costs.
5. System Operation
As input to the SCF Expert FEEDS provides a set of
pole frequencies and Q values for each biquad section
and, for ladder functions, a set of continuous analog
component values.
48
The layout of analog circuits requires careful analy-
sis, and many restrictions must be considered. Output
nets must not cross input nets lest positive feedback
cause circuit instability. Noisy nets such as clock sig-
nals must not cross sensitive nets such as op-amp in-
puts. Common centroid layout must also be considered
to ensure accurate capacitor ratios [11, 3].
Circuit schematics are produced with Cadence
EDGE [17] which has been modified to include SC
components. It is within this environment that non ideal
components are calculated for the netlist macromodels.
After layout of the circuit feedback of the actual layout
capacitance can be used for a post-layout optimization
run.
6. Optimization Development
Many methods of numerical optimization have been
reported, the most effective examples of which require
function derivatives. Obtaining electronic circuit func-
tion derivatives is generally a nontrivial problem exert-
ing restrictions upon the choice of optimization routine.
Approximate derivatives of circuit functions can be
evaluated by perturbation of the component variables,
but this is simulation-intensive requiring n + 1 eval-
uations for an n variable problem. Schematic sim-
ulators exert excess loading on the optimization pro-
cess; SWITCAP II [ 18, 19] typically takes 20 min-
utes (elapsed time on SUN SPARC) for a simulation
involving nonideal circuit components (depending on
circuit complexity and high speed clock frequency).
We can see from this that a method which requires
 Optimal Design of SC Filters for Analog/Mixed-Signal ICs
a minimum of simulations per iteration would be an
attractive choice for the problem. Newton-Gauss least
squares optimization (LSO) [20] offers high-speed con-
vergence at the expense of requiring first derivatives.
LSO with real derivatives should theoretically find
the minimum of a quadratic problem in one iteration,
however, on real engineering design problems, the
method may require many iterations to achieve a solu-
tion and, without suitable damping, may diverge [21].
LSO approximates the error function by a quadratic
function. In common with other Newton-based meth-
ods [21] LSO makes use of the Hessian matrix of sec-
ond partial derivatives of the design objective function,
ill which is given by
(1)
Fig. 9. Flow chart of new algorithm.
225
where J is the vector of error values. In LSO, the Hes-
sian is approximated as
(2)
where J is the Jacobian matrix of first partial deriva-
tives of the elements of f. The algorithm presented
here is developed from a technique reported by Mas-
sara and Fidler [22], and uses the so-called Levenberg
damping parameter,.>., [23] in the modified expression
for H, where
(3)
The new algorithm can be seen in figure 9. Note that
re is the vector of design variables and a is the line
search parameter [22].
If the design objective function is in fact well ap-
proximated by a quadratic then the evaluated approx-
imation to the Hessian should be approximately the
same regardless of the position in the error space. This
led to investigations into the similarity of the matrix at
each iteration. Investigations were extended to a 5th-
order low-pass Chebyshev ladder SCF circuit of the
same structure as figure 5, (this being of reasonable
complexity but sufficiently small to minimize investi-
gation time.)
In this problem, as in most engineering design prob-
lems, it must be supposed that the design objective
function is very far from a simple quadratic form. We
were therefore not surprised to find that, in general,
the Hessian matrix elements varied widely across the
functional surface. On the other hand, it was found
that there were regions in which sequences of large re-
ductions in the value of the sum-of-squares. objective
occurred with relatively little change in the value of
the Hessian. This indication that the design objective
function is, in such regions, well approximated as a
quadratic form can be used to signal the temporary fix-
ing of the Hessian matrix and its use as the basis for a
number of iterations without re-evaluation.
A method was designed which retains the Jacobian
matrix, and hence the approximate Hessian matrix.
The basis is the goodness of the new move; if the matrix
yields a new minimum with better than a given percent-
age improvement, the matrix is retained. Divergence
or an improvement below the percentage criterion re-
sults in the matrix being re-evaluated. In practice, this
has proved to reduce optimization time considerably by
decreasing the number of circuit simulations required
very considerably.
49
226 Gustard and Massara
7. Optimization In Practice
From tests on three different ladder circuits the new al-
gorithm has proved to be effective. It has been used on a
5th-order, a 7th-order and a 9th-order low-pass Cheby-
shev filters of the same structure as figure 5. From
table 4 we see that tests have shown a predictable im-
provement in excess of 20% fewer simulations to solu-
tion, a considerable improvement of several hours less
computation time.
Table 4. Comparison of performance of new algorithm compared to
standard algorithm.
Percentage improvement of new algorithm
Filter Order 5th 7th 9th
Ideal Circuit 15.6% 21.6% 21.3%
Nonideal Circuit 28.3% 20.7% 6.9%
Pre-distorted
Nonideai Circuit SO.O% 45.6% 19.1%
From examination of figure 7 we can see that the
nonideal components yield two distinct forms of dis-
tortion: a reduction of approximately 50% in the pass-
band ripple level, and a frequency shift of approxi-
mately 10%. Optimization of the nonideal circuits is
the most time-consuming operation hence any method
which minimizes this process will considerably reduce
design time. By pre-distorting the ideal filter circuit to
achieve a 100% increase in the ripple and 10% lower
passband frequency it was found that optimization time
was reduced by as much as 66%. Savings from the new
algorithm also increased to as much as 50%, however,
the generality of this pre-distortion technique has not
yet been investigated.
The optimization algorithm was used with approx-
imate stray capacitance included. After layout within
the EDGE environment, actual stray capacitance was
extracted and the circuit submitted to a final optimiza-
tion run. As the starting point for the design is near
to the solution, we would expect the design objective
function to be well approximated by a quadratic form.
Predictably, then, it was found that the Jacobian matrix
had to be calculated once only, after which the algo-
rithm effected a solution using the initial Jacobian ma-
trix with only five iterations. Optimized passive circuit
components had the values shown in table 5.
After extraction of the final layout-component val-
ues, the design was subjected to a series of rigorous
tolerance analyses. Unit capacitors where subjected to
50
Tablt5.
Ladder Filter Component Values (pF)
Cu 0.206000
Cc I 1.325752
Cll 0.440682
Cc2 I.S 17509
Cl2 0.472450
Cc3 1.489371
Cl3 0.456568
Cc4 1.067413
a ±1% tolerance ratio variation as in previous experi-
ments, however the stray capacitance was subjected to
a ±50% tolerance. As stray capacitance is not usually
considered a major feature in integrated-circuit design,
figures for the accuracy of stray capacitance are not
readily available. However, typical figures are quoted
for the absolute value. Given the tolerance of designed
capacitance and applying this to the stray components
we could expect a worst case of ±20% to the designed
capacitor and =t=20% to the stray component. Taking
into consideration the expected inaccuracy of the stray-
capacitors a value of ±50%, though high, would seem
suitable to examine the limits of the design.
Stray capacitance does not have a first-order effect
upon the circuit as it is not relied upon to achieve filter
poles, because of this factor it is not so much the value
of the stray capacitance but rather its presence in the
circuit.
Despite the wide range in values, the structure per-
formed well. As can be seen in figure 10 the Cheby-
shev function is well maintained but with an increase
in passband ripple at higher frequencies. All the values
are normalised to OdB as the tolerance exerts a range
of up to ldB error in the DC gain.
If a more lenient tolerance of ±25% is used, only a
small amount of deviation in the pasband occurs. This
is illustrated in figure 11.
8. Further Work
Biquad and ladder structures each have their own ad-
vantages and disadvantages within a filter design. Each
can be used to good effect for particular applications.
The limiting factor upon biquads is the sensitivity to
component tolerance. High-order filters contain pole-
pairs with high-Q values which are more difficult tore-
alize accurately using biquad structures. Alternatively,
 Optimal Design of SC Filters for Analog/Mixed-SignaiiCs 227

0.5

-0.5
Gain
dB
-1

-1.5

-2
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Frequency (Hz)
Fig. 10. Bft'ect of ±191> nndom component and ±5091> stray-capacitance tolerance upon an optimized 7th-order ladder filter.

0.5 I I

-0.5
Ga.in
dB
-1 •,'
·~.~ ~ ::·.
: :
: :
::
-1.5

-2
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Frequency (Hz)
Fig. II. Bft'ect of ± 191> nndom component and ±2591> stray-capacitance tolennce upon an optimized 7th-order ladder filter.

ladder structures can easily assimilate high-order struc-
tures but are more difficult to design with; further,
they are sensitive to stray capacitance. As we have
shown, this can be corrected with optimization, but an
alternative is the amalgamation of biquads and ladder
structures to achieve the best of both worlds. Biquads
can be used for the low-Q sections, which they can
efficiently achieve, whereas ladder structures can be
used for the high-Q sections. Direct methods to de-
sign ladder filters for such a use do not exist however,

51
228 Gustard and Massara
optimization should be effective for such a situation.
Work is in progress on this area at the present time.
9. Conclusions
A modified algorithm for enhanced optimization of
simulation-intensive problems has been presented in
this paper. Experimental results applied to three ladder
structures have been discussed to verify the improve-
ments. Pre-distortion techniques for nonideal struc-
tures have been suggested which further enhance the
speed of the algorithm.
Further results demonstrating the use of the routine
applied to a 7th-order ladder-filter have been presented,
where effective compensation for the nonideal compo-
nents present in silicon realization has been success-
fully achieved.
Component tolerance has been applied to biquad
structures and ladder structures, the results of which
have been presented and compared.
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Robert E. Massara (born in Sheffield, England, 1947) ob-
tained a first clas s honours degree in Electronic Engineering
from the University of Essex In 1972, and a Ph.D. in 1977.
He worked for GEC Semiconductors and lhe University of
Keele before laking a post as a Lecturer at Essex. He was
promoted 10 Senior Lecturer in 1984 and to Professor in 1991.
He is currently Head of lhe Department of Electronic Sys-
tems Engineering, and of lhe Department's Neural and VLSI
Systems Research Group, and is Director of lhe University's
 Optimal Design of SC Filters for Analog/Mixed-Signal ICs
Centre for VLSI Systems Design. His research Interests In-
clude analogue VLSI design automation; IC filter design and
numerical engineering design methods. He Is a Fellow of the
(UK) Institution of Electrical Engineers.
NlcholllB C. Gustard was born In Louth, Lincolnshire, Eng-
land, in June 1958. He received a B.Eng. degree In Electronic
229
Systems Engineering from the University of Essex in 1991.
Since 1991 he has been working towards a Ph.D. degree in
the area of switched-capacitor filters for integrated circuit
realization at the University of Essex. Mr. Oustard Is an
Associate Member of the (UK) Institution of Electrical En-
gineers.
53
 Analog Integrated Circuits and Signal Procesalng, 6, 231-241 (1994)
0 1994 Kluwer Academic Publishers, Boston.

Optimal Gain Overdesign in Analog Filters

ANT6NIO C. M. DE QUEIROZ AND LUIZ P. CAL6BA

COPPE/EE. Unlvtrsldadt Ftdtrol do Rio dt Jantiro, CP 68504, 21945-970 Rio de Jantlro, RJ, Brazil

caloba@cot.ufrj.br

Abstract. This paper presents a method for the overdesign of gain-shaping filters in an optimal way. The passband
minima and the stopband maxima of a filter approximation are adjusted using an iterative method, with the objective
of obtaining a circuit that satisfies exactly the specifications when the statistical deviation in the filter transfer function
due to errors on its components is considered. The result is a filter that can be significantly more selective than what
is obtained by a simpler overdesign method that results in an equal-ripple ideal design. Two different approaches
are examined, one based in the development of a special approximation followed by synthesis, and the other by
direct optimization of an initial classical design.

1. Introduction is done simply by using more strict filter specifications,

The classical filter approximations for filters with steep
transition bands, the Chebyshev approximation for all-
pole filters and the elliptic approximations· for filters
with finite transmission zeros, result in equal-ripple
passbands, and in the case of the elliptic approxima-
tions, in also equal-ripple stopbands. These character-
istics are necessary if the approximations are to provide
the shortest possible transition bands for a given filter
order and attenuation specifications.
It is recognized, however, that these optimal approx-
imations are in many cases of impractical realization,
because the precision needed in the component values
for the realization of the filter by the desired structure
is unattainable. This happens when errors in the filter
component values can modify the filter transfer func-
tion in a way that violates the filter specifications.
The usual approach when this occurs is to overde-
sign the filter, by reducing the passband ripple, increas-
ing the minimum stopband attenuation, and if neces-
sary increasing the filter order. In some cases, this turns
the approximation into something closer to the Butter-
worth approximation, that is the limit of the Chebyshev
or elliptic approximations when the passband ripple is
reduced and the stopband minimum attenuation is in-
creased. In a filter built with an LC doubly terminated
structure, or any active simulation of one that preserves
the sensitivity characteristics, this approach generally
has success, because the passband and stopband sensi-
tivities decrease in the process. Usually the overdesign
and obtaining an equal-ripple approximation that sat-
isfies them.
An observation of the sensitivity characteristics of
most filter structures realizing an equal-ripple approx-
imation shows that the errors due to component value
errors are not uniform in frequency, but are higher at
the passband and stopband borders. A reason for this
is that in these regions the transfer function is deter-
mined by groups of poles or zeros closely spaced, and
errors in their relative positions cause large errors in
the transfer function magnitude.
Most high-precision filters are based on LC doubly
terminated structures, or realized as active simulations
of passive prototype filters with those structures, due
to the very low sensitivity to variations in element val-
ues attainable [1]. In an LC doubly terminated filter,
the gain cannot exceed the one determined by maxi-
mum power transfer. In consequence, in a filter de-
signed with maximum power transfer at the passband
maxima, the passband errors due to small changes in
component values can affect only the passband min-
ima. This results in the sensitivities to all the LC el-
ement values being null at the passband maxima, and
with peaks located somewhere between adjacent max-
ima. For equal-ripple approximations, these sensitivity
peaks are higher close to the passband border. For
the terminations, the sensitivities have a frequency-
dependent part that follows the same pattern, and a
frequency-independent part (±05) that affects only
the "flat-loss" of the filter, that in most cases can be

55
232 de Queiroz and CaMba

If the passband or stopband ripple is irregular, it can

Fig. 1. Standard 7th-order normalized elliptic low-pass filter. Ele-
ment values in table 2(a).
be shown that, for each passband "valley" (and for each
stopband "hump"), there is a direct proportion between
the depth of the "valley" (or the height of the "hump")
and the error at its frequency. This relation is used in
the optimal overdesign method described below.

ignored. At the stopband, the error analysis by sensi-

tivity presents the artifact of infinite sensitivities to the
values of the elements forming the zeros at the trans-
mission zeros frequencies [2]. The errors that are re-
ally important are the ones at the peaks of the stopband
"humps." For equal-ripple approximations, these er-
rors are higher close to the stopband border. Figures 2
and 3 illustrate these characteristics, by depicting the
gain characteristic of a 7th-order elliptic low-pass filter
with I dB passband ripple, 50 dB minimum stopband
attenuation, and passband border at I rad/s, realized by
a standard LC doubly terminated ladder structure (fig-
ure I), with the gain statistical deviation when uncorre-
lated 5% errors in all the element values are considered.
The error was computed by equation (I), and is shown
subtracted in the passband and added in the stopband,
with the terminations' sensitivities discounted of the
frequency-independent part.
2. Optimum Overdeslgn
The gain specifications that are certainly satisfied by
a filter can be obtained by adding or subtracting the
error curves from the nominal gain curve, as done in
figures 2 and 3. The errors can be computed by several
methods. The one used in the examples in this paper
is the gain statistical deviation, computed by:
t:..G( ) 20 "'"'(V.,· Rc s!,<iwl)2 dB (I)
w = Ln(lO) ~ -
where G(w) is the filter gain in dB, T(jw) is the
transfer function, X; are the filter component values,
V; their relative tolerances t:..x,jx,, and si.(jw) =
x,jT(jw) dT(jw)jdx 1 is the sensitivity of T(jw)
to x 1•

i..,\
: \
l ~\\
1 \.
: : ·~ .
.. ., ......(••······;···'-'~.:···.

dB

Fig. 2. Passband gain curve of a normalized elliptic 7th-order low-pass filter, and the gain curve with the statistical deviation due to S% errors
In all the element values subtracted, with the flat-loss error discounted. The maximum gain was normalized to 0 dB, as in the other figures.

56
 Optimal Gain Overdesign in Analog Filters 233

.......... 1 ···~··········r·········r·········,·········· ····-r········

··········r·········Y . ·····:··········l··········r·········:········ ..
-80~--~--~~--._--~~~--------------~~~
1 r~d/~

Fig. 3. Stopband (beginning) gain curve for the same filter, shown also with the statistical deviation added, discounted of the flat-loss error.

In an LC doubly terminated filter, it is easy to elim-
inate from the errors the flat-loss errors that affect only
the gain of the filter and are easy to compensate. They
are caused only by the errors in the terminations at any
frequency Wm where maximum power transfer occurs.
With the sensitivities of the terminations discounted of
this value (i. e., replacing si,<iw) by si,<Jw>- si,Uwm)
in (1)), the gain statistical deviation ~G(w) in (I)
reduces to zero at the maximum power transfer fre-
quencies, that is, at the passband gain maxima for a
well-designed filter. With this discounted error used,
the passband gain limits are obtained by subtracting
the error curve from the nominal gain curve, since the
maximum power transfer prevents any increase in the
passband gain.
In the stopband, the maximum gain (minimum at-
tenuation) limit is obtained by adding the error curve
to the nominal gain curve. The discount of the flat-
loss error can also be used. The infinite sensitivities at
the transmission zeros can be ignored, by considering
only the error at the stopband maxima and borders, or
by using "slope-normalized" sensitivities [2].
When the errors in an overdesigned equal-ripple fil-
ter are considered, clearly the worst-case (in this case
in statistical sense) resulting filter is not equal-ripple
at all. It is possible, however, to use the fact that er-
rors are higher at the passbands and stopbands limits
to obtain a more selective overdesigned filter. This can
be done by computing the overdesigned approximation
with irregular passband and stopband ripples, in a way
that makes the worst-case resulting filter equal-ripple.
The idea is exemplified in the example below.
3. Example 1
A 7th-order elliptic filter realized as a doubly termi-
nated LC ladder presents the passband and stopband
gains and errors shown in figures 2 and 3. The objec-
tive is to obtain a similar filter that in the worst case is
equal-ripple in the passband and stopband. An algo-
rithm for obtaining an optimally overdesigned filter is:
I. Compute the worst-case gain curve, as the filter gain
curve (dB), minus the flat-loss (-6.0206 dB in the
example), minus the gain statistical deviation (dB,
with flat-loss errors discounted) in the passband, and
plus the gain statistical deviation in the stopband, as
discussed in the last section. If it is equal-ripple,
stop. Else, call E; the gains at the passband minima
of this composite curve:
E; = G(w)- flat-loss - ~G(w;) dB
(2)

57
234 de Queiroz and Cal6ba

Table 1. Nominal passband minimum gains A;, stopband maximum gains A;, and corresponding gains with worst-case error considered, E;
and E;, for the six first steps of the optimization algorithm of the example.
-AJ/ -Et -A2/- E2 -Aa/- Ea -A~/- E; -A;/-E~ -A;/- E~
I I I 50 50 50
1.154 1.341 2.382 40.63 47.51 49.08
0.866 0.746 0.420 61.78 52.62 50.93
2
1.012 1.049 1.154 48.64 50.10 50.00
0.856 0.711 0.364 63.51 52.51 50.93
3 1.037
1.001 1.009 49.23 50.01 50.00
0.855 0.705 0.351 64.50 52.50 50.93
4 1.008
1.000 1.002 49.52 50.00 50.00
0.855 0.703 0.348 65.13 52.49 50.93
5
1.000 1.000 1.001 49.68 50.00 50.00
0.855 0.703 0.348 65.55 52.49 50.93
6 1.000 49.77 50.00 50.00
1.000 1.000

and call E:
the gains of the composite curve at the is slower near the passband and stopband borders. The
stopband gain maxima: final element values, with the same structure of figure I,
are listed in table 2(b).
E; = G(w)- flat-loss - ~G(w;) dB (3)
Table 2. Element values for the example filters.

Rt = R7 = I; L2 = 0.595; L4 = 0.483; L& = 0.928;

Call A; the designed gains (dB) of the filter at the
passband minima and Aj the designed gains at the
stopband maxima, both without considering the flat-
loss, as shown in figures 2 and 3.
2. Compute new A; = (-A max x A;)/ E;, and Aj =
( -Amin x A;)/ E;,
the gains at the passband min-
ima and at the stopband maxima to be used as de-
sign parameters in the next iteration. Amax is the
specified maximum passband attenuation and Am in
is the specified minimum stopband attenuation (dB,
discounted the flat-loss). These expressions assume
that the direct proportions among the E; and Ej, and
the corresponding A; and Aj, are linear and inde-
pendent, which is approximately true, specially at
the passband.
3. Compute a new approximation, with irregular rip-
ple, with passband minima A; and stopband maxima
Aj. Suitable algorithms were described in [3], and
specially in [4). The algorithm described in [4] is
summarized in the appendix. Compute the new val-
ues for the filter network.
4. Return to I.
Table I shows the obtained results for 6 iterations,
starting from a normalized filter with I dB passband
ripple and 50 dB minimum stopband attenuation (the
one in figure I). 5% tolerances in the filter components
were assumed. It can be observed that the convergence
(a) Ct = 1.424; C2 = 1.099; Ca = 1.559; C4 = 1.674;
c~ = 1.941; c6 = 0.305; c 7 = 1.912;
Rt = R7 =I; L2 = 0.604; £4 = 0.622; Ls = 0.941;
(b) c. = 1.237; C2 = 1.066; Ca = 1.675; C4 = 1.159;
C5 = 2.025; C& = 0.295; C7 = 1.712;
Rt = R1 = I; £2 = 0.833; £4 = 0.754; L& = 1.141;
(c) Ct = 1.179; C2 = 0.616; Ca = 1.581; C4 = 0.894;
Cs = 1.825; C& = o. 175; C1 = 1.496;
Rt = 0.757;R7 = 1.321;
(d)
Lt = 1.193;£2 = 1.103;£4 =0.921;£6 = 1.393;
Ct = 1.364; c2 = 0.555; ca = 1.048; C4 = 0.803;
Cs = 1.211; C& = 0.235; C1 = 0.986;
Rt = Rs =I; Ct = 1.186; Lt = 0.312; C2 = 1.198;
(e) L2 = 2.816; La = 0.428; C4 = 1.572; £4 = 1.202;
C5 = 1.183; L~ = 0.348;
Figures 4-7 show the comparison of the optimum
overdesigned filter (figsures 4 and 6) with a conven-
tional equal-ripple overdesign, obtained by the same
algorithm, but considering only Aa, A~ and Ea. Ei
(this results in a 0.41 dB passband ripple and 57.43 dB
minimum stopband attenuation), and with an 8th-order
modified overdesigned elliptic filter (with two trans-
mission zeros at oo, the next that admits a simple lad-
der realization), obtained in the same way, resulting in
0.33 dB passband ripple and 60.61 dB minimum stop-
band attenuation (figures 5 and 7). The element values

58
 Optimal Gain Overdesign in Analog Filters 235

Fig. 4. Optimum overdesigned filter passband gain, with flat-loss discounted, shown also with the gain statistical deviation subtracted.

Fig. 5. Bqoal-rlpple 7th-order and 8th-order overdesigned filters passband gains, as in figure 4.

for the two filters are are in table 2(c) (7th-order) and The optimum overdesigned filter is more selective
2(d) (8th-order). The structure for the 8th-order filter than the equal-ripple one of the same order, and slightly
is the one in figure 1 with an additional inductor, L 1 , less selective that the 8th-order uniform-ripple overde-
in series with the input termination Rt. signed filter, as can be observed in figures 6 and 7.

59
236 de Queiroz and CaMba

o -\~---··r··-----~-~r··~---··:···-·-·····:···-·---·--r·······---!-·-·······r···------·~---····--r
. -~ ·\" --···:· ······;·::-· ··::·· ... :···· .. ··-·:· ........... ··r······· ··-~·-···· ...... ~.. -· ..... ····:·-· ...... ··:
\ : : :: :: . : ; : : ; : :
\ ~ i i; i \ ; ; i . . ~ i

···········!····!·· . +· --·t··········j·········+·········j·········-~---·······-~---· .....

: : : :
1 ·nu
-SOIL---~:~~~~~:----~--~:~--~--~----~:~~
r<ld/S

Fig. 6. Optimum overdesigned filter stopband gain, with Oat-loss discounted, shown also with the gain statistical deviation added.

a .---· . . ·. ............... r·····--...... T...............1...............r...............r······-·· .......

r+. . .·. . j
···-~ ··-~-······n····rrr· ~rT ~

··-\:.-+. ····1·}···1H····~-~ t. . ······.J. -.. . . . . ~·-··········---J ................ j.......

Fig. 7. Uniform-ripple 7th-order and 8th-order overdesigned filters stopband gains, as in 6gure 6.

A frequency scaling shall be done to adjust the tran- ing, the method would find a solution for any values of
sition band of the overdesigned filter in the specifica- Amax and Amln· The limit solution would be a Butter-
tions (not done in the example). This will be discussed worth approximation, frequency scaled as needed tore-
in the next section. Note that, with this frequency seal· duce the worst-case passband and stopband errors. Of

60

course, the order could have to be increased to satisfy
the transition band width specification, and the order
increase would increase the error at the passband and
stopband borders. In critical cases a solution can be
inexistent, by this or by any other overdesign method.
4. Frequency Scaling
The components tolerances also affect the passband
and stopband borders. The reduction in the passband
can be clearly seen in figure 4, but the reduction of the
stopband in figure 6 is not so clear due to the artifact
of infinite sensitivities at the transmission zeros dis-
cussed in Section 1. The worst case stopband border
frequency can be calculated using a formulation based
on [2].
The gain at the ideal stopband border (no in fig-
ure 6) is expected to be increased by the components
tolerances to:
G(no, x, +Ax;) = G(no, x,) + AG(no) (4)
where AG(no) is computed as in (1), with w = n 0 •
As the gain decreases with the frequency, there exists
a frequency no + An such that:
G(no + An, x, + Ax;)
= G(no, x,) + AG(no) + (~)An = G(no, x;)
(5)
and so:
(6)
and the worst case, in statistical sense, stopband border
frequency becomes:
dG(no)
n, =no- AG(no) / ~ (7)
A similar procedure may be used to calculate the
worst-case passband border as:
j
n, = 1 + AG(1) d~1 > (8)
When the passband border is renormalized to
1 radls, the worst-case stopband border is n = n,;n•.
Optimal Gain Overdesign in Analog Filters 237
If the resulting selectivity does not satisfy the filter re-
quirements, a higher order must be used.
5. Direct Optimization
For the implementation of the proposed method, a com-
puter program was used to compute and locate the pass-
band and stopband gain limits, with errors computed
by sensitivity analysis, done by the "adjoint network"
method. The filter synthesis steps were done by an-
other program that implements the algorithm described
in [4]. Although rather complicated, this procedure
is able to design the filters with great precision, in a
reasonable time, and without numerical problems. A
simpler approach was investigated, using direct opti-
mization or the filter structure, using a simple gradient
optimizer included directly in the analysis program.
The algorithm is:
1. Analyze the filter, as in the first step of the previous
algorithm (locating passband minima and stopband
maxima, with error considered), but locate also the
passband maxima of the gain curve alone.
2. For each of the frequencies of these extremes, and
also for the passband edge frequency, write an equa-
tion:
t Re ( s;.cJw)) Ax,
x,
i=l
= ---w- (G(w)deolred -
Ln(10)
G(w)wlth error)
(9)
where the Xt are a set of n elements of the filter,
usually all the reactive elements. The term at the
right side is the error in Nepers between the desired
gain and the obtained gain (with error considered)
with the present filter structure. This results in a sys-
tem oflinear equations for Ax1/ x1 that when solved
gives corrections for the element values that trans-
form the present filter into another with a gain curve
closer to the desired one. The assumption that the
error extremes are proportional to the gain extremes
allows the use of gain sensitivities to compute the
corrections.
3. For usual filter structures, the number of extremes
needed for the complete characterization of the filter
gain curve, plus values that define frequency scal-
ing and bandwidth, is precisely equal to the number
of reactive elements. In these cases the system of
61
238 de Queiroz and CalOba
equations (9) is directly solvable (if not singular). If
there are more reactive elements than needed, or if
the terminations are included among the x,, the sys-
tem (9), in the form Sv = e, has more unknowns
than equations, and there are many solutions. A
convenient solution is obtained by transforming the
system Of equations into SST Z = e, with V (the
!:ix1 fx 1 vector) recovered as v = sT z. It can be
shown that this transformation computes the vector
v with the minimum possible modulus that satisfies
Sv=e.
4. Updatetheelementvaluesbyx, .- x,(l+!:ixtfxi),
and return to 1.
This algorithm is simpler, and less computationally
intensive than the previous one, since it avoids the syn-
thesis of a new approximation, that is also done by
optimization, and the filter synthesis. It presents, how-
ever, some numerical problems. The most serious is
that the LC doubly terminated realization with max-
imum power transfer is an "extreme" solution for an
approximation. The gain sensitivity matrix S becomes
singular at the solution. It is obvious that the lines
of the matrix corresponding to passband maxima are
null, but there are also other relations that tum the ma-
trix singular even if the maxima are substituted by other
frequencies. The problem can be avoided by ignoring
the equations of the maximum power transfer extremes
when the gain is close enough to the desired value, with
the transpose matrix technique (step 3 above} used to
correct the number of unknowns in the system of equa-
tions. This problem does not exist for filters without
maximum power transfer, but another problem appears:
Because there is no relation among gain minima and
error maxima, and the discounting of the flat-loss er-
ror can't be made, the number of extremes in the gain
curve and in the gain-error curve in the passband can
be different. For any filter, the overdesign of pass-
band and stopband borders is also problematic, since
the assumed proportionality between attenuation and
error is not valid in these regions. The multiplication
of the computed !:ixtfx, by a reduction factor (about
0.5) is usually necessary to force the convergence in
these cases.
6. Example2
This example illustrates the overdesign by direct opti-
mization. A normalized 6th-order irregular band-pass
filter, with passband between I and 2 rad/s, with I dB
62
ripple, and an inferior rejection band with 2 transmis-
sion zeros and minimum attenuation of 50 dB was com-
puted directly by the optimization algorithm described,
from an initial approximation with the correct shape,
obtained by estimating empirically the element values
of the structure in figure 8.
Fig. 8. Overdesigned irregular bond-pass filler. Pinal element val-
ues in table 2(e}.
The filter was overdesigned by the consideration of
the errors at the two stopband maxima, the two pass-
band minima, and the passband borders, with the ter-
minations fixed, and 5% tolerances assumed for all the
elements. The final element values are listed in table
2(e). The obtained gain curve is shown in figure 9, with
the passband detailed.
7. Conclusions
1\vo methods for optimized overdesign of gain-shaping
filters with maximum-ripple passbands and stopbands
was presented, with the algorithms described. The first
algorithm is more precise, although more computation-
ally intensive. The second algorithm is simpler and
more general, but somewhat numerically problematic.
The examples used the statistical deviation as a mea-
sure of the worst-case error. A true worst-case error,
or any other kind of error could also be used exactly in
the same way. The method, specially with the second
algorithm, can easily be extended to the overdesign of
phase characteristics, and can also be applied to other
purposes than to only compensate for random errors in
the component values. Deterministic effects, as the ef-
fects of losses and parasitic poles in active realizations
can also be compensated.
Appendix
In this appendix, the algorithm for the design of low-
pass filters with irregular passband and stopband rip-
ple described in [4] is summarized. The algorithm,
 Optimal Gain Overdesign in Analog Filters 239

10 !l . '
. '

2.5 ............ ·-+·········f··--····H··

----·~rr--Ji
~ :: ! ~: :
\: f\::
g
:ii : ! i
.............. ! ......... ....... : ·:-:··
·~· ·~ -~-

\ j li
j \ ~l

-2

Fig. 9. Frequency response of the overdeslgned Irregular band-pass filter.

implemented in a computer program, was used in the
generation of the first example.
The desired approximation has a purely real of imag-
inary characteristic function K(s) for s = jw, and is
in a form that can be called "asymmetrical rational ap-
proximation." Ignoring a possible -1 or ±jw multi-
plying factor, for an nth-order approximation, K(jw)
can be written as:
K( 'w) = eaX(w) = eaX(w)
J wnY(1/w) Yr(w)
The polynomial Yr(w) is simply Y(w) with the co-
efficients in reverse order. The polynomials X(w) and
Y(w) are of the same degree n. The two multiplying
factors are functions of the maximum passband atten-
uation Amtn and of the minimum stopband attenuation
Amax• and given by:
to be determined, and Y(w) has m 11 = (n- p11 )/2 + 1.
The general form of the normalized characteristic func-
tion K(jw)/e is:
aX(w)
Yr(w)
· · · + axp.+2wP•+ 2 + axp.wP• (12)
· · · + aYn-2W 2 + ayn
( 10)
K(jw) presents the maximum possible number of
ripples in the passband and in the stopband. The
normalized characteristic function presents m,-1 ex-
treme values f xi at the passband, each occurring at a
frequency wx; (see figure 10). The values of the fxi
are related to the specified passband gain minima Ai
by:

E: = VlOO.lAmox _ 1 j a=
J yflQO.lAmtn - 1
e
/x; = ±.!.Jw-o.lA, _ 1
e
(13)

The stopband can be specified in the same way us-

(11)
The number of attenuation zeros at w = 0, p.,, is
the number of roots at 0 of X (w). The number of trans-
mission zeros at w = oo, p 11 , is the number of roots at 0
ofY(w). X(w) has m., = (n- p,)/2 + 1 coefficients
ing the function aY(w)/Xr(w), where the two poly-
nomials were interchanged. There are m 11 - 1 extreme
values fy; in the passband of this function, each oc-
curring at a frequency wy;. The values of the fy; are
related to the specified stopband gain maxima A; (be-
ginning with the extreme at the highest frequency, and

63
240 de Queiroz and CaMba

-6~--------~--------~ ~--------~----------~
r ~d/s; 1
0
Fig. 10. Normalized characteristic function of a 7th-order low-pass elliptic filter, showing the meaning of the extreme values fx; and /IIi· 1be
vertical scale is compressed by 11 = ±(1 + Ln IK(jw)fe I) for IK(jw)l > 1.

decreasing in frequency for the others) by:
ea 2
fy; = ± VlO-O.lA,' - 1
(14)
The center of the transition band can be fixed at
w = 1 by fixing X(1) = 1 and Y(1) = 1. (As im-
plemented, a frequency scaling is done after the initial
design to move the passband border tow = 1.) As
initial approximations for the polynomials, X(w) =
wP·- 1 Cn-p,+l(w) and Y(w) = wP•- 1 Cn-v.+l(w),
where Ck(w) is the kth-order Chebyshev polynomial,
are used. The iterative algorithm to refine the initial
approximation is:
(a) Findwx;, k = 1, ... , m, -1, them, -1 roots
immediately smaller than I of the polynomial
Yr(w)- X'(w)- X(w)Y:(w), frequencies of
the maxima and minima of aX(w)jY,.(w) for
o:::;w:::;l.
the system of linear equations:
(b) Solve
aX(wx;) = fx;Yr(wx;), k = 1, ... , m, -1;
X(1) = 1, finding. the new approximation for
the coefficients of X (w).
(c) Interchange X(w) with Y(w), wx; with wy;,
fx; with fy;, p, with p 11 , and m, with m 11 ,
and repeat steps (a) and (b).
(d) Repeat (a), (b), and (c) until convergence.
The convergence is not particularly fast, but is very
robust. Once obtained X(w) and Y(w), the charac-
teristic function K ( s) is obtained by replacing w in
K(jw) by sjj, and ignoring a possible -1 or ±j mul-
tiplying term. The approximation synthesis is com-
pleted in the classical way by the solution FeldtKeller's
equation H(s)H(-s) = K(s)K(-s) + 1 to find
the transducer function H (s ). Note that the algo-
rithm can generate, as particular cases, all the clas-
sical low-pass approximations with a real character-
istic function. The elliptical approximations, for ex-
ample, are obtained with Px = p 11 = 1 for odd
orders, or p,. = p11 = 0 for even orders, and the f x;
and fy; alternating between ±1, with the last equal to
-1, which results in X(w) = Y(w). By increasing
p,. and p 11 , the same algorithm can generate Cheby-
shev approximations (p11 = n ), Inverse Chebyshev ap-
proximations (Pz = n), Butterworth approximations
(p,. = p 11 = n), and many intermediate variations. In
Example I, the fx; and fy; of initially elliptic approx-
imations were computed by (13) and (14), using the
gains in table 1.
References
I. Orchard, H. J., "Inductorless filters," Electronics Letters,
Vol. 2, pp. 224-225, June 1966.

64

2. Fidler, J. K. and Nightingale, C., "Slope-nonnalized sensitiv-
Ity: A new sensitivity measure," Electronics utters, Vol. IS,
pp. 54-56, January 1979.
3. de Quelroz, A. C. M. and CaiOba, L. P., "Physically symmetri-
cal and antimetricalladder fillers with finite transmission u:-
ros," Proc. 30th MWSCAS, Syracuse, USA, pp. 639--643, 1987.
4. de Queiroz, A. C. M. and CaiOba, L. P., "An approximation al-
gorithm for irregular-ripple filters," Proc. STBREEE Interna-
tional Teleco1111t1UIIications Symposium. Rio de Janeiro, Brazil,
pp. 430-433, 1990.
Antanlo Carlos Morel rio de Quelroz received the B.Sc.EE
(1979), M.Sc.EE (1984), and the D.Sc.EE (1990) degrees
from the Universidade Federal do Rio de Janeiro, Rio de
Janeiro, Brazil. Since 1982 he has been with the same institu-
tion, where he is now associate professor in the Department of
Optimal Gain Overdesign in Analog Filters 241
Electronic Engineering and at the Electrical Engineering Pro-
gram of the Coordena~iio dos Programas de P6s-gradua~lo
de Engenharia (COPPE). His main interests are in general fil-
ter theory, monolithic filter realizations, and computer-aided
synthesis and design of electronic circuits.
Lulz Pereira Caloba was born in Rio de Janeiro, Brazil, in
1944. He received the B.Sc.EE (1969) and the M.Sc.EE
(1970) degrees from the Universidade Federal do Rio de
Janeiro, Brazil, and the Dr.lng. (1974) degree from the Uni-
versite Scientifique et M~icale de Grenoble, France. Since
1974 Prof. CaiOba has been with the Universidade Federal do
Rio de Janeiro. His Interest areas are filters, neural networks,
and applications of signal processing in instrumentation.
65
 Analog Integrated Circuits and Signal Proci!BIIing, 6, 243-263 (1994)
0 1994 Kluwer Academic Publishers, Boston.

A 7.2 GHz Bipolar Operational 'Iransconductance Amplifier for

Fully Integrated OTA·C Filters*

M.ATARODI
UMGr T<clrnology Corporation, Milplttu, CA

J. CHOMA, JR.
Unlverdry of Southern California, DepartrMnt of Electrical &glneerlng-Eiectrophyslc.r, Unlverrlt)l Pork, MC: 0271, Los Angeks, CA, 90089-0271

}ohnc(lmi:Jlr.usc.edll

Abstract. Using a complementary bipolar junction transistor process having NPN transistors with a maximum
short circuit common emitter gain-bandwidth product (/T) of 7.2 GHz and PNP transistors with a maximum IT
of 4.5 GHz, an operational transconductance amplifier has been designed for a 3-dB bandwidth of 7.2 GHz. The
design process invokes new phase compensation strategies and develops innovative new ways of exploiting existing
broadbanding techniques. The utility of the design is confirmed by demonstrating its application in two operational
transconductance amplifier-capacitance filters. One of these examples is a 225 MHz lowpass filter, while the other
is a bandpass filter with a center frequency of 250 MHz.

1. Introduction limitations on attainable high frequency performance.

Wideband operational transconductance amplifier-
capacitance (OTA-C) filter topologies require wide-
band OTA-C integrators. In turn, a wideband OTA-
C integrator requires the availability of a broadbanded
operational transconductance amplifier (OTA). The lit-
erature is rife with general broadbanding theories and
techniques for circuits realized in bipolar junction tran-
sistor (BIT) technologies [1-14]. But the majority of
these theories and techniques address wideband video
and RF amplifier applications. With scant few excep-
tions [15-16], relevant literature focused specifically
on broadbanded operational amplifiers (op-amps) is
sparse. A likely reason for this scarcity is that unlike
bipolar video and RF amplifiers, which can be realized
exclusively with NPN transistors, bipolar op-amps in-
variably require both NPN and PNP devices [17, 18].
Until less than a decade ago, the only widely avail-
able PNP BITs were lateral units with limited high fre-
quency signal processing capability. This shortcoming
frustrated the design ofwideband op-amps by imposing
fundamental technological, as opposed to topological,
• This paper Is an elaboration of work presented by tbe authors
at the 36th IEEE Midwest Symposium On Circuill And Systems In
Detroit, Michigan, In August 1993.
However, the continuing maturation of complementary
(NPN-PNP) bipolar fabrication processes has encour-
aged renewed research and engineering interests in the
design ofwideband op-amps [19-23].
In this paper, a complementary bipolar process is ex-
ploited to design a tunable high frequency bipolar OTA.
The design uses a differential folded PNP cascode in
conjunction with an NPN differential stage to minimize
the frequency response limitations imposed by Miller
multiplication of intrinsic base-collector junction ca-
pacitances in the NPN devices. Additionally, broad-
banding measures traditionally reserved for RF ampli-
fier applications are applied to appropriate circuits cells
embedded in the forward signal path of the OTA. The
design propriety of the new OTA is demonstrated by
using it to realize active lowpass and bandpass filters
operating in the frequency range of 200 MHz to 300
MHz [24].
2. Engineering Description of the OTA
Figure 1 shows the basic schematic diagram of the pro-
posed OTA. In this diagram, transistors Q1 and Q2
comprise the balanced input differential pair. This
stage acts as a voltage-to-current converter whose

67
244 Atarodi and Choma, Jr.
Fig. I. The differential bipolar operational transconductance amplifier (OTA).
effective low frequency forward transconductance is
largely determined by the emitter degeneration resis-
tance, R... Four broadbanding schemes are incorpo-
rated into the amplifier.
The first of the broadbanding mechanisms is shunt
peaking via the capacitances, C.e~ and Cee2. which
are nominally the same value, say c••. These capaci-
tances create a left half complex plane zero in the dif-
ferential transconductance response at a frequency of
1/R ••c... The capacitance, c•• , is chosen so that
its associated zero lies close to the dominant pole es-
tablished in the absence of c••. thereby effecting at
least partial cancellation of this dominant pole. A sec-
ond broadbanding vehicle is afforded by the shunt-
anti phase shunt connection of the capacitances, Cc 1
and Cc2· If these nominally identical capacitances are
equal to the intrinsic transistor capacitance between
each base and corresponding collector of the differ-
ential pair, the effective base-collector capacitances of
Ql and ofQ2 are ideally nulled, or neutralized. Since
Miller multiplication in a phase inverting amplifier typ-
ically postures the base-collector capacitance as the
most significant contribution to the amplifier dominant
pole, such neutralization can substantially broadband
the frequency response of the uncompensated ampli-
fier.
68
The neutralization afforded by the capacitors, Gel
and Cc2 , is imperfect because transistors Ql and Q2
have non-zero base resistances, and each has a net emit-
ter impedance comprised of internal emitter resistance
appearing in series with the parallel combination of R ••
and c••. It follows that the object of neutralization is
not merely a base-collector junction capacitance. It is,
in fact, a complicated impedance whose intrinsic ele-
ments are functions of device parameters that are diffi-
cult to predict analytically. In order to offset the Miller
multiplication that resultantly prevails despite the use
of Gel and Cc 2 , a third frequency compensation scheme
in the form of a folded common base cascode is used.
This cascode, which is made up of transistors Q6 and
Q7, is used to couple the differential output current of
Ql and Q2 to the load. In the subject amplifier, the
load is a constant current sink formed of transistors QS
through Q II. Observe that the differential resistance
presented at low signal frequencies to the emitters of
transistors Q6 and Q7 is extremely high owing to the
current sinking emitter degeneration of QS and Q9 that
is afforded by the transistor pair, Q 1Q...Q 11.
The fourth broadbanding vehicle utilized in the OTA
is feedforward compensation via the capacitances,
C11 1 and C112· These capacitances, which are nom-
inally equivalent, bypass the PNP transistors, Q6 and
Q7, at high frequencies. They therefore circumvent the
 A 7.2 GHz Bipolar Operational Transconductance Amplifier for Fully Integrated OTA-C Filters
response degradation problems incurred by a PNP tran-
sistor gain bandwidth product, fT, that is measurably
smaller than its NPN counterpart, despite a comple-
mentary fabrication process capability.
The output signal response is extracted as a volt-
age developed across a single ended capacitive load
that terminates the collector of transistor Q7 to ground.
The current that flows through, and thus charges, this
capacitive load is essentially the signal current flowing
through the collector of Q7, since the differential and
common mode impedances seen at the collectors of
transistors Q8 and Q9 are very large. Accordingly, the
capacitively loaded OTA behaves as an integrator; that
is, the output signal is the integral of the differential
input voltage.
The final major design issue is biasing. In particular,
transistors Q4 and Q5 supply the biasing current com-
mensurate with the operation of transistors Q6 through
Qll in their linear active regimes. But the quiescent
voltages developed at the collectors of transistors Q6
and Q8 and at the collectors of transistors Q7 and Q9
are difficult to define reliably because these voltages
appear at the junction of a current source (Q6 or Q7)
and a current sink (Q8 or Q9). The voltage predictabil-
ity problem is exacerbated by relatively poor matching
among like model parameters in the PNP and the NPN
units of a complementary BIT process.
To rectify the foregoing bias voltage uncertainty,
common mode feedback is implemented with the dif-
ferential to single ended converter formed of transistors
Ql4 through Ql9. In an attempt to demonstrate the
effectiveness of this feedback, suppose that the quies-
cent voltage at the collector of Q8 or at the collector of
Q9 rises due to thermal drift or parametric uncertainty.
Since the collector of Q8 and the collector of Q9 are
connected to the base of Ql4 and Ql7, respectively,
and since the collector of Q 14 is tied to the collector
of Ql7, the voltage at tl)e collector of QI7 decreases.
It follows that the voltage at the collector and base of
the diode-connected transistor, Q 19, and at the base of
transistor Q 18 decreases by the same amount. But this
decrease is met be an increase in the voltage at the node
at which the collector of Q18 and the bases of Q4 and
Q5 are incident. In tum, the voltages at the collectors
of Q4 and QS decrease. Since Q6 and Q7 operate as
common base structures, nearly the same voltage de-
crease is seen at the collectors of Q6 and Q7, thereby
offsetting the original increase in voltage assumed at
the latter collector nodes. Equally important is the fact
245
that the differential voltage between the collectors of
Q8 and Q9 is kept small by the high voltage gain de-
veloped by the transistor quad, Q14 through Q 17. This
high gain is realized by the active current source, Q18,
that loads the collectors of transistors Ql5 and Ql6.
Three noteworthy design-oriented points can be of-
fered with respect to the common mode feedback sub-
circuit. First, the specific value of the quiescent volt-
age developed at the collectors of Q8 and Q9 can be
adjusted by applying a suitable static voltage, Vcm• at
the junction of the bases of transistors Q15 and Ql6.
Under normal operation of the subject orA, Vem = 0.
Second, the use of degeneration resistances in the emit-
ters of Ql4 through Ql7 ensures minimal capacitive
loading of the collector nodes at Q8 and Q9. This
minimization is essential if the pole established by the
integrating external load capacitance is to be predicted
accurately. To this end, it might be interjected that a
fabrication process featuring an insulating or a semi-
insulating substrate is desirable since the substrate ca-
pacitances of transistors Q7 and Q9 also act as para-
sitic load susceptances. Finally, the capacitances used
across the four emitter degeneration resistances in Q14
through Q 17 provide slight gain peaking at high signal
frequencies. Such peaking is useful in that high com-
mon mode subcircuit gain is essential to minimize the
offset in the differential voltage established between
the collectors of Q8 and Q9.
3. OTA Analysis and Simulation
3.1. Transconductance
The low frequency forward transconductance, Gmo• of
the orA is the ratio of the signal current, 10 , , flowing
through the extrinsic capacitive load to the differential
input voltage signal, V.. Assuming balanced operating
conditions, a conventional analysis of the differential
mode half circuit of the orA yields [25]
G _ lo, _
mo - V. - 2
(a:6) ( Ree a:1+ Tibl ) (l)
where 0:1 is the small signal, short circuit, common
base current gain of transistor Ql (and Q2), a:6 is the
corresponding current gain parameter for the PNP tran-
sistors, Q6 and Q7, and r ib1 symbolizes the small signal
common base input resistance of transistors Q 1 and Q2.
For large R ••• this transconductance is largely deter-
mined by R •• itself. On the other hand, small R.e ren-
ders Gmo strongly dependent on r;b1• whose value can
69
246 Atarodi and Choma, Jr.

1- Ree=O -- -· Ree=ISO --- Ree=250 I

-20~----------------------------------------~

-30

-40

--------------------- ........ .
i
'-J -50
~~.-

~
-60

-70

-80L--L-L~LUil-~~-LLUliL-~~~~-~-L~~

lE7 lE8 lE9 lElO lEll

frequency (Hz)
Fig. 2. Frequency response of the uncompensated OTA.

be adjusted through variations in the quiescent current,
Ix, conducted by the current sinking transistor, Q3.
Using BIT parameters provided by the Texas Instru-
ments Corporation, simulations confirm the accuracy
of (1). Moreover, and as depicted in figure 2, these
simulations suggest 3-dB bandwidths well in excess of
a gigahertz.
3.2. Noise
In addition to increasing the 3-dB bandwidth and sta-
bilizing the low frequency forward transconductance
of the OTA, the emitter degeneration resistance, R..,
increases the linear range of OTA operation; that is,
the negative series-series feedback implicit to R.e re-
duces circuit distortion [26]. Unfortunately, increases
in Ree are accompanied by increases in the integrated
total root mean square (RMS) input referred noise volt-
age, VinT• where the integration is conducted over the
3-dB passband of the OTA-C filter in which the OTA
is utilized. This noise dilemma is serious in that VinT
imposes a lower bound on the minimum signal that
can be processed reliably by the OI'A. Moreover, for
low frequency noise analysis purposes, Ree effectively
appears in series with the internal transistor base resis-
tance, Tb, whose thermal noise in the absence of R ••
generally dominates the value of V;nT [27]. The sim-
ulated data itemized in table 1 underscores the delete-
rious impact exerted by R •• on the noise properties of
theai'A.
3.3. Distortion
An especially important figure of merit for an OI'A uti-
lized in filtering applications is its dynamic range, DR,
which is defined as
DR=20log V.m)
(v,-
mT
(2)

70
 A 7.2 GHz Bipolar Operational Transconductance Amplifier for Fully Integrated OTA-C Filters 247

4.1. CapaeiJive Shunt Peaking

Tablel. Simulated noise characteristiCII of the OTA.

Ree ~/(MHz) 1/inTriiiii(IJV) The emitter degen~ration capacitance, c••. indicated

3.16 2.3
in figure 1 effects phase compensation through intro-
0 10 4.7 duction of both a zero and a pole in the frequency do-
316 32 main forward transconductance, say Gm(s). In partic-
3.16 13.1 ular, the effect of c•• is to modify the zero frequency
ISO 10 26.8 transconductance, Gmo• to
316 189.2
3.16 20
250 10 41.8
316 295

3.16 148
2000 10 301
316 2120
where Vim is the maximum RMS input signal ampli-
tude that produces a total harmonic distortion (THO)
of less than 1%. Note that DR is essentially a loga-
rithmic comparison of the maximum allowable input
signal amplitude (for THO < 1%) and the minimum
detectable input signal amplitude.
Since the OTA designed in this work is a fully differ-
ential circuit topology, even order output harmonics of
a single frequency input test sinusoid are theoretically
eliminated. With Ree = 2 KO, and at an input signal
frequency of 3 MHz, the simulated THO is about 1%
for Vim = 3.53 volts. For R.e = 150 nand at an input
signal frequency of 300 MHz, V.m is 99 mV. Using
table 1, it follows that the dynamic range at 3 MHz and
for R •• = 2 KO is 87.5 dB. On the other hand, DR=
54.3 dB at 300 MHz and for R•• = 150 0.
If the frequency and phase responses of the uncom-
pensated (meaning c•• = 0) OTA are known, c•• can
be selected so that the phase contribution of the intro-
duced zero offsets the phase angle associated with poles
of the uncompensated OTA. Implicit to this selection
process is the requirement, R.. :;$> r ibl• so that the
pole time constant in {3) is significantly smaller than
both the time constant, R•• c•• ,and the dominant time
constant of the poles implicit to the uncompensated
OTA. Note, however, that large R.e increases the input
referred noise and diminishes Gmo. Accordingly, ca-
pacitive shunt peaking is not completely effective, and
additional phase compensation schema are mandated.

4. Broadbanded Phase Compensation

A detailed high frequency analysis of the differential

half circuit of the OTA confirms that the subject OTA
is not a dominant pole configuration. This situation
substantially complicates the bandwidth and phase re-
sponse estimation problems [28]. The phase angle of
an OTA is an especially serious concern in OTA-C fil-
ter applications [29] since the phase response of the
utilized OTA must be maximally flat throughout the
passband of the desired filter [30]. Achieving an ap-
propriately compensated phase response is the primary
design objective of realizing an OTA that is suitable for
a particular filter application. Fig. 3. The capacitative neutralization transistors, Qat and Qa2.

71
248 Atarodi and Choma, Jr.
4.2. Capacitive NeutraliZ!llion
A phase compensation method that compromises nei-
ther Gmo nor input noise is the capacitive neutral-
ization achieved by capacitors, Get and Ge2• in fig-
ure I. As discussed earlier, these nominally identical
capacitances are equal to the intrinsic transistor capac-
itance between each base and corresponding collector
of the Ql--Q2 differential pair. Such matching is best
achieved by realizing the subject compensation capac-
itances actively, as shown in figure 3 [4]. In this figure,
Get is the base-collector capacitance of transistor Qal,
and Ge2 is the base-collector junction capacitance of
transistor Qa2, where all four transistor are matched
elements. Since the base-collector depletion capaci-
tance of a BIT is independent of quiescent collector
current, the emitters of the introduced compensation
transistors are left open circuited. Accordingly, transis-
tors Qat and Qa2 introduce no additional circuit noise.
By ideally canceling the base-collector capacitances
of Q I and Q2, Qat and Qa2 neutralize the significant
phase shift that these junction capacitances introduce
in the forward transconductance of the afA. By mak-
ing the base-emitter junction injection areas of Qat and
Qa2 slightly larger than those of Q t and Q2, the effec-
tive capacitance seen between the base and collector
terminals of both Ql and Q2 becomes negative [t4].
Through Miller multiplication of this negative capac-
itance, the net shunt input capacitance at the bases of
QI and Q2 is reduced, thereby further improving the
phase response of the differential input stage.
Unfortunately, the phase compensation afforded by
capacitive neutralization is less than ideal for several
reasons.
I. The effective impedance seen at the base-collector
terminals of transistors Q I and Q2 in the input dif-
ferential pair of figure I is not purely capacitive.
Instead, it contains components of the driving point
impedances established at the base and collector
nodes of these devices. These impedance compo-
nents, which are functions of quiescent operating
point, are negligible in Qal and Qa2, since these
two transistors conduct zero static collector current.
Since the implicit requirement of capacitive neu-
tralization is that the base-collector impedance of
Qal (Qa2) match the corresponding impedance of
Qt (Q2), the subcircuit in figure 3 leaves a resid-
ual impedance at the interconnected base-collector
terminals of transistors Q t and Q2.
72
2. The neutralization scheme in figure 3 is effective
only insofar as the signals at the collectors of tran-
sistors Q t and Q2 are t80° out of phase with one
another. This requirement mandates a differential
input signal drive and/or very high common mode
rejection ratio. Unfortunately, the common mode
rejection ratio deteriorates with increasing signal
frequencies. Such deterioration means that capaci-
tive neutralization becomes progressively less effec-
tive at the very signal frequencies where the phase
lag contributed by the base-collector junction ca-
pacitance becomes more pronounced.
3. The benefits potentially gained by capacitive neu-
tralization are somewhat offset by the fact that tran-
sistors Qal and Qa2 add substrate capacitance to
the collector nodes of transistors Q2 and Q t, re-
spectively. Neutralization is, in fact, most effective
when it is used in conjunction with a fabrication
process that boasts insulating substrate material.
4.3. Feedforward Compensation
As discussed earlier, the nominally equivalent feed-
forward compensation capacitances, Gift and C//2•
bypass the PNP common base cascode transistors, Q6
and Q7, at high signal frequencies. They therefore cir-
cumvent inherent gain bandwidth product limitations
in PNP units by forcing the NPN transistors, Q8 and
Q9, to serve as high frequency common base cascode
compensation of the input differential pair.
Figure 4 dramatizes the effect of feedforward com-
pensation. In particular, curve I gives the frequency
response without capacitive shunt peak compensation
(Geet = Gee2 = 0) and without feedforward compen-
sation (Gift = G112 = 0), but with active capacitive
neutralization incorporated. Curve 2 pertains to the
afA with capacitive shunt peaking added. Note the
resultant enhanced bandwidth at the price of substan-
tive response peaking. Curve 3 applies to the case of
a neutralized OTA with both capacitive shunt peaking
and capacitive feedforward compensation. Observe an
additional slight increase in 3-dB bandwidth to about
7.2 GHz with reduced peaking.
The phase response, referenced to the constant -90°
phase angle of an ideal integrator, of the compen-
sated arA is shown in figure 5. Curve (a) depicts
the phase response for capacitive shunt peaking alone,
while curve (b) illustrates the effects of both capaci-
tive shunt and feed forward compensation. Both curves
 A 7.2 GHz Bipolar Operational Transconductance Amplifier for Fully Integrated OTA-C Filters 249

-38~-------------------------------------,

,~·;;·:-~- .. :~
-42
,,}~"/ \ \\
_____ ..... ..,.~ \\
-46 \\\1
""\I
-SO 'I

"
'I
'.I
\I
\I
'""' -54 '.I
\\
~ •I
I
I
c§ -58
I
I
I
I
I
I
I
I
-62 I
I
I
I
I
I
-66

1-( I
I
I
I
I
I
I ) -- .. ( 2) ---· ( 3)
-70

-74L--L~~~~~_L~~ll-~~~~~~~~~~

1E7 IEB 1E9 IEIO JEll

frequency (Hz)
Flg. 4. Frequency response of the OI'A with: (I) no phase compensation; (2) cnpacltive shunt peaking; (3) capacitive shunt peaking and
feedforward cnpacitlve compensation.

pertain to an OTA that is actively neutralized as per the 6. Conclusions

diagram in figure 3. Note that the phase difference in-
dicated for curve (b) is less than ±0.8° over a passband
greater than 600 MHz.
S. Filter Design Examples
In an attempt to demonstrate the practical utility of the
OTA developed and optimized in this work, two OTA-
C filters have been designed. The first is a lowpass
third order filter whose frequency response is depicted
in figure 6, Observe the maximally flat nature of this
response and a 3-dB bandwidth of approximately 225
MHz. The 6-dB of attenuation at low signal frequen-
cies is due to matched source and load termination re-
sistances.
The second filter is a bandpass structure whose cen-
ter frequency is 250 MHz and whose 3-dB bandwidth
is about i25 MHz. Its realization, which requires four
OTA units, is depicted schematically in figure 7. The
pertinent magnitude response is offered in figure 8.
Using a monolithic complementary bipolar junction
transistor process, this work successfully addresses the
problem of designing low noise, wideband, high dy-
namic range operational transconductance amplifiers
(OTAs). The OTA developed in this effort utilizes a
folded cascade in concert with capacitive feedforward
compensation, capacitive neutralization, and emitter
degeneration to optimize the frequency and phase re-
sponses. As a consequence of this effort, this work
demonstrates the feasibility of realizing high perfor-
mance biquadratic filters that are suitable for mono-
lithic integration. A particularly noteworthy discovery
is that for biquadratic filter applications, the bandwidth
of the utilized OTA is not the only critical design issue.
Equally critical is the phase response of the effective
forward transconductance produced when the OI'A is
transformed into a wideband integrator by terminating
the output port of the OTA in question in a suitably
large capacitance. 'In order to ensure predictable and
reliable filter bandwidths and other frequency response

73
250 Atarodi and Choma, Jr.

(b)
0.6

0.4

0.2

I
0

§ -0.2
f
-0.4

-0.6

-0.8

-I
IE7 1E8 1E9
frequency (Hz)

Fig. 5. Phase response, with respect to a -90° reference (conesponding to an ideal Integrator) of the OTA after: (a) capacitive shunt peaking;
(b) both capacitive shunt peaking and feedforward capacitive compensation.

features, the phase response of the capacitive termi-
nated OTA must be maximally flat at -90° (the phase
angle of an ideal integrator) to within about ± 1° over
the passband of the desired filter.
References
I. Grebene, A. B., Bipolar and MOS Analog Integrated Circuit
Design, chap. 8. New York: Wiley-Interscience, 1984.
2. Solomon, J. E. and Wilson, G. R.. "A highly desensitized
wideband monolithic amplifier," IEEE J. Solid-State Circuits,
Vol. SC-I, pp. 19-28, Sept. 1966.
3. Gilbert, B., "A new wideband amplifier technique," IEEE J.
Solid-State Circuits, Vol. SC-3, pp. 353-365, Dec. 1968.
4. Mataya, J. A., Haines, G. W. and Marshall, S. B., "IF am-
plifier using Cc-compensated transistors," IEEE J. Solid-State
Circuits, Vol. SC-3, pp. 401-407, Dec. 1968.
5. Camenzind, H. R. and Grebene, A. B., "An outline of design
techniques for linear integrated circuits," IEEE J. Solid-State
Circuits, Vol. SC-4, pp. 110-122, June 1969.
6. Wooley, B. A., "Automated design ofDC-coupled monolithic
broad-band amplifiers," IEEE J. Solid-State Circuits, Vol. SC-
6, pp. 24-34, Feb. 1971.
7. Couglin, J. B., Gelsing, R. J., Jochems, P. J. and van der Laak,
H. J. M., "A monolithic silicon wideband amplifier from DC to
I GHz," IEEEJ. Solid-State Circuits, Vol. SC-8, pp. 414-419,
Dec. 1973.
8. Meyer, R. G., Eschenbach, R. and Chin, R., "A wideband ul-
tralinear amplifier from DC to 300 MHz," IEEE J. Solid-State
Circuits, Vol. SC-9, pp. 167-175, Aug. 1974.
9. Allen, P. and Terry, M. B., "Use of cunent amplifiers for high
performance voltage applications," IEEE J. Solid-State Cir-
cuits, Vol. SC-15, pp. 155-162, 1980.
10. Meyer, R. G. and Blauschild, R., "A four terminal wideband
monolithic amplifier," IEEE J. Solid-State Circuits, Vol. SC-
17, pp. 634-638, Dec. 1981.
II. Choma, J., Jr., "Gain and bandwidth characteristics of a vari-
able gain, actively neutralized, differential pair," IEEE Trans.
Circuits and Systems, Vol. CAS-33, pp. 66-71, Jan. 1986.
12. Choma, J., Jr., "Simplified design guidelines for dominant pole
amplifiers peaked actively by emitter or source followers,"
IEEE Trans. Circuits and Systems, Vol. 36, pp. 1005-1010,
July 1989.
13. Armijo, C. T. and Meyer, R. G., "A new wide-band Darling-
ton amplifier," IEEE J. Solid-State Circuits, Vol. SC-24, pp.
1105-1109, Aug. 1989.
14. Beall, W. G. and Choma, J., Jr., "Charge-neutralized differen-
tial pair," J. of Analog Integrated Circuits and Systems, Vol. I,
pp. 33-44, Sept. 1991.
IS. Degrauwe, M.G. R., "CMOS voltage references using lateral
bipolar transistors," IEEE J. Solid State Circuits, Vol. SC-20,
pp. 1151-1157, December 1985.
16. Wyszynski, A., Schaumann, R., Szczepanski, S. and Halen,
P. V., "Design of a 2. 7 GHz linear OTA in bipolar transistor

74
 A 7.2 GHz Bipolar Operational Transconductance Amplifier for Fully Integrated OTA-C Filters 251

-5

-10

-15

-20

..-.. -25
.....
_e.
-30
=8
>
-35

-40

-45

-50

l_l
-55
1E7 1E8 1E9 lElO
frequency (Hz)
Fig. 6. Magnitude response of a lowpass OTA-C filter; the 6-dB loss at low signal frequencies is incurred by source and load termination
resistances.

22. Jost, S. R., "An 850 MHz current feedback operational ampli·
tier," Proc. Bipolar Circuits and Tech. Mtg., pp. 71-74, 1992.
23. Toumazou, C. and Lidgey, F. J., "E•tending voltage-mode am-
plifiers to current-mode performance," lEE Proc. G. Electron.

u~·
Circuits and Systems, Vol. 137, pp. 116-130.
• + -+ 24. Atarodl, M. and Choma, J., Jr., "High frequency fully inte-
3 4 grated OTA-C filters using a 7.2 GHz bipolar OTA," Proc.
- - IEEE 36th Midwest Symp. on Circuits and Systems, 1993.
25. Witherspoon, S. and Choma, J., Jr., "The analysis of balanced
C!L_ ~2 linear differential circuits," IEEE Trans. on Education (to be
published in Dec. 1995).
26. Moree, J. P., Groenwold, G. and van den Broeke, L.A. D., "A
Fig. 7. Basic schematic diagram of a two pole OTA-C
bipolar integrated continuous-time filter with optimized dy-
biquadratic bandpass filter. namic range," IEEE J. of Solid-State Circuits, pp. 954--961,
array technology wilh lateral PNPs." Proc. IEEE International Sept. 1993.
Symp. on Circuits and Systems, pp. 2844-2847, 1992. 27. Moinian, S. and Choma, J., Jr., "The frequency response of
17. Gray, P.R. and Meyer, R. G., Analysis and Dt.dgn of Analog bipolar transistor noise figure," IEEE Trans. on Circuits and
Integrated Circuits. New York: John Wiley & Sons, chap. 6, Systems, Vol. CAS-33, pp. 72-76, Jan. 1986.
1977. 28. Choma, J .. Jr. and Witherspoon, S. A., "Computationally ef-
18. Franco, S., De.rign with Operational Amplifiers and Analog ficient estimation of frequency response and driving point
ICs. New Yodc McGraw-Hill, 1988. Impedance In wideband analog amplifiers," IEEE Trans. on
19. Franco, S., Current Feedback Amplifiers Benefit High Speed Circuits and Systems, Vol. CAS-37, pp. 720--728, June 1990.
Designs. EDN, 1989. 29. Clelger, R. L. and Sanchez-Sinenclo, E!., "Active fllter de-
20. Koulllas, I. A., "A wideband low-offset current-feedback op sign using operational transconductance amplifiers: a tutorial,"
amp design," Proc. Bipolar Circuits and Tech. Mtg., pp. 120- IEEE Circuits and Devices Magazine, pp. 20--32, 1985.
123, 1989. 30. Atarodi, M., Analysi.r and Design of Operational Tronscon·
21. Lidgey, F. J. and Toumazou, C., "Current-mode analogue sig- ductance Amplifiers for Ota-C Filter Applications, Ph. D. Dis-
nal processing," Proc. Bipolar Circuit.• and Tech. Mtg., pp. sertation, University of Southern California, Los Angeles, Cal-
224--232, 1991. ifornia, Aug. 1993.

75
252 Atarodi and Choma, Jr.

O r-------------~----------------~

-5

-10

:0
"C
c: - 15
~

-20

-25

-30 L _L.....I--L...J...-'---L_L_L_J_.I____j_.JL...J...-'---L_L_L_J_.I____j_L__L_1___,_--L.J..J

1E7 1E8 1E9 IEIO

frequency (Hz)

Fig. 8. Frequency response of the OTA-C bandpass filter; the center frequency is 250 MHz, and the quality factor Is 2; that Is the 3-dB bandwidth
is about 125 MHz.

Mojtaba Atarodl received the B.S.E.E. from Amir Kabir
University of Technology (Tehran Polytechnic) in 1985, and
the M.S. degree in Electrical Engineering from the Universi-
ty of California, Irvine, in 1987. He received the Ph.D. de-
gree from the University of Southern California (USC) on the
subject of analog IC design in 1993, and is currently with the
Linear Technology Corporation working on the same subject.
John Choma, Jr. earned his B.S., M.S., and Ph.D. degrees
in electrical engineering from the University of Pittsburgh in
1963, 1965, and 1969, respectively. He is currently a Profes-
sor of Electrical Engineering at the University of Southern
California, where he teaches undergraduate courses in elec-
trical and electronic circuits and graduate courses in analog
electronics and network theory. Prof. Choma consults In the

76
 A 7.2 GHz Bipolar Operational Transconductance Amplifier for Fully Integrated OTA-C Filters
areas of wideband analog and high speed digital integrated
circuit analysis, design, and modeling. Prior to joining the
USC faculty in 1980, Prof. Choma was a senior staff design
engineer in the TRW Microelectronics Center in Redondo
Beach, California. His earlier positions include technical
staff at Hewlett-Packard Company in Santa Clara, Califor-
nia, Senior Lecturer in the Graduate Division of the Depart-
ment of Electrical Engineering of the California Institute of
Technology, and part time or full time positions with the Uni-
versity of Pittsburgh, University of Santa Clara, University of
Pennsylvania, and University at Los Angeles. Prof. Choma,
the author or co-author of 80 journal and conference papers,
is the 1994 recipient of the Prize Paper Award from the IEEE
Microwave Theory and Thchniques Society. He is the author
of a Wiley Interscience text on electrical network theory, and
a forthcoming Richard D. Irwin text on electronic circuit de-
sign. Prof. Choma has contributed several chapters to two
253
edited electronic circuit texts, and he is an area editor of
a forthcoming CRC Press handbook on circuits and filters.
Prof. Choma is currently a member of the Board of Gover-
nors for, and the Vice-President- Administration of, the IEEE
Circuits and Systems Society. He is also a Regional Editor
of the Journal of Circuits, Systems, and Computers, an As-
sociate Editor for the Journal of Analog Integrated Circuits
and Signal Processing, and a former Associate Editor for the
IEEE Transactions on Circuits and Systems. Prof. Choma's
research interests include wideband analog and high speed
digital integrated circuit design, behavioral analysis of elec-
tronic systems, integrated device modeling, and engineering
education in the circuits and systems areas. Prof. Choma, a
Fellow of the IEEE, is the recipient of several teaching awards
and is a ''Teaching Fellow" in the USC Center for Teaching
Excellence.
77
 Analog Integrated Circuits and Signal Processing, 6, 255-263 (1994)
C 1994 Kluwer Academic Publishers, Boston.

Current-Mode Synthesis Using Node Expansion Techniques

MEHUL DESAI AND PETER ARONHIME

O.partltNnt of E/1Ctrlca/ Englnm1ng, Unlvenlty of LDulsvllk, LouIIIIIII•. KY 40292

pbaronDIOulfcyvx./oulsvllk.•du

Abstract. This paper derives node expansion methods by which a given passive network and its nodal admittance
matrix are modified by expanding a node into two nodes and introducing a nullor or a dependent source between the
newly created nodes. Node expansion provides a systematic method to introduce active elements in a network. The
elements of the admitance matrix are modified, but the dimensions of the matrix are unchanged. These methods,
which can be applied repetitively, are used to derive filters and oscillators from parental passive networks in a
systematic manner.

1. Introductfon 2. Node Expansion

It is well known [9, 10] that the introduction of a nul-
Current-mode circuits have been shown to be capable lor into a circuit reduces the order of the square nodal
of greater bandwidths, and they are generally simpler admittance matrix by one. If a node is first expanded
to construct than corresponding voltage-mode circuits into two nodes, followed by the introduction of a nullor
[1]. Thus, there has been a great amount of interest in into the circuit, the order of the square nodal admittance
synthesizing current-mode circuits. Among the proce- matrix remains the same.
Consider a passive network with n + 1 nodes, in-
dures used to synthesize current-mode circuits are those
cluding the ground node, consisting of two-terminal
developed by Roberts and Sedra [2, 3], Carlosena and admittances. An admittance connected between nodes
Moschytz [4], Stevenson [5], and Ouo-hua et al. [6, 7]. i and j is denoted as YiJ• and an admittance connected
Current-mode circuits can also be synthesized by using between node i and ground is denoted as Yi(n+t)· The
Davies's analysis procedures in the reverse [8]. n x n nodal admittance matrix is:
In this paper, the approach to deriving new current-
mode circuits is to directly modify the elements of the
where
nodal admittance matrix of a given or selected passive
network by introducing a nullor into the network while -YiJ• i #j
keeping the dimensions of the square nodal admittance { n+l
'\!
matrix (NAM) constant. This method, which we call .J'ij= ~ (l)
L.J y~q, i = j
node expansion can be applied repetitively to introduce q-l
multiple nullors into the circuit. The nullor can then q " j

be realized using a current conveyor.
Other active devices require two or more nullors
in their network models. In some cases, these devices
may be inserted into a network by repetitive application
of node expansion. However for simplicity and con-
venience, node expansion methods are developed so
that dependent sources can be directly inserted while
keeping the dimension of the NAM constant.
Assume there exists one node k which has three or
more admittances connected to it. If the node k is ex-
panded into two distinct nodes k' and k" by applying
the following procedure:
Procedure ( nullor)
l. Replace node k with two distinct nodes k' and k"
such that at least one branch of the original network
(which was connected to node k) is connected to
node k' and at least two branches to node k",

79
256 Desai and Aronhime
k Yk(p+tl
•
•
Yk(n+l)
Fig. I. Admittances connected to a general node k In a passive net-
work. Note that 1/kk does not exist, anti thus there are at most n
admittances connected to node k.
2. Insert a nullator between node k' and k", and
3. Connect a norator between node k' and ground,
then the new nodal admittance matrix is obtained from
the theorem given below.
1 The nodal admittance matrix of the net-
THEOREM
work modified by the procedure (nullor) is obtained by
replacing the admittances Yik (or Yk;) which are now
connected between node k' and ground and between
node k' and node i, i = 1, 2, ... , k- 1, k + 1, ... , n,
with zero in the kth row of the nodal admittance matrix
of the original network.
Proof: Figure I shows a general node k, k = 1,
2, ... , n, in a passive network that contains n +1 nodes
including the ground node with n ::::>: 3. It is convenient
to assume the network's graph is completely connected.
Thus there are at least three admittances connected to
each node. Applying KCL to node k we obtain
n n+l
o= - L: Vq(Ykq) + vk L: Ykq (2)
q =I q =I
q#k q#k
Node k is expanded into nodes k' and k" such that
at least one admittance is connected to node k' and at
80
Ykt
Ytp
Fig. 2. Results after node k has been expanded.
least two are connected to k". Without loss of general-
ity, assume the first p admittances 1 :::; p :::; (n- 2) are
connected to node k' and the next (n- p) admittances
that were connected to k are now connected to node
k". The nullator is connected to k'. Figure 2 shows
the result of the expansion procedure on node k.
There are now n + 2 nodes in the network, but
vk' = vk". The nodal equations at nodes k' and k"
can be written as:
= - L"
-lout Vq(Ykq) + vk' (3)
q=l
q#k
t
0 =- Vq(Ykq) + Vk' (q =~+ 1 Ykq) (4)
q;~tl q#k
Thus the ( n + 1) square intermediate admittance ma-
trix has two rows, corresponding to nodes k' and k",
replacing the kth row, and two columns replacing the
kth column. Since Vk' = Vk"• the elements of the
(k + 1)th column are added to the elements of the kth
column. There are now (n + 1) equations in (n + 1)
unknowns (n node voltages and the norator current),
and if we are not interested in the norator current, the
kth row and the (k + l)th column are eliminated to
obtain ann x n nodal admittance matrix [10]. Hence,
the new nodal admittance matrix has for its kth row
the nodal equation for node k". As a result, the admit-
tances y;,, 1 :::; p:::; (n- 2), which were connected to
node k' are eliminated from the kth row of the nodal
admittance matrix of the modified network.
•
 Current-Mode Synthesis Using Node Expansion Techniques 257

Yt2 + Yta + Yt4 -Yt2

Y= [ -Yt2 Yt2 + Yza + Y24
-Yta 0
Y14

The other rows of Y are unchanged.

Node 3 in figure 3(a) could also be expanded as
(a)
shown in figure 3(c). In this case, admittance Yta.
which is connected to node 31, is replaced by zero in
row three of eq. (5) yielding

Yt2 + Yta + Yl4 -Yt2

-Ytal
Y = [ -Yt2 Y12 + Y2a + Yz4 -Y23
Y14
0 -Y23 Yza + Ya4
(7)

(b) It is seen from these examples that particular en-

Y23 3•
Y14
(c)
Fig. J. (a) A passive circuit with three nodes; (b) and (c) two exam-
ples of expansion of node 3 Into two nodes 31 and 311 •
Figures 3(a) and 3(b) illustrate the process of node
expansion for a given network with three nodes plus
a ground node. The nodal admittance matrix of the
network shown in figure 3(a) is given by
tries in the matrix may be removed by a simple series
of operations performed on the network. In a simi-
lar way, nodes 1 or 2 of figure 3(a) can be expanded
into two nodes thereby modifying rows 1 or 2 of the
nodal admittance matrix, respectively. This expansion
technique may be applied to more than one node in a
network or may be applied to a node repetitively pro-
vided step 1 in the expansion procedure (nullor) can be
performed.
There are three other ways of connecting the nul-
lor in the circuit with both the nullator and the norator
connected to node k'. These connections and their ef-
fects on the nodal admittance matrix are described in
the following:
COROLLARY If step 3 of procedure (nullor) is modi-

l
fied so that the norator is connected to node j, j f. k'
Y= or k", instead of to the ground nade, then the modi-
fied nodal admittance matrix is obtained by replacing
Yt2 + Yta + Yt4 -y12 admittances Yllc in the kth row with zeros and adding
[ -Yta
-Yl2 Yt2 + Y2a + Y24 -Y23 them with their signs to the corresponding elements in
the jth row.
-Yta -Yzs Yts + Y2s + Ya4
(5)
THEOREM 2 If the nullator and norator are inter-
If node 3 is now expanded into two nodes 3' and 3" as changed In the procedure (nullor), the nodal admit-
shown in figure 3(b), with admittance y 2a connected tance matrix is modified along the columns instead of
to node 3' and admittances Yts and Y34 connected to the rows as given in Theorem 1 and in the corollary.
node 311, the new nodal admittance matrix is obtained
by replacing Y23 by zero in row three of eq. (5) resulting Proof" From [4), interchanging nullators and norators
in: in a network in which all active elements are modeled

81
258 Desai and Aronhime
by nullors yields an adjoint network whose nodal ad-
mittance matrix is the transpose of the nodal admittance
matrix of the original network. • if Ko. and Vpq(Vpq = Vp(n+I) - Vq(n+I)) are known,
The nullor introduced in the passive network has the
form of a negative second generation current-conveyor
(CCII-). Other active elements, viz., transconduc-
tance amplifiers, positive second generation current-
conveyors (CCII+) and dependent sources, are mod-
eled using more than one nullor. Dependent sources,
for example, are modeled with two and sometimes three
nullors together with one or more admittances [10].
Nullors may be introduced into the network repetitively
provided the procedure (nullor) is satisfied, but, with
more than two nullors, this technique becomes cum-
bersome. Hence, for convenience and simplicity, node
expansion theorems are presented which employ de-
pendent sources directly.
Consider the procedure given below for introducing
a dependent voltage source in a network.
Procedure (VCVSICCVS)
I. Replace any node k with two distinct nodes k'
and k" such that there are at least two admit-
tances connected to node k" and one admittance
to node k'. It is assumed that there are m admit-
tances connected to node k with m ~ 3.
2(a). For a VCVS the controlling voltage is taken be-
tween any two nodes p and q, where p f k' or
ground and q can be any node including (triv-
ially) p.
2(b). For a CCVS the controlling current is a branch
current flowing through admittance Ypq·
3. Connect the dependent voltage source between
node k' and ground.
Then the new nodal admittance matrix is obtained from
the theorem given below.
THEOREM 3 The NAM of the network modified by
procedure (VCVS/CCVS) is obtained by replacing the
admittances Yik (or Yk;), i = 1, 2, ... , k - 1, k +
1, ... , n + 1, connected to node k' with zero in the
kth row, multiplying these same admittances still re-
maining in the kth column by 'Ko. 'for a VCVS and
by 'K&Ypq 'for a CCVS, eliminating these admittances
Yik in the kth column, and adding and subtracting them
to the pth and from the qth columns, respectively. Note
that 'Ko.' is unitless while the units for 'Kb' are ohms.
Proof (VCVS): During the process of node expan-
sion node k is replaced with two distinct nodes k'
82
and k". There are still only n unknown node volt-
ages as Vk = Ko. Vpq· Since Vk is immediately known
a node equation for node k' is not required to solve
for the n node voltages. The new NAM will contain
the node equation for node k" in place of the equation
for node k in the original NAM, and hence, the admit-
tances Yik, i = 1, 2, ... , k - 1, k + 1, ... , n + 1 which
are now connected to node k' are replaced with zero
in the kth row of the NAM. Additionally, these same
admittances Yik are multiplied by Ko. in the kth col-
umn, deleted from the kth column, and then added and
subtracted to the corresponding entries of the pth and
qth column respectively, because Vk = Ko. Vpq.
It should be noted that after the expansion procedure
any admittances Yk(n+l) which are now connected to
node k' will be completely eliminated from the admit-
tance matrix and may be viewed as load admittances
•
on the controlled source.
The proof for node expansion employing a CCVS
is similar.
A procedure and a corresponding theorem are now
provided for introducing a VCCS or a CCCS into a
network.
Procedure (VCCSICCCS)
1. Replace node k with two distinct nodes k' and k"
such that at least one ungrounded (floating) ad-
mittance which was connected to node k of the
original network is connected to node k', and at
least one ungrounded admittance is connected to
node k". Grounded admittances that were con-
nected to node k are connected to node k".
2. Connect node k' to ground.
3(a). For a VCCS the controlling voltage is taken be-
tween nodes p and q, where p f k' or ground and
q can be any node including (trivially) p.
3(b). For a CCCS the controlling current is taken as
that current flowing through admittance ypq or
admittance Yp(n+I)·
4. Connect the dependent current source between
node k" and ground.
Then the new nodal admittance matrix is obtained from
the theorem given below.
THEOREM 4 The NAM for the network modified by
the procedure (VCCS/CCCS) is obtained by eliminat-
ing those admittances Yik• i = 1, 2, ... , k - I, k +
1, ... , n + I, connected to node k' (now ground) from
 Current-Mode Synthesis Using Node Expansion Techniques 259

If Yt3 = set, Yt2a = sc2, Y12b = 9to and Y23 = 92 in

Yt2b

(9), the characteristic equation is given by:

IYI = s 2c1c2 + s(ct(91 + 92) + c292) + 9192 = 0
Yt3 (10)

(a)
One way the 's' term can be eliminated is by ampli-
tude scaling Yt2a or Yt2b in Yt2 in (8). Thus, expanding
node 2 and introducing a CCVS as described in the pro-

l
cedure (CCVS) we get the circuit in figure 4(b) which
has a node admittance matrix given by

Y1a + Yt2a + Yl2b -Yt2a - KbY23Yl2b

y = [ (II)
Yt3
-Yt2a + Y2a
Y12a
With Kb = K/9to and c2(9t + 92) + Ct92 = c292K,
(b) we obtain the new characteristic equation
(12)

Figure 4(c) shows how the's' term is eliminated using

the procedure (VCCS ). The resulting admittance matrix

l
is given by
Yt3 + Yt2a + Y12b -Yt2a
Y= [ (13)
-Yt2a -Kc Y12a + Y2a
(c) Using the same choice of components as before we
obtain the characteristic equation
Fig. 4. (a) A passive circuit with two nodes plus a ground node;
(b) expansion of node 2 using procedurt (CCVS); (c) expansion of s 2c1c2 + s(Ct92 + c2(91 + 92 - Kc)) + 9192 = 0
node 2 using procedurt (VCCS).
(14)
the kth row and the kth column, and by adding a con-
stant ~Kc (coefficient of the dependent source) to the With Kc = K92 and c2(9t + 92) + CtY2 = c292K,
admittances in the kth row and the pth and qth columns, we can eliminate the 's' term. All oscillator circuits,
respectively. If the controlling variable is current, re- obtainable with the parent passive circuit shown in fig-
place Kc with K:iYpq or K:iYp(n+l)· ure 4(a), whether voltage- or current-mode, can be ob-
The proof for Theorem 4 is similar to that for The- tained by a systematic application of these theorems.
orem 3. As an example of the use of node expansion Note that the CCVS in figure 4(b) can be replaced by
using dependent sources in the design of sinusoidal os- its nullor model to get the circuit in figure 5. Here the
cillators consider the circuit shown in figure 4(a). Its conductance G can be adjusted to set the coefficient of

l
node admittance matrix is given by the dependent source.

Yt3 + Yt2a + Yt2b -Yt2a - Yt2b

Y= [ (8) 3. Applications
-Yt2a- Yt2b Yt2a + Yt2b + Y23 The node expansion theorems described above can be
The characteristic polynomial is obtained from the de- applied to a passive circuit to generate active filter cir-
terminant of Y and is given by cuits in a systematic manner. For example, application
of Theorem 1 to the four-node completely connected
IYI = Yt3(Yt2a + Yt2b + Y23) + Y23{Yt2a + Yt2b) (9) passive network in figure 3(a) yields the circuit shown

83
260 Desai and Aronhime

Yt2b

r-----------------------------------~w
-,
I
I
I
I
Y23 I
I
I
I

y-----------------}zj
Fig. 5. CCVS in figure 4(b) replaced with a two-nullor representation.

2 Y23 3' lout

Fig. 6. Network of figure 3(b) with 1/14 set to 0, a current excitation applied, and a load admittance attached.

in figure 3(b) and the node admittance matrix in (6). If The circuit in figure 6 is the basis for the circuit pre-
Yt4 is set to zero, node l is excited by a current source, sented by Liu, Tsao and Wu [II]. With suitable choices
and the output is taken through a load admittance YL• of types and values of components, they obtain a cas-
the circuit in figure 6 is obtained which has the transfer cadable filter section which can realize all five second
function: order filter types.
Other filter circuits can be obtained from figure 3(b).
lout Y2a(Ya4Yl2 - Y24Yta)
(15)
If instead of setting Yt4 = 0, we make Y24 = 0 and
I,n = IYI Yt2 = oo, apply. the excitation to node l, and con-
nect the load YL as in figure 4, with a suitable choice
where of components, we can obtain lowpass, highpass and
bandpass circuits. These circuits were presented by
(16) Higashimura et al. [ 12].

84
 Current-Mode Synthesis Using Node Expansion Techniques
(a)
A'
t Klo
(b)
Fig. 7. (a) A second order biquadratic network N excited through a unity gain current buffer; (b) node 'A' expanded.
As an example of the use of Theorem 2, assume
that figure 3(a) is expanded at node 3 with the norator
connected between nodes 3' and 3" and the nullator
between nodes 3' and 2. Also assume admittance y 34
is connected between 31 and ground. Applying an ex-
citation at node 1 or node 2 and connecting the load
YL between 311 and ground, we obtain, with the choice
of suitable types and values of the components, a uni-
versal filter. These circuits have been developed and
presented by Liu, Kuo and Tsay [13]. In the above
examples, the null or can be replaced by a CCII-.
Many existing circuits can be generated using this
procedure. Higher order filter sections can be devel-
oped starting from a completely connected passive net-
work.
261
Node expansion techniques using dependent current
sources can be used to generate several oscillator cir-
cuits. Figure 7(a) shows a second-order passive net-·
work N with an output current / 0 and an input current
excitation It. The transfer function 10 //1 of the pas-
sive network N can be expressed as
(17)
Node A is expanded using procedure (CCCS) and The-
orem 4, yielding the network shown in figure 7(b). The
resulting circuit is a hinged network, but the portion
of the network containing the excitation in figure 7(b)
is removed since by adjusting the gain of the depen-
dent source the circuit will oscillate. The oscillation
85
262 Desai and Aronhime
condition and the frequency of oscillation are given by
(18)
2 boat- btao
(19)
Wo = b2a1 - b1a2
where K is the gain of the dependent source. In devel-
oping different oscillators the only conditions forced
on the network N are a 1 :I 0, and b2a1 :I b1a 1 from
(18) and (19).
4. Conclusions
Procedures, four theorems and a corollary have been
presented which enable a designer to directly modify
the entries of the NAM of a given network. Theorems I
and 2 and the corollary show how the NAM is modi-
fied while keeping the dimensions constant by properly
inserting a nullor into the given network.
In Theorems 3 and 4, dependent sources are em-
ployed to modify the NAM.
Several examples of the applications of these the-
orems are provided in which universal current-mode
filters which have been previously published in the lit-
erature are derived. In addition, a current-mode oscil-
lator circuit is obtained by applying Theorem 4.
Node expansion is shown to provide a systematic
approach to introducing nullors and dependent sources
into a circuit. In general, node expansion can be
used repetitively, and the resulting nullors or dependent
sources can be replaced by a variety of active devices.
References
I . Toumazou, C., Lidgey, F. and Haigh, D., Analogue lC Design:
The Current-mode Approach. London: Peter Pcregrinus Ltd.,
pp. 164-169, 1990.
2. Robert<, G. and Sedra, A., "All current-mode frequency selec-
tive circuits," Electronics Letters, Vol. 25, pp. 759-761, June
1989.
3. Roberts, G. and Sedra. A., "A general class of currenlamplifier-
based biquadratic filter circuits," IEEE Trans. Circuits Syst.,
Part I. Vol. 39, pp. 257-263, April 1992.
4. Carlosena, A. and Moschytz, G., "Nullators and norators in
voltage- 10 currenl-mode lransformations," Int. J. Microelec-
tronics, (lobe published).
86
5. Stevenson, J.. "Use of reciprocity and duality to generate equiv-
alent active-RC networks," in Proc. IEEE Int. Symp. Circuit<
and Sysums, Kyoto, Japan, pp. 821-822, May 1985.
6. Guo-hua, W., Watanabe, K. and Fukui. Y., "An extended dual
transformation approach to current-mode synthesis," in Pmc.
IEEE Int. Symp. Circuits and Systems, New Orleans, LA, pp.
2294-2295, May 1990.
7. Guo-hua, W., Fukui, Y. Kubolo, K. and Watanabe, K.,
"Voltage-mode to currenl-mode transformation using the ex-
tended dual transformation," in Proc.IEEE Int. Symp. Circuits
and Systems, Singapore, pp. 1833-1834, June 1991 .
8. Davies, A., "Matrix analysis of networks containing nullators
and norators," Electronics utters, Vol . 2, pp. 48-50, Feb. 1966.
9. Davies, A., "The significance of nullators, norators and nullors
In active network theory," The Radio and Electronic Engineer,
pp. 259-267, Nov. 1967.
10. Bruton, L., RC-Activt Circuits Theory and De.<ign. Englewood
Cliffs: Prentice-Hall, 1980.
II. Liu, S., Tsao, H. and Wu, J., "Cascadable current-mode single
CCII-biquads," Electronics Leturs, Vol. 26, pp. 2005-2007,
Nov. 1990.
12. Higashimaura. M., Fukui, Y. and Ishida, M., "Synthesis of
current-mode transfer functions using a single currenl con-
veyor," Microelectronics Journal, Vol. 22, pp. 35-46, Nov.
1991.
13. Liu, S., Kuo, J. and Tsay, J., New CCII-based current-mode
biquadratic filters.'' Int. J. Electronit's, Vol. 72, pp. 243-252,
1992.
Mehul Desai was born in Bombay, India, on June 2 I, I966.
He received his B.E. degree in electronics and communica-
tions from Karnatak University, India, In 1987. In 1988,
he entered the University of Louisville to pursue graduate
studies in Electrical Engineering. While at the university, he
became a member of the Eta Kappa Nu and a student mem-
ber of the IEEE. He received his M.S. degree in Electrical
Engineering in May I 990. He entered the doctoral program
offered by the Electrical Engineering Dept. in May 1990.
During his graduate study Mr. Desai has published a dozen
journal and conference publications. His current fields of
interest include analog signal processing, neural networks,
VLSIIIC design, and instrumentation electronics.
 Current-Mode Synthesis Using Node Expansion Techniques
Peter Aronhlme received the B.E.E. degree from the Uni-
versity of Louisville in 1962 and M.S. and Ph.D. degrees
263
from the Colorado State University in 1964 and 1971 . He has
held engineering positions with Bell Laboratories in Winston-
Salem, NC, and Hughes Aircraft in Fullerton, CA, and he has
held academic positions with Tri-State University in Angola,
IN, and Illinois Institute of Technology in Chicago. In 1976
he joined the University of Louisville, where he is Professor
of Electrical Engineering and Coordinator of the Computer
Science and Engineering Ph.D. Program. In 1987 he was
a visiting professor at Colorado State University. His re-
search Interests include network theory, computer-aided cir-
cuit analysis/design/testing, modeling and instrumentation.
Dr. Aronhime is a member of Eta Kappa Nu, Sigma Xi, Phi
Ka-ppa Phi, and Omicron Delta Kappa.
87
 Analog Integrated Circuits and Signal Procetl!!ing, 6, 265-274 (1994)
C1 1994 Kluwer Academic Publlshel'll, B011ton.

Nonlinear Macromodeling with AWE*

RICHARD J, TRIHY
CatkiiCt Dulgn Systenu, 555 Rlwr Oaks l'arlwa)l Building 3, MS 3D I, San Jose, CA 95134

RONALD A. ROHRER
SRC-CMU Center for Compuur-Aided Dtngn. Dept. of Electrical and Compour Engineering, Camegle Mellon Unlwrllty. P/Jtrburglo, PA 15213-3890

Abstract. Asymptotic Waveform Evaluation (AWE) [1, 2] is an efficient and general technique for simulating
linear(ized) circuits. This paper discusses strategies for macromodeling nonlinear circuits with AWE. One approach,
multi-region AWE macromodels, represents an extension of piecewise linear models, with the addition of internal
states. Each region represents an AWE approximation to a linearization (at some bias point) of the nonlinear circuit
of interest. In addition a technique is presented for initializing the internal states when the model transitions from
one linearization to another during a transient simulation. The second approach is to treat nonlinearity as a second
order effect that is superimposed on a linear solution as a post-processing step. A relaxation algorithm that exploits
the reuseable AWE solution is employed to modify the linear solution so that it accounts for the macromodel
nonlinearity.

1. Introduction One strategy for handling this problem is to gen-

Asymptotic Waveform Evaluation (AWE) [I, 2] is an
efficient and general technique for simulating and mod-
eling large linear circuits. An AWE analysis of the lin-
ear circuit results in a dominant pole model that cap-
tures the behavior of the circuit. However, AWE does
not naturally handle nonlinear circuits; it may only be
applied to linear(ized) circuits. This means that a non-
linear circuit such as an opamp must first be linear(ized)
about some bias point before it can be subjected to an
AWE analysis. The resulting AWE macromodel is lin-
ear and contains no information about the nonlinearity
of the device.
Frequently circuits are encountered that contain
large amounts of linear circuitry combined with a lim-
ited number of nonlinear elements, e.g., a nonlinear
buffer driving a clock interconnect line. AWE effi-
ciently macromodels the linear portion of this circuit.
This paper addresses the problem of handling the non-
linear portion in a manner that is compatible with the
AWE technique.
• This work was supported by the Semiconductor Research Corpo-
ration.
erate an AWE macromodel for the linear portion of
the circuit and to employ this macromodel in a SPICE
simulation with the nonlinear elements included [3].
Another approach also partitions the circuit into linear
and nonlinear blocks and then solves the nonlinear por-
tion using waveform relaxation, with the linear portion
represented by an AWE macromodel [4].
A practical strategy for performing nonlinear simu-
lation with AWE is to employ piecewise linear (PWL)
models [5]. A PWL model for a nonlinear device con-
sists of a number of linear segments that model the
behavior of the device in different operating regions.
Hence a transient analysis of a circuit containing PWL
models proceeds with linear circuit evaluations. As
each PWL model transitions to a new operating seg-
ment, a new AWE analysis is performed for the new
linear equivalent circuit. These piecewise linear mod-
els are assumed to be memoryless. A simple PWL
model for a diode is shown in figure I.
Two strategies for handling nonlinearity are pre-
sented in this paper. The first represents an extension
ofPWL models- multi-region AWE macromodels [6).
These are similar to PWL models in that they incorpo-
rate information about the nonlinear characteristic of
the device of interest. However, they differ in that they

89
266 Trihy and Rohrer
Fig. 1. Simple piecewise linear diode model.
are not memoryless but include internal states. The
second strategy is to treat component nonlinearity as a
second order effect that is superimposed on the linear
solution as a postprocessing step [7).
2. Asymptotic Waveform Evaluation (AWE)
AWE is an efficient and general technique for
frequency- and time-domain simulation and modeling
oflarge linear(ized) circuits [1, 2). The AWE approach
is to approximate the response of the circuit with a low-
order dominant pole model that captures the behavior
of the circuit. The advantage of AWE over classical
simulation strategies is that the evaluation of this dom-
inant pole model can be, depending on circuit size,
significantly faster than both classical transient- and
frequency-domain simulations. Furthermore the re-
sultant AWE model forms a macromodel that can be
reused repeatedly, at incremental cost.
AWE employs a form of Pade approximation [8) to
evaluate the reduced order model. This approximation
is obtained by matching characteristics of the original
circuit (namely moments) to a reduced order model.
Hence the steps required in obtaining an AWE approx-
imation are first the evaluation of the circuit moments,
and then Pade approximation.
To obtain a reduced, qth, order approximation to
an nth order system, 2q circuit moments are required.
These 2q circuit moments are obtained with a single
LU factorization of the circuit matrix, followed by 2q
forward and backward substitutions. Assuming that
the cost of the LU factorization is dominant, this is
approximately equal to the cost of a single timepoint
evaluation in SPICE. Once the 2q moments have been
obtained, Pade approximation converts them to a qth
90
order model. An AWE approximation to the response
of an arbitrary node voltage in the circuit consists of
impulse responses with respect to independent sources
in the circuit and an initial condition response. It takes
the form of a convolution,
(1)
where S is the number of independent sources in the
circuit, Ni is the order of the AWE approximation to
the impulse response with respect to the ith source and
M is the order of the AWE approximation to the initial
condition response. The p and k terms are the (possi-
bly complex) poles and their corresponding residues.
This equation (I) can be evaluated inexpensively using
symbolic convolution in the s-domain.
3. Multi-Region AWE Macromodels
Analogous to PWL models, a nonlinear AWE macro-
model needs to incorporate information from multiple
linearizations. These multi-region AWE macromod-
els consist of a number of dominant pole approxima-
tions, corresponding to a number of different linearized
equivalent circuits at the different bias points of the
nonlinear element of interest [6).
Hence, to construct a multi-region AWE macro-
model, the component of interest is biased at a number
of different operating points. At each of these oper-
ating points the circuit is linearized and a dominant
pole AWE macromodel is evaluated. Each of these
linearizations represents a new segment in the model.
Consider the CMOS inverter characteristic curve in
figure 2. If the corresponding circuit is biased at three
operating points, and linearized at these points, then an
AWE dominant pole macromodel can be constructed
for each case. For the example of figure 2, the de gains
of these three macromodels are superimposed on its
nonlinear characteristic. Clearly the de characteristic
of the multiregion AWE macromodel is similar to what
would be expected from a PWL macromodel. How-
ever, it differs from it by including internal states, the
effect of which can only be seen in a transient simula-
tion and not in the de plot of figure 2.
Similar to memoryless PWL models, the AWE
macromodels must transition from model segment
to model segment as the transient analysis proceeds.
 Nonlinear Macromodeling with AWE 267

Vout

Yin

Fig. 2. CMOS inverter DC transfer characterlsllc.

However, because the AWE macromodels have mem- response in the ith region is known and has two com-
ory in the form of internal state variables, these internal ponents, an initial condition response and a forced re-
states must be initialized at each transition. (This prob- sponse,
lem does not arise for the PWL models since, in this
case, there is a one-to-one correspondence betv.-een the
state variables in the different equivalent circuits.) The
y;(t) = t a
kaeP•t +( t
a
kaep.t) * V.n(t) (2)

internal states result from AWE approximations to lin-

earized circuits and as such need not have any physical For the jth region the response has the form,
significance. Furthermore there is no guarantee that
there will be equal numbers of them in the different wW=~W+0W= )
model segments. This greatly complicates the task of (
their initialization. ~ xb(tk)eP•(t-t•) + ( ~ kbeP•(t-t•)) * V.n(t)
(3)
3.1. Suzte Variable Initialization
In (3) the forced response term is known. The initial
In order to choose initial values for a region's state condition response term must be obtained by solving
variables when the model transitions from one region to for the internal states, Xb( tk)· Matching the derivatives
another, continuity in the output variables of the macro- of (2) and (3) at time tk, and rearranging to solve for
model (and their derivatives) is sought. These output the initial conditions gives (4).
variables are expressed in terms of a forced solution
and an initial condition solution. As many derivatives
as necessary are matched, so as to initialize the state y(t)
variable initial conditions of the new region.
Consider a multi-region single-input single-output +
AWE macromodel where a transition from the ith re-
gion to the jth region occurs at time tk. Assume the
Vin(t)
ith and jth regions are modeled with nth and mth or-
der dominant pole approximations, respectively. At
time tk the initial conditions of them state variables in
the jth region must be found. The macromodel AWE Fig. 3. SISO AWB macromodel.

91
268 Trihy and Rohrer

==-
u.;.1::····•oo•
p.,. ~ .11
I I I
I I

\
Jj \I

Fig. 4. HSPICB and multi region macromodel simulation results.

internal states have been evaluated the transient simu·

1 1 1 lation continues until the next region change.
As an exexample a CMOS inverter was biased at
Pt P2 Pm five bias levels, using HSPICE [9] and the small sig-
nal model for each region extracted. Then AWE was
m-1 m-1 p:;:-1 employed to obtain a forward transfer function for
P1 P2 each small signal model. Hence the macromodel con-
sisted of five regions. Figure 4 compares the results
Yi(t) - Y{ (t)lt=t• of HSPICE and the macromodel for a transient simu-
lation. As can be seen they are very close.
~(Yi(t)- y{ (t))'t=t• The models match closely for the rise and fall por-
tions of the waveforms. However, difficulty arises with
(4)
the overshoot component of the waveform. When there
is a fast signal transition at the input to the inverter,
it couples through the overlap capacitors of the MOS
transistors to cause overshoot at the output. This output
overshoot is clamped at around 0.6V by the pnjunction
The matrix on the left-hand side of (4) is the observ- between drain and bulk of the MOS devices. The diode
ability matrix for the jth region AWE model. This characteristic is very nonlinear and many linearizations
Vandermonde matrix has already been inverted in the are required to capture it accurately. In the example of
process of solving for the AWE approximation and figure 4, one linearization was chosen to match the de-
so is guaranteed to be nonsingular [2]. Once these lay of the overshoot as closely as possible.

92

4. Nonlinear Correction via Relaxation
An alternative strategy is to treat the nonlinearity of the
devices as a second order effect that is superimposed
on the linear solution as a postprocessing step [7]. This
means that nonlinear elements are first represented as
linear circuits. The linear solution is obtained, and then
the linear solution is augmented to account for the non-
linearities. The linearizations are augmented with in-
dependent sources, the waveforms of which are solved
with a relaxation algorithm so that their combined IV
characteristic matches that of the original nonlinearity.
The advantage of this approach is that it does not re-
quire any additional matrix LU factorizations beyond
those needed for the basic linear circuit. Also if the
nonlinearity of the device has negligible effect, the lin-
ear solution is adequate.
Consider the nonlinear equation
Cv(t) + f(v(t)) = o (5)
The nonlinear element is represented with a linearized
equivalent, augmented with an independent source,
f(v(t)) = gv(t) + J(t) (6)
so that (5) becomes
Cv(t) + gv(t) + I(t) = o (7)
Now the task of solving the nonlinear circuit (5) has
been transformed to the task of solving for the wave-
form J(t) under the constraints imposed by (6) and
(7). The linear circuit described by (7) can be solved
directly using AWE where the expressions for the state
variables in the circuit (1) are augmented with addi-
tional impulse response terms with respect to I (t). Ini-
tially the independent source is assumed to have a zero
contribution to the circuit. The final waveform takes
the form shown in figure 5. This augmenting current
t
Fig. 5. Waveform of augmenting source.
Nonlinear Macromodeling with AWE 269
is evaluated at discrete timepoints on an element by
element basis using fixed point iteration.
Given an initial guess I 0(tk) to the augmenting cur-
rent at time tk the corresponding voltage v 0 (tk) is ob-
tained from the solution of (7), namely (l). Next the
error in the solution is calculated from (6) as
and the augmenting current is updated for the next iter-
ation, J 1(tk) = I 0 (tk) + g 0, So at each iteration, for
each nonlinear element, an augmenting current Ji ( t) is
chosen and a corresponding errorE i is calculated from
(8). This error is then used to select the new augmenting
current guess. However, the relaxation to convergence
can be slow. In order to speed up this convergence
a spline is fit through some of the (Ii(t),si) points,
as shown in figure 6, and a one-dimensional Newton-
Raphson iteration used to solve for the currentthat gives
zero error. This iterative process is continued until the
error from (8) is less than some specified tolerance.
This greatly speeds up the convergence process.
The final waveform of the augmenting source con-
sists of a series of ramps. The response of the state
variables in the circuit to the independent source J(t)
are obtained from (l) via symbolic convolution. The
costs of these convolutions are kept minimal by careful
evaluation of (l) [3].
4.1. Load Line Interpretation
An alternative view of this approach for handling non-
linearity can be seen by considering the graphical solu-
tion of a de circuit. Consider the simple diode circuit of
£
Zero error
/ I
Fig. 6. Spline.
93
270 Trihy and Rohrer

very efficiently, this technique complements the basic

AWE approach without incurring a steep compromise
in its efficiency.

4.2. Convergence of Relaxation

Fig. 7. Nonlinear circuit.
Consider a nonlinear circuit described by the equation

figure 7 and the graphical representation of the problem H(x) = Mx + b + F(x) = 0 (9)
in figure 8.
In a circuit simulator such as SPICE, Newton- where M is a matrix contributed to by linear elements,
Raphson iterations are employed to converge to the b is a vector of independent sources, F(x) is a matrix
de solution. This involves repeated relinearizations of contributed to by nonlinear elements, and x is a vector
the nonlinearity. An initial guess is assumed for the of solution variables. Employing a single linearization
answer and the nonlinearity is linearized at this point. to solve this equation (9) means approximating F(x)
This corresponds to a linearized resistance of Reqi in as
figure 8. The resultant linearized circuit is solved for
a new solution estimate and the diode is relinearized (10)
at this new solution estimate (Req2)· This process is
continued until convergence. where K is a matrix of constants; and approximating
However, the new strategy allows the use of a single H(x) as
linearization of the nonlinear device, thereby avoiding
the repeated linearizations and circuit changes. The (11)
solution process for the circuit of figure 7 using this
approach is shown in figure 9. The problem with this where A = M + K, a matrix of constants representing
approach is that convergence is slow compared with the linearized circuit. Hence the iteration process may
the SPICE approach. However, as described above, be written
Newton-Raphson iterations can be employed to speed
x; - A - i H(x;)
up the convergence without performing any relineariza- (12)
tions. Furthermore, since AWE solves the linear circuit x 1 - A- 1 [Mx; + b + F(x;)]
For convergence of ( 12) it is required that

p(I- A- 1 H'(x*)) < 1 (13)

where p denotes spectral radius (or maximum eigen-

value), and x• denotes the solution of (9) [10]. This
Initial means that M +K ~ M + F'(x*) is required for con-
Guess vergence, or the linearization K chosen for the nonlin-
earity should be "close" in value to F' (x*). This result
indicates that the relaxation technique is only suitable
v for handling mild nonlinearities.

4.3. Transient Dynamics

Consider the nonlinear differential equation

Fig. 8. Newton-Raphson iterations. Cv(t) + f(v(t)) = o (14)

94
 Nonlinear Macromodeling with AWE 271

case G is a constant that does not change from iteration

to iteration. Hence (if convergence is achieved) there
should be no difference between the two approaches.
The point to be noted from this analysis is that while
a single linearization of the nonlinearity is employed,
Initial the accuracy of the simulation in both the steady state
Guess and the transient portions of the waveform is unaf-
fected.

v
4.4. Examples

This relaxation approach is implemented in a switched

capacitor circuit simulator AWEswit [7]. The nonlin-
ear on-resistance of the switches is represented with
a linear resistor and its nonlinear characteristic is su-
Fig. 9. AWEswit iterations. perimposed using the relaxation technique described
above. The Ron associated with the switch model is
Integrating over a timestep !::J.t gives
augmented with a parallel current source, as in fig-
(t+At) i(t+At) ure 10. The Shichman-Hodges MOSFET model has
i , Cv(t)dt + 1
f(v(t))dt = o (15) been included in AWEswit.

Next, assuming a constant derivative v(t) over the Io

interval !::J.t, then without loss in accuracy (15) may be
rewritten as
Cv(t + !::J.t) - Cv(t)
(16)
+ f(v(t + !::J.t)) + f(v(t)) !::J.t = 0
2 Ron
where a trapezoidal approximation has been applied to Fig. 10. Nonlinear model.
the second integral. To illustrate the effect of MOSFET nonlinearity,
In the process of performing a transient simulation, a switched capacitor amplifier circuit was simulated
this nonlinear equation (16) must be solved for each in AWEswit using NMOS transistors only and us-
!::J.t. Rewriting (16) in the form ing the Shichman-Hodges model. The superimposed
HSPICE and AWEswit waveforms are shown in fig-
vi+ 1 (t + !::J.t) = v(t)- ~~(f(v'(t + !::J.t)) + f(v(t)) ure 11. The HSPICE simulation required 240s of cpu
time on a DECstation 5000, compared with 45s for
(17)
AWEswit. As can be seen, the waveforms are very
it is apparent that an iterative strategy can be employed close.
in its solution - the i + lth guess is calculated from Slew rate limiting in the opamp can cause distor-
the ith guess. The difference between this approach tion in the switched capacitor circuit. It is modeled in
and SPICE lies in the manner in which f(v•(t+ !::J.t))is AWEswit with the aid of a nonlinear resistor. This non-
updated in each iteration. linearity can be handled using the relaxation scheme
presented above. Again, the nonlinear resistance is rep-
f(v'(t + l::J.t)) = f(v(t)) + G'(v'(t + !::J.t)- v(t))) resented as a linear resistance augmented with a parallel
(18) current source, as in figure 10.
To illustrate the effects of opamp slew rate limiting,
In the case of SPICE, f(vi(t + !::J.t)) is updated from a simple switched capacitor integrator circuit was sim-
(18) where Gi = f'(v'(t + !::J.t)). However, in this ulated in AWEswit. 1\vo simulations were performed,

95
272 Trihy and Rohrer

" "
2.00

l.RO
f1 71
uo
1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.00
-0.20

-0.40

-0.60

-1).80

-1.00
-1.20
-1.40

0.00 1.00 2.00 3.00 •.oo

Fig. I I. HSPICE and AWE.<wit simulation results for amplifier.

1.60 Linear
,..r ,..r ,..... s"iewiiii-··············
1.40

1.20
..

1.00
r-
r··
,.:
i If
!

0.80
i l i
i i I!
0.60 ~ J: r
A- J-
0.40 ~ I i
i i
I

0.20
I l

0.00
x x to·6
0.00 20.00 40.00
Fig. 12. Slew rate limiting in switched capacitor integrator.

96

one with and one without opamp slewing. The simu-
lation results are shown in figure 12.
5. Conclusion
Strategies for handling nonlinearity with Asymptotic
Waveform Evaluation have been presented. Piecewise
linear (PWL) models are general and flexible and allow
the simulation accuracy to be adjusted by changing the
number of segments in the PWL models. However, ev-
ery time a model changes segment a new linear circuit
results. The resulting large number of linear circuits
compromises the simulator's efficiency.
The multi-region AWE macromodels allow the cir-
cuit components to be modeled at a higher level of
abstraction. The incorporation of internal states per-
mits greater flexibility in the modeling process. Sim-
ilar to the PWL models, additional macromodel seg-
ments increase the number of linear circuits that need
to be solved; however, the greater model abstraction
allowed reduces this overhead. Furthermore both of
these techniques can have accuracy problems at steady
state. PWL models tend to give accurate results in the
transient portion of the waveform, but the PWL model's
IV characteristic does not match the true IV character-
istic exactly. This can manifest itself in a steady state
error.
The steady state error problem is overcome by using
the relaxation approach, since the true (SPICE) non-
linear model can be employed. Furthermore the relax-
ation technique fits elegantly with AWE and does not
require any additional linear circuits. It does however
have the limitation that it can have convergence prob-
lems if the nonlinearity is too severe. Nevertheless, it
has been found to work well for the nonlinearity associ-
ated with the mosfet switches in the switched capacitor
circuits. This suggests that employing the relaxation
approach and the multi-region AWE macromodels to-
gether would result in better accuracy at steady state
and improve convergence performance.
References
I. Huang. X.. Raghavan, V. and Rohrer, R. A., "AWEism: A pro-
gram for the efficient analysis of linear(ized) circuits," Proc. uf
the IEEE Int. Conf. on Computer Aided Design, pp. 534-537.
November 1990.
2. Pillage, L. T. and Rohrer, R. A., "Asymptotic waveform eval-
uation for timing analysis:' IEEE Transaclions on Compuler·
Aided Design, Vol. 9. pp. 352-366, Aprtl1990.
Nonlinear Macromodeling with AWE 273
3. Raghavan, V., An Integrated Methodology for E/utronlc Sys·
tem Interconnect AMiysis, Ph.D. dissenation, Carnegie Mellon
University, Pittsburgh, PA, 1992.
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analysis of nonlinear ciruits,"lEEE Transactions on Computer-
Aided Design, pp. 1032-1043, August 1992.
5. Dllcmen, C. T., Alaybcyi, M. M., Topcu, S., Atalar, A., Sezer,
E., Tan, M. A. and Rohrer, R. A., "Piecewise linear symptotic
waveform evaluation for transient simulation of electronic cir·
cuils;• Proc. of the IEEE Int. Symp. on Circuits and Systems,
pp. 854-857, June 1991.
6. Trihy, R. J. and Rohrer, R. A., "AWE macromodels for non-
linear circuils," Midwest Symposium on Circuits and Systems,
1993.
7. Trihy, R. J. and Rohrer, R. A., "Simulating sigma-delta modu·
lators in AWEswit," Proc. of the IEEE Int. Conf on Computer
Aided Design, pp. i41 - 144, November, 1993.
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Richard J, Trlhy was born in Cork, Ireland, In 1966. He
received the B.E. and M.Eng.Sc. degrees In electrical engi-
neering from the National University of Ireland at University
College Cork (UCC) in 1988 and 1990, respectively, and the
Ph.D. degree from Carnegie Mellon University, Pittburgh, in
1993. From 1988 to 1990 he was at the National Micro-
electronics Research Centre, UCC. He is currently a Senior
Member of the Technical Staff at Cadence Design Systems,
San Jose, California.
Ronald A. Rohrer received the B.S.E.E. degree from MIT,
Cambridge, MA, in 1960, and the M.S.E.E. and Ph.D. de-
grees from the University of California, Berkeley, in 1961 and
97
274 Trihy and Rohrer
1963, respectively. His 1960s pioneering work in electronic
design automation formed the basis for several advances in
circuit simulation, sensitivity, and optimization. He is the
founding editor ofthe/EEE Transactions on Computer-Aided
Design and the author and coauthor of three textbooks and
numerous technical papers. He is currently the Wilkoff Uni-
versity Professor of Electrical and Computer Engineering at
98
Carnegie Mellon University, Pittsburgh, PA. A Fellow of the
IEEE since 1980, Dr. Rohrer was President of the Circuits
and Systems Society in 1987, and received the CAS Society
Award in 1990. Among other honors, in 1989 he was elected
to the US National Academy of Engineering, and awarded
the IEEE Education Medal in 1993.
 ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
An International Journal

Special Issue on

Modeling and Simulation of Mixed Analog-Digital Systems

With the newer generation of integrated circuits incorporating larger analog portions, verification of mi
analog-digital systems is essential to ensure the performance of these systems at critical specifications. '
digital domain being fairly well developed, most of the bottlenecks are posed by the analog sections and
analog-digital interface. Thus, modeling the analog sections and the mixed-mode interface at higher-Ie·
provides an efficient means for analysis of such systems. A key element in this development is behavi
modeling and simulation applied to various stages of the design process, from synthesis to testability
yield estimation.

The goals of this special issue are to report on recent developments and advances in the area of mode
and simulation of analog and mixed analog-digital circuits and systems, and provide a forum for addres:
critical issues and highlighting potential new problem areas.
Topics of interest for this special issue include, but are not limited to:

-- Behavioral modeling --Macromodeling analog-digital systems

-- Model development and parameter extraction --Model optimization
-- Modeling for testability and yield analysis -- Mixed-signal simulation algorithms
-- Circuit and device modeling issues for mixed systems
-- Experiences with design and simulation of large mixed-mode
industrial circuits that highlight simulation bottlenecks
-- Description languages with mixed-mode interfaces

To be considered for this Special Issue of Analog Integrated Circuits and Signal Processing, prospec
authors should submit six copies of their complete manuscript by March 1, 1995 to one of the two G
Editors:

Dr. Brian A.A. Antao Dr. Kenneth S. Kundert

Coordinated Science Laboratory Cadence Design Systems
University of Illinois, Urbana-Champaign 555 River Oaks Pkwy., MS 3B1
1308 West Main Street San Jose, CA 95134, USA
Urbana, IL 61801, USA Phone: (408)-428-5634
Phone: (217)-244-0041 Fax: (408)-944-7265
Fax: (217)-244-1946 Email: kundert@cadence.com
Email: brian@uivlsi.csl.uiuc.edu

Instructions for Authors are regularly published in the Journal and may also be obtained from the Guest Editors or by contac
Karen S. Cullen, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, MA 02061, or by Tel: (617) 871-6
Fax: (617) 871-6528 or Email: <Karen@world.std.com>. Analog Integrated Circuits and Signal Processing is an archival,
reviewed journal publishing research papers on design and applications of analog integrated circuits and signal processing cw
and systems.
 Analog Interfaces
for Digital Signal
Processing
Systems
by Frank Op 't Eynde, Willy Sansen
New
THE KLUWER INTERNATIONAL SERIES IN ENGINEERING
AND COMPUTER SCIENCE 225
Publication
The ever-increasing complexity and speed of digital
circuits has considerably modified the architecture of
integrated signal processing systems, resulting in the
analog parts of the system being pushed towards the
boundaries of the signal processing chain. The specifi-
cation requirements of these analog interface circuits
are becoming very strict, in order to fully benefit from
the speed performance and the high dynamic range
offered by digital circuits.
Analog Interfaces for Digital Signal Processing Sys-
tems analyzes the analog interfaces of a digital signal
processing chain, and presents techniques to obtain
maximum performance for various technologies and
applications. The book serves as a general introduc-
tion and as a reference work in the fields of low-distor-
tion analog circuits and oversampled data converters.
It can also be used as the text for advanced courses
covering these topics.

Contents
Foreword. Preface. 1. The Power Consumption of
KLUWER
CMOS Wideband Amplifiers. 2. Low-Distortion CMOS
ACADEMIC
Amplifier Design. 3. Oversampled A-to-D and D-to-A PUBLISHERS
Converters. 4. Higher-Order Sigma-Delta A-to-D Con-
verters. 5. The Practical Implementation of Sigma-
Delta D-to-A Converters. Index.

1993, 264 pp. ISBN 0-7923-9348-1

Hardbound $85.00/Dfl.175.00/£63.50
PO. Box 322, 3300 AH Dordrecht, The Netherlands
PO. Box 358, Accord Station, Hingham, MA 02018·0358, U.S.A.