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TCM2.0E: Colour TV Chassis
TCM2.0E: Colour TV Chassis
TCM2.0E
LA
MG8 ME8
H_17740_000.eps
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©
Copyright 2009 Koninklijke Philips Electronics N.V.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.
Published by JY 0963 BU TV Consumer Care Printed in the Netherlands Subject to modification EN 3122 785 17953
EN 2 1. TCM2.0E LA Technical Specifications, Connections, and Chassis Overview
1.1.2 Sound
COMMON INTERFACE
R
CVBS S-VIDEO
AUDIO
HDMI 1 HDMI 2 VGA PC EXT 3 EXT 1
Y Pb Pr
VGA
EXT 2
R L
AUDIO TV (75Ω) SPDIF
I_17950_001.eps
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Note: The following connector colour abbreviations are used 1 - D2+ Data channel j
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= 2 - Shield Gnd H
Grey, Rd= Red, Wh= White, and Ye= Yellow. 3 - D2- Data channel j
4 - D1+ Data channel j
1.2.1 Side connections 5 - Shield Gnd H
6 - D1- Data channel j
7 - D0+ Data channel j
EXT 2: Cinch: Video CVBS - In, Audio - In
Ye - Video CVBS 1 VPP / 75 ohm jq 8 - Shield Gnd H
9 - D0- Data channel j
Wh - Audio L 0.5 VRMS / 10 kohm jq
10 - CLK+ Data channel j
Rd - Audio R 0.5 VRMS / 10 kohm jq
11 - Shield Gnd H
12 - CLK- Data channel j
EXT 2: S-Video (Hosiden): Video Y/C - In
13 - n.c.
1 - Ground Y Gnd H
14 - n.c.
2 - Ground C Gnd H 15 - DDC_SCL DDC clock j
3 - Video Y 1 VPP / 75 ohm j
16 - DDC_SDA DDC data jk
4 - Video C 0.3 VPPP / 75 ohm j
17 - Ground Gnd H
18 - +5V j
EXT 2: Mini Jack: Audio Head phone - Out 19 - HPD Hot Plug Detect j
Bk - Head phone 32 - 600 ohm / 10 mW ot 20 - Ground Gnd H
EXT 2: Common Interface VGA PC: Video RGB - In and Service UART
68p - See diagram B05 jk 1 5
10
6
1.2.2 Rear Connections 11 15
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USB2.0
Figure 1-4 VGA Connector
INVERTER PANEL
(OPTONAL) I
IR LED PANEL J
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4. Mechanical Instructions
Index of this chapter: Notes:
4.1 Cable Dressing • Figures below can deviate slightly from the actual situation,
4.2 Service Positions due to the different set executions.
4.3 Assy/Panel Removal • Follow the disassemble instructions in described order.
4.4 Set Re-assembly They apply mostly to the 26" model unless otherwise
specified, but the described method is comparable for the
other screen sizes.
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4.2 Service Positions The foam bars (order code 3122 785 90580 for two pieces) can
be used for all types and sizes of Flat TVs. See figure “Foam
bars” for details. Sets with a display of 42” and larger, require
For easy servicing of this set, there are a few possibilities
four foam bars [1]. Ensure that the foam bars are always
created:
• The buffers from the packaging. supporting the cabinet and never only the display.
Caution: Failure to follow these guidelines can seriously
• Foam bars (created for Service).
damage the display!
By laying the TV face down on the (ESD protective) foam bars,
4.2.1 Foam Bars a stable situation is created to perform measurements and
alignments. By placing a mirror under the TV, you can monitor
the screen.
1
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4.3.1 Stand
1 1
1 I_17951_010.eps
1 060808
Side
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2 2 2 2
4
1 1
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2 2
1 4
4
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3
Figure 4-9 Keyboard control board 1
2 2
2
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Notes:
1 • While re-assembling, make sure that all cables are placed
and connected in their original position. See figure “Cable
dressing”.
2 2 • Pay special attention not to damage the EMC foams at the
SB shields. Make sure, that EMC foams are put correctly
on their places.
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1 1
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The Service Mode feature is split into different parts: Figure 5-2 SAM menu, Clear
• Service Alignment Mode (SAM).
• Service Default Mode (SDM).
• Customer Service Mode (CSM).
SDM and SAM offer features, which can be used by the Service
engineer to repair/align a TV set. Some features are:
• Activates the blinking LED procedure for error identification
when no picture is available (SDM).
• Make alignments (e.g. white tone), (de)select options,
enter options codes, reset the error buffer (SAM).
• Display information (“SAM” indication in upper right corner
of screen, error buffer, software version, options and option
codes, sub menus).
How to Enter
To enter SAM, use the following method:
• Press on the remote control the code “062596” directly
followed by the “INFO” key.
After entering SAM, the following screen is visible, the values I_17950_018.eps
can be adjusted according to the requested (see Chapter 8). 050808
I_17950_014.eps
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Contents of CSM
I_17950_020.eps
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How to EXIT
Put set in <stand-by> by using the remote control. I_17950_044.eps
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5.2.2 Service Default Mode (SDM) Figure 5-8 CSM Menu -1-
Purpose
• To create a pre-defined setting, to get the same
measurements as given in this manual.
• To override SW protections.
• To start the blinking LED procedure.
How to enter
To enter SAM, use the following method:
• Press on the remote control the code “062596” directly
followed by the “MENU” key.
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Menu Explanation
1. Model Number. Type number and region.
2. Production Serial Number. Product serial no.
3. SW Version. Software cluster and version is displayed (TC
= TCL, M2 = MTK2, E = Europe, 0.49 = software version).
4. Codes. Error buffer contents.
5. SSB. SSB serial number.
6. DISPLAY. Display type.
7. NVM Version. NVM version.
I_17950_043.eps
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HDMI connected. Else blank.
Figure 5-7 SDM menu 9. Digital Signal Quality. Quality of antenna signal in %.
10. Audio System. Audio system (Mono/Stereo/NICAM)
From top to bottom, it gives the following information: 11. n.a.
• Operation hours 12. Video Format. Video format.
• Software version 13. Stand-by μP SW ID. SW version Stand-by
• Error buffer display. microprocessor.
The software is capable of identifying different kinds of errors. The error code buffer contains all errors detected since the last
Because it is possible that more than one error can occur over time the buffer was erased. The buffer is written from left to
time, an error buffer is available which is capable of storing the right. When an error occurs that is not yet in the error code
last five errors that occurred. This is useful if the OSD is not buffer, it is displayed at the left side and all other errors shift one
working properly. position to the right.
Errors can also be displayed by the blinking LED procedure. Basically there are six kind of errors:
The method is to repeatedly let the front LED pulse with as
Code Description Detection method Type
many pulses as the error code number, followed by a period of
1.5 seconds in which the LED is “off”. Then this sequence is 0 no error
repeated. 3 μP Control I2C-bus Error log +
Any RC command terminates the sequence. Error code LED blinking in SDM
blinking is in white colour. 4 General I2C I2C-bus Protection +
bus Error spontaneous
Example: the contents of the error buffer is “013 007 000 000 7 Tuner I2C-bus Error log +
000”. blinking in SDM
After entering SDM, the following occurs: 8 Demodulator I2C-bus Error log +
• 1 long blink of 5 seconds to start the sequence blinking in SDM
• 1 medium blink of 3 seconds and then 3 short blinks
10 MT8295 I2C-bus Error log +
followed by a pause of 1.5 seconds
blinking in SDM
• 7 short blinks followed by a pause of 1.5 seconds
• 1 long blink of 1.5 seconds to finish the sequence. 13 HDMI switch I2C-bus Error log +
The sequence starts again with 12 short blinks. blinking in SDM
For P804 ,Pin 8~11 YES For Q800,pin5~6 YES Is YES Check
is 12V& Pin2~3 of of is 5V & pin7~8 U800~U808&U2 LQFP jointing of
is 5v is12V , OK? 01 OK? U203
, OK?
NO NO NO YES
Check Pin 10 Of
Check PSU U810. is it 3.3v? Replace the bad
Check
one of
X200,C221,C222,C
u800~u808&U201
23,L214 & IIC Bus
YES
Check jointing of
U204,R271~R288,R
248~R260.
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Figure 5-10 No picture, no sound, no backlight, fuse broken (19", 20", and 22" sets)
Service Modes, Error Codes, and Fault Finding TCM2.0E LA 5. EN 15
NO NO NO YES
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Check the
No Check the Yes
output voltage Replace Q203
of Q203. is it voltage of
OK? C of Q204.
Yes
Check Yes
waveform of
L200~L209 is check the
OK? cable to panel
No
Is No check Pin
Pin220,229,238 221~228&Pin
of U203 shorted 230~242 of U203
to earth?
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No
Check the voltage of
Check Q800
Pin 3,13 of u600,is it 12v?
Yes
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No colour
No YES YES
Reset Check
To Tuner Input Check E2PROM
Local system cable & antenna U205
YES
Fine Frequency
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5.5.1 ComPair
Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips
Consumer Electronics products. and offers the following:
1. ComPair helps you to quickly get an understanding on how
to repair the chassis in a short and effective way.
2. ComPair allows very detailed diagnostics and is therefore
capable of accurately indicating problem areas. You do not
have to know anything about I2C or UART commands
yourself, because ComPair takes care of this.
3. ComPair speeds up the repair time since it can
automatically communicate with the chassis (when the uP
is working) and all repair information is directly available.
4. ComPair features TV software upgrade possibilities.
Specifications
ComPair consists of a Windows based fault finding program
and an interface box between PC and the (defective) product.
The (new) ComPair II interface box is connected to the PC via
an USB cable. For the TV chassis, the ComPair interface box
and the TV communicate via a bi-directional cable via the
service connector(s).
How to Connect
This is described in the ComPair chassis fault finding database.
TO TV
TO TO TO
UART SERVICE I2C SERVICE UART SERVICE
CONNECTOR CONNECTOR CONNECTOR
ComPair II
Multi
RC in function
RC out
PC
Optional power
HDMI 5V DC
I2C only
E_06532_036.eps
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How to Order
ComPair II order codes:
• ComPair II interface: 312278591020.
• For latest software see Philips Service website.
• ComPair UART interface cable: 312278591070.
YES NO
layout 1 Plug-in the USB
stick
Detect USB
Kindly remove the USB stick and ‘break-in’ and
restart the set. check autorun file
layout 3
Valid auto-run N
file?
Y
Software update failed!
Would you like to try again?
Is USB sw N Is USB sw
N
YES NO version > set version =< set End
sw? sw?
layout 4
Y Y
Display USB Display USB
sw newer than sw equal/older
the TV sw. than TV sw.
Prompt user to Prompt user to
confirm confirm
See layout 1 See layout 2
N
Proceed?
Prompt user to
remove USB Y N Prompt user to
Successful?
and restart the try again?
set
End
N Y
Retry?
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6. Block Diagrams, Test Point Overview, and Waveforms Wiring Diagram Of Connector 26"
40-1PL37C-PWF1XG
11 GND
P800 CN1 +24V 2
MAIN POWER
13 GND
BL ON/OFF INVERTER_PWR 12V +24V 3
INVERTER
1 1 15 GND
NU/SELECT INVERTER_PWR 12V +24V 4
2 2 17 GND
DIMMING INVERT-SW +24V 5
3 3 19 +24V
6
1
GND
GND DIMMING 21 +24V
4 4 1
GND 7
GND GND 23 +24V
5 5 GND 8
INVERTER_PWR 12V GND 25
BOARD
+24V
6 6 GND 9
INVERTER_PWR 12V 27 +24V
7 GND 10
40-LDMK35-MAE2XG
P800 VDIM 11
40-LDMK35-MAE2XG
BL ON/OFF VBLON 12
MAIN BOARD
1
NU/SELECT
MAIN BOARD
2 PDIM 13
DIMMING
3 GND 14
GND
4
GND
5
P1 INVERTER_PWR 12V
IR BOARD
40-L20PFL-IRC1XG
6 P1
IR BOARD
40-L20PFL-IRC1XG
ON-LCD INVERTER_PWR 12V
1 7
P805 SB-LCD
ON-LCD
1
2 SB-LCD
2
5VSB GND
3
P805 GND
1 DIIR 3
IR 1 5VSB IR
2 4 4
GND 5V-SB
5 2 DIIR 5V-SB
5
3
STANDBY 3 GND
4
POWER_ON 4 STANDBY
5 P601 P601
KEY BOARD
40-L19PFL-KEC1XG
KEY BOARD
40-L19PFL-KEC1XG
KEY 5 POWER_ON
6 GND KEY 6 KEY
KEY
1
1
7 5VSB GND 7 GND
GND
2
2
8 8 5VSB 5VSB-OUT 3
5V_KEY 5VSB-OUT 3
9 9 5V_KEY 5VSB-IN 4
5VSB-IN 4
P4
40-1PL37C-PWF1XG
+12V 1
P804
MAIN POWER
+12V 2
P804 PS1 NU
POWER BOARD
40-PWL20C-PWI1XG
NU 1 GND 3
5V-PW
1 5V-PW
1 2 GND 4
5V-PW 5V-PW
2 5V-PW
2 3 +12V 5
5V-PW GND
3 GND
3 4 +12V 6
GND GND
4 GND 5 GND 7
GND 4 GND
5 GND 6 +12V 8
GND 5 GND
6 GND 7 12V-IN GND 9
GND 6 GND 10
7 12V-IN 8
12V-IN 7 12V-IN
12V-IN 9 P5
40-PWL01B-STE1XG
8 8
STB POWER
12V-IN
12V-IN 12V-IN 9 10 +5V 1
9 12V-IN
12V-IN 12V-IN 10 11 GND 2
10
12V-IN ON/OFF 3
11
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Block Diagrams, Test Point Overview, and Waveforms TCM2.0E LA 6. 20
MT5335
V0.1 DC-DC +12V POWER
12V to 5V RT8110 SUPPLY CONNECTOR
+5V/
ON OFF
VCC Standby+5v
SIF
PARALLEL TS
LVDS
LV TTL
To
FLASH DS TTL
32Mbit 386
DDR
32Mb 170 SCT_R_IN
62 OSCL1 63OSDA1 LVDS
x16 171 SCT_L_IN
73 HDMI_5V
120 Y_IN 116 SCT_R
79 RX0_CB 80 RX0_C
121 Pb_IN 108 SCT_G Broken line is option for TTL
81 RX0_0B 82 RXO_0
104 R 123 Pr_IN 114 SCT_B 129 CVBS 185 interface panel!
83 RX0_1B 84RXO_1
98 B 173 YPbPr_L 149 SCT_FS 172 R_IN HP_R_OUT
85 RX0_2B 86 RX0_2
102 G 174 YPbPr_R 107 SCT_FB 201 173 L_IN 186 PRE AUDIO
205 DDC_SCL
96 VSYNC 176 VGA_R 187 SCT_R_OUT SPDIF 126 SY HP_L_OUT R/L AMP
204 DDC_SDA R
97 HSYNC 177 VGA_L 189 SCT_L_OUT _OUT 125 SC
CEC
COMMAND
AUDIO
HDMI SWITCH AMP
L
SI8195 O/P
EDID
EDID EDID
HEAD PHONE
HDMI1 HDM2 VGA YPbPr SCART SPDIF AV
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Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 21
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Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 22
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Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 23
I_17930_027.eps
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Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 24
I_17930_028.eps
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Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 25
I_17930_029.eps
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Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 26
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E_06532_012.eps
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Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 27
MT5133-GPIO-AD
L108 AV_5V
30R
TUNER_5V
0.1U
0.1U
C137
C138
VCC
E
R145
4LVC1G66GV
12K
ATV-IF-AGC
ANALOG_IF
NC/RFAGC
NC/GND1
NC/GND2
XTALOUT
D110
ANTPWR
IFOUT2
IFOUT1
U101
F LL4148 F
GND
IFAGC
GND1
SDA
NC1
SCL
NC
Y
TU
AS
Z
B1
6V3
C2
47U
0.1U
R124
3
1
11
12
13
14
15
16
17
18
19
20
21
C139
100R
FAT_IN-
5V-OUT
0R
R132
R148
100R
NC
FAT_IN+ R149
NC\0R
R139
6K8 R140 R141
RF-AGC 6K8
0.01U
22K R121
C119
D103 22K
BA982 12K
E R146 E
R135 4K7 C R137
IF_AGC 220K
B
ATV-IF-AGC
R127 100R E
0.01U
TUNER_SDA0_5V Q102
C109
R100
BC847C 680K
X100
R123 0R
100R
0.01U
R126
4M
C111
1500P
C115
C3
TUNER_SCL0_5V
0.1U
R114
R147
100K
R101
330R
22K
X102
C124
C125
IN/GND
D101
OUT1
OUT2
22P
GND
22P
1U
BA982
IN
C112
0.47U
C100
20P
5V-OUT
C114
L103
0.22U
120R
C110
1 2 3 4 5 L102
TUNER_5V 120R
C123
C102
100U
D102
6V3
0.01U
C122
D D
0.1U
TUNER_5V TUNER_5V
C101
100U
BC847C
6V3
0.01U
24
23
22
21
20
19
18
17
16
15
14
13
C
C113
BA982 Q100
R99 NC L104 CVBS_OUT B
NC/120
SIF2
SIF1
OP2
AFC
VP
VPLL
CVBS
REF
NC
AGND
VAGC
TAGC
R118
L100
R113
1UH
NC E
U206 6K8
R129
TDA9886T
8 1 75R
OUT3 GND CVBS0
R97
C103
NC/100U
7 2 NC/4K7
CVBS-OUT
C121
SIOMAD
NC/0.1U
OUT2 IN1
6V3
FMPLL
C126
DGND
DEEM
U100
47P
6 3 75R
VIF1
VIF2
AUD
TOP
SDA
OP1
AFD
SCL
OUT1 IN2 R120
R130 R131
5 4 R96 5V-OUT 0R
NC\180R
OC EN
R102
NC\6K8
R106
NC
10
11
12
NC/100R 5V-TUNER-ON/OF
NC/TPS2049 GND_TUNER
L107 R128
R112 0.01U
C127 120R SIF 0R C131
C 33R 0.1U C C
R109 R110 SIFP
0.01U
1P5
R107
R108
C120
E Q101
0R
L106
5K6 NC\BC847C
NC/100R X101 SIFN
0
C118
IN/GND
OUT1
OUT2
1000P
GND
IN
AV_5V
R116 C132
2 100R 0.01U
TUNER_SCL0_5V
BA592
1 2 3 4 5
D100
R115
R828
100R TUNER_SDA0_5V
Q105
10K
0.47U
2N7002 R105 R93
TUNER_SDA0 TUNER_SDA0_5V NC NC\100R
1000P
TUNER_SCL0 OSCL0
NC\47R
NC\1K5
R103
R104
1000P
0.01U
R117
C105
B B
R138
220R
C128
C116
R111
NC
2K2
C117
0.01U
C107
390P
R119 C108
R94
5K6
0.56UH
NC\100R
AV_5V
L101
C124ET
C
Q103
R829
B
Q104
10K
2N7002 R133
E
TUNER_SCL0 TUNER_SCL0_5V 33R
1000P
C106
A DV33 A
I_17950_021.eps
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8 7 6 5 4 3 2 1
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 28
NC
NC
10K
X800
R816
R833
32K7
R142
OSCO 33R OSCI
R817
D801
LL4148
F STANDBY 5VSB F
20P
20P
C821
C822
1
OIRI 600R
2
R806
POWER_ON DV33
27K
3
L821 600R R805
+3V3SB 4 CEC 100R CEC_IRQ
L822 600R
5
35KEY_5V
100P
6
C819
R819
7
3K3
L823 600R
R842 L811 R22 R10
KEY_5335 8
NC 600R 5V_KEY 0R 0R
KEY
E 9 E
+3V3SB_UP
2N7002/NC Q809
P805
Q817 OSCL0
L820 2N7002
600R
Q810
OSDA0
C871
C823
1U 2N7002
0.1U
+3V3SB_UP
+3V3SB_UP
+3V3SB_UP
10K
D D
C876
10K
NC\1000P
R827
R807
+3V3SB_UP
R810
R809
10K
R826
C875
U810 1
1000P OSCL0_SB
10K
10K
OSCO 1 16 2
R815 OSCO VDD
R822
OSDA0_SB ISP PORT
4K7 OSCI 2 15 33R KEY 3
OSCI AD0
3 14 R830 33R OIRI_MCU
VSS AD3/IR 4
0.1U
4 13
C820
R824 33R P802
NRST SCL1
HDMI_INT 33R R813 5 12 R820 33R
PWMI SDA1
C SHORT_PROTECT 33R R834 C
6 11 R823 33R STANDBY
RXD/IRQ3 SCL2
SW_UPDATE_CTL1 0R R835 CEC_IRQ 7 10 R825 33R 3V3SB_EN
TXD/IRQ2 SDA2
HSYNC 33R R812 8 9 R814 33R VSYNC
HIN VIN
+3V3SB
WT6702F
1U
C802
BT3904
OIRI_MCU E
B B
R144
4K7
+3V3SB
RT9166 U811
L809
120R 2 3 GND
OUT IN 5VSB
GND
C826
C809
C872
0.1U
0.1U
100U
100U
6V3
6V3
1
C825
C824
1U
A
A
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Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 29
SSB v1: DC / DC
8 7 6 5 4 3 2 1
R851
12V/4A
CONNECTOR NC R8013
10K
11
Back Light circuit
R850
10
4K7
F 12V_IN 5V_PW F
C859
0.1U
9 R849 C
BL_ON/OFF 10K Q802 R848
B BT3904 100R 5VSB
8
+3V3SB 0.1U
AV33 E +5V BL ON/OFF
7 C829
R856 IS FOR 26" Q800
6 +5V 19"20"22" NC 12V_IN 1 8 12V
L815 S2 D2A
NC 600R
5
47K
R856
2 7
C860
5VSB R845 1
0.1U
R847 C852 G2 D2B C858
SELECT 5V_OUTSIDE
4K7
C853
NC R9
4 R857 NC
0.1U
L814 2 3 6
1K 1K LL4148 DIMMING 1U R854 S1 D1A
600R
R8
R844 ON/OFF 0R 1U
3 D804 4 5
10K
L813 R860 3
R8011
R843 C G1 D1B
5V_PW 30R 5V_KEY 0R 5VSB BL_DIM 4K7 Q801 R852 C854
0.1U
2 C827 C A04803
B 4 4K7 Q803
C828
R846
5V/2A B 1U
1 BT3904 BT3904
1U
10K
R865
E 5
E
0R
R46
R8001
R855
6
R8003
10K
10K
R8010
4K7
C
0R
Q816 4K7 L819 7
ON/OFF
POWER CINCH BT3904 B
200R
12V_IN P800
E L818
C862
200R
0.1U
3V3SB_EN
100U
C810
16V
E E
NC
C863
12V 5VSB
12V
L14 C846
200R
0.1U
R8006
4 4
L15
200R LD1117S12
10K
AV12
GND/ADJ1
D818 R2
OUT 2
R898
U803
VIN 3
LL4148 510R SHORT_PROTECT
1000U LD1117S33
C804
C800
4U7
16V
4 4
R894
AV_5V
47K
D816
100K
C831
R4
0.1U
LL4148 C
3K9 10K Q805
GND/ADJ1
U800 R91 B BT3904
OUT 2
C807
0.1U
VIN 3
C832 R895
R92
C849
C
5V_OUTSIDE
100U
6V3
10K Q807
120R
R802
0.1U E
2K2
B BT3904
R831
R832
about 1mm
C848
0.1U
R866
22K
2R7
2R7
GND R896
E
R5
D809
10K
D808 U807 8K2
+5V LL4148 12V
LL4148
R876
1 8 +5V
D BOOT PHASE D13N03LT U809 D
NC/KD1084-33
NC
R887
R897
3 2
680R
3 6 S2 D2A VIN OUT
FB GND 3 6
2K2
ADJ/GND
C841
L805
C806
0.1U
C830
C803
1K2
NC
4 5
C839
0.1U
G1 D1B
C870
200R
330R
R801
VCC LGATE
100U
6V3
2 7 1
100U
6V3
1000U
C801
16V
RT8110 S1 D1A
1 8 D810
R888 LL4148
C834
10R
R871
0.01U
DV33 2K7
4U7
U808
0.1U
R872
R867
GND
R889
220R
10R
R870
R869
4K7
4 4
R868
NC
U801
C805
5VSB
GND/ADJ1
LD1117S33 D811 D805
R858
OUT 2
R890
1U
VIN 3
AV33 LL4148 LL4148
2K7 CI_VCC
C833
AV33 2K7
+5V
NC
GND
R859
R891
C812
GND
C818
4K7
0.1U
4K7
C837
6V3
6V3
47U
47U
3V9
GND C840
D814
C 0R R1
0.1U C
D812 D806
R892 LL4148 R861
C R6 2K7 LL4148
+3V3SB 3K DDRV
Q806 10K
B
BT3904
E
R893
R862
12V
4 4
4K7
6K8
R7
R3
10K
U804
1K
GND/ADJ1
LD1117S25 AV25
OUT 2
VIN 3
D817 D807
LL4148 LL4148 R863
CI_DV18 3K AV25
120R
L816
C842
0.1U
0.1U
C843
R864
C811
6V3
47U
6K8
4 4
C816
U806 4 4
R879
U805
100U
16V
GND/ADJ1
0.01U LD1117S GND/ADJ1
LD1117S50
OUT 2
0.1U 4 2
VIN 3
AV9V
OUT 2
B
VIN 3
IN BS DV10 B
1K
R803 R804
1 5R1 6R8
12V
NC1 L801
15UH L13
C850
0.1U
C815
C851
200R
0.1U
5
SW
R884
C814
100U
9
6V3
16V
47U
EN
1K
C874
C844
0.1U
C845
0.1U
330U
C817
16V
4U7
C813
3 R882 C865
100U
16V
0.1U
R885
10 8
6K2
SS COMP
6
A A
I_17950_023.eps
070508
8 7 6 5 4 3 2 1
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 30
R136
R134
10K
NC
NC
10K
C527
L506
C514 C569
1000P NC/20P
F FAT_IN+ AV12 Digital 1.8V Bypass Caps DVDD12 F
R508 0R TUNER_SCL0
AV12
TUNER_SDA0
L500
R507
0.22U
0R 600R
0.22U
DV33
C510
C511
0.1U
0.1U
0.1U
0.1U
0.1U
NC/10K
R151
1U
C515
C517
C519
C516
C518
C500
R150
TUNER_SCL
TUNER_SDA
NC/1K MT5133-GPIO-AD
0.22U
DVDD12
AVDD33
ADVDD33_1
R506
C512
MT5131_IF_AGC 1K IF_AGC
VCMEXT
REFTOP
CLOSE TO MT5133
REFBOT
E DV33 DVDD33 E
DVDD33
C509 Digital 3.3V Bypass Caps
27P
C506
0.047U
48
47
46
45
44
43
42
41
40
39
38
37
R500
U502 L501
27M
X500
600R
VCMEXT
IN+
IN-
VDD1.2_3
DGND1.2_1
TUNER_SCL
REF_TOP
REFBOT
TUNER_SDA
AVDD33_3
AVDD33_1
AVSS33_1
1M
0.1U
27P
XTALO
R503
C507
C508
0.1U
0.1U
0.1U
0.1U
NC
1U
1 36
C521
C523
C520
C522
C501
AVSS33_3 RF_AGC
2 35
AVSS33_2 IF_AGC
XTALI 3 34
4
XTALI VDD3.3_3
33 R505
AVDD33 5
XTALO GPIO0
32 100R MT5133_RESET
AVDD33_2 /RESET
6 31
ALC_IN XTAL_SEL1 R504 10K
R536 DVDD12 7 30
VDD1.2 XTAL_SEL0
33R 8 29
D TS0INDATA7 1 8 9
DGND1.2 DGND3.3_1
28 DVDD33 D
TSDATA7 VDD3.3_2
10 27 DVDD12
TS0INDATA6 2 7 11
TSDATA6 VDD1.2_2
26 SIF_SDA R5010R OSDA0
TSDATA5 HOST_SDA OSCL0 AV33 AVDD33
DVDD33 12 25 SIF_SCL
TS0INDATA5 3 6 VDD3.3 HOST_SCL Analog 3.3V Bypass Caps
VDD3.3_1
VDD1.2_1
R502 0R
DGND3.3
TSDATA4
TSDATA3
TSDATA2
TSDATA1
TSDATA0
TSSYNC
TSERR
TSCLK
TSVAL
4 5
L502
600R
13
14
15
16
17
18
19
20
21
22
23
24
MT5133
R535
33R
0.1U
0.1U
1U
TS0INDATA4 1 8
C502
C525
C526
TS0INDATA3 2 7
DVDD33
DVDD12
TS0INDATA2 3 6
C C
TS0INDATA1 4 5
AV33
ADVDD33_1
TS0INDATA0 33R R542
0.1U
1U
C524
C503
120P/NC
120P/NC
C504
C505
B B
A
A
I_17950_024.eps
070508
8 7 6 5 4 3 2 1
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 31
L509
L508 LD1117S18 30R
R525
R522
600R L507
R521
NC\10K
R519
NC\10K
R517
30R
10K
10K
D
S
NC
3 VIN
2 OUT
1GND/ADJ
C557
C556
CI_IREQ# CI_VS2# CI_WAIT# Q501
6V3
47U
0.1U
G
6V3
CI_INPACK# CI_IOIS16#
47U
C550
10K/NC
R528
NC\A03401A
C546
+5V +5V +5V
100U
6V3
U500
4 4
R527
R518
R516
47K/NC
10K
NC\0.1U
10K
100K/NC
C C558
CI_VCC_EN Q502
R526
3.3V: 0.2W (60mA) B
R520
R523
R524
0.1U/NC
1.8V: 0.2W
10K
10K
10K
E
C547
(100mA) NC\C124ET
CI_CD1# CI_VS1# CI_CD2#
0.1U
0.1U
C559
C560
CI_DV33 CI_DV18 CI_DV18 CI_AV18
E E
CI_DV33 CI_AV33
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
C1
0.1U
0.1U
1U
1U
0.1U
0.1U
1U
C533
0.1U
C531
C532
C539
C538
C535
C534
C537
C536
C554
C541
C540
C552
C544
C545
R549
0.1U
1U
0.1U
C551
C543
C542
10P
C562
CI_DV33 R511
CI_GPIO1 4K7
CLOSE TO MT8295 R550
CI_OE## 100R CI_OE#
10P
C530
R510
4K7
TS_CKO
10P
CI_GPIO0
C563
D D
DV33
CLOSE TO MT8295
R540
R551
C528 C529 100R
CI_WE## CI_WE#
TS_SYNCO
R548
27P 27P
TS_DATAO
TS_VALIDO
R512
NC
33R
10K
R509 1M
10P
R513 MTK_IC_RESET
C564
0R P500
X501 27M
R547
CLOSE TO MT8295
R538
R539
120R
R541
33R
1 35
CI_D3 2 36 CI_CD1#
CI_D4 3 37 CI_OUTDATA3
4K7
33R
33R
CI_IORD##
5V-TUNER-INPUT
10P
CI_A11 10 44 CI_IORD#
C565
CI_A9 11 45 CI_IOWR#
CI_TS_VALIDO
CI_TS_SYNCO
GND
CI_TS_DATAO
CI_POCE1#
CI_POWE#
13 47
CI_XTALO
CI_A13 CI_INDATA0
CI_RB
CI_PDD3
CI_PDD4
CI_PDD5
CI_XTALI
RESET_N
CI_DV33
CI_DV33
CI_AV18
CI_AV33
CI_OEB
C
T
Z501 14 48
CI_CLE
CI_ALE
CI_A14 CI_INDATA1
CI_INT
CI_GPIO14 15 49 C
GND
GND
GND
CI_WE# CI_INDATA2
T
CI_VPP
99
98
97
VCC33_5
GPIO12
GPIO11
GPIO10
CI_OEB
CI_INT
RESETB
CI_RB
CI_CLE
GND33_4
CI_ALE
VCC33_4
TS_CKO
AVSS18_PLL
AVDD18_PLL
TS_VALIDO
XTALI
XTALO
AVSS33_XTAL
AVDD33_XTAL
CI_DATA0
CI_DATA1
CI_DATA3
CI_DATA4
CI_DATA5
CI_DATA6
CI_DATA7
TS_DATAO
CI_A12 21 55 CI_INDATA6
CI_GPIO0 1 96 CI_PDD2 CI_A7 22 56 CI_INDATA7
GPIO0 CI_WEB
10P
CI_GPIO1 2 95 CI_PDD6 CI_A6 23 57 CI_VS2#
10P
C566
GPIO1 CI_DATA2 24 58
HDMIED_WP 3 94 CI_PDD7 C561 CI_A5 CI_RESET
HPDIN GPIO2 CI_CEB 25 59
4 93 CI_VCC_EN CI_A4 CI_WAIT#
5
GPIO3 GPIO9
92 CI_VPP33_EN CI_A3 26 60 NC\0R CI_INPACK#
CI_DV33
VCC33 GPIO8 27 61
TS0INCLK 6 91 CI_VPP5_EN CI_A2 CI_REG#
T0CLK_I_ GPIO7 28 62
TS0INSYNC 7 90 GND CI_A1 CI_OUTVALID R532
T0SYNC_I_ GND18_1 29 63
TS0INVALID 8 89 CI_IOIS16# CI_A0 CI_OUTSYNC
T0VALID_I_ WP 30 64
TS0INDATA0 9 88 CI_CD2# CI_D0 CI_OUTDATA0
T0DATA0_I_ CD2# 31 65 R533
GND 10 87 CI_D2 CI_D1 CI_OUTDATA1
GND33 D2 32 66 CI_VS2# 100R CI_OUTCLK
TS0INDATA1 11 86 CI_OUTDATA2 CI_D2 CI_OUTDATA2
T0DATA1_I_ D10 33 67
TS0INDATA2 12 85 CI_D1 CI_IOIS16# CI_CD2#
T0DATA2_I_ D1 34 68
TS0INDATA3 13 84 CI_OUTDATA1
TS0INDATA4 14
T0DATA3_I_ D9
83 CI_D0 NC/0R
T0DATA4_I_ D0 R531
10P
CI_DV18 15 U501 82 CI_DV18
C567
VCC18 VCC18_1
TS0INDATA5 16 81 CI_OUTDATA0
T0DATA5_I_ D8
TS0INDATA6 17 80 CI_A0
T0DATA6_I_ A0
B
TS0INDATA7
HDMI_SEL
18
19
T0DATA7_I_ BVD1
79
78
CI_OUTSYNC
CI_A1
CLOSE TO MT8295
YPBPR_SW_IN 20
GPIO4 A1
77 CI_OUTVALID
B
GPIO5 BVD2
PWRDN_EN 21 76 GND
GPIO6 GND33_2
GND 22 75 CI_A2
GND18 A2
CI_CD1# 23 74 CI_REG#
CD1# REG#
CI_D3 24 73 CI_A3
D3 A3
CI_OUTDATA3 25 72 CI_INPACK#
D11 INPACK#
CI_D4 26 71 CI_A4
D4 A4
CI_OUTDATA4 27 70 CI_WAIT#
D12 WAIT#
CI_D5 28 69 CI_A5
D5 A5
CI_OUTDATA5 29 68 CI_DV33
D13 VCC33_3
CI_D6 30 67 CI_RESET
D6 RESET
CI_OUTDATA6 31 66 CI_A6
D14 A6
GND33_1
GND33_3
VCC33_1
VCC33_2
CI_D7 32 65 CI_OUTCLK
D7 VS2#
READY
IOWR#
IORD#
CE1#
CE2#
VS1#
WE#
OE#
D15
A10
A11
A17
A18
A13
A19
A14
A20
A21
A22
A16
A23
A15
A24
A12
A25
A9
A8
A7
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
CI_OUTDATA7
CI_INDATA0
CI_INDATA1
CI_INDATA2
CI_INDATA3
CI_INDATA4
CI_INDATA5
CI_INDATA6
CI_INDATA7
CI_INVALID
CI_IOWR##
CI_INSYNC
CI_IORD##
MT8295
CI_CE1##
CI_IREQ#
CI_WE##
CI_OE##
CI_CE2#
CI_VS1#
CI_DV33
CI_DV33
CI_A10
CI_A11
CI_A13
CI_A14
CI_A12
CI_A9
CI_A8
CI_A7
GND
GND
A A
CI_INCLK
100R
R515
I_17950_025.eps
070508
8 7 6 5 4 3 2 1
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 32
P600
1
4
Y600
1
2
L+ R+
U600 TDA7266
PGND
8 PW_GND
9 S_GND
15 OUT2+
1 OUT1+
OUT1-
14 OUT2-
6 MUTE
3 VCC1
13 VCC2
7 STBY
11 NC3
5 NC1
10 NC2
4 IN1
12 IN2
R622
2
L-
AL1O NC L_OUT
MUTE
R621 R620 R_OUT R-
SS
SPEAK-OUTL 0R 2K2 C612 1U
GND
4700P
R624
C611
100K
C610
R617 0.1U
AR1O NC
C608
GND 1U
SPEAK-OUTR 2K2 R600
PGND
0R
R618 R619
0R
R623
4700P
100K
Near the P502
C609
GND PGND
12V
C607
R601
1000U
16V
L600
0.1U
0R
C615
200R
L601
200R Near the P502
GND PGND
PGND
BT3906
12V
Q607
R643 R640
220R 4K7 L602
600R
E
12V
B
L603
R639
R627
600R HP_L
10K
4K7
SS EAR
0R/NC R636
R656
1
4700P/NC
4700P/NC
100U
C600
C601
P601
16V
C602
100R
R628
3300P
3300P
NC
10K 0R/NC R637
2
C614
C613
R631
R641 R632 GND
4K7
R659
10K
100R
B E HP_R 3
Q608 GND
R626
100R
C GND MUTE
BT3906 BT3904 GND GND R+
LL4148 9 6 L+
R644 Q602 C 16V R_OUT 8 5 L_OUT GND
D600 HW_MUTE
R629
10K B 7 4 C617
100R
E R647 100U 16V 100U
R625 C616
C606
AMP_MUTE 4K7
R642
10K
1K
LL4148
GND
GND
I_17950_026.eps
070508
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 33
R211
F DV33 NC F
U203
R209
OSDA0 204
C201
220U
OSDA0
16V
OSCL0 205 207 CI_PDD3 X200
1K
OSDA1 63
OSCL0 GPIO_3
208 CI_PDD4 60M TXC L214
OSDA1 GPIO_4 ORESET# OXTALI OXTALO 0.82UH
OSCL1 62 209 CI_PDD5
OSCL1 GPIO_5
R206
BL_DIM 191 59 CI_PDD6 R208 C
OPWM1 OPWM0 GPIO_6
202 60 CI_PDD7 220R Q202
OPWM1 GPIO_7 B BT3904
1K
OPWM2 203 210 CI_POWE#
MTK_IC_RESET OPWM2 GPIO_8
146 211 CI_OEB
1000P
VCXO GPIO_9 PWRDET E
OXTALO 143 212 CI_ALE
10P
10P
LL4148
XTALO GPIO_10
C223
C221
C222
OXTALI 144 214 CI_CLE
R210
XTALI GPIO_11
D200
AVCC_SRV 147 215 MT5133_RESET
AVDD33_SRV GPIO_12
47K
AVDD33_XTAL 145 216 POWER_ON
AVDD33_XTAL GPIO_13
R200 180K KEY_5335
KEY 152
ADIN4
151
PANEL_SLT ADIN3
E 150 E
ADIN2
SCART_FS_IN 149 92
ADIN1 OPCTRL0 Adjust the power on timing
PWRDET 148 91 LVDSVDD_EN
R44
ADIN0 OPCTRL1
76 CI_INT
10K
OPCTRL2 R207
AVDD33_REG 88 75 AMP_MUTE
AVDD33_REG OPCTRL3 10R
C_XREG 87 90 BL_ON/OFF C_XREG
C_XREG OPCTRL4
ORESET# 71 89 EDID_PRT
ORESET_ OPCTRL5
SW_UPDATE_CTL 72
OPWRSB
C203
4U7
DV33
DV33 R201
4K7
DV33
MT5335PKU
R203
R202
R205
10K
10K
R204
10K
10K
D D
B
HDMI_INT
B
C
E
CEC
BT3904
E
Q200
BT3904
Q201
DV33
DV33
Z959 T
DV33 L210
600R AVCC_SRV
R216
R215
R214
0.1U
Z958 T
1U
C C
C224
C204
U205
10K
4K7
4K7
8 1
R217 VCC E0/NC
33R DV33
R38
7 2
WC E1/NC
10K
L211
OSCL0 6 3 600R AVDD33_XTAL
SCL E2/NC Z960 T
C
Q206 OSDA0 5 4
B C124ET
R36
SDA VSS
10K
0.1U
R39
1U
C M24C16MN
C206
C225
E
EDID_PRT 4K7 Q1 T T Z957
0.1U
Z956
E
R40
R37
NC\0R
NC
B B
DV33
L212
600R AVDD33_REG
0.1U
1U
C205
C226
A
A
I_17950_027.eps
070508
8 7 6 5 4 3 2 1
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 34
AV12
U203 L215
600R AVDD12_PLL
USB_VRT 68 160 AVDD12_PLL
USB_VRT AVDD12_KADCPLL
USB_D- 65 155 AVDD12_PLL
USB_DM AVDD12_TVDPLL
USB_D+ 66 153 AVDD12_PLL
USB_DP AVDD12_KHDMIPLL
AVDD33_USB 67 161 AVDD12_PLL
AVDD33_USB AVDD12_KAPLL
AVDD12_USB 69 159 AVDD12_PLL C228 C249 C250
1U
AVDD12_USB AVDD12_SYSPLL
C207
157 156 AVDD12_PLL
TP0 AVDD12_KDMPLL 1U 0.01U 0.1U
158 154 AVDD12_PLL
TN0 AVDD12_DTDPLL
AV33
MT5335PKU
R218
5K1 AV33 L216 GND
USB_VRT 600R AVDD33_USB
GND C251
1U
C208
0.1U
AV12
AV12 L217
600R AVDD12_USB
GND
C252
1U
C210
0.1U
AV25
AV25 L218
U203 600R AVDD25_SADC
GND
163 AVDD25_SADC
SIFP AVDD25_SADC
164 165
SIFP AVSS25_SADC
SIFN 166 C229 C253 C254
1U
SIFN
C211
167
AF
193 TS_DATAO GND 1U 0.01U 0.1U
TS_VALIDO RF_AGC TS_SYNCO
195 192
TS_CKO 194
TUNER_DATA IF_AGC AV33
TUNER_CLK
L219
AV33 600R AVDD33_H
HDMI_5V
MT5335PKU
HDMI_5V GND
U203 C230 C255
1U
C212
1U 0.1U
RX0_CB 79 77
RX0_CB EXT_RES
RX0_C 80 73
RX0_0B 81
RX0_C OPWR0_5V AV12
RX0_0B
RX0_0 82
RX0_0
RX0_1B 83 AV12
RX0_1B
RX0_1 84 78 AVDD33_H L220
RX0_1 AVDD33_HDMI
RX0_2B 85 74 AVDD12_CVCC 600R AVDD12_CVCC
RX0_2B AVDD12_CVCC GND
RX0_2 86
RX0_2
C248
1U
C213
MT5335PKU 0.1U
GND
I_17950_028.eps
070508
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 35
R227
390R
Footprint is ACM-2012
5V_OUTSIDE
MT5335PKU
L200 +5V
EXC24C C320
A0N 1 4 AN00 10P
NC R25
NC R26
R26 FOR 19" 22" PANEL
L201 12V R25 FOR OTHER +5V SUPPLY PANEL
EXC24C C322 GND T Z210
A1N AN11 10P
1 4 T Z212
P202 12V
AP11 L232
A1P 2 3
C323 10P
39 40 35KEY_5V NC/30R
LVDS OUT
Q203
1 8 VDD_PANEL
L202 AP00 S1 D1
EXC24C C324 GND 37 38 AN00
A2N AN22 10P P209 2 7
1 4
AP11 35 36 AN11 S2 D2
A2P AP22 C325 5 6
C202
220U
10P GND 3 6
16V
2 3 GND
AP22 33 34 AN22 C258 S3 D3
3 4 R219
C209
L203 0.1U 10K 4 5
EXC24C GND CLK11+ G D4
1U
31 32 CLK11-
CK1N 1 4 CLK11-C326 10P 1 2 AO4459
AP33 29 30 AN33
CK1P CLK11+C327 10P
2 3 0R R213 C259
GND
27 28 R221
100K 0.1U
L204 GND 0R R212
EXC24C AN33 C328 25 26 L233 GND GND
A3N 1 4
10P R222
AV33 0R PANEL_CTL1 NC/30R C
23 24 LVDSVDD_EN
C329 Q204
A3P 2 3 AP33 10P B
AV33 PANEL_CTL2 21 22 C143ZT
L205 E
A4N EXC24C AN44 C330 GND
10P
R223 AP44 19 20 AN44
1 4 0R
A4P C331 AP55 17 18 AN55
2 3 AP44 10P
AP66 15 16 AN66
L206
EXC24C GND CLK22+ CLK22-
A5N AN55 C332 10P 13 14
1 4 GND
C333 AP77 11 12 AN77
A5P AP55 10P AV33
2 3
9 10
L207 AV33
EXC24C GND L221 AVDD33_LVDS
A6N AN66 C334 10P 7 8 600R
1 4
1U
L208
C214
EXC24C GND 1U 0.1U
CK2N 1 4 CLK22-C336 10P 1 2
1U
C232
GND
1U 0.1U
GND
GND I_17950_029.eps
070508
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 36
U203
L223
600R
POCE0# 252 95 U0RX U202
POCE0_ U0RX
D POOE# 251 94 U0TX D
PDD0 250
POOE_ U0TX 1 16 POOE#
PDD0 HOLD# SCLK
5
PDD1 249 93 OIRI_MT5335
PDD1 OIRI 2 15 PDD1
1U
VCC SI
C240
R270
R235
10K
CI_RB 245 253 JTMS 3 14 DV33
1K
CI_PDD2 PARB_ JTMS NC PO6
248 1 JTRST#
PDD2 JTRST_ 4 13
256 JTCK PO2 PO5
JTCK GND
255 JTDO
JTDO 5 12
R289
4
254 JTDI PO1 PO4
JTDI
R246
10K
6 11 TVTREF#1
PO0 PO3 2 1
4K7
POCE0# 7 10 JTRST#
R245 CS# GND 4 3
PDD0 0R 8 9 FRESET# JTDI
MT5335PKU SO WP#/ACC 6 5
JTMS
MX25L3205 8 7
+5V
JTCK
10 9
GND
R239 12 11
+5V JTDO 33R
C R90 14 13
Q3 10K OIRI
B
BT3904 16 15
OIRI_MT5335 E JTAG_DBGRQ
C006
18 17
100U
JTAG_DBGACK
6V3
C C
0.1U
C007
20 19
R89
4K7
P203
R236
R238
R237
10K
10K
10K
GND GND
AV33 0R 1
USB_D- R2011
2
USB_D+ 0R R2012
3 GND
1
1
R233
4
R234
EZJZ1V270RA
EZJZ1V270RA
DV33
10K
10K
P200
R87
R88
U0TX
1
2
U0RX
0.1U
0.1U
0.1U
3
1U
1U
2
C262
C263
C264
C234
C235
4
GND
RS-232 P201
GND GND
GND
B B
DV10
DV33
R240
OPWM2 4K7
R241
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
1U
1U
C237
C236
C265
C266
C267
C270
C269
C268
C272
C271
AOBCK 4K7
DV10 R244 R242
DDRV_IC 4K7 AOLRCK NC\4K7
U203
14 10 DDRV_IC
GND
VCCK VCC2IO GND
48 12
VCCK1 VCC2IO1
57 16
VCCK2 VCC2IO2
58 18
VCCK3 VCC2IO3
61 27
VCCK4 VCC2IO4
70 30
DVDD10 VCC2IO5
162 52
DVDD10_1 VCC2IO6 Trap MODE
213 54 OPWM2 AOBLK AOLRCK
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
1U
1U
VCCK6 VCC2IO7
C276
C238
C239
C279
C278
C277
C275
C274
C273
206 55 DV33
VCCK5 VCC2IO8
246 56
VCCK7 VCC2IO9 NORMAL MODE 0 0 0
64
VCC3IO_3_2
197
VCC3IO_3_1 ICE MODE 0 0 1
A 247 A
VCC3IO_3 GND
257
E-PAD
TRAP MODE OPCTRL5 OPCTRL4
GND
CORE RESET 1 US 0 1
MT5335PKU
I_17950_030.eps
5 4 3 2 1 070508
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 37
C306
C305
NC1 VOUT
C304
0.1U
0.1U
0.1U
R267 RDQ12 4 5 4 5
R261
47R 0R MEM_DQ12
MEM_WE# RWE# RT9199
C314
8
16V
100R
1
R269
220U
R266 100K
47U
MEM_CAS# 2 7 RCAS# R260
1K
RCLK0# 22R MEM_CLK0#
MEM_RAS# 3 6 RRAS# 6V3
C217 GND
4 5
GND GND
R278
+1V3D
MEM_CS# 47R
1 8 RCS#
MEM_BA0 2 7 RBA0
MEM_BA1 3 6 RBA1
MEM_ADDR10 4 5 RA10
+1V3D
R279
47R
MEM_ADDR0 1 8 RA0 R280
75R
MEM_ADDR1 2 7 RA1 MEM_CS# 1 8
MEM_ADDR2 3 6 RA2 MEM_RAS# 2 7
MEM_ADDR3 4 5 RA3 MEM_CAS# 3 6
MEM_WE# 4 5
R281
DDRV_IC 75R
DDRV MEM_ADDR10 1 8
MEM_BA1 2 7
L213
600R MEM_BA0 3 6
C315
4 5
100U
6V3
C349
220U
16V
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
C284
C285
C287
C286
C280
C281
C282
C283
C349 IS CLOSE TO PIN33 OF DDR R282
75R
MEM_ADDR7 1 8
DDRV MEM_ADDR6 2 7
+5V GND
4 4
MEM_ADDR5 3 6
U201
MEM_ADDR4
GND/ADJ1
LD1117S MEM_VREF 4 5
OUT 2
+1V3D
VIN 3
R252
MEM_CLKEN 75R
R262
0.1U
4U7
110R
C302
C215
R283
C200
75R
100U
6V3
0.1U
0.1U
0.1U
MEM_ADDR12 1 8
1U
C303
C300
C301
C216
0.1U
0.1U
0.1U
0.1U
C296
C297
C299
C298 MEM_ADDR11 2 7
R263
120R
MEM_ADDR9 3 6
GND MEM_ADDR8 4 5
GND
GND
+1V3D R253
GND MEM_ADDR13 75R
R284
1.25 x (1+120/110) = 2.6V 75R
MEM_ADDR3 1 8
MEM_ADDR2 2 7
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
1U
MEM_ADDR1
C288
C289
C291
C290
C316
C295
C294
C292
C293
3 6
MEM_ADDR0 4 5
GND
I_17950_031.eps
070508
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 38
MT5335PKU
AV33
AV33 ADAC_VCM
AV33 L227 L231
600R AVDD33_AADC 600R AVDD33_ADAC1
AV33
0.1U
0.1U
1U
C219
A 0.1U A
C313
1U
4U7
C246
1U
C311
C241
C245
C307
GND GND
GND GND
GND
GND GND
AV33 AV33
L228 L230 VIMD_AADC
AV33 600R 600R AVDD33_DIG
REFP_AADC
AV33
0.1U
0.1U
1U
1U
C310
C308
C244
C242
4U7
C312
C218
GND GND 0.1U
GND GND
AV33 GND GND
L229
AV33 600R AVDD33_ADAC0
0.1U
1U
C309
C243
GND
GND
A I_17950_032.eps
070508
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 39
100P
C900 R901 R904 R907
C928
AL1O 1U 470R 10K 5K1 C902 R908
47U
10R SPEAK-OUTL
OPAVREF
6V3
R900
2200P
100K
C925
NC
C929
1
GND
VCC-
1IN+
1IN-
1OUT
U1
AV9V
RC4558
GND
GND GND
VCC+
2OUT
L16
2IN+
2IN-
GND 600R
1U
C912
OPAVREF
NC
C930
C901 R903 R905
R910
1U 470R 10K C903 R913
AR1O 5K1 47U GND
10R
SPEAK-OUTR
100P
6V3
R902
C927
R909
100K
33K
2200P
C926
GND
GND
A A
DAC
DV33DV33
DV33 R9020
10K
R9021
U907
10K/NC
R9022
R9030
AV9V OPAVREF AOLRCK 33R R9027 33R AOMCLK
10K
1 14
LRCLK MCLK
R914 R9019 A0SDATA0 33R R9028 2 13
10K 47K DIN FORMAT
OPAVREF 33R R9029 3
AOBCK 12
10K R9023
10K R9024
BCLK DEEMPH
DACVL
DACVL
4 11
R915
ENABLE DVDD
1U
5 10
10K
C911
C9014
1U
VMID DGND
C910
C9015
C9012 6 9 0.1U
ROUT LOUT
1U
0.1U C9013 7 8
GND AGND AVDD R9017 L900
GND GND 0.1U 1U C9017 SCT1_AUL_OUT
0 600R
ADCVA
WM8501
R9025
NC/33K
C9018
1000P
0.1U
C913
GND
C9016 R9018 L901
1U 0 600R SCT1_AUR_OUT
R9026
NC/33K
1000P
+5V ADCVA
DV33 DACVL
C914
L930 L931
30R ADCVA 30R
GND
C9009
C9011
1U
1U
C9010
C9008
1U
0.1U
A I_17950_033.eps
070508
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 40
2
L9
600R
D3V3L4
R21
D108
4K7
AV18-HDMI
C38
0.1U
0.1U
GND
1U
C42
C43
P901
0.1U
C39
DV33-HDMI
1
RX2+
GND1 2
GND
3 R14 R15 R16
RX2- R13
4K7 4K7 NC\4K7
RX1+ 4 4K7
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
GND3 8
R2X0-
R2X0+
AVCC33D
R2X1-
R2X1+
AGND8
R2X2-
R2X2+
AVDD18C
DSDA2
DSCL2
RPWR2
DVCC18B
DGND2
RSVDL
HPDIN
TSDA
TSCL
AGND9
TPWR/I2CADDR
9
R12
NC\4K7
RX0-
R11
4K7
RXC+ 10
60 1 RX0_2
11 AGND7 TX2+
59 2 RX0_2B
GND4 58
RXC2+ TX2-
3
RXC2- AGND1 GND
RXC- 12 57 4 RX0_1 GND
AVCC18D TX1+ RX0_1B
56 5
13 CEC-IN HPD2 TX1-
R42 NC\0R 55 6
NC1 54
AVCC33C U904 AVCC18A
7 RX0_0
14 CEC-A TX0+
NC2 R41 NC\0R 53 8 RX0_0B R45
CEC-D TX0- DV33-HDMI
52 9 0R
15 HDMI1_SCL RPWR1 SII9185 AGND2
10 RX0_C CEC-IN CEC
51
DDCCLK 50
DSCL1 TXC+
11 RX0_CB
DSDA1 TXC-
1
DDCDA 16 HDMI1_SDA 49 12 R31
AVDD18B EXTSWING
48 13 750R
17 R1X2+ RESET#
47 14
D5V0S1
D5V0S1
D5V0S1
D5V0S1
GND5 46
R1X2- LSDA
15 R72
C133
C134
C135
C136
10P
10P
10P
10P
AGND6 LSCL
D104
D105
D106
D107
VCC 18 +5V_HDMI1 45 16
R1X1+ HPD0
44 17 EZJZ1V270RA
19 R1X1- AVCC18B DV33
2
43 18
HPD 42
AVCC33B R0XC-
19
R1X0+ R0XC+
41 20
R1X0- AGND3
I2CSEL/INT
GND
AVCC18C
DVCC18A
AVDD18A
AVCC33A
RPWR0
DGND1
AGND5
AGND4
DSDA0
R1XC+
DSCL0
R0X2+
R0X1+
R0X0+
R1XC-
R0X2-
R0X1-
R0X0-
R32 GND
HPD1
GND
NC\4K7
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
R33 100R
RESET_N
NC\4K7
CEC DV33
R35 NC\100R
R30 GND OSCL0 L10
L11
600R 600R
4K7
0.1U
0.1U
1U
1U
0.1U
0.1U
0.1U
0.1U
R51
0.1U
0.1U
0.1U
0.1U
C20
C21
C23
C19
C22
C11
C12
P903
C13
C14
C15
C16
C17
DV33
1
RX2+ GND
GND1 2
3 R52
RX2- 4K7
RX1+ 4 R54
4K7
5
R55
4K7
GND2 C
6 Q2
RX1- BT3904 B
7 E
RX0+
GND3 8
GND
9
RX0- 100R
R53
RXC+ 10 HDMI_SEL
11
GND4
RXC- 12
13
NC1
NC2 14
15 HDMI0_SCL
DDCCLK
DDCDA 16 HDMI0_SDA
17
GND5
18 +5V_HDMI0 R58
VCC +5V_HDMI1
19 4K7 +5V_HDMI0
HPD
T Z903
T Z908
GND
U906
U905 1 8
R47
R48
R57
47K
47K
R50
47K
1 8 A0 VCC
R49
47K
A0 VCC R56 4K7
2 7
C41
4K7
0.1U
2 7 A1 WP
0.1U
A1 WP
C40
3 6 HDMI1_SCL
5
3 6 HDMI0_SCL A2 SCL
D3V3L4
A2 SCL 4 5 HDMI1_SDA
GND SDA
D109
4 5 HDMI0_SDA
GND SDA AT24C02
AT24C02 T Z904 T Z901
T Z907 T Z902
T Z906 T Z905
2
GND
GND
GND
I_17950_034.eps
070508
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 41
12 SCT1_AUR_IN
2 SCT1_AUL_OUT R968
75R C967
13 47P C969
1U
3 GND_SV
14 SCT1_AUL_IN
1
R971
16 75R C970
R60
6 SCT1_G_IN 16P
R972 C972
EZJZ1V270RA 100R 0.01U
Y0N
GND
17
7
R973 C974
L905
2
GND 0.01U
18 SCT1_B_IN 30R 68R PB0P
SCT1_R_IN
8
STC1_FB_IN R975
1
19
75R C973
9 16P
R61 R974 C975
20 100R 0.01U
GND
PBR0N
EZJZ1V270RA
10 SCT1_AV_OUT T Z920
T Z928 R976
21 SCT1_AV_IN T Z923 75R C976
T Z919 GND
2
T Z918 16P R977 C977
11 T Z922 L906
68R 0.01U
T Z927 SCT1_R_IN 30R PR0P
1
R978 C978
1
R63 R64 100R 0.047U
SC0
EZJZ1V270RA
R62
2
EZJZ1V270RA
EZJZ1V270RA
2
GND
GND GND
NEARLY MT5335
R964 C965
L1 1U
L907 R963 SCT1_AUR_IN 30R 10K SCT_R
STC1_FB_IN 30R 0R SOY0
R965 C966
L2 1U
30R 10K SCT_L
1
SCT1_AUL_IN
C979 R960
75R R966 R967
470P C963 C964 10K
R65 10K
470P 470P
EZJZ1V270RA
2
R67 R68
2
EZJZ1V270RA EZJZ1V270RA
R66
GND
EZJZ1V270RA
2
2
I_17950_035.eps
GND 070508
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 42
T Z917 U203
R945 C953
0.047U
L925
CVBS0 100R
10R
132 139 DVDD25_VADC C920
CVBS0 DVDD25_VADC
CVBS1 130 140 GND 1U
CVBS2 CVBS1 DVSS25_VADC GND_TUNER
129 133
CVBS2 GND_TUNER
SY0 128 131 GND_CVBS
SY0 GD_CVBS
SC0 127 124 GND_SV
SC0 GND_SV
SY1 126
0.01U
SY1
R9003
1U
SC1 125 141 AVDD25_VADC
C003
C004
SC1 AVDD25_VADC
10K AVSS25_VADC
142 GND
R918 137 AVDD25_REF
0R D2SA AVDD25_REF
CVBS_OUT 136 138 GND
D2SA AVSS25_REF
135 AVDD25_VFE
BC847C AVDD25_VFE
R919 C001 R920 GND AVSS25_VFE
134 GND
47U C
D2SA NC 1K Q815
B
CI_GPIO14
6V3 E R9004 R924
75R SCT1_AV_OUT 0R
MT5335PKU
C R921
4K7
C002
Q906 B
47P
R9002 BC847C
E
R9001
10K
470R
R944
4K7
GND GND
AV25
9
Nearly Connector Nearly 5335 AV25
L911
T Z975 R946 C959 600R DVDD25_VADC
7 L915 0.047U
30R 100R
P902
SY1
C954
1
C916
5 1U 0.1U
R70 R947 AV25
T 75R C958
EZJZ1V270RA 47P AV25
Z974 L912 GND
6 600R AVDD25_VADC
2
8
C917 C955
GND R948 C961 1U 0.1U
L916 0.047U AV25
30R 100R SC1
GND AV25
L913 GND
1
600R AVDD25_REF
R949
R69 C960
75R
EZJZ1V270RA C918 C956
47P
1U 0.1U
2
AV25
AV25
L914
GND 600R AVDD25_VFEGND
Z980 Z981
T T C919 C957
R9010 C9001
L926 1U 0.1U
P902 30R 10K AIN2_L 1U
4
WHITE
R9009 C9002
L927 1U
3 30R 10K AIN2_R
RED
GND
2
YELLOW R9012 R9011
1 C9004 C9003 10K
10K
470P 470P
EZJZ1V270RA
GND
R71
1 2
GND
R9013 C9006
L928 0.047U
30R 100R CVBS2
T R9014
75R C9007
Z976
47P
C915
1U GND_CVBS
T
GND I_17950_036.eps
Z978 070508
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 43
U203
RED 4
YPBPR_R_IN
R982 SOY0 107 117 DVDD12_VGA
5 75R C731 Y0P 108
SOY0 DVDD12_VGA
113 GND
BLUE PB_IN Y0P AVSS12_RGBADC
16P Y0N 109 110 AVDD12_RGBADC
6 C729 PB0P 114
Y0N AVDD12_RGBADC
105 GND
R983 PB0P AVSS12_RGBFE
100R 0.01U Y1N PBR0N 115 101 AVDD12_RGBFE
PBR0N AVDD12_RGBFE
PR0P 116
RED PR0P RP
PR_IN SOY1 118 104
SOY1 RP
Y1P 119 106 RN
7 GND Y1N 120
Y1P RN
98 BP
Y1N BP BN
VGA_R_IN PB1P 121 99
PB1P BN
PBR1N 122 102 GP
10 PR1P 123
PBR1N GP
103 GN
T Z939
VGA_L_IN R986 C726 PR1P GN
L5 96 VSYNC
T Z940
9 PB_IN 68R 0.01U PB1P VSYNC
30R 112 97 HSYNC
TN1 HSYNC SOG
111 100
P907 8 TP1 SOG
R985 MT5335PKU
75R C727
16P C725
R987
100R 0.01U PBR1N
1
R74 AV12
R77 AV12
EZJZ1V270RA EZJZ1V270RA L909
GND 600R DVDD12_VGA
R989 C723
L6
2
C989 C990
1U 0.1U
GND
AV12
AV12
L3 GND
600R AVDD12_RGBFE
C991 C992
1U 0.1U
GND
T Z929
C732 R979
0.1U R990 C721
SPDIF_OUT 100R ASPDIF L8 1U
P904 2 YPBPR_L_IN 30R 10K YPBPR_L
BLACK R991 C720
L7
1
R73
EZJZ1V270RA GND
GND
I_17950_037.eps
070508
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 44
Z973 T
10
R716 16P VGA_PLUGPWR
4 W/P_CTR 0R W/P
R997 C713
14 VSYNC_IN VGA_PLUGPWR 0.01U
100R GN
3 C996
9 1 2 +5V 0.1U R715
R720 C710
L919 U903 10K
BLUE BLUE GND 33R 0.01U BP
3 D913 30R
1 8
Z972 T
BAV70 A0 VCC
13 HSYNC_IN C005
2 7 W/P
Z971 T
ESD_0402 A1 WP
8 VGASCL
3 6
Z970 T
R999 C711 A2 SCL
2 GREEN 75R 4 5 VGASDA
16P GND SDA
12 VGASDA_IN GND C709
R701 AT24C02
100R 0.01U
7 BN
1 RED C707
L920 R721
RED 33R 0.01U RP
11 30R GND GND
EZJZ1V270RA
EZJZ1V270RA
6
1
1
17 R702
C708
75R
16P
R86
R84
R703 C706
2
2
100R 0.01U RN
GND
R85
GND
EZJZ1V270RA
GND
5VSB
T Z949 5VSB
T Z950
R705 C701
VGASDA_IN
L923
VGASCL_IN
10K 1U
VGA_L_IN 30R VGA_L 5VSB
R709
VGASCL_IN 100R VGASCL
5VSB
R706 R707
1
C999 C703 10K 10K
470P 470P R712 R714 R713
R80 C998 100R 10K 100R
EZJZ1V270RA 16P
C143ZT
C143ZT
2
Q903
Q904
L921
HSYNC_IN 30R HSYNC U0TX U0RX
GND
E
C
C
1
GND 5VSB
B
R718
C705
22K
R82
10P 5VSB
EZJZ1V270RA
R710 R726 C
0R/NC SW_UPDATE_CTL1 Q905
10K
2
B C143ZT
SW_UPDATE_CTL E
R711 R725
GND
VGASDA_IN 100R VGASDA 10K
L922
VSYNC_IN 30R VSYNC
1
C997
1
R81 16P
R717
C704
22K
R83 EZJZ1V270RA
10P
EZJZ1V270RA GND
2
2
I_17950_038.eps
GND 070508
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 45
DV33A VDD_PANEL
L929
GND
NC\TTL\600R
R293
DV33A_LVDS_RECEIVER NC\TTL\33R P205
T_R7 1 8 R7 C2010
40 39 NC\TTL\0.1U
T_R6 2 7 R6
C2202 38 37
C2015 T_R5 3 6 R5
C2001 C2004 C2006 C2007
R1 36 35 R0
T_R4 4 5 R4
R3 34 33 R2
R294
NC\TTL\33R R5 32 31 R4
NC\TTL\0.1U T_R3 1 8 R3
NC\TTL\0.1U NC\TTL\0.1U
R7 30 29 R6
T_R2 2 7 R2
NC\TTL\0.1U NC\TTL\0.1U
GND DV33A_LVDS_RECEIVER T_R1 28 27
3 6 R1
U207 G1 26 25 G0
NC\TTL\0.1U T_R0 4 5 R0
T_B5 1 56 G3 24 23 G2
RXOUT22 VCC4 R295
2 55 T_B4
T_HSYNC RXOUT23 RXOUT21 54
NC\TTL\33R G5
3 T_B3 T_G7 1 8 G7 22 21 G4
RXOUT24 RXOUT20 53 T_B2
4
T_VSYNC GND1 RXOUT19 52 G6
5 T_G6 2 7 G6 G7 20 19
RXOUT25 GND5 51
T_DE 6 T_B1
T_R6 RXOUT26 RXOUT18 50 T_B7
7 T_G5 3 6 G5 18 17
RXOUT27 RXOUT17 49 T_B6
8
AN00 LVDSGND1 RXOUT16 48
9 T_G4 4 5 G4 B1 16 15 B0
AP00 RXIN0- VCC3 47 T_B0
10
AN11 RXIN0+ RXOUT15 46 T_G5 B2
11 B3 14 13
AP11 12
RXIN1- RXOUT14 45 R296
RXIN1+ RXOUT13 T_G4
13 44 NC\TTL\33R B5 12 11 B4
LVDSVCC1 GND4 T_G3 1 8 G3
14 43 T_G3
AN22 LVDSGND2 RXOUT12 42 T_G7
15 T_G2 B7 10 9 B6
AP22 16
RXIN2- RXOUT11 41 T_G6 2 7 G2
RXIN2+ RXOUT10 40
CLK11- 17 T_G1 8 7
CLK11+ 18
RXCLKIN- VCC2 39 T_G2 3 6 G1
AN33 RXCLKIN+ RXOUT9 38 D_HSYNC D_VSYNC
19 T_G1 T_G0 6 5
AP33 20
RXIN3- RXOUT8 37 T_G0 4 5 G0
RXIN3+ RXOUT7 36 PANEL_CTL2
21
LVDSGND3 GND3
R298 4 3
22 35 T_R5 NC\TTL\33R
PLLGND1 RXOUT6 34 8 B7 DE CLK
23 T_R7 T_B7 1 2 1
PLLVCC1 RXOUT5 33
24 T_R4
PWRDN PLLGND2 RXOUT4 T_B6
25 32 T_R3 2 7 B6
PWRDWN RXOUT3 31
T_CLK 26
RXCLKOUT VCC1 T_R2 T_B5
T_R0 27 30 3 6 B5
RXOUT0 RXOUT2 29
28 T_R1
GND2 RXOUT1 T_B4 4 5 B4
V386
R299
NC\TTL\33R GND
T_B3 1 8 B3
GND T_B2 2 7 B2
T_B1 3 6 B1
T_B0 4 5 B0
R290
NC\TTL\33R
1 8
DV33A T_DE 2 7 DE
T_VSYNC 3 6 D_VSYNC
T_HSYNC 4 5 D_HSYNC
DV33A
I_17950_039.eps
070508
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 46
I_17950_040.eps
070508
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 47
I_17950_041.eps
080508
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 48
4
0.1U
0.1U
0.1U
C137
C138
VCC
E
4LVC1G66GV
6V3
F F
C2
47U
0.1U
BC847C
Q106
C139
R153
ANALOG_IF
C
NC/RFAGC
0R
XTALOUT
NC/GND1
NC/GND2
ANTPWR
IFOUT2
IFOUT1
U101
GND
IFAGC
GND1
SDA
NC1
SCL
E
NC
Y
TU
AS
Z
B1
R124
3
1
11
12
13
14
15
16
17
18
19
20
21
100R
FAT_IN-
R152
5V-OUT 5V-OUT
R148 R125 RF-AGC
47K
R132
100R
NC
0R FAT_IN+ R149
RF-AGC NC\0R
R139
6K8 R140
C129 R141
6K8
0.01U
E 0.1U 22K R121 E
C119
D103 22K
BA982 12K
R146
ATV-IF-AGC
R127 100R E
0.01U
TUNER_SDA0_5V Q102
C109
R100
BC847C 680K
X100
R123 0R
100R
0.01U
R126
4M
C111
1500P
C115
C3
TUNER_SCL0_5V
0.1U
R114
R147
R101
330R
22K
X102
NC
C124
C125
IN/GND
D101
OUT1
OUT2
22P
GND
22P
1U
BA982
IN
C112
0.47U
C100
20P
5V-OUT
C114
L103
0.22U
D 120R D
C110
1 2 3 4 5 L102
TUNER_5V 120R
C123
C102
100U
D102
6V3
0.01U
C122
0.1U
TUNER_5V TUNER_5V
C101
100U
BC847C
6V3
0.01U
24
23
22
21
20
19
18
17
16
15
14
13
C
C113
BA982 Q100
R99 NC L104 CVBS_OUT B
NC/120
SIF2
SIF1
OP2
AFC
VP
VPLL
AGND
CVBS
VAGC
REF
TAGC
NC
R118
L100
R113
1UH
NC E
U206 6K8
R129
TDA9886T
8 1 75R
OUT3 GND CVBS0
R97
C103
NC/100U
7 2 NC/4K7
CVBS-OUT
C121
SIOMAD
NC/0.1U
OUT2 IN1
6V3
FMPLL
C126
DGND
DEEM
U100
47P
6 3 75R
VIF1
VIF2
AUD
TOP
SDA
OP1
AFD
SCL
OUT1 IN2 R120
R130 R131
5 4 R96 5V-OUT 0R
NC\180R
OC EN
R102
NC\6K8
R106
C NC C
10
11
12
NC/100R 5V-TUNER-ON/OF
NC/TPS2049 GND_TUNER
L107 R128
R112 0.01U
C127 120R SIF 0R C131
33R 0.1U C
R109 R110 SIFP
0.01U
1P5
R107
R108
C120
E Q101
0R
L106
5K6 NC\BC847C
NC/100R X101 SIFN
0
C118
IN/GND
OUT1
OUT2
1000P
GND
IN
AV_5V
R116 C132
2 100R 0.01U
TUNER_SCL0_5V
BA592
1 2 3 4 5
D100
R115
R828
100R TUNER_SDA0_5V
B Q105 B
10K
0.47U
2N7002 R105 R93
TUNER_SDA0 TUNER_SDA0_5V NC NC\100R
1000P
TUNER_SCL0 OSCL0
NC\47R
NC\1K5
R103
R104
1000P
0.01U
R117
C105
R138
220R
C128
C116
R111
NC
2K2
C117
0.01U
C107
390P
R119 C108
R94
5K6
0.56UH
NC\100R
AV_5V
L101
C124ET
C
Q103
R829
B
Q104
10K
2N7002 R133
E A
TUNER_SCL0 TUNER_SCL0_5V 33R
1000P
A
C106
DV33
8 7 6 5 4 3 2 1
17953_521_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 49
NC
NC
10K
X800
R816
R833
F 32K7 F
R142
OSCO 33R OSCI
R817
D801
LL4148
STANDBY 5VSB
20P
20P
C821
C822
1
OIRI 600R
2
R806
POWER_ON DV33
27K
3
L821 600R R805
+3V3SB 4 CEC 100R CEC_IRQ
L822 600R
5
35KEY_5V
100P
6
C819
R819
E 7 E
3K3
L823 600R
R842 L811 R22 R10
KEY_5335 8
NC 600R 5V_KEY 0R 0R
KEY
9
+3V3SB_UP
2N7002/NC Q809
P805
Q817 OSCL0
L820 2N7002
600R
Q810
OSDA0
C871
C823
1U 2N7002
0.1U
D +3V3SB_UP D
+3V3SB_UP
+3V3SB_UP
10K
C876
10K
NC\1000P
R827
R807
+3V3SB_UP
R810
R809
10K
R826
C875
U810 1
1000P OSCL0_SB
10K
10K
OSCO 1 16 2
R815 OSCO VDD
R822
OSDA0_SB ISP PORT
4K7 OSCI 2 15 33R KEY 3
OSCI AD0
3 14 R830 33R OIRI_MCU
VSS AD3/IR 4
0.1U
C 4 13
C
C820
R824 33R P802
NRST SCL1
HDMI_INT 33R R813 5 12 R820 33R
PWMI SDA1
SHORT_PROTECT 33R R834 6 11 R823 33R STANDBY
RXD/IRQ3 SCL2
SW_UPDATE_CTL1 0R R835 CEC_IRQ 7 10 R825 33R 3V3SB_EN
TXD/IRQ2 SDA2
HSYNC 33R R812 8 9 R814 33R VSYNC
HIN VIN
+3V3SB
WT6702F
1U
C802
BT3904
OIRI_MCU E
R144
4K7
+3V3SB
RT9166 U811
L809
120R 2 3 GND
OUT IN 5VSB
GND
C826
C809
C872
0.1U
0.1U
100U
100U
6V3
6V3
1
C825
C824
1U A
A
8 7 6 5 4 3 2 1
17953_522_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 50
SSB v2: DC / DC
8 7 6 5 4 3 2 1
NC R8012
P804
R851
12V/4A
F CONNECTOR NC R8013 F
10K
11
Back Light circuit
R850
10
4K7
12V_IN 5V_PW
C859
0.1U
9 R849 C
BL_ON/OFF 10K Q802 R848
B BT3904 100R 5VSB
8
+3V3SB 0.1U
AV33 E +5V BL ON/OFF
7 C829
R856 IS FOR 26" Q800
6 +5V 19"20"22" NC 12V_IN 1 8 12V
L815 S2 D2A
NC 600R
5
47K
R856
2 7
C860
5VSB R845 1
0.1U
R847 C852 G2 D2B C858
SELECT 5V_OUTSIDE
4K7
C853
NC R9
4 R857 NC
0.1U
L814 2 3 6
1K 1K LL4148 DIMMING 1U R854 S1 D1A
600R
R8
R844 ON/OFF 0R 1U
3 D804 4 5
10K
L813 R860 3
R8011
R843 C G1 D1B
5V_PW 30R 5V_KEY 0R 5VSB BL_DIM 4K7 Q801 R852 C854
0.1U
2 C827 C A04803
B 4 4K7 Q803
C828
R846
5V/2A B 1U
1 BT3904 BT3904
1U
10K
R865
E 5
E
0R
R46
R8001
R855
6
R8003
10K
10K
R8010
4K7
C
0R
Q816 4K7 L819 7
ON/OFF
E POWER CINCH BT3904 B
200R E
12V_IN P800
E L818
C862
200R
0.1U
3V3SB_EN
100U
C810
16V
NC
C863
12V 5VSB
12V
L14 C846
200R
0.1U
R8006
4 4
L15
200R LD1117S12
10K
AV12
GND/ADJ1
D818 R2
OUT 2
R898
U803
VIN 3
LL4148 510R SHORT_PROTECT
1000U LD1117S33
C804
C800
4U7
16V
4 4
R894
AV_5V
47K
D816
100K
C831
R4
0.1U
LL4148 C
3K9 10K Q805
GND/ADJ1
U800 R91 B BT3904
OUT 2
C807
0.1U
VIN 3
C832 R895
R92
C849
C
5V_OUTSIDE
100U
6V3
10K Q807
120R
R802
0.1U E
2K2
B BT3904
R831
R832
about 1mm
C848
0.1U
R866
22K
2R7
2R7
D GND R896
E D
R5
D809
10K
D808 U807 8K2
+5V LL4148 12V
LL4148
R876
1 8 +5V
BOOT PHASE NC U809
NC/KD1084-33
NC
R887
R897
3 2
680R
3 6 S2 D2A VIN OUT
FB GND 3 6
2K2
ADJ/GND
C841
L805
C806
0.1U
C830
C803
1K2
NC
4 5
C839
0.1U
G1 D1B
C870
200R
330R
R801
VCC LGATE
100U
6V3
2 7 1
100U
6V3
1000U
C801
16V
NC S1 D1A
1 8 D810
R888 LL4148
C834
10R
R871
0.01U
DV33 2K7
4U7
U808
0.1U
R872
R867
GND
R889
220R
10R
R870
R869
4K7
4 4
R868
NC
U801
C805
5VSB
GND/ADJ1
LD1117S33 D811 D805
R858
OUT 2
R890
1U
VIN 3
AV33 LL4148 LL4148
2K7 CI_VCC
C833
AV33 2K7
+5V
NC
GND
C
R859
C
R891
C812
GND
C818
4K7
4K7
0.1U
C837
6V3
6V3
47U
47U
3V9
GND C840
D814
0R R1
0.1U
D812 D806
R892 LL4148 R861
C R6 2K7 LL4148
+3V3SB 3K DDRV
Q806 10K
B
BT3904
E
R893
R862
12V
4 4
4K7
6K8
R7
R3
10K
U804
1K
GND/ADJ1
LD1117S25 AV25
OUT 2
VIN 3
D817 D807
LL4148 LL4148 R863
CI_DV18 3K AV25
120R
L816
C842
0.1U
0.1U
C843
R864
C811
6V3
47U
6K8
4 4
C816
B
4 4
U806 B
R879
U805
100U
16V
GND/ADJ1
0.01U LD1117S LD1117S50
GND/ADJ1
OUT 2
0.1U 4 2
VIN 3
AV9V
OUT 2
VIN 3
IN BS DV10
1K
R803 R804
1 5R1 6R8
12V
NC1 L801
15UH L13
C850
0.1U
C815
C851
200R
0.1U
5
SW
R884
C814
100U
9
6V3
16V
47U
EN
1K
C874
C844
0.1U
C845
0.1U
330U
C817
16V
4U7
C813
3 R882 C865
100U
16V
0.1U
R885
10 8
6K2
SS COMP
6
A A
8 7 6 5 4 3 2 1
17953_523_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 51
C513 C568
FAT_IN- 1000P NC/20P
F F
R136
R134
10K
NC
NC
10K
C527
L506
C514 C569
1000P NC/20P
FAT_IN+ AV12 Digital 1.8V Bypass Caps DVDD12
R508 0R TUNER_SCL0
AV12
TUNER_SDA0
L500
R507
0.22U
0R 600R
0.22U
DV33
C510
C511
0.1U
0.1U
0.1U
0.1U
0.1U
NC/10K
R151
1U
C515
C517
C519
C516
C518
C500
R150
TUNER_SCL
TUNER_SDA
NC/1K MT5133-GPIO-AD
E E
0.22U
DVDD12
AVDD33
ADVDD33_1
R506
C512
MT5131_IF_AGC 1K IF_AGC
VCMEXT
REFTOP
CLOSE TO MT5133
REFBOT
DV33 DVDD33
DVDD33
C509 Digital 3.3V Bypass Caps
27P
C506
0.047U
48
47
46
45
44
43
42
41
40
39
38
37
R500
U502 L501
27M
X500
600R
AVDD33_3
REF_TOP
VCMEXT
REFBOT
IN+
IN-
AVDD33_1
AVSS33_1
VDD1.2_3
DGND1.2_1
TUNER_SCL
TUNER_SDA
1M
0.1U
27P
XTALO
R503
C507
C508
0.1U
0.1U
0.1U
0.1U
NC
1U
1 36
C521
C523
C520
C522
C501
AVSS33_3 RF_AGC
2 35
AVSS33_2 IF_AGC
XTALI 3 34
4
XTALI VDD3.3_3
33 R505
D XTALO GPIO0 100R D
AVDD33 5 32 MT5133_RESET
AVDD33_2 /RESET
6 31
ALC_IN XTAL_SEL1 R504 10K
R536 DVDD12 7 30
VDD1.2 XTAL_SEL0
33R 8
DGND1.2 DGND3.3_1
29
TS0INDATA7 1 8 9 28 DVDD33
TSDATA7 VDD3.3_2
10 27 DVDD12
TS0INDATA6 2 7 11
TSDATA6 VDD1.2_2
26 SIF_SDA R5010R OSDA0
TSDATA5 HOST_SDA OSCL0 AV33 AVDD33
DVDD33 12 25 SIF_SCL
TS0INDATA5 3 6 VDD3.3 HOST_SCL Analog 3.3V Bypass Caps
VDD3.3_1
VDD1.2_1
TSDATA4
TSDATA3
TSDATA2
TSDATA1
TSDATA0
R502 0R
DGND3.3
TSSYNC
TSERR
TSCLK
TSVAL
4 5
L502
600R
13
14
15
16
17
18
19
20
21
22
23
24
MT5133
R535
33R
0.1U
0.1U
1U
TS0INDATA4 1 8
C502
C525
C526
C C
TS0INDATA3 2 7
DVDD33
DVDD12
TS0INDATA2 3 6
TS0INDATA1 4 5
AV33
ADVDD33_1
TS0INDATA0 33R R542
0.1U
1U
C524
C503
B B
120P/NC
120P/NC
C504
C505
A
A
8 7 6 5 4 3 2 1
17953_524_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 52
L508 LD1117S18
L509
R525
R522
600R L507
R521
NC\10K
30R
R519
NC\10K
R517
30R
10K
10K
NC
3 VIN
2 OUT
1GND/ADJ
C557
C556
CI_IREQ# CI_VS2# CI_WAIT#
5
6V3
47U
0.1U
6V3
CI_INPACK#
1U
CI_IOIS16#
47U
C550
C558
C546
VIN
VOUT
0.1U
C548
+5V +5V +5V
0.1U
100U
6V3
U500
C547
4 4
RT9711
R518
R528
R516
10K
EN/EN#
10K
10K
GND
FLG
U503
3.3V: 0.2W (60mA)
R520
R523
R524
R527
1.8V: 0.2W CI_VCC_EN
1
0R
10K
10K
10K
(100mA)
CI_CD1# CI_VS1# CI_CD2#
0.1U
0.1U
C559
C560
E CI_DV33 CI_DV18 CI_DV18 CI_AV18 E
CI_DV33 CI_AV33
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
C1
0.1U
0.1U
1U
1U
0.1U
0.1U
1U
C533
0.1U
C531
C532
C539
C538
C535
C534
C537
C536
C554
C541
C540
C552
C544
C545
R549
0.1U
1U
0.1U
C551
C543
C542
10P
C562
CI_DV33 R511
CI_GPIO1 4K7
CLOSE TO MT8295 R550
CI_OE## 100R CI_OE#
10P
C530
R510
4K7
TS_CKO
10P
CI_GPIO0
D D
C563
DV33
CLOSE TO MT8295
R540
R551
C528 C529 100R
CI_WE## CI_WE#
TS_SYNCO
R548
TS_DATAO
27P 27P
TS_VALIDO
R512
NC
33R
10K
R509 1M
10P
R513 MTK_IC_RESET
C564
0R P500
X501 27M
R547
CLOSE TO MT8295
R538
R539
120R
R541
33R
1 35
CI_D3 2 36 CI_CD1#
CI_D4 3 37 CI_OUTDATA3
4K7
33R
33R
10P
CI_A11 10 44 CI_IORD#
C565
11 45
CI_TS_VALIDO
CI_A9 CI_IOWR#
CI_TS_SYNCO
CI_TS_DATAO
GND
CI_POCE1#
CI_POWE#
CI_XTALO
CI_A13 13 47 CI_INDATA0
CI_RB
CI_XTALI
C
CI_PDD3
CI_PDD4
CI_PDD5
RESET_N
CI_DV33
CI_DV33
CI_AV18
CI_AV33
C
CI_OEB
T
Z501 14 48
CI_CLE
CI_ALE
CI_A14 CI_INDATA1
CI_INT
CI_GPIO14 15 49
GND
GND
GND
CI_WE# CI_INDATA2
T
CI_VPP
99
98
97
CI_A12 21 55 CI_INDATA6
CI_GPIO0 1 96 CI_PDD2 CI_A7 22 56 CI_INDATA7
GPIO0 CI_WEB
10P
CI_GPIO1 2 95 CI_PDD6 CI_A6 23 57 CI_VS2#
10P
C566
GPIO1 CI_DATA2 24 58
HDMIED_WP
C561
3 94 CI_PDD7 CI_A5 CI_RESET
HPDIN GPIO2 CI_CEB 25 59
4 93 CI_VCC_EN CI_A4 CI_WAIT#
5
GPIO3 GPIO9
92 CI_VPP33_EN CI_A3 26 60 NC\0R CI_INPACK#
CI_DV33
VCC33 GPIO8 27 61
TS0INCLK 6 91 CI_VPP5_EN CI_A2 CI_REG#
T0CLK_I_ GPIO7 28 62
TS0INSYNC 7 90 GND CI_A1 CI_OUTVALID R532
T0SYNC_I_ GND18_1 29 63
TS0INVALID 8 89 CI_IOIS16# CI_A0 CI_OUTSYNC
T0VALID_I_ WP 30 64
TS0INDATA0 9 88 CI_CD2# CI_D0 CI_OUTDATA0
T0DATA0_I_ CD2# 31 65 R533
GND 10 87 CI_D2 CI_D1 CI_OUTDATA1
GND33 D2 32 66 CI_VS2# 100R CI_OUTCLK
TS0INDATA1 11 86 CI_OUTDATA2 CI_D2 CI_OUTDATA2
T0DATA1_I_ D10 33 67
TS0INDATA2 12 85 CI_D1 CI_IOIS16# CI_CD2#
T0DATA2_I_ D1 34 68
TS0INDATA3 13 84 CI_OUTDATA1
TS0INDATA4 14
T0DATA3_I_ D9
83 CI_D0 NC/0R
T0DATA4_I_ D0 R531
10P
CI_DV18 15 U501 82 CI_DV18
C567
VCC18 VCC18_1
TS0INDATA5 16 81 CI_OUTDATA0
T0DATA5_I_ D8
TS0INDATA6 17 80 CI_A0
T0DATA6_I_ A0
B TS0INDATA7
HDMI_SEL
18
19
T0DATA7_I_ BVD1
79
78
CI_OUTSYNC
CI_A1
CLOSE TO MT8295 B
GPIO4 A1
YPBPR_SW_IN 20 77 CI_OUTVALID
GPIO5 BVD2
PWRDN_EN 21 76 GND
GPIO6 GND33_2
GND 22 75 CI_A2
GND18 A2
CI_CD1# 23 74 CI_REG#
CD1# REG#
CI_D3 24 73 CI_A3
D3 A3
CI_OUTDATA3 25 72 CI_INPACK#
D11 INPACK#
CI_D4 26 71 CI_A4
D4 A4
CI_OUTDATA4 27 70 CI_WAIT#
D12 WAIT#
CI_D5 28 69 CI_A5
D5 A5
CI_OUTDATA5 29 68 CI_DV33
D13 VCC33_3
CI_D6 30 67 CI_RESET
D6 RESET
CI_OUTDATA6 31 66 CI_A6
D14 A6
GND33_1
GND33_3
VCC33_1
VCC33_2
CI_D7 32 65 CI_OUTCLK
READY
D7 VS2#
IOWR#
IORD#
CE1#
CE2#
VS1#
WE#
OE#
D15
A10
A11
A17
A18
A13
A19
A14
A20
A21
A22
A16
A23
A15
A24
A12
A25
A9
A8
A7
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
CI_OUTDATA7
CI_INDATA0
CI_INDATA1
CI_INDATA2
CI_INDATA3
CI_INDATA4
CI_INDATA5
CI_INDATA6
CI_INDATA7
CI_INVALID
CI_IOWR##
CI_INSYNC
CI_IORD##
MT8295
CI_CE1##
CI_IREQ#
CI_WE##
CI_OE##
CI_DV33
CI_CE2#
CI_DV33
CI_VS1#
CI_A10
CI_A11
CI_A13
CI_A14
CI_A12
CI_A9
CI_A8
CI_A7
GND
GND
A A
CI_INCLK
100R
R515
8 7 6 5 4 3 2 1
17953_525_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 53
P600
F F
4
Y600
1
2
L+ R+
U600 TDA7266
PGND
8 PW_GND
9 S_GND
15 OUT2+
1 OUT1+
OUT1-
14 OUT2-
6 MUTE
3 VCC1
13 VCC2
7 STBY
11 NC3
5 NC1
10 NC2
4 IN1
12 IN2
R622
2
L-
AL1O NC L_OUT
MUTE
R621 R620 R_OUT R-
SS
SPEAK-OUTL 0R 2K2 C612 1U
E GND E
4700P
R624
C611
100K
C610
R617 0.1U
AR1O NC
C608
GND 1U
SPEAK-OUTR 2K2 R600
PGND
0R
R618 R619
0R
R623
4700P
100K
Near the P502
C609
GND PGND
12V
D D
GND R603 R648
2R7 2R7 R602
0R
C607
R601
1000U
16V
L600
0.1U
0R
C615
200R
L601
200R Near the P502
GND PGND
PGND
BT3906
12V
Q607
R643 R640
220R 4K7 L602
C 600R C
E
12V
B
L603
R627
4K7
SS EAR
0R/NC R636
R656
1
4700P/NC
4700P/NC
C600
C601
P601
100R
100U
R628
16V
C602
3300P
3300P
NC
C614
C613
R631
R659
4K7 10K
100R
B E HP_R 3
R626
100R
Q608 GND GND MUTE
C
BT3906 BT3904 GND GND R+
LL4148 9 6 L+
R644 Q602 C 16V R_OUT 8 5 L_OUT GND
B D600 HW_MUTE B
R629
10K B 7 4 C617
100R
E R647 100U 16V 100U
C616
C606
R630 10K
16V
22U
10K
R642
1K
GND GND
R625 D601
AMP_MUTE 4K7
A
A LL4148
8 7 6 5 4 3 2 1
17953_526_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 54
F F
U203
AV12
USB_VRT 68 160 AVDD12_PLL
USB_VRT AVDD12_KADCPLL
USB_D- 65 155 AVDD12_PLL AV12
USB_DM AVDD12_TVDPLL
USB_D+ 66 153 AVDD12_PLL L215
USB_DP AVDD12_KHDMIPLL
AVDD33_USB 67 161 AVDD12_PLL 600R AVDD12_PLL
AVDD33_USB AVDD12_KAPLL
AVDD12_USB 69 159 AVDD12_PLL
AVDD12_USB AVDD12_SYSPLL
157 156 AVDD12_PLL
TP0 AVDD12_KDMPLL
158 154 AVDD12_PLL
TN0 AVDD12_DTDPLL
C228 C249 C250
1U
C207
MT5335PKU 1U 0.01U 0.1U
R218
USB_VRT 5K1
E E
AV33
C251
1U
C208
0.1U
AV12
AV12 L217
600R AVDD12_USB
U203
GND
D C252 D
1U
163 AVDD25_SADC
C210
SIFP AVDD25_SADC
164 165 0.1U
SIFP AVSS25_SADC
SIFN 166
SIFN
167
AF TS_DATAO GND AV25
193
TS_VALIDO RF_AGC TS_SYNCO
195 192
TUNER_DATA IF_AGC L218
TS_CKO 194 AV25
TUNER_CLK 600R AVDD25_SADC
GND
MT5335PKU
1U
C211
1U 0.01U 0.1U
HDMI_5V
AV33
HDMI_5V
C U203 L219 C
AV33 600R AVDD33_H
RX0_CB 79 77
RX0_CB EXT_RES GND
RX0_C 80 73
RX0_C OPWR0_5V
RX0_0B 81 C230 C255
1U
RX0_0B
C212
RX0_0 82
RX0_0 1U 0.1U
RX0_1B 83
RX0_1B
RX0_1 84 78 AVDD33_H
RX0_1 AVDD33_HDMI AV12
RX0_2B 85 74 AVDD12_CVCC
RX0_2B AVDD12_CVCC
RX0_2 86
RX0_2
AV12
L220
600R AVDD12_CVCC
GND
MT5335PKU
C248
1U
B B
C213
0.1U
GND
A
A
8 7 6 5 4 3 2 1
17953_527_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 55
F F
U203
AV12
USB_VRT 68 160 AVDD12_PLL
USB_VRT AVDD12_KADCPLL
USB_D- 65 155 AVDD12_PLL AV12
USB_DM AVDD12_TVDPLL
USB_D+ 66 153 AVDD12_PLL L215
USB_DP AVDD12_KHDMIPLL
AVDD33_USB 67 161 AVDD12_PLL 600R AVDD12_PLL
AVDD33_USB AVDD12_KAPLL
AVDD12_USB 69 159 AVDD12_PLL
AVDD12_USB AVDD12_SYSPLL
157 156 AVDD12_PLL
TP0 AVDD12_KDMPLL
158 154 AVDD12_PLL
TN0 AVDD12_DTDPLL
C228 C249 C250
1U
C207
MT5335PKU 1U 0.01U 0.1U
R218
USB_VRT 5K1
E AV33 E
C251
1U
C208
0.1U
AV12
AV12 L217
600R AVDD12_USB
U203
GND
C252
1U
D 163 AVDD25_SADC D
C210
SIFP AVDD25_SADC
164 165 0.1U
SIFP AVSS25_SADC
SIFN 166
SIFN
167
AF TS_DATAO GND AV25
193
TS_VALIDO RF_AGC TS_SYNCO
195 192
TUNER_DATA IF_AGC L218
TS_CKO 194 AV25
TUNER_CLK 600R AVDD25_SADC
GND
MT5335PKU
1U
C211
1U 0.01U 0.1U
HDMI_5V
AV33
HDMI_5V
U203 L219
C AV33 600R AVDD33_H C
RX0_CB 79 77
RX0_CB EXT_RES GND
RX0_C 80 73
RX0_C OPWR0_5V
RX0_0B 81 C230 C255
1U
RX0_0B
C212
RX0_0 82
RX0_0 1U 0.1U
RX0_1B 83
RX0_1B
RX0_1 84 78 AVDD33_H
RX0_1 AVDD33_HDMI AV12
RX0_2B 85 74 AVDD12_CVCC
RX0_2B AVDD12_CVCC
RX0_2 86
RX0_2
AV12
L220
600R AVDD12_CVCC
GND
MT5335PKU
C248
1U
C213
B 0.1U B
GND
A
A
8 7 6 5 4 3 2 1
17953_528_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 56
U203 DV33
NC R25
NC R26
MT5335PKU R26 FOR 19" 22" PANEL
L201 12V R25 FOR OTHER +5V SUPPLY PANEL
EXC24C C322 GND T Z210
A1N AN11 10P
1 4 T Z212
P202 12V
AP11 L232
A1P 2 3
C323 10P
39 40 35KEY_5V NC/30R
LVDS OUT
Q203
1 8 VDD_PANEL
L202 AP00 S1 D1
EXC24C GND 37 38 AN00
D A2N AN22 C324 10P P209 2 7
D
1 4
AP11 35 36 AN11 S2 D2
A2P AP22 C325 5 6
C202
220U
10P GND 3 6
16V
2 3 GND
AP22 33 34 AN22 C258 S3 D3
3 4 R219
C209
L203 0.1U 10K 4 5
EXC24C GND CLK11+ G D4
1U
31 32 CLK11-
CK1N 1 4 CLK11-C326 10P 1 2 AO4459
AP33 29 30 AN33
CK1P CLK11+C327 10P
2 3 NC R213 C259
GND
27 28 R221
100K 0.1U
L204 GND NC R212
EXC24C AN33 C328 25 26 L233 GND GND
A3N 1 4
10P R222
AV33 0R PANEL_CTL1 30R C
23 24 LVDSVDD_EN
C329 Q204
A3P 2 3 AP33 10P B
AV33 PANEL_CTL2 21 22 C143ZT
L205 E
C A4N NC AN44 C330 GND
NC
R223 AP44 19 20 AN44 C
1 4 0R
A4P C331 AP55 17 18 AN55
2 3 AP44 NC
AP66 15 16 AN66
L206
NC GND CLK22+ CLK22-
A5N AN55 C332 NC 13 14
1 4 GND
C333 AP77 11 12 AN77
A5P AP55 NC AV33
2 3
9 10
L207 AV33
NC GND L221 AVDD33_LVDS
A6N AN66 C334 NC 7 8 600R
1 4
1U
B L208 B
C214
NC GND 1U 0.1U
CK2N 1 4 CLK22-C336 NC 1 2
CK2P CLK22+C337 NC
2 3 AV33
L209 AV33
NC C338 GND GND VDD_PANEL L222 AVDD33_VPLL
A7N AN77 NC 600R GND
1 4
A7P AP77 C339 NC C260
2 3
0.1U
C220 C257
1U
C232
GND
1U 0.1U
GND A
A GND
8 7 6 5 4 3 2 1
17953_529_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 57
1 16 POOE#
HOLD# SCLK
2 15 PDD1
1U
U203 VCC SI
C240
3 14 DV33
F NC PO6 F
5
POCE0# 252 95 U0RX
POCE0_ U0RX
POOE# 251 94 U0TX 4 13
POOE_ U0TX PO2 PO5
R270
R235
PDD0 250 GND
10K
PDD0
PDD1 249 93 OIRI_MT5335 5 12
1K
R289
PDD1 OIRI PO1 PO4
R246
10K
6 11
CI_RB 245 253 JTMS PO0 PO3
4K7
CI_PDD2 PARB_ JTMS
POCE0#
4
248 1 JTRST# 7 10
PDD2 JTRST_ R245 CS# GND
256 JTCK
JTCK 0R TVTREF#1
255 JTDO PDD0 8 9 FRESET#
JTDO SO WP#/ACC 2 1
254 JTDI
JTDI JTRST#
MX25L3205 4 3
JTDI
MT5335PKU +5V 6 5
GND JTMS
+5V 8 7
E JTCK E
10 9
AV33 C R90
Q3 10K OIRI R239 12 11
C006
B
BT3904 JTDO 33R
100U
6V3
14 13
0.1U
C007
OIRI_MT5335 E
16 15
R233
JTAG_DBGRQ
R234
18 17
R89
10K
4K7
JTAG_DBGACK
10K
GND 20 19
U0TX
1 0R 1
R2011 P203
R236
GND USB_D- DV33
R238
R237
2 2
10K
0R R2012
10K
USB_D+
10K
U0RX
3 3
D D
1
4 4
EZJZ1V270RA
EZJZ1V270RA
RS-232 P201
0.1U
0.1U
0.1U
P200
1U
1U
R87
R88
C262
C263
C264
C234
C235
GND GND
DV33
R240
4K7
2
GND
2
OPWM2
R241
AOBCK 4K7 DV10
R244 R242 GND
4K7 AOLRCK NC\4K7
GND
C C
GND
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
1U
1U
C237
C236
C265
C266
C267
C270
C269
C268
C272
C271
Trap MODE OPWM2 AOBLK AOLRCK
DV10
DDRV_IC NORMAL MODE 0 0 0 GND
U203 DDRV_IC
ICE MODE 0 0 1
14 10
VCCK VCC2IO
48 12
VCCK1 VCC2IO1
57 16
VCCK2 VCC2IO2
58 18
VCCK3 VCC2IO3
61 27
B 70
VCCK4 VCC2IO4
30 TRAP MODE OPCTRL5 OPCTRL4 B
DVDD10 VCC2IO5
162 52
DVDD10_1 VCC2IO6
213 54
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
1U
1U
VCCK6 VCC2IO7 CORE RESET 1 US 0 1
C273
C238
C239
C279
C278
C277
C275
C274
C276
206 55
246
VCCK5 VCC2IO8
56
DV33
VCCK7 VCC2IO9
64
VCC3IO_3_2
197
VCC3IO_3_1
247
VCC3IO_3
GND
257
E-PAD
GND
MT5335PKU
A
A
8 7 6 5 4 3 2 1
17953_530_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 58
+1V3D
F F
U203
U204
MEM_DQ0 2 49 MEM_VREF R271 R287
DQ0 VREF 47R 75R
MEM_DQ1 4 RDQ0 MEM_DQ0
RDQS0 11 47 RA0 DQ1 1 8 1 8
RDQS0 RA0 MEM_DQ2 5
RDQM0 13 36 RA7 DQ2 MEM_ADDR0
RDQM0 RA7 MEM_DQ3 7 29
RDQ0 9 40 RWE# DQ3 A0 RDQ1 2 7 MEM_DQ1 2 7
RDQ0 RWE_ MEM_DQ4 8 30 MEM_ADDR1
RDQ1 8 43 RBA0 DQ4 A1
RDQ1 RBA0 MEM_DQ5 10 31 MEM_ADDR2
RDQ2 7 37 RA6 DQ5 A2 RDQ2 3 6 MEM_DQ2 3 6
RDQ2 RA6 MEM_DQ6 11 32 MEM_ADDR3
RDQ3 6 44 RBA1 DQ6 A3 MEM_ADDR4
RDQ3 RBA1 MEM_DQ7 13 35
RDQ4 5 38 RA5 MEM_DQ8 54
DQ7 A4
36
RDQ3 4 5 MEM_DQ3 4 5
RDQ4 RA5 DQ8 A5 MEM_ADDR5
RDQ5 4 42 RRAS# MEM_DQ9 56 37
RDQ5 RRAS_ DQ9 A6 MEM_ADDR6
RDQ6 3 35 RA8 MEM_DQ10 57 38
RDQ6 RA8 DQ10 A7 MEM_ADDR7 R272 R286
RDQ7 2 45 RA10 MEM_DQ11 59 39
RDQ7 RA10 MEM_ADDR8 47R 75R
RDQS1 17 39 RA4 DQ11 A8 RDQ4 8 MEM_DQ4 8
RDQS1 RA4 MEM_DQ12 60 40 MEM_ADDR9 1 1
RDQM1 15 41 RCAS# DQ12 A9
RDQM1 RCAS_ MEM_DQ13 62 28 MEM_ADDR10
RDQ8 19 32 RA12 DQ13 A10/AP MEM_DQ5
RDQ8 RA12 MEM_DQ14 63 41 MEM_ADDR11 RDQ5 2 7 2 7
RDQ9 20 31 RCKE DQ14 A11 MEM_ADDR12
RDQ9 RCKE MEM_DQ15 65 42
RDQ10 21 33 RA11 DQ15 A12 RDQ6 MEM_DQ6
RDQ10 RA11 3 6 3 6
RDQ11 22 34 RA9 14
RDQ11 RA9 NC
RDQ12 23 51 RA3 MEM_ADDR13 RDQ7 MEM_DQ7
RDQ12 RA3 17 4 5 4 5
RDQ13 24 49 RA1 NC1 MEM_CLK0
RDQ13 RA1 19 45
RDQ14 25 50 RA2 NC2 CLK MEM_CLK0#
RDQ14 RA2 25 46
RDQ15 26 NC3 CLK
RDQ15 44 MEM_CLKEN R248 R254
DDRV_IC CKE
43 47R 75R
MEM_VREF 53 28 RCLK0# NC4 RDQS0 MEM_DQS0
RVREF0 RCLK0_ 50 R249 R255
RCS# 46 29 RCLK0 NC5 MEM_CS#
E RCS_ RCLK0 53 24 RDQM0 47R 75R E
NC6 CS MEM_RAS# MEM_DQM0
23 R250 R256
RAS MEM_CAS#
1 22 47R 75R
VDD CAS RDQM1 MEM_DQM1
18 21 MEM_WE# R251 R257
VDD1 WE
33 RDQS1 47R 75R
3
VDD2 MEM_DQS1
MT5335PKU VDDQ MEM_DQS0
9 16
VDDQ1 LDQS
15 51 MEM_DQS1
VDDQ2 UDQS
55
VDDQ3
61
VDDQ4 MEM_DQM0 R273 R285
20
LDM MEM_DQM1
R275 34 47 47R 75R
VSS UDM RDQ11 1 8 MEM_DQ11 1 8
47R 48
VSS2
MEM_ADDR12 1 8 RA12 66
6
VSS1
26 MEM_BA0 RDQ10 2 7 MEM_DQ10 2 7
2 7 VSSQ1 BA0 MEM_BA1
MEM_ADDR11 RA11 12 27
VSSQ2 BA1 RDQ9 3 6 MEM_DQ9 3 6
52
3 6 VSSQ
MEM_ADDR9 RA9 58
VSSQ3 RDQ8 4 5 MEM_DQ8 4 5
64
MEM_ADDR8 4 5 VSSQ4
RA8
32M*16DDR
R276
GND R274 R288
47R
MEM_ADDR7 1 8 RA7 47R 75R
RDQ15 1 8 MEM_DQ15 1 8
D MEM_ADDR6 2 7 RA6 D
RDQ14 2 7 MEM_DQ14 2 7
MEM_ADDR5 3 6 RA5
RDQ13 3 6 MEM_DQ13 3 6
MEM_ADDR4 4 5 RA4
RDQ12 4 5 MEM_DQ12 4 5
+5V DDRV
R277 +1V3D
47R R258 R265 R268 MEM_VREF
L224 U200
MEM_WE# 1 8 RWE# 22R MEM_CLKEN 0R 100K
RCKE 600R 8 1
NC3 VIN
MEM_CAS# 2 7 RCAS# R280
7 2 75R
R259 NC2 GND L225
MEM_RAS# RRAS# 22R MEM_CS# 1 8
3 6 RCLK0 MEM_CLK0 0R 6 3 600R
R264 VCNTL REFEN L226
4 5 MEM_RAS# 2 7
5 4 600R
C306
C305
NC1 VOUT
C304
0.1U
0.1U
0.1U
R267 MEM_CAS# 3 6
R261
0R RT9199
C314
16V
100R
R269
220U
R278 R266 100K
47U MEM_WE# 4 5
MEM_CS# 47R R260
1K
1 8 RCS#
RCLK0# 22R MEM_CLK0# 6V3 R281
MEM_BA0 2 7 RBA0 C217 GND 75R
MEM_ADDR10 1 8
MEM_BA1 3 6 RBA1 GND GND
MEM_BA1 2 7
C C
MEM_ADDR10 4 5 RA10
MEM_BA0 3 6
+1V3D
R279 4 5
47R
MEM_ADDR0 1 8 RA0
DDRV_IC R282
MEM_ADDR1 2 7 RA1 DDRV 75R
MEM_ADDR7 1 8
MEM_ADDR2 3 6 RA2
C349 IS CLOSE TO PIN33 OF DDR MEM_ADDR6 2 7
MEM_ADDR3 4 5 L213
RA3 600R MEM_ADDR5 3 6
C315
MEM_ADDR4 4 5
100U
6V3
C349
220U
16V
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
C284
C285
C287
C286
R252
C280
C281
C282
C283
MEM_CLKEN 75R
R283
75R
GND MEM_ADDR12 1 8
MEM_ADDR11 2 7
MEM_VREF
+1V3D MEM_ADDR9 3 6
B B
MEM_ADDR8 4 5
R253
MEM_ADDR13 75R
0.1U
0.1U
1U
C300
C301
C216
R284
0.1U
0.1U
0.1U
0.1U
+5V
C296
C297
C299
C298
75R
MEM_ADDR3 1 8
DDRV
MEM_ADDR2
4 4
2 7
R28
R27
R29
LD1117S GND
+1V3D
OUT 2
VIN 3
MEM_ADDR0 4 5
2R2
2R2
2R2
R262
0.1U
4U7
110R
C302
C215
C200
100U
6V3
0.1U
C303
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
1U
C288
C289
C291
C290
C292
C293
C316
C295
C294
R263
120R
GND A
A
GND
GND
8 7 6 5 4 3 2 1
17953_531_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 59
F F
U203
MT5335PKU
AV33
D D
AV33 L227
600R AVDD33_AADC
AV33 ADAC_VCM
C219
0.1U
L231
1U
4U7
C241
C307
600R AVDD33_ADAC1
AV33
GND
0.1U
0.1U
1U
C313
C246
1U
C311
C245
GND
GND
AV33 GND
L228
AV33 600R GND GND
REFP_AADC GND
C AV33 C
0.1U
L230
1U
C308
VIMD_AADC
C242
600R AVDD33_DIG
AV33
GND
0.1U
1U
C310
C244
4U7
C312
C218
AV33 GND
GND 0.1U
L229
AV33 600R AVDD33_ADAC0
GND
GND GND
0.1U
1U
C309
C243
GND
B B
GND
A
A
8 7 6 5 4 3 2 1
17953_532_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 60
F F
100P
C900 R901 R904 R907
C928
AL1O 1U 470R 10K 5K1 C902 R908
47U
10R SPEAK-OUTL
OPAVREF
6V3
R900
2200P
100K
C925
NC
C929
1
GND
VCC-
1IN+
1IN-
1OUT
U1
AV9V
RC4558
GND
GND GND
VCC+
2OUT
L16
2IN+
AV9V_REF
2IN-
GND 600R
E E
1U
5
C962
C912
220U
16V
OPAVREF
NC
C930
C901 R903 R905
R910
AR1O 1U 470R 10K C903 R913
5K1 47U
GND 10R
SPEAK-OUTR
100P
6V3
R902
C927
R909
100K
33K
2200P
C926
GND
D DAC D
GND DV33DV33
DV33 R9020
10K
R9021
U907
10K/NC
R9022
R9030
AOLRCK 33R R9027 33R AOMCLK
10K
1 14
LRCLK MCLK
R9019 A0SDATA0 33R R9028 2 13
47K DIN FORMAT
OPAVREF AOBCK 33R R9029 3 12
10K R9023
10K R9024
BCLK DEEMPH
DACVL
R914 DACVL
4 11
AV9V_REF 10K ENABLE DVDD
OPAVREF
5 10 C9014
C VMID DGND C
C9015
C9012 6 9 0.1U
R915
ROUT LOUT
1U
0.1U C9013
1U
7 8
10K
C911
R9017
1U
ADCVA
WM8501
R9025
NC/33K
GND GND
GND
C9018
1000P
0.1U
C913
GND
C9016 R9018 L901
1U 470 600R SCT1_AUR_OUT
B B
+5V ADCVA
DV33 DACVL
R9026
NC/33K
L930 L931
1000P
30R ADCVA 30R
C914
C9009
C9011
1U
1U
C9010
C9008
1U GND
0.1U
A
A
8 7 6 5 4 3 2 1
17953_533_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 61
1
F F
R72 CI_DV18 DV18-HDMI
GND DV33
EZJZ1V270RA
2
DV18-HDMI
L10
2
600R
L9
600R GND
D3V3L4
R21
D108
4K7
0.1U
1U
0.1U
0.1U
AV18-HDMI
C20
C21
C23
C22
1
C38
0.1U
0.1U
GND
1U
C42
C43
P901
0.1U
C39
DV33-HDMI CI_DV18 AV18-HDMI
1
RX2+
GND1 2
GND L11
3 R14 R15 R16 600R
RX2- R13
4K7 4K7 NC\4K7
RX1+ 4 4K7
R17 HPDIN
0.1U
5 100R
1U
E E
0.1U
GND2 R59
0.1U
0.1U
0.1U
0.1U
0.1U
C19
C11
C12
100R
C13
C14
C15
C16
C17
R20 OSDA1
RX1- 6 R18
4K7 100R OSCL1
7 R19 100R HDMI_5V
RX0+
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
GND3 8
R2X0-
R2X0+
AVCC33D
R2X1-
R2X1+
AGND8
R2X2-
R2X2+
AVDD18C
DSDA2
DSCL2
RPWR2
DVCC18B
DGND2
RSVDL
HPDIN
TSDA
TSCL
AGND9
TPWR/I2CADDR
9
R12
NC\4K7
RX0-
R11
DV33-HDMI
4K7
RXC+ 10
60 1 RX0_2
11 AGND7 TX2+
59 2 RX0_2B
GND4 58
RXC2+ TX2-
3
RXC2- AGND1 GND
RXC- 12 57 4 RX0_1 GND
D5V0S1
D5V0S1
D5V0S1
D5V0S1
AVCC18D TX1+ RX0_1B
56 5
C133
C134
C135
C136
10P
10P
10P
10P
13 CEC-IN HPD2 TX1-
D104
D105
D106
D107
R42 NC\0R 55 6
NC1 54
AVCC33C U904 AVCC18A
7 RX0_0
14 CEC-A TX0+
NC2 R41 NC\0R 53 8 RX0_0B
CEC-D TX0-
52 9
15 HDMI1_SCL RPWR1 SII9185 AGND2 RX0_C
51 10
DDCCLK 50
DSCL1 TXC+
11 RX0_CB
16 HDMI1_SDA DSDA1 TXC-
DDCDA 49 12 R31
AVDD18B EXTSWING
48 13 750R GND
17 R1X2+ RESET#
47 14
GND5 46
R1X2- LSDA
15
18 +5V_HDMI1 AGND6 LSCL
VCC 45 16
D R1X1+ HPD0
17
D
44
19 R1X1- AVCC18B DV33
43 18
HPD 42
AVCC33B R0XC-
19
R1X0+ R0XC+
41 20
R1X0- AGND3
I2CSEL/INT
AVCC18C
DVCC18A
AVDD18A
AVCC33A
+5V_HDMI1
R929
RPWR0
DGND1
AGND5
AGND4
DSDA0
R1XC+
DSCL0
R0X2+
R0X1+
R0X0+
R1XC-
R0X2-
R0X1-
R0X0-
R32
HPD1
GND
7K5
NC\4K7
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
R33 100R
RESET_N
T Z903
U906 R57
R34 NC\100R 1 8 4K7
R47
R48
47K
47K
OSDA0
NC\4K7
CEC DV33 A0 VCC
R35 NC\100R 2 7
R30
C41
0.1U
T
GND OSCL0 A1 WP
3 6 Z983 HDMI1_SCL
A2 SCL
4 5 HDMI1_SDA
GND SDA
4K7 AT24C02
P903 R51 T Z904 T Z901
DV33 T Z902
C GND C
1 +5V_HDMI0
RX2+ GND
GND1 2
3 R52
RX2- 4K7
RX1+ 4 R54 T Z908
4K7
5
R55
4K7
GND2 C U905
R56
R50
47K
6 Q2 1 8
R49
47K
RX1- BT3904 B A0 VCC 4K7
7 2 7
0.1U
T
E A1 WP
C40
RX0+
GND3 8 3 6 Z982 HDMI0_SCL
A2 SCL
GND
9 4 5 HDMI0_SDA
RX0- GND SDA
R53 100R
RXC+ 10 HDMI_SEL AT24C02
T Z907 T Z906 T Z905
11 GND
GND4
RXC- 12
13
B NC1
B
NC2 14
15 HDMI0_SCL
DDCCLK
DDCDA 16 HDMI0_SDA
17
GND5
18 +5V_HDMI0 R58
VCC
19 4K7
HPD
R928
7K5
GND
5
1
D3V3L4
A A
D109
GND
8 7 6 5 4 3 2 1
17953_534_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 62
12 SCT1_AUR_IN
F AIR F
AOL 2 SCT1_AUL_OUT R968
75R C967
13 47P C969
AGND
1U
BGND 3 GND_SV
14 SCT1_AUL_IN
AIL
B 4 SCT1_B_IN GND C971
L904 R969
SCT1_G_IN 68R 0.01U
15 SCT1_FS_IN 30R Y0P
SWITCH
GGND 5
1
R971
CLKOUT 16 75R C970
R60
G 6 SCT1_G_IN 16P
E R972 C972 E
EZJZ1V270RA 100R 0.01U
Y0N
GND
17
DATA
RGND 7
R973 C974
L905
2
GND 0.01U
18 SCT1_B_IN 30R 68R PB0P
DATAGND
SCT1_R_IN
R 8
STC1_FB_IN R975
1
19
BLNK 75R C973
VGND 9 16P
R61 R974 C975
20 100R 0.01U
GND
BLNKGND PBR0N
EZJZ1V270RA
VOUT 10 SCT1_AV_OUT T Z920
D T Z928 R976 D
21 SCT1_AV_IN T Z923 75R C976
VIN T Z919 GND
2
T Z918 16P R977 C977
SHIELD 11 T Z922 L906
68R 0.01U
T Z927 SCT1_R_IN 30R PR0P
1
R978 C978
1
R63 R64 100R 0.047U
SC0
EZJZ1V270RA
R62
SCT1_AUR_OUT
2
SCT1_AUL_OUT
EZJZ1V270RA
1
EZJZ1V270RA
2
GND R67 R68
C EZJZ1V270RA C
EZJZ1V270RA
2
GND GND
2
GND NEARLY MT5335
R964 C965
L1 1U
R963 SCT1_AUR_IN 30R 10K
L907 SCT_R
STC1_FB_IN 30R 0R SOY0
R965 C966
L2 1U
30R 10K SCT_L
1
SCT1_AUL_IN
C979 R960
75R R966 R967
B 470P C963 C964 10K B
R65 10K
470P 470P
EZJZ1V270RA
2
C980 R962
470P 10K GND
A
A
2
R66
GND
EZJZ1V270RA
8 7 6 5 4 3 2 1
17953_535_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 63
0.01U
R9003 SY1 126
1U
SY1
C003
C004
10K SC1 125 141 AVDD25_VADC
F R918 SC1 AVDD25_VADC F
142 GND
CVBS_OUT 0R AVSS25_VADC
137 AVDD25_REF
D2SA AVDD25_REF
136 138 GND
D2SA AVSS25_REF
C001 BC847C 135 AVDD25_VFE
R919 R920 GND C
AVDD25_VFE
134 GND
47U Q815 AVSS25_VFE
D2SA NC 1K
B
CI_GPIO14
6V3 E R9004 R924
75R SCT1_AV_OUT 0R
R921 MT5335PKU
R923 C
4K7
C002
0R Q906 B
47P
R9002 BC847C
E
R9001
10K
470R
R944
4K7
E E
GND GND
AV25
9
Nearly Connector Nearly 5335 AV25
L911
T Z975 R946 C959 600R DVDD25_VADC
7 L915 0.047U
30R 100R
P902
SY1
C954
1
C916
5 1U 0.1U
D R70 R947 AV25 D
T 75R C958
EZJZ1V270RA 47P AV25
Z974 L912 GND
6 2 600R AVDD25_VADC
8
C917 C955
GND R948 C961 1U 0.1U
L916 0.047U AV25
30R 100R SC1
GND AV25
L913 GND
1
600R AVDD25_REF
R949
R69 C960
75R
EZJZ1V270RA C918 C956
47P
1U 0.1U
C C
2
AV25
AV25
L914
GND 600R GND
AVDD25_VFE
Z980 Z981
T T
R9010 C9001 C957
L926 C919
P902 10K 1U
4 30R AIN2_L 0.1U
1U
WHITE
R9009 C9002
L927 1U
3 30R 10K AIN2_R
RED
2 GND
YELLOW R9012 R9011
1 C9004 C9003 10K
10K
470P 470P
EZJZ1V270RA
B B
R71
GND
1 2
GND
R9013 C9006
L928 0.047U
30R 100R CVBS2
T R9014
75R C9007
Z976 A
47P C915
A 1U GND_CVBS
T
GND
Z978
8 7 6 5 4 3 2 1
17953_536_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 64
RED 4 U203
YPBPR_R_IN
R982
5 75R C731 SOY0 107 117 DVDD12_VGA
BLUE PB_IN SOY0 DVDD12_VGA
Y0P 108 113 GND
6 16P Y0P AVSS12_RGBADC
R983 C729 Y0N 109
Y0N AVDD12_RGBADC
110 AVDD12_RGBADC
100R 0.01U Y1N PB0P 114
PB0P AVSS12_RGBFE
105 GND
PBR0N 115 101 AVDD12_RGBFE
RED PBR0N AVDD12_RGBFE
PR0P 116
PR_IN PR0P RP
SOY1 118 104
7 SOY1 RP
GND Y1P 119 106 RN
Y1N Y1P RN
120 98 BP
VGA_R_IN Y1N BP BN
PB1P 121 99
E 10 PB1P BN E
PBR1N 122 102 GP
VGA_L_IN C726 PBR1N GP
R986 PR1P 123 103 GN
T Z939
L5 0.01U PR1P GN
9 PB_IN 30R 68R PB1P 96 VSYNC
T Z940
VSYNC
112 97 HSYNC
P907 8 TN1 HSYNC SOG
111 100
TP1 SOG
R985
75R C727 MT5335PKU
16P C725
R987
100R 0.01U PBR1N AV12
1
R74 AV12
L909
R77 600R
EZJZ1V270RA EZJZ1V270RA DVDD12_VGA
GND
R989 C723
D L6 C987 C988 D
2
C989 C990
1U 0.1U
GND
AV12
T Z929
AV12
L3 GND
C C
C732 600R AVDD12_RGBFE
R979
0.1U 100R ASPDIF
P904 2 SPDIF_OUT
C991 C992
BLACK
0.1U
1
1 1U
R980
C993 100R
33P GND
2
R73
EZJZ1V270RA GND
B B
R990 C721
L8 1U
YPBPR_L_IN 30R 10K YPBPR_L
R991 C720
L7 1U
YPBPR_R_IN 30R 10K YPBPR_R
R992 R993
C719 C722 10K
10K
470P 470P
A
A
GND
8 7 6 5 4 3 2 1
17953_537_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 65
Z973 T
T Z941
T Z942 C712 VGA_PLUGPWR
R998
T Z943 4700P
F P908 T Z944 Nearly Connector 0R SOG F
T Z946
T Z948 C996
16 T Z947
T Z955 R719 C714 0.1U R715
L918 0.01U 10K
5 GREEN 30R 33R GP U903
1 8
Z972 T
15 VGASCL_IN A0 VCC
2 7 W/P
Z971 T
10 R996 A1 WP
R716 C715 VGASCL
75R 3 6
Z970 T
4 W/P_CTR 0R W/P A2 SCL
16P
4 5 VGASDA
14 VSYNC_IN VGA_PLUGPWR GND SDA
R997 C713
3 0.01U AT24C02
9 +5V 100R GN
1 2
3 BLUE D913 R720 C710
E BAV70 L919 0.01U E
BLUE 30R GND 33R BP
13 HSYNC_IN C005
GND
VGASDA_IN
ESD_0402
VGASCL_IN
8 5VSB
2 GREEN
R999 C711
12 VGASDA_IN GND 75R 5VSB
16P
7 R701 C709
100R 0.01U R712 R714 R713
BN 100R 10K 100R
1 RED
11 R721 C707
L920 0.01U
RED 33R RP
EZJZ1V270RA
EZJZ1V270RA
30R
C143ZT
C143ZT
GND
Q903
Q904
6
1
1
D U0TX U0RX D
17
E
C
C
R702
C708
75R
B
R86
16P
R84
2
2
R703 C706
GND 0.01U RN
100R SW_UPDATE_CTL1 C
R85
Q905
B C143ZT
GND
EZJZ1V270RA
E
GND R725
10K
T Z949
C T Z950 C
R704 C702
L924 1U 5VSB
30R 10K VGA_R
VGA_R_IN GND
R705 C701
L923 1U 5VSB
VGA_L_IN 30R 10K
VGA_L 5VSB
5VSB
R706 R707 R708 R710
C999 C703 10K 10K 10K 10K
470P 470P
R709 R711
B VGASCL_IN 100R VGASDA_IN 100R VGASDA
B
VGASCL
1
1
GND C997
R80 R81 16P
C998
L921 L922
HSYNC_IN 30R HSYNC VSYNC_IN 30R VSYNC EZJZ1V270RA 16P EZJZ1V270RA
2
2
1
1
R718
R717
C705 C704
22K
22K
R82 R83
10P 10P GND
EZJZ1V270RA EZJZ1V270RA GND
A
2
GND
GND
8 7 6 5 4 3 2 1
17953_538_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 66
GND
R294
100R C014 P205
T_R3 1 8 R3 10P C2010
C2202 10P C015 40 39 0.1U
C2004 C2007 C2015 T_R2 2 7 R2
C2001 C2006
T_R1 10P C016 38 37
3 6 R1
T_R0 10P C017 R1 36 35 R0
4 5 R0
R295 R3 34 33 R2
0.1U 0.01
0.1U 100R 10P C018
E T_G7 1 8 G7 R5 32 31 R4 E
0.1U 0.1U
GND T_G6 10P C019 R7 R6
2 7 G6 30 29
10P C020
T_G5 3 6 G5 28 27
10P C021 G0
T_G4 4 5 G4 G1 26 25
DV33A_LVDS_RECEIVER G3 G2
R296 24 23
U207 100R 10P C022 G5
T_G3 1 8 G3 22 21 G4
T_B5 1 56
RXOUT22 VCC4 T_G2 10P G7 G6
2
RXOUT23 RXOUT21
55 T_B4 2 7 G2 C023 20 19
T_HSYNC 3 54 T_B3
RXOUT24 RXOUT20 53 T_B2 T_G1 10P C4 18 17
4 3 6 G1
T_VSYNC GND1 RXOUT19 52
5
T_DE 6
RXOUT25 GND5 51 T_B1 T_G0 10P C024 B1 16 15 B0
RXOUT26 RXOUT18 4 5 G0
D T_R6 7 50 T_B7 D
RXOUT27 RXOUT17 49 T_B6 R298 B3 14 13 B2
8
AN00 LVDSGND1 RXOUT16 48 100R
9 10P C025
AP00 10
RXIN0- VCC3 47 T_B0 T_B7 1 8 B7 B5 12 11 B4
AN11 RXIN0+ RXOUT15 46 T_G5
11 C026
RXIN1- RXOUT14 45 T_B6 2 7 B6 10P B7 10 9 B6
AP11 12 T_G4
RXIN1+ RXOUT13 44
13 T_B5
14
LVDSVCC1 GND4 43 T_G3 3 6 B5 10P C027 8 7
AN22 LVDSGND2 RXOUT12 42 T_G7
15 10P C028
AP22 16
RXIN2- RXOUT11 41 T_G6 T_B4 4 5 B4 D_HSYNC 6 5 D_VSYNC
RXIN2+ RXOUT10 40
CLK11- 17
CLK11+ RXCLKIN- VCC2 39 T_G2 4 3 PANEL_CTL2
18 R299
AN33 RXCLKIN+ RXOUT9 38
19 T_G1 100R 10P C029
AP33 RXIN3- RXOUT8 37 T_G0 T_B3 DE 2 1 CLK
20 1 8 B3
RXIN3+ RXOUT7 36
21
LVDSGND3 GND3 T_B2
22
PLLGND1 RXOUT6
35 T_R5 2 7 B2 10P C030
23 34 T_R7
PLLVCC1 RXOUT5 T_B1 B1 C031
C 24 33 T_R4 3 6 10P C
PWRDN PLLGND2 RXOUT4 32
25 T_R3
PWRDWN RXOUT3 31 T_B0 B0 10P
T_CLK
GND
26 4 5 C032
RXCLKOUT VCC1 30 T_R2
T_R0 27
RXOUT0 RXOUT2 29
28 T_R1
GND2 RXOUT1 R290 GND
100R
V386 1 8
T_DE 2 7 DE
DV33A R292
L239
T_CLK 120R 33R CLK
B B
DV33A C2011
16P
R291
10K
R23
100R GND
AN00 AP00
PWRDN
R24
AN11 100R AP11 C
PWRDN_EN Q5
B C143ZT
R2003
AN22 100R AP22 E
R2004 A
CLK11- 100R CLK11+ GND
A
R2005
AN33 100R AP33
8 7 6 5 4 3 2 1
17953_539_090330.eps
090331
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 67
17953_600_090330.eps
090330
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 68
17953_601_090330.eps
090330
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 69
R602 K605
1K vol+ 1 3
2 4
P601
R701 R603 menu K604
5VIN 1 3
4 0 1K5
2 4
3 5VSB
R604 K603
ch- 1 3
2GND 2K7
2 4
KEY R605 K602
1 ch+ 1 3
4K3
2 4
0.1U
R606 K601
C601
1 3
7K5 POWER
2 4
I_17930_031.eps
250408
I_17930_032.eps
220408
E_06532_012.eps
131004
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 70
Inverter Panel
1 2 3 4 5 6 7 8
I INVERTER I
T1 CN2
CN1 F1 4 7
5A 1
1 C28 2
2 10pF
C1 R17
3 C3
220uF/25V 100(1206) 1
4 220uF/25V 6
5 C35 C36 C37
6 471
Q4 222 NC
DTA143 D17 BAV99
O/S 1
R50
820
D D
R24 R4 IC-Vcc
K
5.6K
NC FB
Q1 C14 ZD1
C4 105 8.2V
104 DTC143 D9 C21
C20
A
225(1206) C
R34 225(1206)
22K 4
T2 7
BAW56K C29 D23
C16 U2 10pF BAV99
4 5
G2 D2
R42 10 1
R5 C5 6 C39
223 3 6
S2 D2
B
C53 C38
47K 105 471
2 7 222 NC
G1 D1
R43 10 CN3
R31 1
D7 R35 1 8
NC C22 S1 D1 D21 2
150
2222 3
105 4
D10 1N4148 BAV99
U1 O/S2 5
R6 D
1 16 C15 CON5
270K C6 R20 R19 R18 R54
K
2 15 100K 100K 100K 103
105 ZD2
Q7 820
R2 0 R30 4.3V
3 14 2907
560 FB D27
4 13 BAV99
A
O/S
5 12 D11 4 T3 7
R36 C30
6 11 R21
R7 C7 C8 22K 10pF
22
R8 R9 7 10 1
A
20K 681 NC BAW56K 6 C42
33k 16k
8 9 C17 U3 C40 C41 D18
471
4 5 NC BAV99
G2 D2 222
C O/S 3 C
R44 10
223 3 6
S2 D2 R51
2 7 820
R22 G1 D1
R45 10
C9 C10 R37 1 8
331 NC 22 S1 D1
150 C23
FB
105
D12 1N4148
Q2
2N7002 D24
R12
100 BAV99
T4
4 7
R56 R33 D8 C31
2K NC 10pF
B
R26 NC 2222
1
6
C11 103 C51
D4 C49 C50
471
NC
R23 0 222
R11 3K FB CN4
K
ZD3 1
R13 C12 R25 R57 Q8
R32 4.3V 2
NC 104 1K 2907
BAV99 4.7K 560 3
D19 O/S 4 4
A
R52 5
BAV99 820 CON5
CN5
D15 4 T6 7
1
R58 R40 C33 2
10K 22K 10pF
IC-Vcc
R601K Q11 1
6
BAW56K
C45
2222 C19 U5 C43 C44
D1/NC R10 R27 471
R59 C56 4 5 222 NC
1M D5 100 G2 D2
O/S 1 1N4148 30K 104 R48 10 C
Q5 223 3 6
S2 D2
DTA143 O/S 6
O/S 2
R15 2 7
R14 G1 D1 D22 R55
BAW56K 100K R49 10
1M R41 1 8
D2/NC 150
S1 D1 BAV99 820
C27
O/S 3 105
D16 1N4148 FB
Q6
O/S 4
A R1 2N7002 A
BAW56K 300K
Q3 D6
D3/NC
2222 O/S
O/S 5
R3 1N4148
100K C13 C34 R29
O/S 6 R16 NC
1M\NC
BAW56K 105 105
I_17930_035.eps
220408
1 2 3 4 5 6 7 8
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 71
I_17930_036.eps
220408
I_17930_037.eps
220408
Circuit Diagrams and PWB Layouts TCM2.0E LA 7. 72
IR LED Panel
G1
VCC
GND
100R
100R
R6
R5
10U
C1
4K7
R9
P1 R7
+5V 4K7
5
4 IR
6V3
C3
R3
47U
10U
3 GND
C2
1K
2 LED1
1 LED2
R1 C
4K7 R4
Q1 E
B 3K3
B
BT3904 E Q2
C BT3906
D3
1 3 D1
R51
4K7
R2
4K7 R W
R52 C 2
4K7 Q5
B
BT3904 E
I_17930_033.eps
220408
E_06532_012.eps
I_17930_034.eps 131004
220408
Alignments TCM2.0E LA 8. EN 73
8. Alignments
Index of this chapter: Table 8-2 Alignment for 26" with a colour analyser
8.1 Electrical Alignments
8.2 Hardware Alignments Cool (11000K) Normal (9000K) Warm (6500K)
8.3 Software Alignments
x (70 IRE) 0.278 +/- 0.003 0.289 +/- 0.003 0.314 +/- 0.003
y (70 IRE) 0.278 +/- 0.003 0.291 +/- 0.003 0.319 +/- 0.003
Note:
The Service Modes are described in chapter 5. Menu
navigation is done with the CURSOR UP, DOWN, LEFT or 8.3.2 Display Code
RIGHT keys of the remote control transmitter.
When after an SSB or display exchange, the display option
code is not set properly; it will result in a TV with “no display” or
8.1 Electrical Alignments
strange resolution.
Therefore, it is required to set this display option code after
Perform all electrical adjustments under the following such a repair.
conditions: To do so, press (slowly) the following key sequence on a
• Power supply voltage (depends on region): standard RC transmitter: “062598” directly followed by
– AP-NTSC: 120 VAC or 230 VAC / 50 Hz (± 10%). “MENU” and “xxx”, where “xxx” is a 3 digit decimal value of
– AP-PAL-multi: 120 - 230 VAC / 50 Hz (± 10%). the panel type: see column “Display code” in table below.
– EU: 230 VAC / 50 Hz (± 10%). When ready, the set will go to stand-by.
– LATAM-NTSC: 120 - 230 VAC / 50 Hz (± 10%). After this, perform a cold start.
– US: 120 VAC / 60 Hz (± 10%).
• Connect the set to the mains via an isolation transformer LCD Panel: Display Code:
with low internal resistance.
AUO 19” 096
• Allow the set to warm up for approximately 60 minutes.
• Measure voltages and waveforms in relation to correct CMO 19” - M190Z1-L01 094
ground (e.g. measure audio signals in relation to LG 20” - LC201V02-SDD1 093
AUDIO_GND). AUO 22” 097
Caution: It is not allowed to use heatsinks as ground. CMO 22” - M220Z1-L03 022
• Test probe: Ri > 10 MΩ, Ci < 20 pF.
AUO 26” - T260XW03 V3 030
• Use an isolated trimmer/screwdriver to perform
alignments. AUO 26” VM 098
CMO 26” 095
Not applicable.
Table 8-1 Alignment for 19", 20", and 22" with colour
analyser
9.1 Introduction
This chassis is a digital derivative from the TCM1.0E LA The platform is also designed for the lowest power
chassis and supports DVB-T reception. It uses the Mediatek consumption in off/stand-by mode (<0.3W) to fulfil new Philips
MT5335 main chip. It processes the following input/output CE environment policy requirement.
signals: The MT5335 is surrounded by a tuner, a video demodulator, a
• Analog and digital RF signals (PAL B/G, D/K, I, SECAM B/ HDMI interface, SDR and flash memory, an audio amplifier,
G, D/K, L/L’, DVB-T) and optionally a stand-by microprocessor (26"). For the smaller
• SCART input signals (CVBS & RGB) set versions also the inverter board is serviceable.
• CMP input signals (YPbPr)
• VGA input signals For the block diagram, refer also to chapter 6 “Block diagrams,
• HDMI input signals, v1.2 compliant, with HDCP, audio Test Point Overviews, and Waveforms”.
included as EIA-861B standard
• S-Video input
• Headphone output
• SPDIF output.
I_17951_012.eps
060808
half the number of the total amount of 3.575612 MHz and PAL N= 3.582056
lines. The fields are written in “pairs”, MHz)
causing line flicker. PCB Printed Circuit Board (same as “PWB”)
IR Infra Red PCM Pulse Code Modulation
IRQ Interrupt Request PDP Plasma Display Panel
ITU-656 The ITU Radio communication Sector PFC Power Factor Corrector (or Pre-
(ITU-R) is a standards body conditioner)
subcommittee of the International PIP Picture In Picture
Telecommunication Union relating to PLL Phase Locked Loop. Used for e.g.
radio communication. ITU-656 (a.k.a. FST tuning systems. The customer
SDI), is a digitized video format used can give directly the desired frequency
for broadcast grade video. POR Power On Reset, signal to reset the uP
Uncompressed digital component or Progressive Scan Scan mode where all scan lines are
digital composite signals can be used. displayed in one frame at the same
The SDI signal is self-synchronizing, time, creating a double vertical
uses 8 bit or 10 bit data words, and has resolution.
a maximum data rate of 270 Mbit/s, PTC Positive Temperature Coefficient,
with a minimum bandwidth of 135 non-linear resistor
MHz. PWB Printed Wiring Board (same as “PCB”)
ITV Institutional TeleVision; TV sets for PWM Pulse Width Modulation
hotels, hospitals etc. QRC Quasi Resonant Converter
JOP Jaguar Output Processor QTNR Quality Temporal Noise Reduction
LS Last Status; The settings last chosen QVCP Quality Video Composition Processor
by the customer and read and stored RAM Random Access Memory
in RAM or in the NVM. They are called RGB Red, Green, and Blue. The primary
at start-up of the set to configure it color signals for TV. By mixing levels
according to the customer's of R, G, and B, all colors (Y/C) are
preferences reproduced.
LATAM Latin America RC Remote Control
LCD Liquid Crystal Display RC5 / RC6 Signal protocol from the remote
LED Light Emitting Diode control receiver
L/L' Monochrome TV system. Sound RESET RESET signal
carrier distance is 6.5 MHz. L' is Band ROM Read Only Memory
I, L is all bands except for Band I R-TXT Red TeleteXT
LORE LOcal REgression approximation SAM Service Alignment Mode
noise reduction S/C Short Circuit
LPL LG.Philips LCD (supplier) SCART Syndicat des Constructeurs
LS Loudspeaker d'Appareils Radiorécepteurs et
LVDS Low Voltage Differential Signalling Téléviseurs
Mbps Mega bits per second SCL Serial Clock I2C
M/N Monochrome TV system. Sound SCL-F CLock Signal on Fast I2C bus
carrier distance is 4.5 MHz SD Standard Definition
MIPS Microprocessor without Interlocked SDA Serial Data I2C
Pipeline-Stages; A RISC-based SDA-F DAta Signal on Fast I2C bus
microprocessor SDI Serial Digital Interface, see “ITU-656”
MOP Matrix Output Processor SDRAM Synchronous DRAM
MOSFET Metal Oxide Silicon Field Effect SECAM SEequence Couleur Avec Mémoire.
Transistor, switching device Color system mainly used in France
MPEG Motion Pictures Experts Group and East Europe. Color carriers=
MPIF Multi Platform InterFace 4.406250 MHz and 4.250000 MHz
MUTE MUTE Line SIF Sound Intermediate Frequency
NC Not Connected SMPS Switched Mode Power Supply
NICAM Near Instantaneous Compounded SoC System on Chip
Audio Multiplexing. This is a digital SOG Sync On Green
sound system, mainly used in Europe. SOPS Self Oscillating Power Supply
NTC Negative Temperature Coefficient, S/PDIF Sony Philips Digital InterFace
non-linear resistor SRAM Static RAM
NTSC National Television Standard SRP Service Reference Protocol
Committee. Color system mainly used SSB Small Signal Board
in North America and Japan. Color STBY STand-BY
carrier NTSC M/N= 3.579545 MHz, SVGA 800x600 (4:3)
NTSC 4.43= 4.433619 MHz (this is a SVHS Super Video Home System
VCR norm, it is not transmitted off-air) SW Software
NVM Non-Volatile Memory: IC containing SWAN Spatial temporal Weighted Averaging
TV related data such as alignments Noise reduction
O/C Open Circuit SXGA 1280x1024
OSD On Screen Display TFT Thin Film Transistor
OTC On screen display Teletext and THD Total Harmonic Distortion
Control; also called Artistic (SAA5800) TMDS Transmission Minimized Differential
P50 Project 50: communication protocol Signalling
between TV and peripherals TXT TeleteXT
PAL Phase Alternating Line. Color system TXT-DW Dual Window with TeleteXT
mainly used in West Europe (color UI User Interface
carrier= 4.433619 MHz) and South uP Microprocessor
America (color carrier PAL M= UXGA 1600x1200 (4:3)
Circuit Descriptions, Abbreviation List, and IC Data Sheets TCM2.0E LA 9. EN 77
This section shows the internal block diagrams and pin layouts
of ICs that are drawn as "black boxes" in the electrical diagrams
(with the exception of "memory" and "logic" ICs).
Block Diagram
Pin Configuration
I_17950_048.eps
080808
Block Diagram
Component
TS CVBS/ Analog HDMI Tuner Audio
Panel 16-bit DDR
In YC Input Input Rx In Input
DRAM Bus
IO Bus
CKGEN
Audio DSP
JTAG IrDA Serial IF USB2.0 Watchdog Serial Flash Servo ADC
Audio I/F
Audio DAC BScan PCR RTC UART MS,SD,SM,xD PWM NAND Flash
I_17950_049.eps
SPDIF, I2S 090508
Block Diagram
I_17950_050.eps
090508
Block Diagram
H_17370_074.eps
100807
CAGC(neg) CBL
VIF2 2 (31)
SOUND CARRIER (18) 17 CVBS
VIF1 1 (30) VIF-PLL TRAPS
4.5 to 6.5 MHz video output: 2 V (p-p)
[1.1 V (p-p) without trap]
TDA9885
TDA9886
(7) 8 AUD
SINGLE REFERENCE QSS MIXER audio output
SIF2 24 (27) AUDIO PROCESSING
INTERCARRIER MIXER AND SWITCHES (3) 5 DEEM
AND AM DEMODULATOR
SIF1 23 (26)
de-emphasis
network
MAD
(4) 6 AFD
CAGC
Block Diagram
RxIN0+ 8
RED
RxIN0- 8
GREEN
RxIN1+ 8
BLUE
RxOUT0..27
RxIN1-
LVDS to TTL
RxIN2+ De-serializer HSYNC
RxIN2- VSYNC
RxCLKIN+
PLL RxCLKOUT
RxCLKIN-
PWRDWN
V386
Pin Configuration
RxOUT22 1 56 VCC
RxOUT23 2 55 RxOUT21
RxOUT24 3 54 RxOUT20
GND 4 53 RxOUT19
RxOUT25 5 52 GND
RxOUT26 6 51 RxOUT18
RxOUT27 7 50 RxOUT17
LVDS_GND 8 49 RxOUT16
RxIN0- 9 48 VCC
RxIN0+ 10 47 RxOUT15
RxIN1- 11 46 RxOUT14
RxIN1+ 12 45 RxOUT13
LVDS_VCC 13 44 GND
LVDS_GND 14 43 RxOUT12
RxIN2- 15 42 RxOUT11
RxIN2+ 16 41 RxOUT10
RxCLKIN- 17 40 VCC
RxCLKIN+ 18 39 RxOUT9
RxIN3- 19 38 RxOUT8
RxIN3+ 20 37 RxOUT7
LVDS_GND 21 36 GND
PLL_GND 22 35 RxOUT6
PLL_VCC 23 34 RxOUT5
PLL_GND 24 33 RxOUT4
PWRDWN 25 32 RxOUT3
RxCLKOUT 26 31 VCC
RxOUT0 27 30 RxOUT2
GND 28 29 RxOUT1
56-pin TSSOP
V386
I_17950_051.eps
090508
I_17930_073.eps
250408
Block Diagram
32K Oscillator
2nd SIIC
RTC
3rd SIIC
RC
Oscillator
HV DPMS
Detector
Key Pad ADC
Interrupt
Reset Processor
Processor
IR Detector
Clock
Processor
PWM
Clock off &
Wake Up
4 IRQ
Watchdog Processor
timer
GPIO
Processor
Pin Configuration
32KOSCO 1 24 VDD_RTC
32KOSCO 1 20 VDD_RTC 32KOSCI 2 23 VDD
32KOSCI 2 19 VDD VSS 3 22 GPIOA0/AD0
VSS 3 18 GPIOA0/AD0 NRST 4 21 GPIOA1/AD1
NRST 4 17 GPIOA3/AD3/IR PWM1/GPIOC1 5 20 GPIOA2/AD2
PWM1/GPIOC1 5 WT6702F_S200 16 GPIOA4/SCL3/P1.0 PWM0/GPIOC0 6 WT6702F_S240 19 GPIOA3/AD3/IR
RXD/IRQ3/GPIOB7 6 15 GPIOA5/SDA3/P1.1 RXD/IRQ3/GPIOB7 7 18 GPIOA4/SCL3/P1.0
TXD/IRQ2/GPIOB6 7 14 GPIOA6/SCL1 TXD/IRQ2/GPIOB6 8 17 GPIOA5/SDA3/P1.1
HIN/GPIOB5 8 13 GPIOA7/SDA1 HIN/GPIOB5 9 16 GPIOA6/SCL1
VIN/GPIOB4 9 12 GPIOB0/SCL2 VIN/GPIOB4 10 15 GPIOA7/SDA1
IRQ1/P1.3/GPIOB3 10 11 GPIOB1/SDA2 IRQ1/P1.3/GPIOB3 11 14 GPIOB0/SCL2
IRQ0/P1.2/GPIOB2 12 13 GPIOB1/SDA2
I_17950_052.eps
090508
Block Diagram
additional 4Kb
Address
X-Decoder
Generator
Memory Array
SI Data
Register
Y-Decoder
SRAM
Buffer
Sense Output
Mode State Amplifier Buffer
CS#, ACC, Logic Machine HV
WP#,HOLD# Generator
SO
Pin Configuration
HOLD# 1 16 SCLK
VCC 2 15 SI
NC 3 14 PO6
PO2 4 13 PO5
PO1 5 12 PO4
PO0 6 11 PO3
CS# 7 10 GND
SO/PO7 8 9 WP#/ACC
Block Diagram
VCC
470μF 100nF
3 13
0.22μF
4
IN1 + 1 OUT1+
-
ST-BY 7
S-GND
9 - 2 OUT1-
Vref
+
0.22μF
12
IN2 + 15 OUT2+
-
MUTE 6
- 14 OUT2-
PW-GND
8 +
Pin Configuration
15 OUT2+
14 OUT2-
13 VCC
12 IN2
11 N.C.
10 N.C.
9 S-GND
8 PW-GND
7 ST-BY
6 MUTE
5 N.C.
4 IN1
3 VCC
2 OUT1-
1 OUT1+
I_17950_054.eps
090508