VHDL Suma Con Carry

JESSICA LORENA CASTILLO
CAMILO HERNANDEZ TABET
NATALIA MORALES VARÓN
VHDL DEL SUMA CON CARRY
No se que parte del procesador es esta. Si es parte de la ALU, no entiendo por qué utilizan
flip-flop. La ALU es un circuito combinatorio.
Si son dos bloques, el sumador y un registro, me preocupa porque no se como se conecta
con el resto de bloques.
Y finalmente, es preferible usar una entidad full adder y hacer 16 instancias.
--******************************************************--
-- PONTIFICIA UNIVERSIDAD JAVERIANA --
-- ORGANIZACIÓN DE COMPUTADORES --
-- Seccion de Tecnicas Digitales --
-- Título: --
-- Fecha: --
--******************************************************--
--Definicion de las bibliotecas
library IEEE;
use IEEE.std_logic_1164.all;
library ALTERA;
use ALTERA.altera_primitives_components.all;
--******************************************************--
-- Comentarios --
-- --
-- --
--******************************************************--
entity Jmmm is
port(
--DECLARACION DE ENTRADAS Y SALIDAS DEL BLOQUE
enable: in std_logic;
Clk: in std_logic;
Reset: in std_logic;
Reg_a: in std_logic_vector (15 downto 0);
Reg_b: in std_logic_vector (15 downto 0);
Carry_in: in std_logic;
A: out std_logic_vector (15 downto 0);
Carry_out: out std_logic
);
end Entity Jmmm;
architecture JmmmArch of Jmmm is
component dffe is
port(
d, clk, clrn, prn, ena : in std_logic;
q : out std_logic
);
end component dffe;
signal Carry: std_logic_vector (15 downto 0);
signal Sum,Q: std_logic_vector (15 downto 0);
begin
Sum(0)<= ((not Reg_a(0) and (Reg_b(0) xor Carry_in)) or (Reg_a(0) and not (Reg_b(0) xor Carry_in))) and
enable;
Carry(0)<= ((Carry_in and (Reg_a(0) xor Reg_b(0))) or (Reg_a(0) and Reg_b(0))) and enable;
Sum(1)<= ((not Reg_a(1) and (Reg_b(1) xor Carry(0))) or (Reg_a(1) and not (Reg_b(1) xor Carry(0)))) and
enable;
Carry(1)<= ((Carry(0) and (Reg_a(1) xor Reg_b(1))) or (Reg_a(1) and Reg_b(1))) and enable;
enable;
enable;
enable;
enable;
enable;
Carry(6)<= ((Carry(5) and (Reg_a(6) xor Reg_b(6))) or (Reg_a(6) and Reg_b(6)));
enable;
enable;
enable;
Sum(10)<= ((not Reg_a(10) and (Reg_b(10) xor Carry(9))) or (Reg_a(10) and not (Reg_b(10) xor Carry(9))))
and enable;
Sum(11)<= ((not Reg_a(11) and (Reg_b(11) xor Carry(10))) or (Reg_a(11) and not (Reg_b(11) xor
Carry(10)))) and enable;
df0: dffe port map(Sum(0),Clk,not Reset,'1',enable,Q(0));

A<=Q;
Carry_out<=Carry(15);
End JmmmArch;

VHDL CON CARRY CORRECCIÓN
--******************--
--******************--
library IEEE;
library ALTERA;
--******************--
-- Comentarios --
-- --
-- --
--******************--
entity Suma is
port(
Reg_a: in std_logic;
Reg_b: in std_logic;
Sum: out std_logic;
Carry: out std_logic
);
end Entity Suma;
architecture SumaArch of Suma is
begin
Sum<= ((not Reg_a and (Reg_b xor Carry_in)) or (Reg_a and not (Reg_b xor Carry_in)));
Carry<= ((Carry_in and (Reg_a xor Reg_b)) or (Reg_a and Reg_b));
End SumaArch;
--******************--
--******************--
library IEEE;
library ALTERA;
--******************--
-- Comentarios --
-- --
-- --
--******************--
entity Suma is
port(
Reg_a: in std_logic;
Reg_b: in std_logic;
Sum: out std_logic;
Carry: out std_logic
);
end Entity Suma;
architecture SumaArch of Suma is
begin
Sum<= ((not Reg_a and (Reg_b xor Carry_in)) or (Reg_a and not (Reg_b xor Carry_in)));
Carry<= ((Carry_in and (Reg_a xor Reg_b)) or (Reg_a and Reg_b));
End SumaArch;
Fecha: 07/05/2020
VHDL DEL SUMA Y RESTA CON CARRY

--******************--
--******************--
library IEEE;
library ALTERA;
--******************--
-- Comentarios --
-- --
-- --
--******************--
entity Jmmm is
port(
Reg_a: in std_logic_vector (15 downto 0);
Reg_b: in std_logic_vector (15 downto 0);
Resta: in std_logic;
A: out std_logic_vector (15 downto 0);
Carry_out: out std_logic
);
end Entity Jmmm;
architecture JmmmArch of Jmmm is
signal Carry: std_logic_vector (15 downto 0);

signal Sum,aux1,aux2: std_logic_vector (15 downto 0);
begin
twoscomplement: entity work.A2COMPLEMENT

PORT MAP ( a =>
Reg_b,
INVERT =>
aux1
);
aux2<=Reg_b when(Resta = '0') else

aux1;
S0: entity work.Suma

PORT MAP(
Reg_a => Reg_a(0),
Reg_b => aux2(0),
Carry_in => '0',
Sum => Sum(0),
Carry => Carry(0)
);
PORT MAP(
Reg_a => Reg_a(1),
Reg_b => aux2(1),
Carry_in => Carry(0),
Sum => Sum(1),
Carry => Carry(1)
);

PORT MAP(
Reg_a => Reg_a(2),
Reg_b => aux2(2),
Sum => Sum(2),
Carry => Carry(2)
);

PORT MAP(
Reg_a => Reg_a(3),
Reg_b => aux2(3),
Sum => Sum(3),
Carry => Carry(3)
);

PORT MAP(
Reg_a => Reg_a(4),
Reg_b => aux2(4),
Sum => Sum(4),
Carry => Carry(4)
);

PORT MAP(
Reg_a => Reg_a(5),
Reg_b => aux2(5),
Sum => Sum(5),
Carry => Carry(5)
);

PORT MAP(
Reg_a => Reg_a(6),
Reg_b => aux2(6),
Sum => Sum(6),
Carry => Carry(6)
);

PORT MAP(
Reg_a => Reg_a(7),
Reg_b => aux2(7),
Sum => Sum(7),
Carry => Carry(7)
);

PORT MAP(
Reg_a => Reg_a(8),
Reg_b => aux2(8),
Sum => Sum(8),
Carry => Carry(8)
);

PORT MAP(
Reg_a => Reg_a(9),
Reg_b => aux2(9),
Sum => Sum(9),
Carry => Carry(9)
);

PORT MAP(
Reg_a => Reg_a(10),
Reg_b => aux2(10),
Sum => Sum(10),
Carry => Carry(10)
);
PORT MAP(
Reg_a => Reg_a(11),
Reg_b => aux2(11),
Sum => Sum(11),
Carry => Carry(11)
);

PORT MAP(
Reg_a => Reg_a(12),
Reg_b => aux2(12),
Sum => Sum(12),
Carry => Carry(12)
);

PORT MAP(
Reg_a => Reg_a(13),
Reg_b => aux2(13),
Sum => Sum(13),
Carry => Carry(13)
);

PORT MAP(
Reg_a => Reg_a(14),
Reg_b => aux2(14),
Sum => Sum(14),
Carry => Carry(14)
);

PORT MAP(
Reg_a => Reg_a(15),
Reg_b => aux2(15),
Sum => Sum(15),
Carry => Carry(15)
);
A<=Sum;
Carry_out<=Carry(15);
End JmmmArch;
--devuelve el complemento a2 de la señal en caso de que el bit de resta se encuentre en alto.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY A2COMPLEMENT IS
PORT ( a : in
std_logic_vector(15 DOWNTO 0);
INVERT : out
std_logic_vector(15 DOWNTO 0));
END ENTITY A2COMPLEMENT;
ARCHITECTURE generic_arch OF A2COMPLEMENT IS
constant todos1 : std_logic_vector (15 downto 0) := (OTHERS => '1');

SIGNAL AUXILIAR,auxiliar2 : UNSIGNED (15 DOWNTO 0);
SIGNAL auxiliar3: STD_logic_vector (15 DOWNTO 0);
BEGIN
auxiliar3 <= a xor todos1;

AUXILIAR <= unsigned(auxiliar3);
auxiliar2 <= AUXILIAR+1;
INVERT <= std_logic_vector(auxiliar2(15 downto 0));
END ARCHITECTURE generic_arch;
Tiene una señal llamada resta, que identifica si se quiere sumar o restar.
Si la señal resta esta en 0 suma y si la señal resta esta en 1 resta, como se puede apreciar en
la simulacion anterior.

VHDL Suma Con Carry

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JESSICA LORENA CASTILLO

CAMILO HERNANDEZ TABET

NATALIA MORALES VARÓN

VHDL DEL SUMA CON CARRY

-- PONTIFICIA UNIVERSIDAD JAVERIANA --

-- Seccion de Tecnicas Digitales --

--Definicion de las bibliotecas

--DECLARACION DE ENTRADAS Y SALIDAS DEL BLOQUE

Reg_a: in std_logic_vector (15 downto 0);

Reg_b: in std_logic_vector (15 downto 0);

A: out std_logic_vector (15 downto 0);

Carry_out: out std_logic

end Entity Jmmm;

architecture JmmmArch of Jmmm is

d, clk, clrn, prn, ena : in std_logic;

end component dffe;

signal Carry: std_logic_vector (15 downto 0);

signal Sum,Q: std_logic_vector (15 downto 0);

Carry(6)<= ((Carry(5) and (Reg_a(6) xor Reg_b(6))) or (Reg_a(6) and Reg_b(6)));

df0: dffe port map(Sum(0),Clk,not Reset,'1',enable,Q(0));

df1: dffe port map(Sum(1),Clk,not Reset,'1',enable,Q(1));

df2: dffe port map(Sum(2),Clk,not Reset,'1',enable,Q(2));

df3: dffe port map(Sum(3),Clk,not Reset,'1',enable,Q(3));

df4: dffe port map(Sum(4),Clk,not Reset,'1',enable,Q(4));

df5: dffe port map(Sum(5),Clk,not Reset,'1',enable,Q(5));

df6: dffe port map(Sum(6),Clk,not Reset,'1',enable,Q(6));

df7: dffe port map(Sum(7),Clk,not Reset,'1',enable,Q(7));

df8: dffe port map(Sum(8),Clk,not Reset,'1',enable,Q(8));

df9: dffe port map(Sum(9),Clk,not Reset,'1',enable,Q(9));

df10: dffe port map(Sum(10),Clk,not Reset,'1',enable,Q(10));

df11: dffe port map(Sum(11),Clk,not Reset,'1',enable,Q(11));

df13: dffe port map(Sum(13),Clk,not Reset,'1',enable,Q(13));

df14: dffe port map(Sum(14),Clk,not Reset,'1',enable,Q(14));

df15: dffe port map(Sum(15),Clk,not Reset,'1',enable,Q(15));

JESSICA LORENA CASTILLO

VHDL CON CARRY CORRECCIÓN

architecture SumaArch of Suma is

architecture SumaArch of Suma is

VHDL DEL SUMA Y RESTA CON CARRY

architecture JmmmArch of Jmmm is

signal Carry: std_logic_vector (15 downto 0);

twoscomplement: entity work.A2COMPLEMENT

aux2<=Reg_b when(Resta = '0') else

S0: entity work.Suma

S2: entity work.Suma

S3: entity work.Suma

S4: entity work.Suma

S5: entity work.Suma

S6: entity work.Suma

S7: entity work.Suma

S8: entity work.Suma

S9: entity work.Suma

S10: entity work.Suma

S12: entity work.Suma

S13: entity work.Suma

S14: entity work.Suma

S15: entity work.Suma

--devuelve el complemento a2 de la señal en caso de que el bit de resta se encuentre en alto.

constant todos1 : std_logic_vector (15 downto 0) := (OTHERS => '1');

auxiliar3 <= a xor todos1;

END ARCHITECTURE generic_arch;

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