Alternative Sequential Logic Design

• Large regular structures can be designed

using alternative methods to avoid large state
diagrams and K-maps
¾Good candidates are:
• Registers
• Counters
• Basic approach:
¾Design a single bit of an N-bit structure
• Consider only inputs/outputs for that bit
¾Replicate design N times to create N-bit structure
C. E. Stroud Alternative Sequential Design (11/07) 1
 Register Examples
• Recall registers Din Qa Qb Qc
¾Serial shift register
Clk
• Also serial-to-parallel
Da Db Dc
¾Universal shift register 0 0 0

• Serial-to-parallel Din 1 1 1

• Parallel-to-serial Clk
¾Parallel load register Shift/Load Qa Qb Qc
Da Db Dc
Note that each 0 0 0

1 1 1
bit of register
is identical Clk
Load
C. E. Stroud
Qa
Alternative Sequential Design (11/07)
Qb 2
Qc
 Design Example
• Assume an rising-edge triggered N-bit
register with following functions and order
of precedence: P
D N N Q
¾Synchronous active low reset (R) N-bit
C
¾Synchronous active high preset (P) Clk Reg
¾Active high clock enable (C) R
• This assumes parallel load of data per register bit (Di)
• Common control signals = R, P, and CE
¾And Clock (of course)
• Individual signals = Di and Qi
C. E. Stroud Alternative Sequential Design (11/07) 3
 Design Example R P C Qi+
• Begin with function table 0 X X 0
• Populate K-map 1 1 X 1
¾ Obtain minimized SOP 1 0 0 Qi
¾ Use BA T&P if desirable 1 0 1 Di
• Draw logic diagram for ith bit RP
• Replicate design N times C
00 01 11 10
Qi+=RP+RC’Qi+RCDi 0 0 0 1 Qi
=R(P+C’Qi+CDi) 1 0 0 1 Di
=R(P+(C’Qi+CDi))
P R
MUX Note: we can obtain same design working
Qi out from FF input by order of precedence:
Qi 0 Active low Reset implies AND
Di 1 Clk Active high Preset implies OR
C Clock enable implies MUX
C. E. Stroud Alternative Sequential Design (11/07) 4
 Accumulator Register Example
• Accumulator in PSIM AC-C2
ACi
¾ Functions controlled DRi 0
by combinational AC-C1 DRi
1
logic design ACi
• Including holding data 2
Cin Sumi
when no operations
are specified
ACi adder 3 Zi ACi

9 Via feedback of ACi ACi

4

¾ Only need a flip-flop DRi 5

ACi
at output of MUX DRi 6
• AC register (8-bits) ACi
7
• C register (1-bit) DRi
9 Similar to ACi 3
design shown here AC_C2-0
Clock
C. E. Stroud Alternative Sequential Design (11/07) 5