JOURNAL OF ELECTRONIC TESTING: Theory and Applications 19, 233–244, 2003

c 2003 Kluwer Academic Publishers. Manufactured in The Netherlands.

LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low

Number of Seeds∗

DIMITRI KAGARIS AND SPYROS TRAGOUDAS

Department of Electrical and Computer Engineering, Southern Illinois University, Carbondale, IL 62901

Received March 14, 2001; Revised March 25, 2002

Editor: S. Kajihara

Abstract. A fully scanned digital circuit can be tested pseudo-exhaustively by first introducing a number of extra
bypass storage cells to limit the test-phase input dependency of each test-phase output and then using a Linear
Feedback Shift Register (LFSR) to feed the chain of the original scan cells and the extra cells. For the design of
the LFSR, the goal is to minimize the pseudo-exhaustive test length with low hardware overhead. If the LFSR uses
a primitive characteristic polynomial then it requires only one seed, but the candidate primitive polynomials may
all fail to satisfy the target test length. In this paper, we present a methodology that enlarges the list of candidate
polynomials, if the prescribed number of seeds is more than one. Experimental results show that the new candidate
polynomials are often instrumental in satisfying the given test length and seed restriction.

Keywords: built-in self-test (BIST), test pattern generation (TPG), Linear Feedback Shift Registers (LFSR)

1. Introduction test phase) in to segments satisfying the condition. For

Linear Feedback Shift Registers (LFSRs) are widely
used for built-in self-test (see, e.g., [1]) of digital
combinational or fully scanned circuits, for pseudo-
exhaustive or pseudo-random test pattern generation
(TPG). In pseudo-exhaustive TPG, the goal is to ap-
ply to each test-phase output of the circuit all possible
patterns that it needs to be tested. A necessary condi-
tion for a pseudo-exhaustive test length of 2w is that
each test-phase output depend on at most w test-phase
inputs. The set of test-phase inputs that affect the func-
tion of a specific test-phase output will be referred to as
Aset (Affector set). If the size of an Aset in the original
circuit is greater than the target value off w, a number
of additional cells (referred to as bypass storage cells in
[2]) have to be inserted so as to partition the circuit (in
∗ Thiswork was partially supported by NSF grant CCR-0096119. A
preliminary version appeared in the Proceedings of the IEEE Inter-
national Conference on Computer Design, Sept. 2000, pp. 42–47.
such partition methods see, for instance [3, 4]. We as-
sume here a partitioned circuit for some specified value
w, which in practice, is close to 25.
Consider a fully scanned circuit, where the set of
original flip-flops, along with the test cells for the pri-
mary inputs and any bypass storage cells that may have
been inserted are linked into a single scan chain. The
w first cells of that scan chain are configured into an
LFSR with an appropriate characteristic polynomial.
(Alternatively, the w LFSR cells may be extra cells,
distinct from the scan chain cells, but this is not usually
the case.) The scheme will be referred to as LFSR/SR,
where the SR (Shift Register) part signifies the chain of
the scan cells and/or any extra bypass cells. An example
is shown in Fig. 1. Assume we want to have a pseudo-
exhaustive test set of size no more than 16, i.e., w = 4.
In the original circuit of Fig. 1(a), the Aset of output E
is A E = {I1 , I2 , I3 , I4 , I5 }, which has size larger than
w = 4. A bypass storage cell (cell C6 in Fig. 1(b)) can
be inserted to satisfy the requirement for w. Then the
234 Kagaris and Tragoudas
I_1 I_2
I_3 I_4 I_5
A B
C D
FF
E F
(a)
Fig. 1. (a) Original circuit. (b) Overall scan chain and LFSR.
primary inputs (cells C0 –C4 ), the original flip-flop (cell
C5 ) and the bypass storage cell (cell C6 ) are connected
to a scan chain (local conversions for the flip-flops and
the multiplexers for the primary inputs are not shown
in the figure). Cells C0 –C3 are configured into an LFSR
with characteristic polynomial P(x) = x 4 + x 3 + 1.
The test-phase inputs are C0 –C6 , the test-phase out-
puts are C, D, E, F, and the Asets of the test–phase
outputs are AC = {C0 , C1 , C2 , C3 }, A D = {C2 , C3 },
A E = {C0 , C1 , C4 , C6 }, and A F = {C4 , C5 , C6 }. (In
the following we assume that the Asets consist actu-
ally of the numerical indices of the cells in the chain.)
When the LFSR part is initialized by a non-zero vector
(seed), it cycles through p distinct states, where p is
the period of the characteristic polynomial. The period
of a polynomial is the least integer p for which the
polynomial divides x p + 1 [5]. As the successive states
C_0 C_1 C_2 C_3 C_4
I_1 I_2 I_3 I_4 I_5
A B
C D
C_6 C_5
E F
(b)
of the LFSR are shifted through the rest of the chain,
they provide test patterns for the test-phase outputs.
The efficacy of this scheme depends on the choice
of an appropriate characteristic polynomial. The prob-
lem is that linear dependencies (see., e.g., [6]) may
occur between Asets. In order to guarantee a pseudo-
exhaustive test set, the characteristic polynomial must
satisfy certain criteria, one of which was described in
[7–9] and has been widely used in practice. According
to this criterion,
Lemma 1.1 (Criterion of [7–9]). An LFSR with char-
acteristic polynomial P(x) of degree d ≥ w yields
a pseudo-exhaustive test set of size (2d − 1), if and
only if, in every Aset Ai = {a1 , a2 , . . . , awi }, wi ≤ w,
all polynomials x a1 mod P(x), x a2 mod P(x), . . . ,
x awi mod P(x) are linearly independent.