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    Power Management System CP2102: USB To Serial Port Header

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    Juan Sebastian Mejia Rincon
    This document describes a power management system that uses a CP2102 USB to serial port chip and auto switches between USB, battery, and VDD power sources. The system includes resistors, diodes, capacitors, and a CE6260 power management IC to regulate power from the different sources and ensure components do not receive overvoltage. Pins on the CP2102 and power management IC are labeled to indicate their roles in switching between power supplies and controlling power states.

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    Power Management System CP2102: USB To Serial Port Header

    Uploaded by

    Juan Sebastian Mejia Rincon
    254 views1 page
    This document describes a power management system that uses a CP2102 USB to serial port chip and auto switches between USB, battery, and VDD power sources. The system includes resistors, diodes, capacitors, and a CE6260 power management IC to regulate power from the different sources and ensure components do not receive overvoltage. Pins on the CP2102 and power management IC are labeled to indicate their roles in switching between power supplies and controlling power states.

    Original Description:

    Original Title

    HTCC-AB01_SchematicDiagram

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    This document describes a power management system that uses a CP2102 USB to serial port chip and auto switches between USB, battery, and VDD power sources. The system includes resistors, diodes, capacitors, and a CE6260 power management IC to regulate power from the different sources and ensure components do not receive overvoltage. Pins on the CP2102 and power management IC are labeled to indicate their roles in switching between power supplies and controlling power states.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    254 views1 page

    Power Management System CP2102: USB To Serial Port Header

    Uploaded by

    Juan Sebastian Mejia Rincon
    This document describes a power management system that uses a CP2102 USB to serial port chip and auto switches between USB, battery, and VDD power sources. The system includes resistors, diodes, capacitors, and a CE6260 power management IC to regulate power from the different sources and ensure components do not receive overvoltage. Pins on the CP2102 and power management IC are labeled to indicate their roles in switching between power supplies and controlling power states.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 1

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    Power management system CP2102: USB to Serial port Header

    Vin
    A A
    Vin D2
    USB1 F1 U1 Vin
    1 5 R19
    1 IN OUT U4 4.7K
    2 R1 22R D_N 3 C30 1uF P3 P2
    R2 22R D_P 6V 500mA 1N5819 EN 7 9 ADC RESET
    3 D1 R4
    2 4
    USB/Battery/VDD Power Supply Auto Switch System GND C31 0.1uF 8 REGIN !RST GPIO1 11 GPIO4 11
    4 RSB6.8S 10k GND NC VBUS 10 10
    GND 12 GPIO2 GPIO5
    5 CE6260 C32 1uF 6 SUSPEND 11 GPIO3 9 GPIO0 9
    VDD !SUSPEND 8 8
    Header 5 D4 GND GND U0RXD SDA
    7 7
    1N5819 D_P 4 2 U0TXD SCL
    GND GND VDD D+ RI 6 6
    1 SCK
    DCD 5 5
    - USB maximum input voltage: 7V D_N 5 28 DTR MISO
    D- DTR 4 4
    27 MOSI
    Charging management system - Battery input voltage: 3.5 ~ 4.2V DSR 3 3
    26 U0RXD
    - VDD input: 3~3.5V (Recommend 3.3V) TXD Vin 2 2
    25 U0TXD
    Solar Panel USB(Vin) Charge input Voltage: 0 RXD 24 RTS 1 1
    4.2~7V (≈80mA) GND@EXP RTS
    3 23 Header 11 Vext VDD VS Header 11
    GND CTS
    Solar Panel input: 5.5~7V GND GND GND
    CP2102
    LiPo GND
    Battery

    P1
    GPIO7
    1
    GPIO6
    2
    Header 2

    B B

    MCU & LoRa C1 C2 C3 L1


    L2

    GND
    C6 L3 C7
    R5 R6
    Cannot open file F:\Develop\ASR-Node-duino\PCB\TruthTable.png
    C10 U2 C8
    C11 C12 1 6 J3
    OUT1 Vcont1 L4
    2 5 ANT
    GND IN
    3 4
    OUT2 Vcont2 C14 C19
    C13 IPEX
    GND GND GND C34

    L6
    C17
    C18 R7

    R9
    VDD
    VDD GND
    LED1
    R22 3 2 C20 1uF ANT_SW_CTRL R10 Q5
    Vext DIN VSS GND GND
    4.7K
    Vext 4 VDD DOUT 1
    C21 100nF
    GND
    SK6812 VDD

    C22 0.1uF
    GND
    GPIO4

    R21
    G2 NC USR1
    R14 40.2k VDD DTR 1 6 GPIO7
    GND S1 D1 GND
    C BTN-0 C
    C27
    R15 NC 2 5
    G1 G2
    GND 10K
    RESET 3 4
    D2 S2 Auto Boot
    C23 Auto Boot DTR = 1; RTS = 0 System Hanging
    RST1 2.2uF
    48
    47
    46
    45
    44
    43
    42
    41
    40
    39
    38
    37

    RTS = 0 → 1 Run from user code in FLASH


    ASR6501 RESET DTR = 0 → RTS = 0 → RTS = 1 → DTR = 1 Access Boot Loader mode
    U1
    RFI_P

    LoRa_NSS
    XRES

    RTS
    VR_RA
    RFO
    RFI_N

    VSSA
    VDDA
    VDDD
    VCCD
    GND/SCAN

    LoRa_SCK

    VDD 1 VDD_IN LoRa_MOSI 36 GND


    L7 ADC 2 35
    C24 ADC_IN LoRa_MISO
    BLM15PG100SN1D X1 GND 3 GND UART_RTS 34 GPIO4
    100nF 4 3 4 33 GPIO5
    VDD OUT XTA UART_CTS
    1 2 5 32 Y1
    C37 VC GND XTB P0.5(32KOUT)
    GPIO1 6 ASR6501 31 2 1 32.768kHz
    100nF GPIO1 P0.4(32KIN)
    GND X-TAL-2520-32MHz GPIO2 7 30 GPIO0
    GPIO2 GPIO0 C25
    GND GPIO3 8 29 C28
    GPIO3 SDA
    9 DIO3 SCL 28 15pF 15pF VBAT
    GND 10 27
    VREG SPI_NRESET/P5.7 VDD
    11 26 40.2K R12

    ADC
    L5 GND GND2 SPI_BUSY/P4.7
    12 25 R16
    DCC_SW DIO1/P4.6 GND GND
    15uH VDD 10K
    VBAT_DIO
    P4.1 MISO
    P4.0 MOSI
    VBAT_RF

    P4.2 SCK
    P4.3 NSS

    BR1
    VDDD

    PGND

    C35
    DIO2
    SWD
    SWC

    0R
    RXD
    TXD

    470nF R23 R25


    NC NC VDD VDD
    G3
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24

    49

    GND R17
    SDA R13 1 S1 D1 6 GND R20
    U0RXD
    U0TXD

    SCL
    GPIO6
    GPIO7

    10K 10K 10K


    VDD GPIO7 R18 2 5 GPIO6
    G1 G2
    GND MOSI 1K
    MISO
    C29 3 4
    SCK Vext D2 S2 VDD
    D 47uF NSS D
    AO7801
    ANT_SW_CTRL VDD

    GND
    C36
    VDD 100nF

    C33 GND
    100nF
    *
    Title CubeCell Board Block Diagram *
    Heltec Automation
    GND
    *
    CubeCell
    Size: A2 Board
    Number:* Block Diagram
    Revision:V1.0
    *
    https://heltec.org
    Date: 2019/12/13 Time: 18:01:26 Sheet * of * *
    https://heltec.org/project/htcc-ab01
    File: E:\DreamSpark\ASR-Node-duino\PCB\Board\V1.1\Cubecell Board Block Diagram.SchDoc

    1 2 3 4 5 6 7 8

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