BIOGRAPHIES
Abe, Kenichi (5F.2)
Kenichi Abe (S’07) was born in Shiogama, Japan in 1983. He
received the B.S. degrees in electronic engineering and M.S.
degree in management of science and technology from Tohoku
University, Sendai, Japan, in 2006 and 2008, respectively. He is
currently working toward the Ph.D. degree in Tohoku University
from April 2008. His current research topics are low-frequency
noise and random telegraph noise in deep submicron devices
and variability of MISFET characteristics in ULSI. Mr. Abe
received the IEEE Electron Devices Society Japan Chapter
Student Award in 2008.
Ackermann, Markus (RM.2)
Markus Ackermann is with X-FAB Semiconductor Foundries,
being responsible for process characterisation and primitive
device reliability in the field of CMOS technologies. He works
on characterisation and modelling of semiconductor device
degradation. Before joining X-FAB he studied physics at the
University of Jena and received the diploma in 2008.
Acosta, Antonio (5F.3)
Antonio Acosta received his B.S. from Georgia Tech in 2005
and M.S. from the University of Florida in 2009, both in
Electrical Engineering. He is currently working towards his
Ph.D. in Electrical Engineering at the University of Florida. His
main research interests are the development of next-generation
semiconductor devices and nanotechnology. He has worked as
an intern within the Analog Technology Development group at
Texas Instruments since the summer of 2008. His past projects
have been the characterization of PZT ferroelectric capacitors
for decoupling applications, and scaling reliability and modeling
of fully embedded ferroelectric capacitors.
Afanas’ev, Valery (5A.2)
Valery Afanas’ev received the Ph. D. degree from Leningrad
State University in 1985 and worked there as a member of
research staff till 1992. In 1992 he joined Delft Institute of
Microelectronics as research fellow. In 1994, he moved the
University of Erlangen to develop the internal photoemission
spectroscopy of oxidized SiC. Since 1995 he is with the
Laboratory of Semiconductor Physics, University of Leuven,
focussing on applications of internal photoemission
spectroscopy to wide spectrum of solid interfaces. The main
research results were published in more than 250 journal papers,
150 conference contributions, 10 book chapters, and 1
monography.
Ahlbin, Jonathan (3A.2, 6E.2)
Jonathan R. Ahlbin received B.E. and M.S. degrees in electrical
engineering from Vanderbilt University in 2005 and 2009
respectively, and is currently pursuing his Ph.D. there. His
research interests include microelectronic circuit analysis and
design, and the effects of radiation on integrated circuits,
specifically the modeling of circuit-level soft errors.
Ahn, Kun-Ok (MY.7)
Kun-ok Ahn received the B.S. degree in electrical engineering
for Dankook University, Seoul Korea in 1982. In 1983, he
joined Samsung Electronics, Keheung Korea. Since then he has
been engaged in development and producction of nonvolatile
memory devices such as MaskROM, NOR and NAND flash
memory production. He left Samsung Electronics in 2003 and he
has worked for Hynix Semiconductor from 2007, Cheongju-si,
Korea and then he has been engaged in production for NAND
flash memory devices as the VP of Process Integration and
Device Engineering now.
Aichinger, Thomas (XT.6, XT.8)
Thomas Aichinger received his M.S. degree in physics from the
Karl-Franzens University in Graz in May 2007. During his diploma
thesis, concerning the implementation of Charge Pumping in the
laboratory soft- and hardware environment, he was integrated in the
Quality and Reliability group of Infineon Technologies Villach.
Currently he is toward his doctor degree at Infineon Villach and
KAI in cooperation with the “Christian Doppler Laboratory” group
of the Institute for Microelectronics in Vienna. In 2007, he recieved
the Best Paper arward at ESREF.
Akira, Toriumi (3D.4)
Akira Toriumi received the B.S. degree in physics, the M.S. and
Ph.D. degrees in applied physics from the University of Tokyo in
Japan, 1978, 1980 and 1983, respectively. He joined R&D Center of
Toshiba Corporation in 1983. In May 2000, he moved to the
University of Tokyo. His research interests have been on silicon
device physics and related materials science throughout his
professional carrier. He is currently studying the materials science
of high-k dielectrics, and physics and technology of Ge as well as
organic electron devices. He is a member of the JSAP, JPS, APS,
ECS and IEEE.
Alain, Bravaix (2B.2)
Alain Bravaix graduated from the University of Sciences of Paris
and joined the R&D research laboratory of BULL S.A. in 1988 (Les
Clayes sous Bois-France). He received the Ph.D. degree in
microelectronics in 1991. From 1991 to 1993, he worked on gate-
oxide nitridation optimization as a postdoctorate fellowship in the
Solid-State Physics Research group of the Institut d'Electronique et
de Microélectronique du Nord (IEMN). Since 1994 he is developing
research activities and teaching for Engineering and Master degrees
at the Institut Supérieur d’Electronique et du Numérique (ISEN-
Toulon) as a member of the Institut Matériaux Microélectronique
Nanosciences de Provence (IM2NP) UMR 6242. He works in
collaboration with ST Microelectronics Crolles since 1995 on the
reliability and optimization of CMOS and BICMOS technologies.
His research interests cover device to circuit reliability developing
electrical characterization techniques for novel and ultra-small
CMOS nodes.
Alam, Muhammad Ashraful (2B.3, 3E.2, XT.7)
Muhammad Ashraful Alam received the B.S. from Bangladesh
University of Engineering and Technology in 1988, the M.S. degree
from Clarkson University in 1991, and the Ph.D. degree from
Purdue University in 1994, all in electrical engineering. He is a
Professor of Electrical and Computer Engineering at Purdue
University where his research and teaching focus on physics,
simulation, characterization and technology of classical and novel
semiconductor devices, including theory of oxide reliability,
nanocomposite thin film transistors and nano-bio sensors. From
1995 to 2001, he was with Bell Laboratories as a Member of
Technical Staff in the Silicon ULSI Research Department. From
2001 to 2003, he was a Distinguished Member of Technical Staff at
Agere Systems. Dr. Alam has published over 80 papers in
international journals and has presented many invited and
contributed talks at international conferences. He is an IEEE Fellow,
Purdue University Faculty Scholar, and also received the 2006 IEEE
Kiyo Tomiyasu Award for his contributions to device technology for
communication systems.
Albin, David (3E.3)
David Albin is a Senior Scientist at the National Renewable Energy
Laboratory (NREL) in Golden, CO. He obtained his Ph.D. in
Materials Science and Engineering from the University of Arizona
with a Masters Degree in Ceramic Engineering from the University
of Illinois. He has over 20 years experience in both
Cu(In,Ga)Se2 and CdTe thin film solar cell development, with
over 100 scientific publications, and three patents.
Approximately half of his research at NREL is funded through
collaborative research with outside companies including
PrimeStar Solar and the GE Global Research Center in New
York.
Allmon, Randy (3A.1)
Randy Allmon received a B.S.E.E. degree from the University
of Cincinnati in 1981. Since that time he has worked at Digital
Equipment Corporation, SiByte and Broadcom Corporation as a
Circuit Designer and Technical Leader, and has been active in
the Circuit and Layout design of numerous PDP-11, VAX,
Alpha and MIPS high-performance microprocessors. Since
joining Intel in 2003, he has worked in both the Itanium and
Xeon design teams, and is currently in a Technical Leader in the
High Performance Computing Group. He holds 4 Patents and
has 1 Patent Pending
Ambrose, Vinod (3A.1)
Vinod Ambrose works in the Server Microprocessor Group in
Intel. Starting in 1996, he has worked in the areas of Device
Modeling, Reliability, Power Estimation, and Circuit Design for
microprocessors in DEC, Compaq, and HP. He joined Intel in
2003. Vinod holds a BS in Physics/Math from Monmouth
College, IL, and a PhD in Physics from Texas Christian
University.
Amoroso, Salvatore Maria (MY.5)
Salvatore Maria Amoroso was born in Catania, Italy, in 1983.
He received the B.S. and M.S. degrees in physics engineering
from the Politecnico di Milano, Milano, Italy, in 2005 and 2008,
respectively, where he is currently working toward the Ph.D.
degree in information technology in the Dipartimento di
Elettronica e Informazione. He is also with the Italian University
Nano-Electronics Team, Milano, Italy. His research activities
include modeling and numerical simulation of semiconductor
devices, with particular interest on innovative nonvolatile
memories.
Andrea, Marmiroli (MY.6)
Andrea Marmiroli received the Degree in Physics (cum laude)
from Milano University in 1984, with a thesis work on an
algebraic approach to quantum field theory. In September 1985
he joined SGS (now STMicroelectronics). He worked at first
within the New Technologies Development group, then within
the Technology CAD team. Since its foundation (March 2008),
he is with Numonyx, in the position of “Technology and Device
Modelling Director“. He coordinated ST activity within different
European funded project. He is reviewer for the IEEE- TED. His
major interests are in Non Volatile Memory modeling.
Andreani, Carla (4B.3)
Carla Andreani (CA) received a Laurea Cum Laude in Physics
in 1977 at the Università di Roma "La Sapienza". CA is now full
professor in Condensed Matter at the University of Rome Tor
Vergata. She is an experimental physicist, with a background in
condensed matter physics. CA designed several neutron
scattering instruments to study the structure and dynamics of
fluids and materials. Most recently CA has used neutron
spectroscopy to produce quantitative measurements and 3D
images of the elemental composition and physical structure of
artifacts. CA has authored about 150 publications on
international journals and delivered over 80 invited talks.
Ang, Diing Shenp (4A.4, XT.5)
D. S. Ang received the B.Eng. (Hons) and Ph.D. degrees in
electrical engineering from the National University of Singapore
(NUS) in 1994 and 1998, respectively. He was a teaching staff of
the Bachelor of Technology Programme in NUS before joining the
School of Electrical and Electronic Engineering, Nanyang
Technological University as an assistant professor in 2002. From
2008, he has been an associate professor. His current research
interests are bias-temperature instability of advanced CMOS
devices, application of scanning probe microscopy for gate stack
characterization, and resistance memory devices. He has published
more than 90 papers in international journals and conferences and
has served on the technical programme committee of several
conferences (IRPS, IIRW, and IPFA).
Angyal, Matthew (5A.5)
Matt Angyal received his B. S. in Electrical Engineering from the
University of Maryland in 1991 and his Ph. D. in Electrical
Engineering from Cornell University in 1996. From 1996 through
2001 he worked at Motorola’s Advanced Products Research and
Development Lab where he contributed to the development and
qualification of copper interconnect technology. He joined the IBM
Semiconductor Research and Development Center in 2001, where
he has been involved in the development and qualification of copper
/ low-k interconnect technology for advanced CMOS technologies.
Aoulaiche, Marc (XT.13)
Marc Aoulaiche received the M.S. degree in physics and
Microelectronics from the University of Provence (Aix-Marseille I),
France, in 2004. He pursued the Ph.D degree in microelectronics on
Bias-Temperature-Instability effects in MOSFET’s with high-k
dielectrics and metal gates, characterization and modeling, at the
Interuniversity Microelectronics Center (IMEC) and Department of
Electrical Engineering, Katholieke Universiteit of Leuven
(K.U.Leuven), Belgium. Since January 2009, he is working at IMEC
in the Logic Device Design group. His main research topics are
reliability, electrical characterization of floating body RAM devices
and compact modeling.
Arreghini, Antonio (6C.1)
Antonio Arreghini was born in Udine, Italy, in 1979. He received
the Laurea degree in electronic engineering and the Ph.D. degree in
industrial and information engineering from the University of Udine,
in 2004 and 2008, respectively. From July 2006 to July 2007, he was
a visiting scientist with NXP Semiconductors, Leuven, Belgium,
where he worked on the modeling and simulations of long-term
retention, program, and erase transients of SONOS non volatile
memories. Since 2008, he has been with IMEC, Leuven. His
research topics include modeling, simulation and advanced
experimental characterization of charge-trapping non volatile
memory cells.
Asheghi, Mehdi (2C.5)
Dr. Mehdi Asheghi completed his Ph.D. (1999) and postdoctoral
(2000) at the Stanford university conducting research in the area of
nanoscale thermal engineering of microelctronic devices. He led a
well-known and funded research program (2000-2006) at the
Carnegie Mellon University that focused on nanoscale thermal
phenomena in semiconductor and data storage devices. He is
currently a consulting associate professor at the Stanford University
focusing on further development of PCRAM technology. He is the
author of more that 100 book chapters, journal publications and
fully-reviewed conference papers.
Atkinson, Nick (3A.2)
Nicholas M. Atkinson received the B.E. degree in electrical
engineering from Vanderbilt University, Nashville in 2008. He
is currently working toward the M.S. degree at Vanderbilt
University. His research interests include VLSI circuit design
and single-event effects.
Aubel, Oliver (2D.3 , 5A.4, 5B.2, IC.9)
Dr. Oliver Aubel has earned his diploma (M.S.) in electrical
engineering with focus on microelectronic engineering from the
University of Hannover (Germany) in 2000. Early 2004 he
finished his PhD study at the same university with focus on ultra
highly accelerated electromigration testing. Immediately after
that he joined GLOBALFOUNDRIES (formerly AMD)
(Germany) as a reliability engineer for interconnect reliability.
In his early years at GLOBALFOUNDRIES he was assigned to
the IBM technology development alliance at Burlington site in
Vermont, US (2004-2005) responsible for the reliability transfer
to GLOBALFOUNDRIES. He is now coordinating all BEOL
related reliability activities in GLOBALFOUNDRIES
(Germany).
Auluck, Kshitij (NA.2)
Kshitij Auluck is currently working towards B.Tech and M.Tech
in Microelectronics (dual-degree) from the Department of
Electrical Engineering, Indian Institute of Technology Bombay,
Mumbai, India, and will graduate in 2010. From May 2008 to
July 2008, he was a student intern at Corporate Technology
Group, Intel Corp., Bangalore, India. His research interests are
physics, fabrication, modeling and simulation of novel
semiconductor devices for logic and memory.
Baccarani, Giorgio (HV.1)
Received the B.S. degree in electrical engineering and in physics
from the University of Bologna, Bologna, Italy, in 1967 and
1969. In 1969, he joined the Bell Laboratories, Murray Hill, NJ.
In 1970, he became Research Assistant and in 1980 Full
Professor with the University of Bologna. In 1981, 1983 and
1989 he was with the IBM T.J. Watson Research Center,
Yorktown Heights, NY. He is the Director of the ARCES
Research Center at the University of Bologna. His current
research interests include device simulation, synthesis of analog
circuits, analog and digital architectures for image processing,
and integrated circuit design.
Baek, Chang-Ki (2C.4)
Received the B.S. degree in electronic engineering from
Chungnam National University, Daejeon, Korea, in 1999, the
M.S. degree in electronic and electrical engineering from
Pohang University of Science and Technology (POSTECH),
Korea, in 2002, and the Ph. D. degree in electrical engineering
and computer science from Seoul National University, Seoul,
Korea, in 2008. Currently he is a research fellow in the
Computational Sciences Division, Korea Institute for Advanced
Study (KIAS), Seoul, Korea. His current research interests are in
3-dimensional quantum transport, semiconductor device
analysis, modeling and simulation of MOSFET, Silicon
Nanowire and Flash memory cells, particularly on oxide
reliability issues in nano-scale CMOS devices.
Baek, Rock-Hyun (2C.4)
Received the B.S. (2004) in electronics engineering from the
Korea University, Korea. He received the M.S. (2006) in
electronics engineering from the Pohang University of Science
and Technology (POSTECH), Pohang, Korea. He is currently in
Ph.D. course at POSTECH. His main research interests include
CMOS devices and nanowires FET.
Bagatin, Marta (4B.3)
Marta Bagatin received the Laurea degree (cum laude) in Electronic
Engineering from the University of Padova, Italy, in 2006. Since
January, 2007, she has been following the Ph.D. School in
Information Science and Technology at the Department of
Information Engineering, University of Padova. Her research
interests concern radiation and reliability effects on electronic
devices, especially on volatile and non-volatile semiconductor
memories. The results of her work were recognized with the
Outstanding Student Paper Award at NSREC 2008, the Best Student
Presentation Award at RADECS 2008, and the NPSS Phelps Award
2009.
Baghini, M. Shojaei (4D.4, EL.2)
Maryam Shojaei Baghini received M.S. and Ph.D. degrees in
Electrical Engineering from Sharif University of Technology,
Tehran, in 1991 and 1999, respectively. She worked for two years in
industry on the design of analog and mixed-signal VLSI ICs. In
2001, she joined IIT-Bombay as a Postdoctoral Fellow, where she is
currently a faculty member. She has been a Designer/Co-designer of
several analog chips in industry and academia. As a part of her
research in IIT Bombay, she has designed one of the most power-
efficient CMOS instrumentation amplifiers for biomedical
applications in 2004. Dr. Shojaei is author/co-author of 49 Int.
journal & conference papers, inventor/co-inventor of seven patent
applications, and author of one invited book chapter. She is a co-
recipient of the best research award in circuit design at Intel
Corporation AAF'08 and the third award on research and
development at 15th International Festival of Kharazmi in 2002. Her
team of students won the first Cadence Design Systems, Inc. Student
Design Contest, among SAARC countries in 2006. Dr. Shojaei is
member of Emerging Applications and Technologies sub-committee
of IEEE A-SSCC and member of Low-Power Design/Circuits and
Technology Track of IEEE Int. Conf. on VLSI Design. Her current
research interests include device-circuit interaction in emerging
technologies, high-performance low-power analog/mixed-signal/RF
VLSI design and test, analog/mixed-signal/RF EDA, power
management for SoCs, high-speed interconnects and circuit design
with organic thin film components.
Balasubramanian, Anu (3A.1)
Anu Balasubramanian joined the Microprocessor and Graphics
development (MGD) Quality and Reliability Team at Intel in Dec
2008. Her focus is in the areas of ESD, High Speed Bus reliability,
and SER modeling. Anu Balasubramanian received her Ph.D. in
Electrical Engineering in 2008 from Vanderbilt University. Her
areas of research interests include biological sensors,
microelectronic-circuit analysis and design, and effects of radiation
on integrated circuits, specifically designing for radiation hardness,
reliability and modeling circuit-level soft errors.
Balk, Ludwig Josef (3C.4)
Ludwig Josef Balk studied physics at the RWTH Aachen and
received his diploma in 1971, hereafter he received his PhD in
electrical engineering from the same university in 1976. After an
intermediate stay at the University of Duisburg as academic director
he joined University of Wuppertal in 1991 as full professor for
electronics. Additionally he became director of the institute of
polymer technology in 2005. His main research is in the area of
micro and nano characterization of materials and devices.
Barbato, Marco (3F.2)
Marco Barbato was born in Dolo (Venice), Italy, in 1984. He
graduated in Electronics Engineering at University of Padova in
2009 with a thesis on reliability of RF micro electro mechanical
systems. He currently holds a scholarship with University of
Padova, working on the development of measurement set-up in
particular on RF-MEM systems. Moreover he works on
development of HV systems and power converters. In his career
he has coauthored 5 papers.
Bashir, Muhammad (IC.3)
Muhammad Bashir is a doctoral candidate in electrical and
computer engineering at the Georgia Institute of Technology.
His research interests include modeling yield and reliability of
semiconductors. He has an MS in electrical and computer
engineering from the Georgia Institute of Technology.
Baumann, Robert (4B.2)
Dr. Baumann heads the Texas Instruments radiation effects
program and is a TI and IEEE Fellow and EDS Distinguished
Lecturer with 20 years of experience in semiconductor
reliability. He co-led the SIA Panel investigating the impact of
the ITAR on export restrictions and was directly responsible for
changes that reduced the risk of U.S. commercial electronics
becoming inadvertently controlled. He led and was one of the
authors of the JEDEC JESD89 test standard for radiation testing
of commercial microelectronics and was awarded the JEDEC
Chaiman's Award. He has published > 55 papers, two book
chapters, and holds eight U.S. patents.
Bauza, Daniel (3C.2)
Daniel Bauza received the M.S. degree in electronics and the Ph.
D degree in Energetics and Complex Systems Dynamics, both
from the University of Paris XII Créteil-France in 1982 and
1986, respectively. In 1986, he was an engineer with CNRS and
the “Laboratoire de Physique des Composants à
Semiconducteurs, Grenoble-France”, which became the Institute
of Microelectronics, Electromagnetism and Photonics (IMEP) in
2001. Since 2003, he has been an Associate Scientist with
CNRS. Currently with the IMEP-LAHC, MINATEC, his
research interests are on the characterization of defects in silicon
devices, on the electrical characterization of silicon-insulator
interface traps, on the electrical properties of MOSFET’s gate
insulator, and on the development of related characterization
tools.
Beltrami, Silvia (4B.3, 5C.2)
Silvia Beltrami was born in Bergamo, Italy, in 1978. She
received the Laurea degree in Electronic Engineering from
Politecnico di Milano, Italy, in 2003. She joined
STMicroelectronics in 2003 and now she is working in the R&D
Technology Center of Numonyx. Her work is about the
reliability improvement of flash memory and, in particular,
NAND and multilevel devices. She is a co-author of various
scientific papers about flash memories.
Benakanakere Sheshadri, Vijay (SE.3)
Vijay B Sheshadri received the B.E. degree in Electronics &
Communication engineering from BMS College of Engineering,
Bangalore, India (affiliated to the Vishweshwariah
Technological University, Belgaum, India) in 2006 and is
currently working toward the M.S. degree in electrical
engineering at Vanderbilt University, Nashville, TN,
Bender, Hugo (6A.3)
Hugo Bender is team leader of the Structural Analysis (SA)
team in the Materials and Components Analysis (MCA) group at
imec. He has over 25 years experience in materials
characterization for semiconductor applications, in particular
with transmission electron microscopy, scanning electron
microscopy, focused ion beam, Auger spectroscopy, spectroscopic
ellipsometry, infrared spectroscopy. In these fields he is author/co-
author of about 200 journal papers, 280 conference contributions
and 3 book chapters. His current interests are focused on the
application of transmission electron microscopy for strain analysis,
electron tomography, and chemical analysis by
STEM/EDS/EELS/ELNES on device structures for next generation
technologies.
Benvenuti, Augusto (5C.4)
Augusto Benvenuti received the Ph.D. degree in electronic
engineering from Politecnico di Torino in 1993. During 1991-1992
he was a research visitor at Bell Labs, Murray Hill; in 1993 he was
at the Centre d'Electronique de Montpellier. During 1994 he worked
at ETH Zuerich on the implementation of the hydrodynamic model
in the device simulation program Dessis. Since 1995 he works in
Agrate, initially with STMicroelectronics and later with Numonyx
R&D, where he is currently managing TCAD activities. He has been
involved in the support of several EEPROM, NOR, NAND and
PCM technology platforms, and has coauthored about fifty papers.
Bersuker, Gennadi (2B.4, 4A.4, 4F.4)
Gennadi Bersuker (M’05) received the M.S. degree in physics from
Leningrad State University, St. Petersburg, Russia, and the Ph.D.
degree in physics from Kishinev State University, Kishinev,
Moldova. He was with the Moldavian Academy of Sciences,
Kishinev; Leiden University, Leiden, The Netherlands; and the
University of Texas, Austin. Since 1994, he has been with
SEMATECH Inc., Austin, TX, where he is working on
processinduced charging damage, electrical characterization of
Cu/low K interconnect, high-κ gate dielectrics, and advanced CMOS
process development
Beyer, Gerald P. (5B.4)
Gerald Beyer is the program manager of Cu/low-k program. His
background is sputter deposition. He earned a PhD in Materials
Science from Imperial College, London.
Bhatia, Charanjit (4E.4)
Prof Bhatia, Charanjit Singh received his MS and PhD in Electrical
Engineering from University of Minnesota, Minneapolis MN USA
in 1978 & 1979 respectively. Prof Bhatia joined NUS as a Professor
of Electrical & Computer Engineering and also has 25%
appointment in the Institute of Materials Research & Engineering
(IMRE). Prof Bhatia was a Temasek Professor in NUS from 2001 to
2005. He worked as a Senior Technical Staff Member (STSM) in
the Advanced Magnetic Storage Lab (AMRL) of IBM and Hitachi
GST. Prof Bhatia was awarded the coveted IBM’s Faculty award in
2008 for his project on Fabrication, Characterization and
Performance of Thin Film Si Photovoltaic (PV) Cells. He also set up
a Joint Study agreement (JSA) with IBM’s T J Watson Jr Research
lab at Yorktown Heights, NY, to work on the Si based photovoltaic
cells.
Bhuva, Bharat (3A.2, 6E.2, SE.3)
Bharat L. Bhuva received the B.S. degree in electrical engineering
from Maharaja Sayajirao University of Baroda, Baroda, India, in
1982 and the M.S. and Ph.D. degrees in electrical engineering from
North Carolina State University, Raleigh, in 1984 and 1987,
respectively. He is currently an Associate Professor of electrical
engineering with the Department of Electrical Engineering and
Computer Science, Vanderbilt University, Nashville, TN. His
research interests include radiation effects on electronics,
biosensors, optical-signal transmission using all Si process, and
cognitive science.
Bisht, Gaurav (NA.2)
Gaurav Bisht obtained his M.Sc (2007) in physics from Indian
Institute of Technology (IIT) Roorkee. Since 2007 he is
pursuing M. Tech. in microelectronics from department of
Electrical Engineering at IIT Bombay India. His research
interests are in the areas of non-volatile memories, device
reliability and characterization.
Bisschop, Jaap (CR.3)
Jaap Bisschop received the M.Sc. in physics in 1978 and Ph.D.
in electrical engineering in 1983. He worked on oxide reliability
at the University of Groningen, The Netherlands. In 1986 he
joined Philips Research, where he worked on device physics and
reliability of solid state image sensors. In NXP Semiconductors
he has been responsible for coordination of company reliability
activities. His current focus is on wafer level reliability, building
in reliability and automotive reliability. He is convenor of the
IEC TC47 Wafer Level Reliability working group. He is a
member of the ESREF steering committee.
Bittel, Brad (IC.13)
Brad Bittel received his B.S. degree in Electrical Engineering
from the Pennsylvania State University in 2007 and is now
pursuing a Ph.D. in Materials Science and Engineering also
from the Pennsylvania State University.
Blaauw, David (5F.1)
David Blaauw received his B.S. in Physics and Computer
Science from Duke University in 1986, and his Ph.D. in
Computer Science from the University of Illinois, Urbana, in
1991. Until August 2001, he worked for Motorola, Inc. in
Austin, TX, were he was the manager of the High Performance
Design Technology group. Since August 2001, he has been on
the faculty at the University of Michigan where he is a
Professor. He has published over 300 papers and hold 30
patents. His work has focussed on VLSI design with particular
emphasis on ultra low power and high performance design. He
was the Technical Program Chair and General Chair for the
International Symposium on Low Power Electronic and Design.
He was also the Technical Program Co-Chair of the ACM/IEEE
Design Automation Conference and a member of the ISSCC
Technical Program Committee.
Bluet, Jean-Marie (2E.3)
Jean-Marie BLUET his PhD from University of Montpellier II
in 1997, with speciality in condensed matter. He has then
worked in LMGP lab in Grenoble and in CEA LETI as a post
doc . He then obtained an assistant professor position at INSA
de Lyon in 1999. His research activity is focused on wide band
gap semiconductors materials and devices characterizations (SiC
and GaN). At present, he also performs spectroscopic studies of
semiconductors at the nanoscale with investigations of Si and
SiC nanoparticules and porous SiC. He is author and co-author
82 publications in international journals and conferences.
Boit, Christian (IC.2)
Prof. Dr. Ing. Chris Boit is dean of the faculty for CS&EE in the
TUB Berlin University of Technology (Germany) and head of
the semiconductor device department with special focus on
functional analysis and debug of Integrated Circuits and
semiconductor devices. From 1986 to 2002 he has been with
Siemens AG’s Research Laboratories and Semiconductor
Group, and Infineon Technologies, respectively. 1990 to 1993
he participated in the joint IBM-Siemens 64M DRAM
development team in East Fishkill NY. In the following years,
he took responsibility as Manager and then Director of Failure
Analysis. He received the Physics Diploma and the PhD in
Electrical Engineering from TUB Berlin. In the field of
electronics, Chris has been co-founder of several international
societies on failure analysis like EDFAS and EUFANET and has
served in their Boards of Directors. He has been supporting the
respective international conferences for many years, for ISTFA as
Seminar Chair in 2000 and General Chair in 2002. He has also been
co-editor of the Electronics Failure Analysis Desk Reference. He is
member of the German Academy of Science and Engineering,
ACATECH. In the German association of electrical engineers, VDE,
he is speaker of the section for reliability and failure analysis of
microelectronics.
Boku, Katsushi (6C.4)
Katsushi Boku received a B.Sc. degree in material science from
University of Electro Communications (Tokyo, Japan) in 1988.
Katsushi joined Texas Instruments Japan on 1989, and has worked
for DRAM development. In 2002, Katsushi moved to the US and
became involved in FeRAM reliability and yield analysis. He has
been issued 10 patents and has coauthored several technical papers.
In his spare time, Katsushi loves playing golf and soft ball.
Boselli, Gianluca (4D.3)
Gianluca Boselli (MS ’96, Ph.D ’01) joined Texas Instruments,
Dallas, Texas, in 2001, where was responsible for advanced CMOS
ESD/Latch-up development. Recently his responsibilities extended
into ESD development of Analog technologies.
He authored several papers in the area of ESD/Latch-up. He
presented his work at major conferences, including EOS/ESD
Symposium, IEDM, and IRPS. He also presented several invited
papers and/or tutorials at the EOS/ESD Symposium, IRPS, IEDM,
ESREF and RCJ. Dr. Boselli has been the recipient of the “Best
Paper Award” on behalf of Microelectronics Reliability Journal in
2000. He received “The Best Paper Award” at the EOS/ESD
Symposium 2002. He also received the “The Best Presentation
Award” at the EOS/ESD Symposium in 2002 and in 2006. Dr.
Boselli is a member of ESD Association and an IEEE senior
member. Dr. Boselli serves on the TPC of the EOS/ESD
Symposium, IRPS and ESREF. Dr. Boselli has served as TPC Chair
at the EOS/ESD Symposium 2006, Vice-General Chair at the
EOS/ESD Symposium 2007 and General Chair at the EOS/ESD
Symposium 2008.
Bosman, Michel (4A.1, BD.2)
Michel Bosman received his M.Sc. degree in Materials Science from
the Delft University of Technology, Delft, Netherlands, and Ph.D.
degree in Electron Microscopy from the University of Sydney,
Australia. He is currently with the Institute of Microelectronics,
A*STAR, Singapore. His research interests include nanoscale optics
and atomic-resolution spectroscopy using transmission electron
microscopes.
Bounasser, Mounaim (3A.3)
Mounaim Bounasser received his B.E. and M.S. in Electrical
Engineering from University of Montpellier II, Montpellier, France,
in 2004 and 2006, respectively. He has previously worked on
radiation effects on circuits and radiation hardened circuit design at
Vanderbilt University and with Ridgetop Group Inc. He is currently
working on radhard circuit design and simulation with Robust Chip
Inc.
Breuer, Taro (IC.2)
Taro Breuer received his diploma degree in electrical engineering
(equivalent to M.S.) in 2006 from TU Berlin (Berlin University of
Technology). In 1998-2003 he studied electrical engineering with
focus on telecommunications engineering at TU Hamburg-Harburg.
His PhD research at TU Berlin in cooperation with Advanced Micro
Devices (AMD) Dresden (now GLOBALFOUNDRIES) focuses on
ultra-low-k dielectric reliability .
Brewer, Forrest (IC.10)
Professor Brewer (B.S (Physics), Caltech; PhD (Computer
Science) ,UIUC) joined the UCSB faculty in 1988, He was
formerly a consulting engineer and a senior engineer at Northrop
Corp. Advanced Technology Division. His research interests are
in mixed signal VLSI design as well as computer aided design
tools and analysis. His research in mixed signal design involves
investigating solutions for data transmission for inter-chip and
intra-chip communications which includes the application of
communications and signal processing theory and techniques to
analyze high-speed I/O links and looking into ESD solutions for
mixed signal I/Os. Recent work includes development of a
family of specialized microprocessors for low-power/ high-
performance embedded closed loop control. This work spans
mixed signal design at the sensor and actuator interfaces to
multi-threaded digital system design in the digital processing
parts. He teaching interest includes VLSI design and coupled
tools development based on systematic and formal approaches
as well as heuristic analysis. Other interest includes low Power
Control: to drastically reduce the power consumption of digital
feedback controller which have become ubiquitous in embedded
systems used in automotive,cars, appliances and portable
phones.
Bru-Chevallier, Catherine (2E.3)
Catherine Bru-Chevallier received her PhD from Paris XI
University. She is currently senior scientist (CNRS) at Lyon
Institute of Nanotechnology (INL), head of “Spectroscopy and
Nanomaterials ” group and of « Material Department » at INL.
She is mainly involved in optical spectroscopy of III-V
heterostructures and nanostructures using photoluminescence as
well as photoreflectance spectroscopy. She is developing local
optical spectroscopy in order to characterize operating devices
(transistors) as well as to study radiative emission from single
nanostructures. She is author and co-author of more than 120
publications in international journals and conferences.
Butera, Geni (6A.3)
Geni Butera was born in Lamezia Terme, Italy, in 1982. He
received the Bachelor’s degree in electronics engineering and
the Master’s degree in electronic engineering cum laude from
University of Calabria, Rende, Italy, in 2006 and 2009,
respectively. From October 2008 to April 2009, he was with
imec, Leuven, Belgium, as Internship student (Erasmus Project)
for Katholieke Universiteit Leuven, Belgium, focusing on the
topic: electrical characterization of advanced MOS devices with
Cu contacts.
Bychikhin, Sergey (4D.4)
Sergey Bychikhin studied physics at Moscow State University
and received Ph.D. in 2000. During his study he was specialized
on noise phenomena in electronic systems and devices. His
Ph.D. thesis was dedicated to fluctuations in scanning tunneling
microscope. Since 2000 he is with device characterization group
at Vienna Technical University. He is engaged in thermal and
electrical characterization of devices with optical methods and in
thermal modeling.
Cagli, Carlo (5D.1)
Carlo Cagli was born in Naples, Italy, in 1984. He received the
B.S. and M.S. degrees (cum laude) from Università degli Studi
di Milano, Italy, in 2005 and 2007, respectively. For his M.S.
thesis, he worked on resistive-switching memories (RRAMs)
within the Dipartimento di Elettronica e Informazione,
Politecnico di Milano, Milano, where he is currently working
toward the Ph.D. degree. In 2009 he was a User at the Lawrence
Berkeley National Laboratories, Berkeley, California (USA).
His research interests include the characterization and modeling
of electrical and physical properties in RRAM devices as well as
nanowire-based nanostructure for memory applications.
Calderoni, Alessandro (6C.2, MY.6)
Alessandro Calderoni received the second (master) level Laurea
degree in Electrical Engineering (cum laude) from Politecnico di
Milano, Italy, in 2006, with an experimental thesis on MOSFET's
noise under microwave irradiation. In 2006 he joined the Research
and Development department of STMicroelectronics (now
Numonyx) within the Compact Modeling team. Since that, he has
been working on advanced CMOS modeling and Floating Gate-
based Memory noise characterization and modeling. Than he
worked on Phase Change Memories transport mechanism and low-
frequency noise. His current research interests include statistical
physical characterization and reliability of PCM over large arrays.
Camozzi, Elisa (MY.5)
Elisa Camozzi was born in Milan, Italy in 1980. In 2004 she
received her Master Degree in Physics (cum laude) from the
Università degli Studi Milano-Bicocca, Milano, Italy, as a result of
one full-time year of research work in the field of biophysics. In
2008 she received a Bachelors degree in Philosophy (cum laude)
from the Università degli Studi di Milano, Milano, Italy, with a
dissertation about human mind, knowledge and the best way to
describe both of them. From 2005 she works in the R&D of
STMicroelectronics (now Numonyx) in the field of NOR/NAND
memories.
Cannon, Ethan (SE.2)
Ethan Cannon is a Radiation Effects Engineer with the Solid State
Electronics Development organization in Boeing Research &
Technology in Seattle, where he works on characterization and
mitigation of radiation sensitivity of advanced deep sub-micron
technologies. Previously, he worked as a Reliability Engineer
focusing on radiation-induced soft error simulations, measurements
and qualifications in the IBM Systems and Technology Group in
Essex Junction, Vermont. He received the B.S. degree in
engineering physics from the University of California, Berkeley, and
the M.S. and Ph.D. degrees in physics from the University of Illinois
at Urbana-Champaign.
Cao, Yiqun (4D.1)
Yiqun Cao studied electrical and electronic engineering at the
Rheinisch-Westflische Technische Hochschule (RWTH) Aachen in
Germany. He received his Dipl. Ing. degree in 2007. The same year
he joined smart power technology R&D at Infineon Technologies in
Munich, where he is currently working on his Ph.D. thesis in close
collaboration with the Institute for On-Board Systems Lab at the
Technische Universität Dortmund. His field of research is ESD
protection concepts in high voltage automotive technologies, with
focus on chip- and system-level ESD.
Carine, Besset (2B.2)
Carine Besset received the Engineer Degree in physics (2001) from
the INPG (Institut National Polytechnique de Grenoble, France).
She joined STMicroelectronics (Crolles, France) in 1992, where she
worked on back-end dielectric process developments and
industrialization during 9 years. Since 2001, she is in the Reliability
Group where she is involved in process development-qualification
and process support for reliability aspects in CMOS technologies,
Analog and derivative applications. Her main interests are BEOL
dielectrics reliability and front-end device reliability.
Cartier, Eduard (2B.1, 4A.3, BD.3)
Eduard Albert Cartier was born in Switzerland in 1951. He earned a
bachelors degree (1971), a masters degree (ETH, Zurich,
Switzerland, 1977) and Ph.D degree (Dr.sc.nat., granted with
honors) from ETH in 1982. From 1984 till 1987 he worked as a
research staff member at the ASEA Brown Boweri (ABB) Research
Center in Baden-Dattwil, Switzerland. Since 1988, he works as a
research staff member of the IBM Research Division at the T.J.
Watson Research Center in Yorktown Heigths, NY, USA. Over
the last 10 years he has been working on the development of
alternative, high-k gate dielectrics for CMOS applications.
Catthoor, Francky (SE.1)
Francky Catthoor received a Ph.D. in EE from the Katholieke
Univ. Leuven, Belgium in 1987. Between 1987 and 2000, he has
headed several research domains in the area of high-level and
system synthesis techniques and architectural methodologies,
including related application and deep submicron technology
aspects, all at IMEC Leuven, Belgium. Currently he is an IMEC
fellow. He is also part-time full professor at the EE department
of the K.U.Leuven. He has been elected IEEE fellow in 2005.
Cellere, Giorgio (4B.3)
Giorgio Cellere got his MS and Ph.D. degrees in 1998 and 2002
at Padua University. As a post-doc researcher at Padua
University, he worked on ultrathin gate oxides reliability, on
radiation effects on advanced nonvolatile devices, and on
microelectronic devices for biological applications. He is now
with Applied Materials Baccini, Treviso, Italy, where he is
working at the development of advanced tools and processes for
crystalline silicon solar cells. He holds more than 100 scientific
publications, including two book chapters and ten patents. He
served as Reviewer and Session Chair in international
conferences and his research works won several prices.
Ceric, Hajdin (IC.6)
Hajdin Ceric was born in Sarajevo, Bosnia and Herzegovina, in
1970. He studied electrical engineering with the University of
Sarajevo, Sarajevo, and received the Dipl.Ing. degree in 2000
and the Ph.D.degree in technical sciences in 2005 from
Technische Universität Wien, Vienna, Austria. In June 2000, he
joined the Institute for Microelectronics, Technische Universität
Wien, where he is currently a Postdoctoral Researcher. His
scientific interests include interconnect and process simulation.
Cester, Andrea (4F.2)
Andrea Cester received the degree (magna cum laude) in
electronic engineering and the Ph.D. degree in electronic and
telecommunication engineering from the Padova University,
Italy, in 1998 and 2002, respectively. He is currently an
Assistant Professor with the Department of Information
Engineering, Padova University. He is the author of more than
120 papers published in international journals and conference
proceedings. His previous research interest included the
reliability issues of deep-submicrometer CMOS devices and
advanced nonvolatile memories. His current research interests
are characterization, reliability, and modeling of organic
electronic devices such as OTFT, OLED, and organic and
hybrid solar cells.
Chancellor, Cathy (4A.6, 5E.5)
Cathy Chancellor received her Bachelor of Science degree in
Engineering Technology from the University of Arkansas at
Little Rock in 1983. She is a Member of the Group Technical
Staff in the Texas Instruments External Development and
Manufacturing Reliability group. She has been with TI for over
25 years and is responsible for reliability testing for TI’s leading
edge technology development. She is co-author on ten papers
covering TDDB, NBTI, and process integration and co-inventor
on one patent.
Chang, C. Y. (CD.3)
C. Y. Chang received the Ph.D. degree in 2006 in physics from
the National Central University, Taiwan, R.O.C. During 2005–
2006, he was a visiting student in Department of Chemical
Engineering, University of Florida, Gainesville. He is a postdoctoral
associate in the Department of Materials Science & Engineering,
University of Florida, Gainesville, FL. His interests are in growth of
carbon nanotube and GaN nanowires, and characterization of III-V
compounds materials and devices. He has published over 30 journal
publications.
Chang, Wing L. (BD.3)
Wing L. Chang received the bachelor of science degree in
Mathematics and Chemistry from Lyon College in 1995 and the
PhD in Physical Chemistry/Material Science from the University of
North Carolina at Chapel Hill in 1999. Currently, she is a
technology reliability engineer with the IBM Technology Group in
Hopewell Junction, NY.
Chao, Yuan-Peng (MY.3)
Yuan-Peng Chao was born in HsinChu, Taiwan, R.O.C., in 1984. He
received the B.S. and M.S. degrees in electrical engineering from
National Chiao-Tung University, HsinChu, Taiwan, R.O.C., in 2006
and 2008, respectively. In 2008, he joined Macronix International
Co., Ltd. (MXIC), Hsinchu, Taiwan, R.O.C., and has been with the
Device Engineering Department, where he has engaged in MOS
device characterization and modeling, interconnect capacitance
characterization, and high-voltage device modeling.
CHAPPAZ, CEDRICK (IC .1)
Cedrick Chappaz received the M.S. in electrical and optronics
engineering from the Ecole Nationale Superieure d’Ingenieur (ENSI
CAEN) in 1998. Afterwards, he pursued a Ph.D. in the field of
Microsystems. He obtained its Ph.D. in 2003. its expertise in
MEMS, integrated optics and characterization lead him to do a post-
doctorate year in the Commissariat a l’Energie Atomique (CEA) in
LETI laboratories from 2003 to 2004. Then, he joined
STMicroelectronics as an expert in Reliability and Characterization
fields in 2004. Since this date, he’s in charge of the qualification of
BEOL of advanced technologies and specific 3D integration.
Chatterjee, Amitabh (EL.5, IC.10)
Amitabh Chatterjee graduated from IIT Powai with (5yrs Int.)
M.Tech in electrical engineering and subsequently, he joined as a
scientist at the Centre for Advanced Technology, Indore in the Laser
Physics Division in 1996. His work involved development of ultra
fast avalanche transistor based HV Marx Bank Circuit ands its
impact on the stability of ultra-short laser pulses. His research
included analysis of bipolar snapback due to low doped resistive
drift region of a HV BJT under avalanche break-down and study of
avalanche injection mechanisms from the ohmic contacts. Currently
he is working on his doctoral dissertation on the reliability of Drain
Extended NMOS (DeNMOS) under ESD stressing at the Univ. Of
CA, Santa Barbara.
Chatty, Kiran (EL.3)
Kiran Chatty received his B. Tech in Electrochemical Engineering
in 1995 from Central Electrochemical Research Institute (CECRI),
India, and M.S. in 1996 in Materials Science from New Jersey
Institute of Technology (NJIT), Newark, NJ and his Ph.D. in 2001 in
Electrical Engineering from Rensselaer Polytechnic Institute (RPI),
Troy, NY. He is a Senior Engineer in IBM’s Semiconductor
Research and Development Center (SRDC) focusing on ESD and
Latchup development in digital and analog & mixed signal CMOS
and BiCMOS technologies. Kiran served as the chair of the
ESD/Latchup session at the 2006 IRPS, co-chair of the 2009 IRPS,
chair of the Bipolar, RF and HV ESD session at 2009 EOS/ESD
symposium, served as a member of EOS/ESD symposium and IRPS
technical committees. He has authored or co-authored over 35
technical papers in journals/conferences, has 10 issued patents and
many patent applications.
Chen, An (2C.2)
An Chen is a Member of Technical Staff at
GLOBALFOUNDRIES. He is working in the Strategic
Technology Group on emerging logic and memory technologies.
He is an assignee of the Nanoelectronics Research Initiative
(NRI) within SRC, and collaborates with university research
groups to develop beyond-CMOS logic solutions. An Chen
received his Ph.D. in Electrical Engineering from Yale
University in 2004. Before joining AMD (currently
GLOBALFOUNDRIES) in 2007, he worked in the Advanced
Memory Development Group at Spansion LLC.
Chen, Fen (5A.5)
Fen Chen received his Ph.D. degree in Electrical Engineering in
1998 from University of Delaware. From 1997 to 1998, he was
with IBM System Group at Rochester, MN and Intel Component
Research at Santa Clara, CA as a graduate intern working on
system stress and IC interconnect reliability. He joined IBM
microelectronics at Essex Junction, VT in 1998 and has worked
on semiconductor technology reliability issues since that time.
During the past several years he has focused on low-k ILD
TDDB issue for various IBM and IBM Alliance development
programs.
Chen, Kangguo (XT.14)
Dr. Kangguo Cheng is currently a Lead Engineer of IBM
Research at Albany Nanotech, responsible for leading the
exploration of fully depleted devices for 22nm node and beyond.
He received a B.Eng. and a M.Eng. from Tsinghua University,
China, and a Ph.D. degree from University of Illinois at Urbana-
Champaign (UIUC). Since joining IBM in 2001, he has worked
on process/device integration in a variety of advanced
semiconductor technologies including memory, embedded
memory, bulk, SOI, finFET, ETSOI, etc. He is a Master
Inventor of IBM with over 200 patents and patent applications.
He has over 50 peer-reviewed journal/conference publications.
Chen, Ke-Hung (CD.3)
Ke-Hung Chen is currently working toward the Graduate degree
in the Department of Chemical Engineering,University of
Florida, Gainesville. He is the author or coauthor of more than
12 papers published in refereed journals. His current research
interests include advanced wide bandgap sensors and III-V
compound electronics reliability.
Chen, Kuan-Fu (5D.3)
Kuan-Fu Chen was born in Taipei, Taiwan, R.O.C. on
September 21, 1978. He received the B.S. degree in physics
from National Taiwan University, Taipei, Taiwan, R.O.C. in
2000 and the M.S. degree in electrical engineering from
National Taiwan University, Taipei, Taiwan, R.O.C. in 2002. He
joined Macronix International Company, Ltd., Hsinchu, in 2002
as a Process Integration Engineer. He worked on process
integration and devices characteristics analysis for nonvolatile
floating-gate-type and nitride storage flash memory.
Chen, Kuang-Chao (5D.3, MY.1, MY.3)
Kuang-Chao Chen received the M.S. degrees in chemistry from
the National Chong-Shan University, Taiwan, in 1987. From
1989 to 1995, he joined Electronic Research and Service
Organization (ERSO), Hsinchu, Taiwan, where he has been
involved in the development of BEOL planarization process
technology. From 1995 to 1998, he was with Mosel-Vitelic
International Co., Ltd, Hsinchu, Taiwan. He performed yield
improvement in manufacturing line. In 1998, he joined
Vanguard International Semiconductor Co., Ltd, Hsinchu,
Taiwan, as a department manager. He was responsible for thin
film module development. In 2000, he joined Macronix
International (MXIC), where he worked on advanced module
development. He is currently Executive Director of Technology
Development Center.
Chen, Ming-Shiang (5D.2, 5D.3)
Ming-Shiang Chen was born in Tainan, Taiwan, R.O.C. on
September 22, 1970. He received the B.S. and M.S. degrees in
electronics engineering from National Chiao-Tung University,
Hsinchu, Taiwan, in 1992 and 1994, respectively. He joined
Macronix International Company, Ltd., Hsinchu, Taiwan, in 1996 as
a Device Engineer. From 1996 to 1998, he has worked on
nonvolatile memory devices characteristics analysis. Since 1998, he
has been engaged in the development floating-gate Flash memory
technology and Nitride-based NBit technology.
Chen, Wen-Yi (EL.6)
Wen-Yi Chen received the B.S. degree and the M.S. degree both
from the the Institute of Electronics, National Chiao-Tung
University, Hsinchu, Taiwan, in 2003 and 2005, respectively. In
2005, he joined the Circuit Design Department, SoC Technology
Center, Industrial Technology Research Institute (ITRI), Hsinchu, as
a circuit design engineer. In 2006, he joined the Amazing
Microelectronic Corporation and worked with system-level ESD
protection design. He is currently working toward the Ph.D. degree
in the Institute of Electronics, National Chiao-Tung University,
Hsinchu, Taiwan.
Chen, Yi Ning (2C.3)
Yi Ning Chen received the B.Eng degree from Zhejiang University,
China, in 2004, and the M.Eng in materials for microelectronics in
Catholic University of Leuven, Belgium, in 2005. He joined IMEC
(Inter-university MicroElectronic Centre) for student internship in
2005. Since 2007, he is pursuing his Ph.D in Electrical and
Electronic Engineering at Nanyang Technological University,
Singapore.
Chen, Yin-Jen (5D.3)
Yin-Jen Chen was born in Taipei, Taiwan, R.O.C. on October 30,
1976. He received the B.S. and M.S. degrees in electronics
engineering from National Chiao-Tung University, Hsinchu,
Taiwan, R.O.C. in 1999 and 2001, respectively. He joined Macronix
International Company, Ltd., Hsinchu, in 2001 as a Process
Integration Engineer. From 2001 to 2003, he worked on process
integration and reliability testing for floating-gate-type Flash
memory. Since 2004, he worked on nitride stroage memory and
focus on the optimization of operation condition.
Chen, Zuhui (NA. 1)
Zuhui Chen received the B.S. degree in physics from Fujian Normal
University and M.S. degree in solid-state physics from Xiamen
University, Fujian, China, respectively in 1998 and 2001, and Ph.D.
in engineering science from University of Florida, FL, USA, in
2005. In 2006, he was a faculty of the Pen-Tung Sah MEMS
Research Center, Xiamen University, China. In 2007, he joined
Nanyang Technological University as a research fellow with Lee
Kuan Yew Postdoctoral Fellowship. His current interests include
NBTI and interface-trap modeling in silicon MOSFETs.
Cheng, Cheng-Hsien (5D.3)
Cheng-Hsien Cheng was born in Yunlin, Taiwan, ROC., on
December 11, 1982. He recieved the BS and MS degree in
Engineering and System Science from National Tsing Hua
University, Hsinchu, Taiwan, in 2005 and 2007. In 2007, he joined
the Advanced Device Department of Macronix International
Company Ltd., Hsinchu, Taiwan. His research interests include the
device characterization of Flash memory devices.
Chi Wen, Soo (3C.5)
Chi Wen was born in Johor, Malaysia. He received his B.Sc (Merit)
and B.Sc (2nd upper Hons.) in Materials Science from National
University of Singapore in 2000 and 2001 respectively. He is
still pursuing a Master degree in Management Science in
National University of Singapore. He is currently working in
GLOBALFOUNDRIES Singapore and responsible for
Semiconductor chip Failure Analysis work. His strength is
Transmission Electron Microscopy (TEM) Imaging Analysis.
His area of interests include TEM Imaging techniques and
Management Science. He is one of the authors of 1paper in In-
situ TEM studies published in Applied Physics Letter.
Chihiro, Uchibori (3A.5)
Dr. Chihiro J. UCHIBORI received his Ph. D. degree from
Kyoto University, before he started his carrier in Fujitsu
Laboratories LTD in 1996. In 2002, he joined a project in the
University of Texas at Austin as a visiting scientist. Since 2004,
he is working for Fujitsu Laboratories of America as a Senior
Researcher. His interests are in the electrical and mechanical
reliability of ULSI devices. Not only evaluating the reliability
and the manufacturing yield, he is also working on clarification
of the reliability degradation mechanism by experiment and
simulation.
Chih-Yuan, Lu (5D.4)
Chih-Yuan Lu received B.S. degree from National Taiwan
University in 1972, and Ph.D. degree in physics from Columbia
University, NYC, in 1977. In Dr. Lu has been a professor in
National Chiao-Tung Univ. and with AT&T Bell Labs from
1984-1989; later joined ERSO/ITRI in 1989 as a Deputy
General Director responsible for the MOEA grand Submicron
Project. This project successfully developed Taiwan first 8-inch
manufacturing technology with high density DRAM/SRAM. He
was therefore granted the highest honor prize--National Science
& Technology Achievement Award by the Prime Minister of
ROC, due to his leadership and achievement in this Submicron
Project. In 1994, Dr. Lu becomes the co-founder of Vanguard
International Semiconductor Corporation, which is a spin-off
memory IC Company from ITRI’s Submicron Project. He was
the VP of Operation, VP of R&D, and later President from
1994-99. Dr. Lu now is the founding chairman and CEO of
Ardentec Corp. a VLSI testing service company; and also serves
Macronix International as a Senior VP/CTO, and now the
President. Dr. Lu led MXIC’s technology development team to
successfully achieve the state of the art nonvolatile memory
technology and now responsible for MXIC’s overall operation.
Dr. Lu has published more than 300 papers and has been granted
140 worldwide patents, and was elected a Fellow of IEEE, and a
Fellow of APS. He also received IEEE Millennium Medal, and
the most prestige semiconductor R&D Award in Taiwan from
Pan Wen Yuan Foundation.
Chikhaoui, Walf (2E.3)
Walf Chikhaoui was born in Tunisia in 1983. He obtained his
Master degree at the National Institute of Applied Science
"INSA Lyon" in 2007. He is currently PhD student at Institute of
Nanotechnology of Lyon (INL). His work consists in the
analysis of degradation mechanisms of AlGaN/GaN and
AlInN/GaN HEMT structures by electrical and optical methods.
Child, Craig (5A.5)
Craig Child received a Ph.D. degree in Chemical Physics in
1996 from The University of Texas at Austin. From 1996 to
2001, he was with 3M Corporation in Austin, Tx working as a
laser physicist in the Electronic Products Division. In 2001, he
joined Intel Corporation in Hillsboro, OR as a backend of line
integration engineer working on 130nm, 90nm, 65nm, and 45nm
technology nodes. In 2007, Craig joined the IBM ASTA/ISDA
alliance as an AMD employee working on ULK integration in
the 45nm and 32nm technology nodes.
Chin, Melida (4C.6, 5A.4)
Melida Chin received her M.S. and Ph.D. in Mechanical
Engineering from the University of Michigan in 2001 and 2005,
respectively. After graduation, she joined the Technology and
Development group in GLOBALFOUNDRIES (formerly AMD),
where she currently works as a Senior Technology and Integration
Engineer. Her research work focuses on thermo-mechanical analysis
and modeling of subjects such as chip-package interaction and
reliability of back-end-of-line (BEOL). Before attending graduate
school, she worked as a general engineer at the Panama Canal for
the design, build, repair and improvement of electrical and
mechanical infrastructure systems.
Chioko, Kaneta (4A.5)
Chioko Kaneta received the B.S., M.S., and D.S. degrees in Physics
from Tohoku University, Sendai, Japan in 1980 and 1982, and 1985,
respectively. She joined Fujitsu Laboratories Ltd., Japan in 1985 and
has been engaged in atomic scale simulations of defects in Si
crystal, gate dielectrics, and the interfaces between them for
advanced silicon devices. She is a member of the Japan Society of
Applied Physics and The Physical Society of Japan. She received a
fellow award from the Japan Society of Applied Physics for
contributions in the atomic scale simulations.
Chiu, Jung-Piao (MY.3)
Jung-Piao Chiu was born in Kaohsiung, Taiwan, R.O.C., in 1985.
He received the B.S. degree in electronics engineering from
National Chiao-Tung University, Hsinchu, Taiwan, in 2007, where
he is currently working toward the Ph.D. degree in electronics
engineering. His main research interests are in the field of reliability
analysis in high-k devices and Monte Carlo simulation.
Chloé, Guerin (2B.2)
Chloé Guérin obtained the Engineer degree in materials and
microtechnologies from the Institut National des Sciences
Appliquées (INSA), Toulouse, France, and the M.S. in nanophysics
from the Université Paul Sabatier, Toulouse, France in 2005. She
worked in the Reliability Group of STMicroelectronics, Crolles,
France, in collaboration with the Institut Matériaux
Microélectronique Nanoscience de Provence (IM2NP), Toulon,
France to receive her Ph.D in microelectronics from the Université
de Provence, Aix-Marseille I, France in 2008. The aim was to study
Hot Carrier degradation on advanced CMOS technologies under
both static and dynamic supply voltage. She is currently working in
Photovoltaic for Roth and Rau Switzerland, on high efficiency c-Si
cells development.
Cho, Moonju (XT.9, XT.10, XT.13)
Received the M.Sc. and the Ph.D. degrees in materials science and
engineering from Seoul National University, Korea, in 2003 and
2007, respectively. Her study was focused on the physical properties
of ALD-HfO2 films and reliability problems based on
chlorine/carbon residues.In 2005, she stayed at IMEC, Leuven,
Belgium, working on TDDB and charge pumping. From 2007 till
February 2009, she did postdoctoral study at IMEC in theoretical
modeling for oxide trap characterization. She is currently working at
the Reliability Group, IMEC. Her current interest is on hot carrier
injection and trap characterization study on ultrathin high-k gate
oxide.
Cho, Myoung Kwan (MY.7)
Myoung Kwan Cho received the B.S. degree in E.E. from Yonsei
University, in 1988, and the M.S. and Ph.D. degrees in E.E. from
Pohang University of Science and Technology 1997 and 2000,
respectively. In 1988, he joined Samsung Electronics Company,
Korea, where he had been engaged in the development of 2 Tr.
EEPROM, Mask ROM, OTP-EPROM, NOR flash, SONOS, NAND
flash. Since 2004, he had worked in Korea Intellectual Patent Office
as a patent examiner for Non volatile semiconductor memory patent.
And received the B.S degree from KNOU and M.S. degree in law
from Yonsei University in 2007, 2008, respectively and in
pursuit of Ph.D in law. Since joined Hynix Semiconductor in
2009, he has been working on device and process integration of
SLC and 3bit/cell NAND in 32, 41nm technology.
Choi, Gil-Bok (2C.4)
Received the B.S. (2004) and Ph.D (2010) in electronics
engineering from the Pohang University of Science and
Technology (POSTECH), Pohang, Korea. His main research
interests include CMOS devices and RF measurement.
Choi, Hyun Ki (5C.1)
Hyun Ki Choi was born in Busan, Korea, on May 3, 1980. He
received the B.S. degree in electronic engineering from Inha
University, Korea, in 2006. He has been working for Samsung
electronics, Gyunggi-Do, Korea since 2006 and has been in a
Flash Memory Process Architecture team and worked in 42nm
16Gb NAND flash and 35nm, 32nm 32Gb NAND flash. His
recent research interests include 27nm NAND flash memory
development and reliability.
Choi, Hyun-Sik (2C.4)
Received the B.S. (2004), M.S. (2006) and Ph.D (2010) in
electronics engineering from the Pohang University of Science
and Technology (POSTECH), Pohang, Korea. His main research
is related to CMOS devices.
Choi, Rino (RM.3)
Rino Choi received his BS and MS in the Department of
Inorganic Materials Engineering of the Seoul National
University in 1992 and 1994, respectively. After he worked for
Daewoo Motors Company from 1994 to 1999, he joined a Ph.D
program of Materials Science and Engineering in the University
of Texas at Austin. After his completion of his Ph.D in 2004, he
worked as a project manager of the electrical characterization
and reliability of advanced gate stacks at SEMATECH.
Since September, 2007, he is with School of Materials Science
and Engineering, Inha University, Korea
Choi, Jeong-Hyuk (5C.1)
Jeong-Hyuk Choi was born on March 8, 1962, in Seoul, Korea.
He received the B.E. degree in chemical engineering from Inha
University, Korea in 1985. He joined the Memory Division,
Samsung Electronics, Gyunggi-Do, Korea, in 1985, where he
has been working on the process integration of EEPROMs, NOR
flash memories, and NAND flash memories. Currently, he is an
executive director of Flash Product & Technology division, and
leader of Flash Process Architecture team. His current work is
focus on high-density NAND flash memories sub 30nm
technology, and research interests are NVM reliability, cell
technology, yield modeling and field.
Chong, Lit-Ho (5D.3)
Was born in Johor Bahru, Malaysia, in 1976. He received the
PhD degree in Microelectronics from the University of
Southampton in 2006. He joined Macronix International
Company, Ltd., Hsinchu, Taiwan, in 2006 as a device engineer.
He has been working on the research and development of the
nitride storage Flash memory.
Chou, H.L. (2F.3)
H.L. Chou received the M.S. degree in Mechanical Engineering
from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C.
in 2002. He joined the Taiwan Semiconductor Manufacturing
Company (TSMC) , Hsinchu, Taiwan, R.O.C. in 2002. He
works in Division of Anolog Power IC and Special Technology.
He is currently the Principle Engineer for the development on
power IC and BCD technology.
Chou, Tso-Min (4F.3)
Tso-Min Chou graduated in Physics from the Tamkang University,
Taipei in 1988, and obtained the M.S. and Ph.D. degrees from
Southern Methodist University, Dallas, TX in 1990 and 1996
respectively. Between 1996 and 2000, he worked at Southern
Methodist University as a post-doctoral researcher. Currently he
works as researcher scientist in the R&D organization at TriQuint
Semiconductor, TX.
Chou, Y. C. (CD.1)
Y. C. Chou received the Ph.D. degree in electrical engineering and
computer science from the University of California, Irvine, in 1997.
Since 1996, he has been a HEMT product engineer at Northrop
Grumman Aerospace Systems (NGAS, Redondo Beach, CA). At
NGAS, he has been involved in the technology development of high
reliability assurance on 4-inch GaAs and InP-based HEMT MMICs
for commercial, military, and space applications. In 2009, he was
elevated to the IEEE Senior member. He has authored and co-
authored more than 100 papers in the journals and conferences in the
areas of GaAs, InP, GaN-based , and AlSb/InAs HEMT devices and
MMICs.
Chou, You-Liang (MY.3)
You-Liang Chou received the B.S. degree in electrical engineering
from National Chiao-Tung University, Hsinchu, Taiwan, in 2006.
He is currently pursuing the Ph.D. degree at the same university. His
research is devoted to the study of microscopic mechanisms in flash
memory devices. His research interests include reliability analysis in
semiconductor memory and high-voltage devices.
Chouard, Florian Raoul (CR.2)
Florian Raoul Chouard received the Dipl.-Ing. degree in electrical
engineering from the Technische Universität München (TUM),
Germany, in 2007. He is currently working towards the Dr.-Ing.
degree on reliability aspects of advanced analog circuits at the
Institute for Technical Electronics, TUM, in collaboration with
Analog Circuit Exploration, Infineon Austria AG, Austria. His
research interests are aging mechanisms of advanced CMOS devices
and the impacts on analog/RF circuits.
Chowdhury, Uttiya (4F.3)
Uttiya Chowdhury received the B. Sc. Engg. in Electrical and
Electronic Engineering from Bangladesh University of Engineering
and Technology in 1995 and the Ph. D. (2002) in Electrical
Engineering from University of Texas at Austin. He has worked as
researcher at Georgia Institute of Technology and Arizona State
University and presently works at TriQuint Semiconductor, Texas as
a development engineer. His present focus is failure analysis and
reliability of GaN HFET devices.
Chu, Fan (6C.4)
Dr. Fan Chu was born on Dec. 26, 1960 in Beijing, China. He
received the B.S. and M.S. degree in electrical engineering from
Xi'an Jiaotong University of Xi'an, China, in 1982 and 1987
respectively. He received PhD. Degree in electronic material science
from Swiss Federal Polytechnique Institute (EPFL) in Lausanne,
Switzerland, in 1994. From 1994 to 1996, he was a post-doctoral
research fellow in EPFL , Switzerland and in MRL in the
Pennsylvania State University, USA. He is presently a principal
scientist in Ramtron International Corp. dealing with F-RAM
process and product development.
Chu, Byung-Hwan (CD.3)
Byung-Hwan Chu received his B.S. degree in chemical engineering
at New Mexico State University in 2006. He joined the Chemical
Engineering department at the University of Florida in 2006 and
earned his M.S. degree in 2008. He is currently continuing his study
at University of Florida as a Ph.D. student. His research interests are
in GaN devices.
Chung, Chilhee (5C.1)
Chilhee Chung is an Executive Vice President of Semiconductor
R&D Canter in Samsung Electronics. He is in charge of
Technology Development for DRAM, Flash Memory, PRAM,
and Advanced Logic in Semiconductor R&D Center. He has
been with Samsung Electronics, Semiconductor Business since
1979. he was promoted to Senior Vice President in January
2005. He was in charge of LSI Technology Development as
wall as product development of Image sensor and Driver IC.
Along with promotion to Executive VP in January 2009, he
moved to Memory Division as a head of Flash Product and
Technology group. Dr. Chung has got Bachelor of Science in
Physics from Seoul National University, Master of Science in
Physics from KAIST (Korea Advanced Institute of Science and
Technology), and PhD in Physics from Michigan State
University.
Cirba, Claude (5E.5)
Claude R. Cirba was born in August, 21, 1965 in Dakar,
Senegal. He attended the University of Montpellier in France,
receiving his Ph.D. in Electrical Engineering in 1996. He was a
Senior Research Associate in the field of radiation effects on
semiconductors at Vanderbilt University, Nashville TN, from
1997 to 2003. Since 2003 he is a modeling specialist within the
RF-CMOS Spice Modeling Lab at Texas Instruments, Dallas
TX. For several years he has been an industrial liaison on TI-
sponsored university research projects and actively participated
on the GEIA Compact Model Council, an international
consortium which promotes standardization of models for
integrated circuit design. Claude is author or co-author of 18
refereed professional publications.
Croes, Kristof (5A.1, 5A.2, 5B.4, 6A.3)
Kristof Croes received his BSc in physics at the Catholic
University of Louvain (Belgium) in 1993 and his MSc in
biostatistics at the Limburgs Universitair Centrum (LUC) in
1994. In 1999, he obtained his PhD, concerning the development
of statistical techniques for planning reliability experiments.
After that, he joined the reliability business unit of XPEQT, first
as the software responsible and than as the manager of the R&D.
From 2003 till end 2006, he was product and application
manager of the package level reliability products of Chiron
holdings. Beginning 2007, he went back to research, working as
a BEOL reliability engineer in IMEC.
Curutchet, Arnaud (2E.3)
Arnaud Curutchet was born in Dax, France, in 1975. He
received the Ph.D. degree in electronics from the University of
Bordeaux, Talence, France, in 2005. In 2006, he held a post-
doctoral position with the Institut d'Electronique, de
microelectronique et de nanotechnnologies (IEMN) laboratory.
One topic of his post-doctoral position was non linear
characterization of CNFETs. He is currently an Associate
Professor with the University of Bordeaux (ENSEIRB-
MATMECA), and carries out his research at the Intégration du
Matériau au Système (IMS) laboratory. He has authored or
coauthored 13 publications in international conferences and
journals. His research concerns electric characterization (low-
frequency noise, pulsed and microwave measurements) and
modeling of GaN HEMTs devices.
De Jaeger, Jean Claude (2E.3)
Jean-Claude DE JAEGER is currently Professor of
electronics.He is head of the Microwave Power Devices
research group at IEMN. Current research and developed
projects concern the simulation, the design, the fabrication and
the measurement of microwave power HEMTs based mainly on
GaN as well as devices based on wide bandgap semiconductors
such as BN, AlN and diamond. From 2002 to 2007, he was also
deputy manager of TIGER, a common laboratory between IEMN
and ALCATEL - THALES III-V Lab, working on wide bandgap
semiconductors. He is the author or a co-author of about 250
publications and communications.
Defrance, Nicolas (2E.3)
Nicolas Defrance received his M.Sc. and Ph.D. degrees in Electrical
Engineering in 2004 and 2007, respectively. He worked on
characterization, modeling and technology of AlGaN/GaN HEMTs
for microwave power applications. After graduation he worked at
Thalès Alenia Space - Belgium within Research & Innovation
group. Since 2009 he joined the Institute of Electronics,
Microelectronics and Nanotechnology (IEMN) as an associate
professor. His current research activities rely on the study of
advanced wide bandgap-based devices for millimeter wave
applications with emphasis on electrical characterization. He carries
out his teaching activities at the University of Lille in the field of
electrical engineering.
Degraeve, Robin (2A.3, XT.9, XT.13)
Robin Degraeve received the M.Sc. degree in electrical engineering
from the University of Gent, Belgium, in 1992, and the Ph.D. degree
from the Catholic University of Leuven, Belgium, in 1998. He
joined the Interuniversity Microelectronics Center (IMEC), Leuven,
in 1992 in the CMOS Reliability and Characterization group, where
he is working as a Principal Scientist. His work currently focuses on
advanced and novel characterization techniques for studying
electrical defects in dielectrics and related reliability aspects. This
includes characterization and reliability of high-k material in
transistor and memory applications, hot-carrier related issues and
breakdown physics.
Della Marca, Vincenzo (6C.1)
Vincenzo Della Marca was born in Modena, Italy, in 1983. He
received B.S. and M.S. degrees in electronic engineering from the
Università degli Studi di Modena e Reggio Emilia, Modena, Italy, in
2005 and 2008, respectively. During his M.S. degree thesis, he
studied and characterized electrical properties, in Phase Change
Memory (PCMs) devices. Since 2008 he has been working for
Università degli Studi di Modena e Reggio Emilia, on
characterization of electrical properties in TANOS devices. His
research interests also include the characterization and modeling of
resistive-switching memories (RRAMs).
Demirtas, Sefa (2E.2)
Sefa Demirtas graduated from Bogazici University in June 2007
with a Bachelor of Science degree in Electrical and Electronics
Engineering. He earned his Master's degree from MIT in June 2009
in the area of device physics and reliability of GaN high electron
mobility transistors. He is currently pursuing his Ph.D at MIT.
Demuynck, Steven (6A.3)
Steven Demuynck received a PhD in Physics from the Katholieke
Universiteit Leuven in 2000. In 2001 he joined imec where he
joined the interconnect integration team. His research focuses on
advanced contact module and narrow pitch low-k integration. He
has (co-) authored over 70 conference and journal publications in
the field of microelectronics.
Denison, Marie (HV.1)
Obtained her M.Sc. degree in Applied Physics from the University
of Liege, Belgium in 1997 and the Ph.D. degree in Electrical
Engineering from the University of Bremen, Germany in 2004.
From 1998 to 2005 she worked on the development of Smart Power
devices and technologies at Infineon Technologies in Germany.
Since 2005, she has been working at Texas Instruments, Dallas,
Texas on the development of BCD (Linear BiCMOS) technologies
and on high-voltage component design and process integration.
Deora, Shweta (XT.15)
Shweta Deora received her bacholar of engineering degree in
Electronics and communication Engineering from Sardar Patel
University, Gujarat, India in 2004. She was at IIT Bombay
working as research assistant on radtion sensor project during
2005-2006. Since 2006, she is doing her PhD in electrical
engineering department, IIT Bombay. Her reserch interest are in
field of semiconductor device physics, reliability and modeling
of CMOS devices. She is currently working on NBTI in SiON
and high-k gate dielectrics.
Depner, Martin (6C.4)
"Marty" Depner lives in Colorado Springs with his wife,
daughter, and three sons. He graduated in 1989 with B.S. in
Physics from the University of Colorado at Colorado Springs.
He started in the semiconductor industry at Ramtron, working
from 1995 to 2001 as an Engineering Technician in the FAB. He
worked for Atmel, Corp., in the FAB, for most of 2001 and
returned to Ramtron in February 2002 where he worked on the
joint TI/RIC project helping to create the world's first high
density F-RAM product. He is presently a Product Engineer at
Ramtron.
Derkits, Gustav (FA.5)
Gustav Derkits, Ph.D., is a Reliability Physicist in the Alcatel-
Lucent Reliability Physics Group in Murray Hill, NJ. He joined
Bell Laboratories in 1982 and has worked in a variety of
technical areas including design and fabrication of III-V
electronic and optoelectronic devices, and physics and chemistry
issues affecting yield, quality, and reliability of
telecommunications products. Gus has over 30 US patents and
has authored over 20 papers in peer-reviewed journals. He has
been certified by the American Society for Quality as a Six
Sigma Black Belt.
Detcheverry, Celine (2D.2)
Celine Detcheverry received her PhD in Electronics from the
University of Montpellier II, France. She joined Philips
Research in 1998 to work on Polymer Electronics circuits and
models. In 2001 she moved to Philips Resarch Leuven, Belgium,
to explore process options in advanced CMOS for RF
applications. In 2004 she joined Philips Semiconductors 300mm
Foundry in Crolles, France, within the Alliance of Philips (to
become NXP in 2007) / ST microelectronics and Freescale
Semiconductors. She hold there a position of RFCMOS Project
coordinator for the 3 companies. In 2007 she became Process
Owner CMOS065 at NXP Semiconductors in Nijmegen.
Detzel, Thomas (IC.6)
Thomas Detzel received the M.S. degree in physics from the
University of Konstanz, Konstanz, Germany, and the Ph.D.
degree in surface and thin film physics in 1994 from the Max-
Planck-Institute, Garching, Germany. In 1995, he was with
Rodel Europe GmbH, where he was an Application Manager for
chemical–mechanical polishing. In 1999, he joined Infineon
Technologies Austria AG, Villach, Austria, where he was
responsible for the metallization development of power
semiconductors, has been the Project Manager of different
power integrated circuit developments since 2004, and has been
leading the research project Robust Metallization and
Interconnect in the Competence Center for Automotive and
Industrial Electronics since 2006.
Di Sarro, James (EL.3)
James Di Sarro received the B.S. degree in electrical
engineering and economics from Duke University in 2004. He
received the M.S. degree in 2006 and the Ph.D. degree in 2009
from the University of Illinois at Urbana-Champaign, both in
electrical engineering. In 2009, he joined IBM as an Advisory
Engineer/Scientist in the Semiconductor Research & Development
Center (SRDC) focusing on ESD device and model development in
SOI technologies.
Didier, Goguenheim (2B.2)
Didier GOGUENHEIM received the Engineer degree in electrical
engineering from Institut Supérieur d'Electronique du Nord (ISEN-
Lille) in 1987 and the Ph.D degree in Physics from the University of
Lille in 1992. In 1992, he joined ISEN-Toulon (Institut Supérieur de
l'Electronique et du Numérique) school, where he still works as
Director of the Research activities. Since 2000, he has been member
of the IM2NP laboratory (Institut Matérieux Microélectronique et
Nanosciences de Provence, UMR CNRS 6242). His current research
fields concern static and dynamic degradation modes in advanded
MOSFETs, reliability of ultra-thin gate insulators (< 2 nm), and
defect characterization in insulators and semiconductors.
Digh, Hisamoto (PI.3)
Digh Hisamoto received the B.S., M.S. degrees in reaction
chemistry and the Ph. D. degree in electronic engineering from the
University of Tokyo, Tokyo, Japan, in 1984, 1986, and 2003,
respectively. In 1986, he joined Central Research Laboratory,
Hitachi Ltd., Tokyo, where he has been working on ULSI device
physics and process technologies. His current research interests
include thin-film SOI materials, short-channel MOSFETs,
semiconductor memories, Si-RF devices, and Si-Photonics devices.
Dr. Hisamoto is a member of IEEE Electron Device Society, the
Japan Society of Applied Physics, and the Institute of Electronics
and Communication Engineers of Japan.
Djelassi, Christian (4C.5)
Christian Djelassi received his Diploma degree in electronics and
equipment engineering from the Carinthia University of Applied
Science in Villach in July 2009. Since his diploma thesis he works
as a researcher in the Quality and Reliability Group of KAI and
Infineon, respectively. His main research fields contain package
stress and short circuit measurements as well as FEM simulations.
Domengie, Florian (3C.2)
Florian Domengie was born in France in 1984. He received the
engineer degree in physics engineering and the M.S. degree in
materials for electronics and plasma engineering in 2007 from the
Institut National des Sciences Appliquées (INSA), Toulouse,
France. Since 2007, he is working as a Ph.D. student in
STMicroelectronics (Crolles, France) in collaboration with the
Institute of Microelectronics, Electromagnetism and Photonics
(IMEP-LAHC, Grenoble, France). His current research interests are
the electrically active defects in CMOS image sensors and the
metallic contamination in silicon.
Douvry, Yannick (2E.3)
Yannick Douvry was born in Cambrai, France, in 1985. He obtained
both his master degree at the University of Lille1 and his engineer
diploma at the “Institut Supérieur d’Electronique et du Numérique
(ISEN)” in 2008. He is currently working as a PhD student at the
Institute of Electronics, Microelectronics and Nanotechnology
(IEMN). The topic of the thesis consists to improve design and
manufacture of AlGaN / GaN HEMTs for microwave power
application in K-band and Ka-band. His main activities are
processing and characterization. He is also following an applied
mathematics’ master degree.
Doyen, Lise (IC.8)
Lise Doyen received the Engineering degree in materials and
microelectronics from the Institut National des Sciences Appliquées,
Toulouse, France, in 2005, and the Ph.D. degree in micro- and
nanoelectronics from the Université Joseph Fourier, Grenoble, in
2009. Her dissertation focused on electromigration in advanced
copper interconnects. in collaboration with the CEA-Leti/Minatec
and the Science et Ingeniére des Matériaux et Procédés
Laboratory, Grenoble, France. She is now with Central CAD
Design Solutions, STMicroelectronics, Crolles, France, working
on silicon integrity.
Du, Guoan (XT.5)
G. A. Du received the B.Eng. (Hons) degree from the School of
Electrical and Electronic Engineering, Nanyang Technological
University, Singapore. He is currently pursuing the Ph.D. degree
in the same school under a NTU Graduate Research Scholarship.
His research project is on the characterization of bias-
temperature instability in advanced P-MOSFETs.
Du, Pei-Ying (MY.1)
Pei-Ying Du was born in Taipei, Taiwan in 1982. She received
her B.S in engineering and system science from National Tsing-
Hua University (NTHU) in 2004, and Ph.D. degree in electrical
engineering from National Chiao-Tung University (NCTU) in
2009. She joined Emerging Central Lab. (ECL) in Macronix
International (MXIC) in 2006, where her current research is
engaged in the theoretical modeling and reliability physics of
nitride trapping Flash Memories.
Dua, Christian (2E.3)
Christian Dua received the Engineer degree in Physics from the
University of Clermont Ferrand (France) in 1980. He has
worked in different Units of THOMSON-CSF Group (previous
name of THALES) in the field of microwave devices and
optoelectronic components. From 1982 to 1996 he gained
experience in crystal growth and physical and electrical
characterization of semiconductor materials. In 1997 he joined
the research unit of Thales, TRT, and is participating in the
development of wide band gap semiconductor technologies. His
present activities include the study of reliability of GaN HEMTs.
Eliason, Jarrod (6C.4)
Jarrod Eliason received his BSEE in Electrical Engineering from
GMI Engineering and Management Institute (now Kettering
University) and currently leads the memory macro design group
at Ramtron. Between 2001 and 2004, Jarrod participated in the
joint development program between Ramtron and Texas
Instruments to commercialize F-RAM on TI’s 130nm process.
Jarrod holds 18 patents related to ferroelectric memory. Along
with his father, Jarrod developed a side scan sonar system which
has been used to locate 10 Lake Superior Shipwrecks. They are
currently planning a trip to Newfoundland to search for U-656,
the first U-boat sunk by U.S. forces in WWII.
Emmanuel, Vincent (2B.2)
Emmanuel Vincent received the Engineer degree in electronics,
the M.S. degree in microelectronics in 1992 and the Ph.D.
degree in microelectronics in 1996 from the Institut National
Polytechnique de Grenoble (INPG), Grenoble, France. He
received the Ph.D. degree through a collaboration between
STMicroelectronics Central R&D Labs, Crolles, France, and the
Laboratoire de Physique des Composants à Semiconducteur
(now IMEP/ENSERG), Grenoble. Since 1993, he has been with
STMicroelectronics, where he held various positions in the
reliability area. He is currently an Electrical Characterization
and Reliability Manager in the Crolles 2 Alliance.
Eneman, Geert (XT.10)
Geert Eneman received the B.S. and M.S. degrees in electrical
engineering and the Ph.D. degree on the topic of “Design,
fabrication, and characterization of strained silicon transistors”
from the Catholic University of Leuven, Leuven, Belgium, in
1999, 2002, and 2006, respectively. His Ph.D. work was done in
the Interuniversity MicroElectronics Center (IMEC), Leuven.
He is currently with the CMOS Technology Department, IMEC.
He also holds a postdoctoral position at the Catholic University of
Leuven. He is a Postdoctoral Fellow with the Fund for Scientific
Research-Flanders, Belgium. His current research interests include
the characterization and modeling of Ge MOS devices, Ge junction
analysis, and modeling of alternative device structures.
Enichlmair, Hubert (2A.5)
Hubert Enichlmair received the M.S.(1991) from the University of
Graz and the Ph.D.(1995) in solid state physics from the Technical
University in Linz, Austria. In 1995 he joined austriamicrosystems
AG, Unterpremstaetten, Austria, where his present activities are
focussing on the reliability of integrated power devices. He is author
and co-author of over 30 papers in international journals and
proceedings and issued several patents.
Erica, Douglas (CD.3)
Erica Douglas received her B.S. degree in Physics at the University
of Floirda in 2008. She is currently a graduate student in the
Department of Materials Science & Engineering at the University of
Florida. She has published 5 papers in refereed journals, and her
interests are in wide bandgap devices and their reliability.
Fang, Zheng (MY.4)
Fang Zheng received his B.Eng in Electrical and Electronics
Engineering (EEE) from Nanyang Technological University (NTU)
Singapore in 2008. He is currently pursuing his PhD degree in EEE,
NTU working on metal oxide based resistive random access
memory. His research interest includes memory device fabrication
as well as physical and electrical characterization.
Fantini, Paolo (6C.2, MY.6)
Paolo Fantini received the Laurea and the Ph.D. degree in physics
from Modena University, Italy in 1999. In 2000 he has been
engaged by STMicroelectronics to work in the Compact Modeling
team. Since 2004 he is a Team Leader of Compact Modeling of
STMicroelectronics. After the Numonyx foundation in 2008 he held
the Compact Modeling Manager position in Numonyx. He published
more 50 papers covering many fields, from the solid-state physics to
device physics, modeling, low-frequency noise.
Faqir, Mustapha (2E.5)
Received the M.S. degree (summa cum laude) in electronics
engineering from the University of Modena e Reggio Emilia, Italy.
In 2009, he received the Ph.D. degree in electronics engineering,
jointly from the University of Modena e Reggio Emilia and the
University of Bordeaux 1, France. He was with MD Microdetectors,
Modena, where he worked for two years as an R&D Engineer. His
research interests include the study and the analysis through
experimental measurements and numerical simulations of trapping
effects in gallium nitride devices and their reliability, as well as
thermo-mechanical modeling and characterization of GaN
electronics packaging. Currently, he is a research assistant in the
CDTR at the University of Bristol, UK.
Farbiz, Farzan (4D.2)
Farzan Farbiz is a Ph.D. candidate in the Department of Electrical
and Computer Engineering at the University of Illinois at Urbana-
Champaign. He received his B.S. degree in electrical engineering
from the University of Tehran, Iran. Since 2005, he has been at the
University of Illinois, studying integrated circuit reliability in the
Illinois Center for Integrated Microsystems (iCIMS). He has held
summer positions at Freescale and Texas Instruments. He has
received the 2008 IRPS best student paper award and the 2010
Gregory Stillman semiconductor research award from University of
Illinois for excellence in semiconductor research.
Farina, Fabrizio (MY.6)
Fabrizio Farina was born in Brindisi, Italy, in 1985. He received
the B. degree in Electronics Engineering from the Politecnico di
Milano, Milan, Italy in 2007. Since 2009 he has been working
on characterization and modelling of Advanced non-volatile
memories. His research interest is in the areas of application-
specific integrated circuit design.
Ferro, Massimo (6C.2)
Massimo Ferro was born in Italy, in 1983. He received the
master Laurea in electronic engineering from the Politecnico di
Milano, Milan, Italy, in 2009. During his thesis, he worked on
phase change memories with the Department of Electronic
Engineering, Politecnico di Milano, collaborating with the
Modeling & Characterization team of the Advanced R&D,
Numonyx, Agrate Brianza, Italy, where he has been working on
modeling and characterization of transport properties of
amorphous chalcogenide-based devices.
Fleming, Debra (FA.5)
Debra Fleming is a Member of the Technical Staff for
Reliability Engineering Group at Alcatel-Lucent in Murray Hill,
New Jersey. Debra is a materials engineer with expertise in
materials processing, characterization, failure mode analysis,
and component prototyping. Her present work is focused on the
reliability of lead-free solder and the failure mode analysis of
telecommunication components.. She received her B.S. and
M.S. in Ceramic Science and Engineering from Rutgers
University in New Brunswick, NJ. Debra has 18 U.S. patents
and has coauthored more than 50 papers in the area of novel
optical, electronic, and magnetic materials and components.
Francis, Rick (2D.3)
Rick Francis is an associate engineer at GLOBALFOUNDRIES
in Sunnyvale California where he works on reliability testing for
lifetime and design manual characterization of sub-micron
devices. He graduated from Heald College in San Jose with a
degree in electrical engineering in 2000 when he joined
Advanced Micro Devices. He has been with AMD and
GLOBALFOUNDRIES for over nine years as an associate
engineer and software programmer. He is currently attending
University of Phoenix to obtain a B. S. degree in software
engineering.
Franco, Jacopo (2A.3, XT.10, XT.13)
Jacopo Franco received the B.Sc. and M.Sc. degrees in
Electronic Engineering from the University of Calabria - Italy,
in 2005 and 2008 respectively. His M.Sc. thesis was developed
during an internship at IMEC, Leuven - Belgium, and is related
to reliability issue in advanced Silicon and Germanium
MOSFETs. Since Feb. 2009 he is working toward a Ph.D.
degree in the reliability group of IMEC and at the Katholieke
Universiteit Leuven, on the topic “Interface stability and
reliability of Ge and III-V transistors for future CMOS
applications”. He is the recipient of the Ed Nicollian Best
Student Paper Award at the 40th IEEE Semiconductor Interface
Specialists Conference (SISC).
Franey, John (FA.5)
John Franey P.E. is a Distinguished Member of Technical Staff
in the Alcatel-Lucent Reliability Physics Group in Murray Hill,
NJ. He joined Bell Laboratories in 1970. His work has been
focused on failure analysis and the interactions of materials with
people and atmospheric environments. With degrees in
Electronics, Chemistry, and Material science he has been a
corrosion consultant on the Restoration of the Statue of Liberty,
and, the State Department in Washington, DC. John has 36 US
and Foreign Patents in the areas of Corrosion and ESD
Protection, and has authored over 100 papers in those areas of
expertise.
Frei, Stephan (4D.1)
Stephan Frei was born in Germany in 1966. He received his diploma
in electrical engineering in 1995. From 1995 till 1999 he was a
research assistant for EMC at the University of Technology in
Berlin. There he investigated the influence of ESD on electronic
devices and the occurrence rate of ESD in typical environments. In
1999 he received his Dr.-Ing. degree. From 1999 till 2005 he
worked at the car manufacturer AUDI AG in Germany. Here he
introduced and developed, among other things new methods for the
computation of EMC in automobiles. In 2006 he was appointed as
professor for vehicular electronics at the University of Technology
in Dortmund, Germany. His recent research interests include
automotive EMC, Signal Integrity of automotive bus systems, ESD,
and numerical modelling. Professor Frei is active and chairman in
several national and international EMC standardization groups.
From 2008 till 2009 he was appointed as Distinguished Lecturer
from the IEEE EMC Society.
Frost, Christopher (4B.3)
Christopher Frost has been a research scientist at ISIS, the UK’s
pulsed neutron source sited at the Rutherford Appleton Laboratory,
UK, since 1998. He took his BA degree at Trinity College,
Cambridge University where he stayed to complete an M.Phil. and
Ph.D. in neutron science at the Cavendish Laboratory. He undertook
a Post-Doctoral position at Warwick University where he was
seconded to ISIS to help develop the world leading MAPS
spectrometer. He currently leads the design and development of
CHIPIR, a new neutron irradiation facility for electronics. He is a
co-author on over sixty scientific and technical papers in the areas of
condensed matter and fast neutron science.
Fugazza, Davide (6C.3)
Davide Fugazza was born in 1981. He received the M.S. degree
(cum laude) in Electronic Engineering from Politecnico di Milano,
Italy, in 2006. In 2006-07 he worked as a digital hardware engineer,
developing base band processing algorithms for PtP microwave
radio systems. In January 2008 he joined the Dipartimento di
Elettronica e Informazione, Politecnico di Milano, as a Ph.D. student
in Information Technology. His primary research interests are in the
area of microelectronics devices and his research activity is actually
mainly focused on the characterization and modeling of switching
and reliability characteristics for phase change non volatile
memories (PCMs).
Fujii, Shosuke (MY.2)
Shosuke Fujii received the B.S. (2005) and M.S. (2007) in materials
science and engineering from Kyoto University, Kyoto, Japan. He
joined Advanced LSI Technology Lab, Toshiba Corp., Yokohama,
Japan, in 2007, where he has been engaged in the research on
reliability physics of non-volatile memories.
Fujiki, Jun (MY.2)
Jun Fujiki received the B.S. (2003) and M.S. (2005) in applied
physics from the department of applied physics school of
engineering, Tokyo University, Tokyo, Japan. He joined the
Advanced LSI Technology Lab, Toshiba Corp., Yokohama, Japan,
in 2005, where he has been engaged in the research on reliability
physics of non-volatile memory devices.
Fujisawa, Takafumi (5F.2)
Takafumi Fujisawa was born in Nagano, Japan, on March 22, 1985.
He received the B.S. degree in electronic engineering from Tohoku
University, Sendai, Japan in 2008. He is currently working toward
the M.S. degree in the Graduate School of Engineering, Tohoku
University (MC2).
His research interests are the development of processes
suppressing the variability of MOSFETs and Random Telegraph
Signal (RTS) noise.
Fujitsuka, Ryota (MY.2)
Ryota Fujitsuka received the B.S. (2003) and M.S. (2005)
degrees, from Nagoya University, Nagoya, Japan. In 2005, He
joined Process and Manufacturing Engineering Center, Toshiba
Corporation, Semiconductor Company, Yokohama, Japan,
where he worked on development of dielectric film for advanced
nonvolatile memory device. He is currently engaged in
development of nonvolatile memory device in Advanced
Memory Development Center, Semiconductor Company,
Toshiba Corporation, Yokkaich, Japan
Fujiwara, Tetsuo (PI.1)
Tetsuo Fujiwara received his B.E. and M.E. in materials science
from Kyoto University, Kyoto, Japan in 1987 and 1989,
respectively. He joined Hitachi Research Laboratory of Hitachi,
Ltd., Ibaraki, Japan in 1989. Since 2005, he has been working as
a senior engineer for Renesas Technology Corp. (now Renesas
Electronics Corporation), Ibaraki, Japan, where he is engaged in
developing metallization processes.
Fukatsu, Shigeto (4C.2)
Shigeto Fukatsu, received the B.E. (2000), M.S. (2002), and
Ph.D. (2005) in applied physics from Keio University, Japan. In
2005, he joined Advanced LSI Technology Laboratory, Toshiba
Corporation, Yokohama, Japan. He has been engaged in the
research on the reliability physics of MOSFETs.
Fuketa, Hiroshi (3A.4)
Hiroshi Fuketa received the B.E. degree from Kyoto University,
Kyoto, Japan, in 2002 and the M.E. degree in information
systems engineering from Osaka University, Osaka, Japan, in
2008. He is currently pursuing the Ph.D. degree from the
Graduate School of Information Science and Technology, Osaka
University. His research interests include ultra-low-power
circuit design and variation modeling. Mr. Fuketa is a student
member of IEEE and IEICE.
Fukuda, Toshikazu (5F.4)
Toshikazu Fukuda received B.S. degree and M.S. degree in
mathematics from the Osaka University, Osaka, Japan, in 1993
and 1995, respectively. He joined TOSHIBA Corporation in
1995 as a TCAD development engineer. Since 2000, he has
worked on static-RAM development: circuit and layout design,
library development, yield estimation and soft-error related
issues. He joined Environmental Variability Tolerant Device
Technology Program of MIRAI project in 2008.
Fukutani, Atsuyuki (4C.1)
Received D.Sc. from the University of Tokyo in 1990. From
1990 to 1995, he worked as a research associate in the Surface
Science group at Institute for Solid State Physics of the
University of Tokyo. Since 1995, he has been at Institute of
Industrial Science of the University of Tokyo where he is a
Professor of the Department of Fundamental Engineering. His
major is surface and interface physics, and he is currently
interested in chemistry and physics of hydrogen at solid surfaces
and interfaces.
Fulde, Michael (CR.2)
Michael Fulde received the Dipl.-Ing. degree in electrical
engineering from the Technische Universität München (TUM),
Germany, in 2005 and the Dr.-Ing. degree in 2009. From 2005
to 2008, he was with the Institute for Technical Electronics,
Technische Universität München, where he worked on
technology oriented analog and mixed-signal circuit design in
emerging multi-gate CMOS technologies. In 2008 he joined the
Analog Circuit Exploration group at Infineon Technologies Austria
AG. He is currently working on high-speed mixed signal and digital
enhanced RF circuits in advanced CMOS nodes.
Funayama, Kota (PI.2)
Kota Funayama received his B.E. and M.E. in materials science
from Tohoku University, Miyagi, Japan in 1995 and 1997,
respectively. He joined Hitachi, Ltd., Tokyo, Japan in 1997. Since
2003, he has been working as an engineer for Renesas Technology
Corp. (now Renesas Electronics Corporation), Ibaraki, Japan, where
he is engaged in the research and development of advanced MCU
technology.
Futase, Takuya (PI.1, PI.2)
Takuya Futase received his B.E. and M.E. in materials science and
engineering from Muroran Institute of Technology, Hokkaido, Japan
in 1994 and 1996, respectively. He began pursuing a Ph. D. in
materials science from the University of Tsukuba, Ibaraki, Japan in
2010. He joined Hitachi ULSI Engineering Corp. in 1996 and then
joined Hitachi, Ltd. and Renesas Technology Corp. in 2001 and
2002, respectively. Since 2010, he has been working for Renesas
Electronics Corporation, where he is engaged in front-end
metallization for advanced logic devices. Mr. Futase is a member of
The Japan Society of Applied Physics and of IEEE.
Gadlage, Matthew (3A.2, 6E.2)
Matthew J. Gadlage received his B.S. in electrical engineering from
the University of Evansville in 2002 and his M.S. in electrical
engineering from Vanderbilt University in 2004. Since 2002, he has
been a member of the Radiation Sciences Branch at Crane Naval
Surface Warfare Center. His primary research interests include the
effects of radiation on electronic circuits and soft errors. He has
authored or co-authored over 30 papers in these research areas. He
is planning to finish his Ph.D. in electrical engineering at Vanderbilt
University in the spring of 2010.
Galbiati, Nadia (MY.5)
Nadia Galbiati graduated in physics from the University of Milano
Italy, (1994) and received the Material Science Diploma in (1997)
from the University of Milano Italy. In 1998 she joined the
STMicroelectronics in Agrate Brianza (Italy) working in the Non
Volatile Memory Process Development group within the Dielectric
Reliability group of Central R&D. Her research activities include
failure and wear-out mechanism of all active dielectric of non
valatile memories, in particular characterization of dielectrics and
new materials for charge trap memory applications.
Gasiot, Gilles (4B.4)
Gilles GASIOT received the M.S. (2000) and Ph.D. (2004) in
microelectronics from the University of Bordeaux, France. His
thesis research (in collaboration with STMicroelectronics and
French Atomic Energy Commission, Military applications centre at
Bruyères-le-Chatel) focused on the reliability of bulk and SOI
devices in the natural radioactive terrestrial environment (neutrons
and alpha particles). In 1999, he joined for a trainee period the
Radiation Effect Group at Vanderbilt University, USA. Since 2004,
he has been with Central R&D, STMicroelectronics, Crolles,
France, and has been actively working on soft error rate
characterization (experimental and simulated) for ultradeep
submicrometer CMOS processes. Dr. Gasiot has coauthored more
than 40 articles and holds 2 patents in radiation hardening. He is also
member of the IEEE.
Gauthier Jr., Robert (EL.3)
Robert Gauthier has worked in IBM’s Microelectronics Division
since 1995. He has worked in the areas of ASIC design, CMOS
device design (350nm -180nm technology nodes), ESD/Latchup
technology and design enablement development (250nm - 15nm
technology nodes). He is currently a Senior Technical Staff Member
(STSM) and Manager in IBM’s System and Technology Group
(Semiconductor Research and Development Center’s - SRDC)
where his department focuses on ESD/Latchup development for
IBM’s analog and mixed signal, leading edge bulk CMOS , RF-
CMOS, silcon-on-insulator (SOI) and research technologies.
His current research interests are in the area of next generation
ESD devices/solutions for 15nm and beyond technology nodes.
His external involvement outside of IBM consists of serving as
the vice-chair of the ESD/Latchup session at the International
Reliability Physics Symposium (IRPS) for the 2000 symposium
and chair of the ESD/Latchup session in 2001. He was session
chair and moderator of the On-chip CMOS session at the
EOS/ESD symposium in 2003 and in 2007 the session chair of
the On-chip physics session at the EOS/ESD symposium. In
addition, from 2002-2009, he has been actively serving on the
EOS/ESD symposium TPC sub-committees. In 2007 he was
one of the founders of the International ESD Workshop (IEW)
where he has served roles as Communication Chair and
Technical Program Chair. In 2009 he was the EOS/ESD
symposium Technical Program Chair and in 2010 is the
EOS/ESD symposium Vice General Chair. In 2010 he will be
serving as a member of the ESD Association Board of Directors
and will be taking on the mission of Secretary on the ESD
Association Executive Committee. He has authored or co-
authored over 50 papers and has received the 33rd level
invention plateau at IBM (over 128 patents filed).
Geinzer, Thomas (3C.4)
Thomas Geinzer studied electrical engineering at the University
of Cooperative Education Ravensburg, Germany, gaining his
Bachelor in 2003. He continued his studies at the University of
Wuppertal and received his Master degree within the Faculty of
Electrical, Information and Media Engineering. Since 2005 he is
PhD student at the Department of Electronics of the University
of Wuppertal.
Genoe, Jan (4F.2)
Jan Genoe was born in Leuven, Belgium on May 19, 1965. He
obtained his Ph.D. degree in electronic engineering on May 31,
1994. Afterwards, he joined the Grenoble High Magnetic Field
Laboratory as a Human Capital and Mobility (HCM) Fellow of
the European Community. Currently, he's professor at the
Katholieke Hogeschool Limburg (KHLim) and head of the
Polymer and Molecular Electronics (PME) group of imec.
Gerardin, Simone (3F.2, 4B.3)
Simone Gerardin received the Laurea degree (cum laude) in
Electronics Engineering in 2003, and a Ph.D. in Electronics and
Telecommunications Engineering in 2007, both from the
University of Padova - Italy. He is currently a research assistant
at the same university. His research is focused on soft and hard
errors induced by ionizing radiation in advanced CMOS
technologies, and on their interplay with device aging and ESD.
Simone has authored or co-authored more than 40 papers
published in international journals and more than 50 conference
presentations, three of which won awards at RADECS 2007,
NSREC 2008, and RADECS 2008.
Ghetti, Andrea (5C.4)
Andrea Ghetti received the Laurea (summa cum laude) and
Ph.D. degrees in electrical engineering both from the University
of Bologna, Bologna, Italy. In 1994, he was a Visiting Scientist
at the TCAD Department of Intel Corporation. From March
1997 to March 2000, he held a postdoctoral position with Lucent
Technologies, Bell Laboratories, Murray Hill, NJ. In May 2000,
he joined STMicroelectronics, that later became Numonyx. He
has authored or coauthored more than 70 peer-reviewed papers,
contributed a chapter to a book on Oxide Reliability and served
in the IEDM Modeling and Simulation subcommittee. His
research interests are in the field of nonvolatile memory
development and device modeling, simulation and characterization.
Dr. Ghetti received twice the “Outstanding paper award” at the
International Reliability Physics Symposium in 2000 and 2008.
Ghidini, Gabriella (MY.5)
Gabriella Ghidini received the Ph.D. in physics in 1983 from the
City College of New York. In 1983 she joined the Central R&D
department of STMicroelectronics in Agrate Brianza, Italy. In 1987
she moved to the Non-Volatile Memory division, becoming the
leader of the Dielectric Reliability Group. Her research activities
include failure and wear-out mechanism of active dielectric of
Flash NOR and NAND memory devices and the evaluation of new
technologies for the future generations. She is coauthored over 130
papers and 12 patents in the abovementioned topics. From 2008 she
joined Numonyx (Agrate Brianza, Italy) with the same role.
Ghidotti, Michele (5C.2)
Michele Ghidotti was born in Cremona, Italy, in 1981. He received
the Bachelor’s and Master’s degrees in Electrical Engineering from
the Politecnico di Milano, Milano, Italy, in 2003 and 2006,
respectively. He is currently working toward the Ph.D. degree with
the Dipartimento di Elettronica e Informazione, Politecnico di
Milano, working on experimental characterization and modeling of
ultra-scaled Flash memory reliability.
Ghilardi, Tecla (MY.5)
Tecla Ghilardi, graduated in Physics in 1990 at the University of
Milan. After degree, she joined the Research and Development
group of STMicroelectronics, and, since 1998, of Numonyx. Her
field of work is NOR and NAND Flash memories process
development.
Giai Gischia, Gianni (5A.2)
Gianni Giai Gischia received the M.Sc. Degree in physic in 2002
from the University of Turin, Italy and the advanced master in
material science in 2008 from the University of Pavia, Italy. He is
part of the BEOL group at Imec, Belgium and his research activity
focuses on dielectric reliability in advanced copper/low-k
interconnect.
Giliberto, Valentina (3F.2)
Valentina Giliberto was born in Brindisi, Italy, in 1984.
She graduated in Electronics Engineering at the University of
Padova in 2009, working on the reliability of switch RF-MEMS, in
particular on the study of the degradation of contact resistance.
Gill, Balkaran (3A.1)
Balkaran Gill received the B.E. degree in electronics and
communication engineering from Gulberga University, Gulberga,
India in 1998 and the M.S. and Ph.D. degrees in computer
engineering from the Case Western Reserve University, Cleveland
Ohio in 2002 and 2005 respectively. Dr. Gill worked with IROC
Technologies in 2003 and 2004. He is currently a component design
engineer in architecture for quality and reliability with Intel
Corporation, Hillsboro, Oregon. His interests are modeling and
mitigation of transient errors and robust circuit design
methodologies for low power systems. He has published more than
ten technical papers and holds several pending U.S. patent
Glaser, Ulrich (4D.1)
Ulrich Glaser received the Dipl.-Phys. degree in physics from the
University of Bayreuth, Bayreuth, Germany, in 2002 and the Ph.D.
degree from the Swiss Federal Institute of Technology (ETH),
Zurich, Switzerland, in 2007. He worked in the field of quantum
information theory in his Diploma thesis.In 2002, he joined the
Integrated Systems Laboratory, ETH, where he was involved in
research and development projects about device simulation of
electrostatic discharge (ESD) phenomena in close collaboration with
the CMOS ESD group of Infineon Technologies AG, Munich,
Germany. In 2006, he joined the automotive power technology
research and development group of Infineon Technologies,
where, since then, he has been responsible for the development
of ESD devices and concepts, as well as the ESD on-chip
protection in advanced smart power technologies.
Glavanovics, Michael (4C.5)
Michael Glavanovics studied electrical engineering at the
Technical University of Vienna, Austria, where he obtained his
PhD in 1994 . In 1997 he went to Villach, Austria to join
Infineon technologies as a Senior Staff Engineer for smart
power design. Since 2006 he has been involved in the
foundation and building up of the KAI competence center for
automotive and industrial electronics in Villach. His main focus
is on the development of power cycling reliability test methods
for smart power semiconductors.
Gnani, Elena (HV.1)
Received the Laurea and Ph.D. degrees in electrical engineering
from the University of Bologna, Bologna, Italy, in 1999 and
2003, respectively. Since October 1999, she has been with the
Department of Electronics (DEIS), University of Bologna, in the
field of investigations on physics of carrier transport and
numerical analysis of semiconductor devices, where she is also
currently with the Advanced Research Center for Electronic
Systems (ARCES).
Gnudi, Antonio (HV.1)
Received the B.S. and the Ph.D. degree in electrical engineering
and computer science from the University of Bologna, Bologna,
Italy, in 1983 and 1989. From 1989 to 1990, he was a Visiting
Scientist with the IBM T. J. Watson Research Center, NY. He
became a Research Assistant in 1990 and has been an Associate
Professor of electronics since 1998 with the University of
Bologna, where he worked on the design of analog CMOS
circuits for RF applications and of RF MEMS devices. His
current research interests include numerical simulation of
nanometric devices and efficient algorithms for their solution.
Goodson, Kenneth (2C.5)
Dr. Kenneth E. Goodson is Professor and Vice Chair of
Mechanical Engineering at Stanford University. Goodson was
educated at MIT (Ph.D. 1993, MS 1991, BSME 1989, BSH
1989) and spent two post-doctoral years with the Materials
Group at Daimler-Benz AG. His Stanford research group
includes approximately 20 students, research associates, and
affiliated faculty. The group studies thermal transport
phenomena in semiconductor nanostructures, energy conversion
devices, and microfluidic heat sinks, with a focus on those
occurring with very small length and time scales. Goodson is a
co-founder and former CTO of Cooligy, Inc., which builds
microfluidic cooling systems for computers and was acquired by
Emerson, Inc., in 2005. Goodson received the ASME Journal of
Heat Transfer Outstanding Reviewer Award, and now serves as
an Associate Editor for this Journal. Goodson serves as Editor-
in-Chief of Nanoscale and Microscale Thermophysical
Engineering. He has been a JSPS Visiting Professor at The
Tokyo Institute of Technology and received the ONR Young
Investigator Award and the NSF CAREER Award. He and his
group have published more than 100 archival journal articles,
150 conference papers, and ten books and book chapters, which
have been recognized through best paper awards at SEMI-
THERM, the Multilevel interconnect Symposium, SRC
TECHCON, and the IEDM.
Gorini, Giuseppe (4B.3)
Giuseppe Gorini. After graduating cum laude in Physics at Pisa
University and Scuola Normale Superiore in 1985, Giuseppe
Gorini (GG) received a PhD cum Laude in Physics at Scuola
Normale Superiore (Pisa) in 1991. Since 2000 Giuseppe Gorini is
associate professor at the Physics Department of Milano-Bicocca
University. For the past 20 years GG has been engaged in the
development of new experimental methods for neutron
measurements in fusion and material science. The scientific
production by GG is documented in 130 journal papers.
Gornik, Erich (4D.4)
Prof. Erich Gornik has studied at the Technical University of
Vienna, where he finished his Ph.D. in 1972. He was Postdoc from
1975 to 1977 with the Bell Laboratories. From 1979 until 1988 he
was full Prof. for Experimental Physics at the University of
Innsbruck from where he changed to the Technical University of
Munich as director of the Walter Schottky Institute. Since 1993 he is
full Prof. for Semiconductor Electronics and since 1995 he is head
of the Microstructure Center at the Technical University of Vienna.
In 2003-2008 he was a managing director of Austrian Research
Center Seibersdorf. Erich Gornik is author and co-author of more
than 750 publications in scientific journals mainly in the field of
semiconductor physics and technology. His main expertise is current
transport and mid-infrared to far-infrared emission spectroscopy of
semiconductor nanostructures.
Gossner, Harald (4D.4, EL.2)
Harald Gossner received the degree in physics (Dipl.Phys.) from the
Ludwig–Maximilians University, Munich, Germany, in 1990, and
the Ph.D. degree in electrical engineering from the Universität der
Bundeswehr, Munich, in 1995. Since 1995, he has been with
Infineon technologies AG, Munich, working on the development of
ESD protection concepts for bipolar, BiCMOS, and CMOS
technologies. He is the Head of the team of Infineon’s center of
competence for ESD and external latchup development and also a
Senior Principal who guides the company activities in the field of
overvoltage robust design. He has authored and coauthored more
than 40 technical papers and one book in the field of ESD. Dr.
Gossner is a member of the management board of the International
ESD Workshop (IEW) and a Cochair of the Industry Council on
ESD Target Values. He is serving in the TPC of EOS/ESD
Symposium, IEDM, and IEW.
Goto, Masakazu (4C.2)
Masakazu Goto received the B. E. and M. E. degrees in applied
physics from University of Tsukuba, Tsukuba, Japan, in 2003 and
2005, respectively. He joined the Center for Semiconductor
Research & Development of Toshiba Semiconductor Company,
Yokohama, Japan, in 2005. His current work is the development of
metal gate /high-k CMOS devices. He is a member of the Japan
Society of Applied Physics.
Grasser, Tibor (2A.1, 2A.2, 2A.3, 2A.5, XT.6, XT.8, XT.10)
Tibor Grasser received his Ph.D. degree in technical sciences from
the TU Wien where he is currently employed as an Associate
Professor. In 2003 he was appointed head of the Christian Doppler
Laboratory for TCAD in Microelectronics. Dr. Grasser is the co-
author or author of over 250 scientific articles, editor of a book on
advanced device simulation, a senior member of IEEE, has been
involved in the program committees of SISPAD, IWCE, ESSDERC,
IRPS, IIRW, and ISDRS, and is a recipient of the Best Paper
Awards at IRPS and ESREF. He was also a chairman of SISPAD
2007.
Green, Keith (5F.3)
Keith Green received the Ph.D. and M.S. degrees in Electrical
Engineering from the University of Florida in 1993 and 1990,
respectively, and the B.S. degree in Electrical Engineering from the
University of Delaware in 1988. He has been with Texas
Instruments in Dallas, TX since 1993, with a career dedicated to the
development and extraction of compact models for integrated circuit
design. He has worked on models for CMOS and BiCMOS
technologies for analog, digital, and RF design applications. He
has modeled almost every major component type: MOSFETs,
LDMOS, BJTs, diodes, capacitors, resistors, and many more. He
is currently a Distinguished Member of the Technical Staff and
responsible for the development of new compact models to
support analog technology and circuit development. He is the
Chairman of the Semiconductor Research Corporation’s
Compact Modeling Technical Advisory Board and the Vice-
Chair of the Compact Model Council, a standards consortium of
approximately 40 semiconductor and EDA companies from
Asia, Europe, and the United States.
Groeseneken, Guido (2A.3, 5A.2, 6A.3, XT.9, XT.10, XT.13)
received the M.Sc. degree in electrical and mechanical
engineering (1980) and the Ph.D degree in applied sciences
(1986), both from the Katholieke Universiteit Leuven, Belgium.
In 1987 he joined the R&D Laboratory of IMEC (Interuniversity
Microelectronics Center) in Leuven, Belgium, where he is
responsible for research in reliability physics for deep submicron
CMOS technologies. From October 2005 until April 2007 he
was also responsible for the IMEC Post CMOS Nanotechnology
program within IMEC’s core partner research program. Since
2001 he is also Professor at the KU Leuven,where he is Program
Director of the Master in Nanoscience and Nanotechnology, and
where he is also coordinating a European Erasmus Mundus
Master program in Nanoscience and nanotechnology. He
became an IEEE Fellow in 2005 and an IMEC Fellow in
2007.He has made contributions to the fields of non-volatile
semiconductor memory devices and technology, reliability
physics of VLSI-technology, hot carrier effects in MOSFET's,
time-dependent dielectric breakdown of oxides, Negative-Bias-
Temperature Instability effects, ESD-protection and –testing,
plasma processing induced damage, electrical characterization
of semiconductors and characterization and reliability of high k
dielectrics. Recently he has also interest in nanotechnology for
post-CMOS applications, such as carbon nanotubes for
interconnect applications, tunnel FET’s for alternative nanowire
devices etc.He has served as a technical program committee
member of several international scientific conferences, among
which the IEEE International Electron Device Meeting (IEDM),
the European Solid State Device Research Conference
(ESSDERC), the International Reliability Physics Symposium
(IRPS), the IEEE Semiconductor Interface Specialists
Conference (SISC) and the EOS/ESD Symposium. From 2000
until 2002 he also acted as European Arrangements Chair of
IEDM. In 2005 he was the General Chair of the Insulating Films
on Semiconductor (INFOS) conference, organized in Leuven,
Belgium.He has authored or co-authored more than 500
publications in international scientific journals and in
international conference proceedings, 6 book chapters and 10
patents in his fields of expertise.
Grossi, Alessandro (MY.5)
Alessandro Grossi received the Laurea degree (cum laude) in
Physics from the University of Milan in 1991. In 1993 he joined
the STMicroelectronics R&D Non Volatile Memory
Development group. From 1999 he has been Technology
Development Project Leader for NOR memory applications and
from 2007 he is involved in NAND development. Since 2008,
he has been with Numonyx R&D as Flash Memory Manager
working on new architectures for Flash devices. He is coauthor
of several publications and patents on abovementioned topics.
He has been lecturer in Electron Device Physics at the
University of Milan, University of Parma and University of
Udine.
Gustin, Wolfgang (2A.1)
Wolfgang Gustin received the diploma in physics (1990) from the
University of Stuttgart, and the Ph.D. (1994) from the Max-Planck-
Institut Stuttgart. From 1994-1998, he had been with Philips & IBM,
working on Integration and Unit Process Issues for Logic and
DRAM Technologies. In 1998 he joined the DRAM Development
Group at Infineon Technolgies. Currently, he is the Manager of the
Device Reliability Group at Infineon Technologies.
Haggag, Amr (2D.5, XT.16)
Amr Haggag, from Egypt, was born in Buenos Aires, Argentina, in
1975. He received the B.S. degree in computer engineering and the
M.S. and Ph.D. degrees in electrical engineering from the University
of Illinois at Urbana-Champaign, USA, in 1996, 1999, and 2002,
respectively. Since September 2002, he has been with Freescale
(previously Motorola Semiconductors) in Austin, TX. He serves on
both management and technical committees for the International
Reliability Physics Symposium and the Integrated Reliability
Workshop and has given invited talks/tutorials at conferences such
as International Reliability Physics Symposium, VLSI Test
Symposium, International Test Conference, Design for Variability-
Reliability Workshop and also at Middle East Nanotechnology
Conference patronage of King Abdullah of Jordan. His primary
research interests include transistor and chip-level reliability
specifically those which integrate logic, SRAM and NVM memory
and has led the certification of multiple technology nodes co-
integrating these devices specifically for automotive and networking
applications.
Han, T. T. (5D.2, 5D.3)
Tzung-Ting Han was born in I-Lan, Taiwan, ROC., on November
18, 1973. He received the B.S. degree in engineering science from
National Cheng Kung University, Tainan, Taiwan, R.O.C. in 1997
and the M.S. degree in electrical engineering from National Cheng
Kung University, Tainan, Taiwan, R.O.C. in 1999. In 1999, he
joined Macronix International Co., Ltd., Hsinchu, Taiwan, to work
on advanced diffusion module process development. Since 2002, he
has worked on process integration of advanced non-volatile
memory.
Hang-Ting, Lue (5D.4)
Hang-Ting Lue was born in Hsinchu, Taiwan in 1975. He received
his B.S and M.S degrees in physics from National Tsing-Hua
University (NTHU) in 1997 and 1999, respectively, and Ph.D
degree in electrical engineering in National Chiao-Tung University
(NCTU) in 2002. He joined Emerging Central Lab. (ECL) in
Macronix International (MXIC) in 2003. Currently he is the
department manager of nano-technology R&D, and leads a team to
develop the advanced Flash Memory devices, and the related
theoretical modeling and reliability physics. One of his famous
invention is “bandgap engineered SONOS” (BE-SONOS), which
solves the fundamental problems of SONOS, providing both
efficient hole tunneling erase as well as good data retention.
Currently he is the project manager of BE-SONOS NAND Flash
R&D, and deep involved in the NAND Flash test chip developments
in the company. From 2004 he has published more than 30 papers
in the premier semiconductor conferences including 10 IEDM, 5
VLSI and 15 IRPS, and a total of more than 75 technical papers in
IEEE journal/letter/conference. He was also invited to give invited
papers in ICSICT, MRS, and several workshops. So far he has 11
granted US patents, and more than 30 patents in applications. In
2007, he received the “Outstanding Young Innovator Award of the
Industrial Technology Advancement Awards” by Taiwan’s
government. Currently, he is the chair of IRPS 2010 memory
subcommittee, and committee member in VLSI-TSA.
Hashikawa, Naoto (PI.1, PI.2)
Naoto Hashikawa received his B.S. from the National Defense
Academy in 1987 and his M.S. and Ph. D. in physics from
Tokyo University of Science, Tokyo, Japan in 1992 and 1996,
respectively.
Since 1996, he has been working for the Process Technology
Development Div., Renesas Technology Corp. (now Renesas
Electronics Corporation), on developing ULSI processes and
device-analysis engineering. He is engaged in failure analysis of
ULSIs using advanced TEM technology.
Hashimoto, Masanori (3A.4)
Masanori Hashimoto received the B.E., M.E., and Ph.D. degrees
in communications and computer engineering from Kyoto
University, Kyoto, Japan, in 1997, 1999, and 2001, respectively.
Since 2004, he has been an Associate Professor with the
Department of Information Systems Engineering, Osaka
University, Osaka, Japan. His research interests include
computer-aided-design for digital integrated circuits, and high-
speed circuit design. Dr. Hashimoto was a recipient of the Best
Paper Award at ASP-DAC 2004. He is a member of IEEE,
IEICE, and IPSJ. He served on the technical program
committees for international conferences including DAC,
ICCAD, ASP-DAC, ICCD, and ISQED.
Heh, Dawei (4A.4)
Dawei Heh received the B.S. degree in physics from National
Taiwan University, Taipei, Taiwan, R.O.C., in 1996 and the
M.S. and Ph.D. degrees in electrical engineering from the
University of Maryland, College Park, in 2001 and 2005,
respectively.He was with the CMOS and Novel Devices Group,
NIST, where he studied the reliability and breakdown
mechanisms of ultrathin dielectrics. He joined SEMATECH as a
research engineer in the electrical characterization and reliability
group from 2005 to 2009. He is currently a associate researcher
in the National Nano Device Laboratories in Taiwan. His
research focuses on simulating and characterizing advanced gate
dielectrics on different substrate materials. He also participates
in developing new characterization techniques for future
devices.
Heiderhoff, Ralf (3C.4)
Dr.-Ing. Ralf Heiderhoff became head of the group: "Optical and
Thermal Microscopy Techniques" at the Department of
Electronics within the Faculty of Electrical, Information, and
Media Engineering at the University of Wuppertal, Germany, in
1997. 1999 he was Visiting Lecturer at the National University
of Singapore followed by a Visiting Professorship at the
Belarusian State University of Informatics and Radioelectronics
2001 and at the Beijing University of Technology 2008. His
major research is focused on failure analyses and reliability
investigations in the nanometer range as well as the combination
of Scanning Electron Microscopes and Scanning Probe
Microscopes to hybrid systems.
Hendriks, Teun (SE.1)
Teun Hendriks received his MSc degree from Delft University
of Technology in 1986, with a specialization in aerospace
engineering. He subsequently joined Philips Research
Laboratories in Eindhoven, as a member of Research Staff,
continuing in 1988 at Philips Laboratories in Briarcliff Manor,
NY, USA. In 1996, he returned to The Netherlands to work for
Philips on car navigation systems with emphasis on the
integration of traffic information. Since 2005, he is employed by
the Embedded Systems Institute (ESI) in Eindhoven, The
Netherlands as a research fellow. His research interests lie in
system reliability and interoperability in context of embedded
systems.
Heryanto, Anson (5B.3)
Anson Heryanto was born in Indonesia in 1985. He received his
B.Eng (2006) and M.Sc (2007) degrees in Electrical and Electronic
Engineering from Nanyang Technological University (NTU),
Singapore. He is currently working toward a Ph.D degree at the
same institution. He is a recipient of the Singapore
GLOBALFOUNDRIES-NTU Graduate Research Scholarship
award. His current research interests are reliability of copper
interconnects and 3D-chipstacks. He is currently a Graduate Student
Member of IEEE.
Hideaki, Tsuchiya (6A.4)
Hideaki Tsuchiya received the B.S. and M.S. degrees in physics
from Tohoku University, Sendai, Japan, 2000 and 2002,
respectively. In 2002, he was with NEC Corporation, Sagamihara,
Japan. Since 2002, he has been with the Advanced Device
Development Division, NEC Electronics Corporation, Kawasaki,
Japan, where he has been working on reliability engineering of Cu
interconnects.
Hideki, Makiyama (PI.3)
Hideki Makiyama received the B.S. and M.S.degrees in material
engineering from Kyushu University in 2005 and 2007, respectively.
In 2008, he joined the Renesas Technology Crop., Tokyo, Japan.
Since then, he has been working on research and development of
Low Leakage MOSFET devices.
Hideya, Matsuyama (3A.5, 4A.5)
Hideya Matsuyama received his B.S. from Nagoya University
(1985), Nagoya, Japan. He joined FUJITSU LIMITED in 1985. He
has worked for Product reliability for several years, and has worked
for Wafer Level reliability of BEOL and FEOL. Currently he is a
director of ULSI reliability. He is a chairman of JEITA (Japan
Electronics and Information Technology industries Association)
Failure Mechanism Wafer Reliability Project Group and IEC
(International Electro technical Commission) TC47/WG5 Japanese
International Expert.
Hirano, Izumi (4C.2)
Izumi Hirano, received the B.S. (2000) and M.S.(2002) in physics
from Kyoto University, Kyoto, Japan. She joined the Advanced LSI
Technology Laboratory, TOSHIBA Corporation, Yokohama, Japan,
in 2002, where she has been engaged the study of the reliability of
gate dielectrics, especially High-k gate dielectrics, for ULSI
technology. She is a member of the Japan Society of Applied
Physics.
Hiroko, Mori (4A.5)
Hiroko Mori received the B.S. and M.S. degrees in Physics from
Keio University, Kanagawa, Japan, in 1996 and 1998, respectively.
She joined Fujitsu Ltd. in 1998. Her currently work is reliability
physics for gate dielectrics of ULSI devices.
Hiroshi, Minakata (4A.5)
Hiroshi Minakata was born in 1969 in Aichi Pref., Japan. He
graduated from Higashiyama technical highschool, Aichi, Japan in
1988. He joined Fujitsu Lab. Ltd., Atsugi, Japan in 1988. He is
currently concerned with development of the gate-dielectric, SiON
and High-k, process at Fujitsu Microelectronics Pacific Asia LTD.,
R.O.C
Hiroshima, Shoichi (4C.1)
Joined NEC Corporation. in 1987. He is working on the physical
analysis of LSI process from 2002, in NEC Electronics Corporation.
Hirotoshi, Terada (FA.4)
Hirotoshi Terada received the B.S. degree in Mechanical
Engineering from Keio Univ., Japan in 1985. He joined
Hamamatsu Photonics K.K., and worked as an optics engineer.
He has studied video microscopy and developed confocal
microscope at Marine Biological Laboratory, M.A.,U.S.A. in
1991. He is now in charge of developing optical systems in
Hamamatsu Photonics K.K..He is a member of Reliability
Engineering Association of Japan.
Hiroyuki, Yoshimoto (PI.3)
Hiroyuki Yoshimoto received the B.S., M.S., and Ph.D. degrees
in solid state physics from Waseda University in 2000, 2002,
and 2006, respectively. In 2006, he joined the Central Research
Laboratory, Hitachi, Ltd., Tokyo, Japan. Since then, he has been
working on research and development of CMOS devices
including SOI and high-k MOSFETs. Since 2009, he has also
been working on research and development of power electronics
devices.
Ho, Paul (5B.2)
Dr. Paul S. Ho is the Director of the Laboratory for Interconnect
and Packaging at The University of Texas at Austin. He
received his Ph.D. degree in physics from Rensselaer
Polytechnic Institute. In 1972, he joined the IBM T.J. Watson
Research Center and became the Senior Manager of the
Interface Science Department in 1985. In 1991, he joined the
faculty at the University of Texas and was appointed the
Cockrell Family Regents Chair in Materials Science and
Engineering department. His current research is in the areas of
materials and processing science for interconnect and packaging
applications.
Hoel, Virginie (2E.3)
Virginie Hoel received the Ph.D. degree from the university of
Lille, Lille, France, in 1998. She is currently an Assistant
Professor at Institut d'Electronique, de Microelectronique et de
Nanotechnologie (IEMN), Villeneuve d’Ascq, France. From
1995 to 2000, she was working on design, fabrication and
characterization of InP HEMTs for application in millimeter-
and submillimeter-wave ranges. Since 2000, she worked on
power devices. His main research interests include design,
fabrication and characterization of AlGaN/GaN HEMTs for high
power applications in centimeter- and millimeter-wave ranges.
She carries out his teaching activities at Lille1 University in the
field of electrical engineering.
Hoffmann, Thomas (IC.9, XT.13)
Dr. Thomas Hoffmann has earned his diploma in electrical
engineering, specializing in engineering statistics from the
Dresden University of Technology (Germany) in 1988. He
finished his PhD study at the same university on topics of finite-
element modeling (FEM) of plasma CVD reactors in 1991. After
post-doc research work in the fields of computer simulation and
statistics for semiconductors and microsystems he joined
GLOBALFOUNDRIES (formerly AMD) (Germany) as quality
engineer in 2001. At GLOBALFOUNDRIES he established and
improved methods and processes for manufacturing quality and
reliability statistics. He is responsible for the coordination of
manufacturing quality support at GLOBALFOUNDRIES
(Germany).
Hofmann, Ralf (NA.2)
Ralf Hofmann is a Member of Technical Staff in the Advanced
Technology Group under the Office of the CTO at Applied
Materials. His work involves the evaluation and development of
new processing techniques and equipment for new and emerging
applications in the IC space as well as the energy sector. He
joined Applied Materials in 1994 in the PVD Technology group,
working on various aspects of metal deposition and process
integration. In 2001 he joined ZMD America, Inc., a mixed-signal
ASIC design company, where he worked on two successfully
productized IC designs. He worked from 2002 to 2003 as an
independent consultant for a telecommunications start-up company
as well as a small company in the transportation sector before
rejoining Applied Materials in 2004. Mr. Hofmann received a
Diplom-Ingenieur degree in Electrical Engineering (MSEE) from
Chemnitz University of Technology in Germany.
Holman, Tim (3A.2)
W. Timothy Holman received the B.S.E.E. degree from the
University of Tennessee, Knoxville, in 1986 and the M.S.E.E. and
Ph.D.E.E. degrees from the Georgia Institute of Technology,
Atlanta, in 1988 and 1994, respectively.From 1994 to 2000, Dr.
Holman was an Assistant Professor at the University of Arizona. In
2000, he joined the Department of Electrical Engineering and
Computer Science at the Vanderbilt University School of
Engineering, Nashville, Tennessee. His current research interests
include the modeling and mitigation of radiation effects in analog
and mixed-signal microelectronics. Dr. Holman is a member of the
Institute for Space and Defense Electronics at Vanderbilt University.
Hong, Chong-A (MY.7)
Chong-A Hong received the B.S. degree in electrical engineering
from Chung-Nam University, Korea, in 2006 She joined the Flash
Memory Division of Hynix Semiconductor Inc.,Gyunggi-Do, Korea
, where she has been working on the failure analysis of Nand Flash
Memories. Currently, she is involved in the development of 3x-nm
Nand flash.
Hong, Shih-Ping (MY.1)
Shih-Ping Hong was born in Pingtung, Taiwan in 1975. He received
his PhD. in Chemistry from National Tsing-Hua University, Taiwan,
R.O.C., in 2002. He is currently a project deputy dept. manager of
Etch Process Development Department in Technology Development
Center in Macronix International (MXIC).
Hsiao, Yi-Hsuan (MY.1)
Yi-Hsuan Hsiao was born in Chia-Yi, Taiwan in 1980. He received
his B.S and M.S degrees in electrical engineering from National
Chiao-Tung University (NCTU) in 2002 and 2004, respectively. His
M.S thesis focused on TFT devices. He joined Emerging Central
Lab. (ECL) in Macronix International. Co. (MXIC) in 2005, where
his current research includes developing new nonvolatile memory
devices and reliability studies of nitride trapping Flash Memories.
Hsieh, Jung-Yu (MY.1)
Jung-Yu Hsieh was born in Hsinchu, Taiwan, R.O.C., in 1971. He
received the B.S. degree in chemical engineering from the National
Tsing Hua University, Hsinchu, Taiwan, in 1995, and the M.S.
degree in chemical engineering from the National Tsing Hua
University, Hsinchu, Taiwan, in 1997. He joined the Advanced
Module Process Development Division of Macronix International
(MXIC), in 1997 where he has been working on the process
development of chemical mechanical planarization (CMP). His
current works are engaged in advanced diffusion module process
development.
Hsieh, Kuang-Yeu (5D.2, MY.1)
Kuang-Yeu Hsieh was born in Tainan Taiwan in 1958. He received
his B.S (Physics) and MS (Materials Science) degrees from National
Tsing-Hua University (NTHU) and National Sun Yet-sen University
(NSYSU) in 1980 and 1985, respectively. He obtained his Ph.D. at
North Carolina State University in Materials Science in 1989.
Before he joined Macronix International in 2001, he had been an
Associate Professor at Institute of Material Science in National Sun
Yet-sen University since 1992. His research interests include MBE
thin film growth, characterization of material, solid-state physics, IC
fabrication, and optoelectronic materials. Currently, he is the
Director of Nano-technology R & Div./Emerging Central Lab in
Macronix and involves in developing new nonvolatile memory
devices and exploring new material for the next generation
nonvolatile memory. Meanwhile, he has more than 70 journal
papers published and 15 patents granted.
Hsieh, Sunnys (2F.3)
Sunnys received a B.S degree in Chemistry major from Chung-
Yuan Christian University, Taiwan in 1993, and the M.S. degree
in Chemical Engineering from National Tsing-Hua University,
Taiwan in 1995. He worked in Mosel-Vitelic in 1995 and joined
TSMC since 2000 till now. He involved process integration in
R&D for SRAM development, and then joined HV reliability
team as a section manager in 2005. Currently, he works on HV
PMIC Field Technology Service in Asia-Pacific Business Unit.
Hsu, Fang-Hao (MY.1)
Fang-Hao Hsu received the M.S. degree in mechanical
engineering from the National Taiwan University of Science and
technology, Taipei, Taiwan, R.O.C., in 2006. He is currently a
Principal Engineer in the etch process development department
of Technology Development Center, Macronix International
(MXIC).
Hsu, Tzu-Hsuan (5D.3, MY.1)
Tzu-Hsuan Hsu received the B.S. and M.S. degrees from the
Department of Electrical Engineering and Institute of
Microelectronic Engineering, National Cheng-Kung University,
Tainan, Taiwan, R.O.C., in 2000 and 2002, respectively, and
Ph.D. degree in Institute of Electronics, National Tsing-Hua
University (NTHU) in 2009. He joined Emerging Central Lab
(ECL) in Macronix International Company, Ltd., Hsinchu,
Taiwan, R.O.C., in 2002 working on nanodevice research and
development. His current research areas include high-density
memory development, nitride-trapping memory devices, and
advanced nonvolatile memory technologies.
Hu, Youzhou (XT.5)
Y. Z. Hu, received the B.Sc. and M.Sc. degrees in Applied
Physics from TianJin University, China, in 2001 and 2004,
respectively. He worked as a Process Integration Engineer in
SMIC of China and Chartered Semiconductor Manufacturing for
two and half years. He is currently pursuing the Ph.D. degree in
the School of Electrical and Electronic Engineering, Nanyang
Technological University. His research interest lies in the
meaurement methodologies and mechanisms of bias temperature
instability.
Huang, I. J. (5D.2)
I-Jen Huang received the B.S. degree in electrical engineering
from National Taiwan University, Taiwan, in 1992, and the M.S.
degree in electrical engineering from National Taiwan
University in 1994. He joined Macronix International Co., Ltd.,
Hsinchu, Taiwan, in 1996 as a process integration engineer. He
has worked on process integration of non-volatile memory and
SRAM for several generations. He is presently engaged in array
characterization of NVM products.
Huang, Elbert (5A.5)
Elbert Huang received B. S. degrees in Chemical Engineering
and Materials Science from the University of Minnesota in 1995
and his Ph. D. in Polymer Science and Engineering from the
University of Massachusetts in 1999. From 1999 through 2001
he worked at the IBM Almaden Research Center on the
development and characterization of ultralow-k porous
dielectrics. He moved the IBM T. J. Watson Resarch Center in
Yorktown Heights in 2001, where he has been involved in the
research and development of exploratory materials and integration
for advanced CMOS technologies.
Huang, I-Jen (5D.3)
I-Jen Huang received the B.S. degree in electrical engineering from
National Taiwan University, Taiwan, in 1992, and the M.S. degree
in electrical engineering from National Taiwan University in 1994.
He joined Macronix International Co., Ltd., Hsinchu, Taiwan, in
1996 as a process integration engineer. He has worked on process
integration of non-volatile memory and SRAM for several
generations. He is presently engaged in array characterization of
NVM products.
Huang, Jyun-Siang (5D.3)
Jyun-Siang Huang was born in Chiayi, Taiwan,R.O.C., in 1981. He
received the M.S. degree from Electrophysics Department, National
Chiao Tung University, Hsinchu, Taiwan, in 2006. In 2006, he
joined the Advanced Device Department of Macronix International
Company Ltd., Hsinchu, Taiwan. His research interests include the
device characterization of Flash memory devices
Huang, Rui (IC.6)
Rui Huang received the B.S. degree in materials science and
engineering from Zhejiang University, Zhejiang, China, and the
M.S. degree in materials science and engineering from Kiel
University, Kiel, Germany. He is currently working toward the
Ph.D. degree with Kompetenzzentrum Automobil-und
Industrieelektronik GmbH (KAI), Villach, Austria, in cooperation
with the institute of Microelectronics, Technische Universität Wien
(TU Vienna), Vienna, Austria.
His research is focused on mechanical and thermo-mechanical
properties of copper metallization used in semiconductor devices.
Huang, Yu-Hui (2F.3)
Yu-Hui Huang was born in Taoyuan, Taiwan, R.O.C., on Sep. 19,
1979. She received the B.S. degree in Physics from National Central
University, Taoyuan, Taiwan, R.O.C., in 2002, and the M.S. degree
in electronics engineering from National Chiao Tung University,
Hsinchu, Taiwan, R.O.C., in 2004. She has been working in Taiwan
Semiconductor Manufacturing Company (TSMC), Hsinchu,
Taiwan, R.O.C., as an High Voltage Process Integration Engineer
from 2004 to 2008 and a HV Reliability Engineer now.
Hurkx, G. A. M. (2C.5)
Fred Hurkx was born in Best, The Netherlands, in 1956. He received
the MSc degree in physical engineering and the Ph.D. degree from
the Technical University of Eindhoven, The Netherlands, in 1985
and 1990, respectively. His thesis involved the modeling of
downscaled bipolar transistors. In 1979 he joined Philips Research
Laboratories, Eindhoven, where he has been working in the field of
semiconductor research since 1983. Currently he is with NXP-
TSMC Research Center, Leuven, Belgium.
Hurley, Paul (BD.1)
Paul Hurley received his Ph.D. (1990) and B.Eng.(1985 - First class
honors) in Electronic Engineering at the University of Liverpool. He
is a Senior Research Scientist at the Tyndall National Institute,
University College Cork where his work focuses on high dielectric
constant (high-k) materials intended for use as gate level insulators
in transistors for future integrated circuits. The emphasis of his
current research is the formation and characterisation of high-k films
on silicon and III-V semiconductor substrates. Paul is a member of
the Technical Committee of the Insulating Films on Semiconductors
(INFOS) conference and the International Workshop on Dielectrics
in Microelectronics (WoDiM). In addition to research activities, he
is a part time lecturer in the Department of Microelectronic
Engineering at University College Cork. He has published over sixty
papers in the field of microelectronics.
Hutter, Herbert (XT.6)
Herbert Hutter received his Ph.D. degree in technical sciences
from the TU Wien where he is currently employed as an
Associate Professor. Dr. Hutter is the co-author or author of over
140 scientific articles; all of them were published in the field of
Secondary Ion Masspectrometry (SIMS) of materials and
measurement data treatment. His main working areas are
material analysis, corrosion of nitrides, and diffusion of oxygen
in oxides (using isotope enriched oxygen) and oxidation of
metals. In the field of semiconductors he is working on diffusion
and migration of light mobile ions and high energy implantation
Ielmini, Daniele (5D.1, 6C.2, 6C.3)
Daniele Ielmini received the Laurea (cum laude) and Ph.D. in
Nuclear Engineering from Politecnico di Milano in 1995 and
1999, respectively. In 1999, he joined the Dipartimento di
Elettronica e Informazione, Politecnico di Milano, where he is
an Assistant Professor from 2002. In 2006 he was Visiting
Scientist at Intel Corporation and the Center for Integrated
Systems (CIS), Stanford University. His most recent research
interests include the modeling and the characterization of
emerging phase change memory (PCM) and resistive switching
memory (RRAM). He authored/coauthored two book chapters,
more than 140 papers in international journals and international
conferences.
Iida, Hitoshi (FA.4)
Hitoshi Iida Received MSEE from Tokyo Institute of
Technology in 1971. Has been involved in technical
management for the development of various image
acquisition/analysis/processing systems at Hamamatsu
Photonics K.K. Currently, General Manager of Systems
Division at Hamamatsu Photonics K.K. Japan
Inaba, Yutaka (PI.1)
Yutaka Inaba received his B.E. in electrical engineering from
Kinki University, Osaka, Japan in 1988. He joined Mitsubishi
Electric Corporation, Hyogo, Japan in 1988. Since 2003, he has
been working as a senior engineer for Renesas Technology
Corp. (now Renesas Electronics Corporation), Ibaraki, Japan,
where he is engaged in developing diffusion processes. Mr.
Inaba is a member of The Japan Society of Applied Physics.
Inan, Umran (3A.3)
Umran S. Inan is Professor of Electrical Engineering and
Director of the Space, Telecommunications, and Radioscience
Laboratory at Stanford University. Prof. Inan has published over
300 refereed journal articles and 2 textbooks in
electromagnetism, and actively conducts research on near-Earth
low frequency electromagnetic waves and their applications in
space telecommunications. Prof. Inan is a Fellow of IEEE, the
American Geophysical Union (AGU), and the American Physics
Society (APS). He is the recipient of the Appleton Prize of the
International Union of Radio Science and Royal Society. He is
also currently President of Koç University, Istanbul, Turkey.
Inumiya, Seiji (4C.2)
Seiji Inumiya received B.S. and M.S. degrees in physics from
Waseda University, Tokyo, Japan, in 1992 and 1994,
respectively. He joined the R & D Center, Toshiba Corporation,
in 1994, where hewas engaged in the research on the process
and the reliability of thin silicon oxide in Si MOS devices. In
1997, he moved to the Process & Manufacturing Engineering
Center, Semiconductor Company, Toshiba Corporation,
Yokohama, Japan, where he has been engaged in the research
and the development of high-k gate dielectrics and silicon
oxynitride for logic LSI devices. In 2004, he joined
Semiconductor Leading Edge Technology, Inc., where he had
worked on the process development and the reliability of high-k
gate stacks. Currently, he is in charge of the high-k gate stack
process development at Process & Manufacturing Engineering
Center, Toshiba Corporation.He is a member of the Japan Society of
Applied Physics.
Ioannou, Dimitris (EL.3, XT.1)
Dimitris E. Ioannou: BS in Physics (1974), University of
Thessaloniki, Greece; MS (1975) and PhD (1978) in Solid-State
Electronics, University of Manchester, UK. Prior to joining George
Mason University as a professor of electrical engineering, held
positions at Manchester and Middlesex Universities (UK),
Democritus University of Thrace (Greece), University of Maryland
(USA) and the Institute National Polytechnique de Grenoble
(France). Authored or coauthored over two hundred fifty research
papers and conference presentations, and advised over thirty five
research students. Technical program chairman (2001) and general
chairman (2002) of the IEEE Inter. SOI Conf. Recipient (twice: 04
and 05) of the IBM Faculty award and Fellow IEEE (2010).
Irene, Tee (3C.5)
Irene TEE was born in Malaysia, she attended Informatics Computer
School where she completed diploma & advance diploma in
computer science discipline before gained her Bachelor Degree,
Information System & Software Engineering from Oxford Brooke
University (UK) in 2005.
Irene is currently working as Failure Analysis Engineer for
GLOBAL FOUNDRIES SINGAPORE. Her main responsibilities
include Transmission Electron Microscopy (TEM) sample
preparation & analysis and overall laboratory IT supports. She is the
author of 1 paper and co-author of several papers plus 1 patent on
failure analysis and TEM sample preparation technique.
Ishigaki, Takashi (XT.2)
Takashi Ishigaki received the B.E. and M.E. degrees in electrical
and electronic engineering from Kobe University, Hyogo, Japan, in
1999, 2001, respectively. He joined Compound Semiconductor
Division, NEC Corporation in 2001, where he was involved in the
research and development of GaAs HJFETs and HBTs for
microwave power amplifiers and RF switch ICs. Since 2004, he has
been working in Central Research Laboratory, Hitachi, Ltd. on the
research and development of high-capacity flash memories and SOI
CMOSFETs. Mr. Ishigaki is a member of the IEEE Electron
Devices Society.
Islam, Ahmad Ehteshamul (2B.3, XT.7)
Ahmad Ehteshamul Islam received the B.S.E.E from Bangladesh
University of Engineering and Technology (BUET) in 2004. He is
currently enrolled in the direct Ph.D. program at ECE, Purdue
University. During 2004-2005, he worked as Lecturer in the
Department of EEE, BUET. His current research focuses on the
variation resilience aspects of strained/III-V CMOS transistors. He
has (co)-authored more than 20 journals and conference papers. He
is a student member of the IEEE EDS and APS and also serves as a
reviewer for several IEEE, Elsvier, APS and ECS journals. He is
also the recipient of Kintar-Ul-Haque Gold Medal (2005) for his
undergraduate result, and IEEE EDS PhD Fellowship (2008), Intel
PhD Fellowship (2009-2010) for his work on transistor reliability.
Itaru, Yanagi (PI.3)
Itaru Ynagi received the B.S., M.S. degrees in solid state physics
from Waseda University in 2003, 2005. In 2005, he joined the
Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan. Since
then, he has been working on research and development of non-
volatile memory.
Ito, Shuu (4C.1)
Received the B.S. (1990) and M.S. (1992) in mathematical science
from Osaka Prefecture University, Osaka, Japan. In 1992, he joined
NEC Corp. He is currently engaged in the research and development
of embedded flash memory LSIs. He is a member of the
Physical Society of Japan and the Japan Society of Applied
Physics.
Iwai, Hidenao (FA.4)
Hidenao Iwai received the B.S. (1995) in Mechanical
Engineering and the M.S. (1997) in Biomedical Engineering
from Keio Univ., Japan. In 1997, he joined Hamamatsu
Photonics K.K., and worked on diffused optical tissue
spectroscopy. He was at Massachusetts Institute of Technology
from 2001-2002 as a visiting scientist, where he was involved in
low-coherence interferometry. Currently he moved back to
Hamamatsu Photonics K.K. His research interests include
biological application of interferometric quantitative phase
microscopy.
Jack, Nathan (4D.5, EL.1)
Nathan Jack received a B.S. from Utah State University in 2007
and a M.S. in 2009 from the University of Illinois at Urbana-
Champaign, both in Electrical and Computer Engineering. He is
currently pursuing a Ph.D. degree at UIUC in ECE. His
research interests include on-chip ESD protection and ESD test
methods. He has completed five summer internships at Micron
Technology, Inc, in Boise, Idaho, of which two were in the
ESD/LUP R&D Reliability Group.
Jagannathan, Hemanth (XT.14)
Hemanth Jagannathan (M’98) received the M.S. and Ph.D.
degrees in electrical engineering from Stanford University in
2003 and 2007 respectively. He is currently a Research Staff
Member at IBM Research based at IBM @ Albany NanoTech,
Albany, NY and IBM T. J. Watson Research Center, Yorktown
Heights, NY. His research interests include high-k/metal gate
CMOS devices and integration, semiconductor technology,
semiconductor nanowire synthesis and device design, nanoscale
science, materials, and technology.
Jain, Palkesh (6A.1)
Palkesh Jain graduated from the Indian Institute of Technology
(IIT) Bombay in 2004, with Bachelors and Masters in Electrical
Engineering. His Masters thesis research was on soft errors and
Radiation Reliability. Since then, he has been with the
Reliability CAD Group at ASIC, Texas Instruments India. He
has contributed to the CAD and methodology development for
several technology nodes for reliability assessment. He has over
ten international publications and 6 filed patents to date.
Jammy, Raj (2B.4)
Raj Jammy received his doctoral degree in Electrical
Engineering from Northwestern University (1996). He joined
IBM’s Semiconductor Research and Development Center in
East Fishkill, NY, where he worked on various aspects of
DRAM technology development in engineering and managerial
roles. In 2002 he moved to IBM T. J. Watson Research Center
in Yorktown Heights, NY, to manage IBM’s efforts on high k
gate dielectrics and metal gates. From 2005 to 2008 he was an
IBM assignee to SEMATECH as the Director of the Front End
Processes Division in Austin, TX. Since June 2008 he has been
with SEMATECH and currently serves as Vice President of
Materials and Emerging Technologies. He holds more than 50
patents and is an author/co-author of over 200
publications/presentations.
Jeng-Hwa, Liao (5D.4)
Jeng-Hwa Liao was born in Taipei, Taiwan in 1979. He received
his Ph. D degree in material science and engineering from
National Tsing-Hua University (NTHU) in 2007. He joined
Technology Development Center in Macronix International
(MXIC) since 2007. His current works are focused on advanced
diffusion module process development, and technology development
of NAND Flash and charge trapping memories.
Jeong, YeonJoo (MY.7)
YeonJoo Jeong received the B.S. degree in Quantum and Electronic
Engineering from the University of Tsukuba, Tsukuba, Japan, in
2007, and the M.S. degree in Electrical Engineering from the
University of Tokyo, Tokyo, Japan, in 2009. He is currently with
the Flash Memory Division, Hynix Semiconductor Inc., Cheongju,
Korea, working on device engineering of Hynix’s multi-level Flash
cell.
Jeong, Yoon-Ha (2C.4)
Received the Ph.D. (1987) in electronics engineering from the
University of Tokyo, Japan, where he pioneered in situ vapor phase
deposition and the development of photo-chemical vapor deposition
(CVD) technology for InP metal–insulator–semiconductor field-
effect transistors (MISFETs). In 1987, he joined the Pohang
University of Science and Technology (POSTECH), Pohang, Korea,
where he is a Professor with the Department of Electronics
Engineering and a Director of the National Nano Devices Center for
Industry, where he is involved with nano-CMOS devices and
circuits for RF applications. His research interests include
microwave and millimeter-wave device fabrication, RF circuit
design, single electron transistors, and nano-CMOS devices. He was
a conference chair in IEEE Nanotechnology Materials and Devices
Conference 2006 (IEEE NMDC). He was nominated on Who`s Who
in Science and Technology. He is IEEE senior member, director in
National Nanodevices Center for Industry, IEE fellow member,
director in National Center for Nanomaterials Technology (NCNT)
of the MKE (Korea), industrial developement committee member in
Ministry of Commerce Industry and Energy (MOCIE), chair in
IEEE EDS Yeongnam chapter (Korea), and board member in
National Science & Technology Council (Korea).
Jimenez, Jose (4F.3)
Jose Jimenez received the B.A (1992) in Electrical Engineering
from the Universidad Politecnica de Madrid and the Ph. D. (1996) in
Electrical Engineering from Columbia University in New York. He
has worked in both integrated optics and in transport and
optoelectronics semiconductor devices for the last 15 years in
Telefonica R&D (Spain), T. J. Watson IBM Research Laboratory,
Beckman Institute and Nanovation. For the last six years, he has
been part of the R&D organization of TriQuint Semiconductor
focusing early on in 4'' inch optoelectronics devices (DFB lasers and
high speed photodetectors) and later in GaN FET technology
(physics, test and reliability).
Jo, Das (2E.4)
Jo Das received the M.Sc. and Ph.D. degrees in electrical
engineering from the Catholic University of Leuven, Leuven,
Belgium, in 1998 and 2003, respectively. His research topic for his
Ph.D. dissertation is on magnetic random access memories. Since
2003, he has been Senior Engineer with imec, Leuven, Belgium. His
current research interests are the fabrication and circuit integration
of GaN-based Devices for Power switching and RF power
applications.
John, Aitken (5A.5)
John Aitken joined IBM in 1974 at the T.J. Watson Research
Center. He is a currently a Senior Technical Staff Member at IBM
Burlington managing the Semiconductor Technology Reliability
Engineering Department evaluating reliability of new technologies
and materials for advanced semiconductor device technologies . He
is a Senior Member of the IEEE and past committee member and
General Chairman of the International Electron Devices Meeting .
He received a MS and Ph.D. in Physics /Materials Science from
Rensselaer Polytechnic Institute 1972 and a BS in Physics from
Fordham University. John is an Adjunct Professor at
University of Vermont.
Jung, Seong-Ook (RM.3)
Seong-Ook Jung received the Ph.D. degree from University of
Illinois at Urbana Champaign in 2002. From 1989 to 1998, he
was with Samsung Electronics where he worked on specialty
memories and merged memory logic. He led thyristor based
memory design team in T-RAM Inc. from 2001 to 2003. He also
worked on embedded memories, process variation tolerant
circuit , and low power circuit in Qualcomm Inc. from 2003 to
2006. He has been an associate professor in Yonsei University
since 2006. His research interest includes process variation
tolerant circuit, low power circuit, mixed-mode circuit, and
future generation memory.
Jungemann, Christoph (2F.4)
Christoph Jungemann holds the chair for Microelectronics at the
Bundeswehr University. He has more than 15 years of
experience in the field of physics-based device simulation. He
developed the first full-band Monte Carlo device simulator for
SiGe HBTs and pioneered numerical methods for the solution of
the Langevin-Boltzmann equation. He is a co-developer of
hierarchical device simulation including the first 2D bipolar
hydrodynamic model for noise in SiGe devices, where all
transport and noise parameters are generated by consistent
Monte Carlo simulations. He developed CPU efficient models of
impact ionization for the classical device simulators. He has
authored one book on hierarchical device simulation and more
than 180 journal and conference papers in this field. He is a
member of the editorial board of the IEEE Transaction on
Electron Devices and a recipient of the IEEE EDS Paul-
Rappaport-Award for 2005. He was or is a program committee
member of IEDM, ICCAD, and IWCE.
Jung-Yu, Hsieh (5D.4)
Jung-Yu Hsieh was born in Hsinchu, Taiwan, R.O.C., in 1971.
He received the B.S. degree in chemical engineering from the
National Tsing Hua University, Hsinchu, Taiwan, in 1995, and
the M.S. degree in chemical engineering from the National
Tsing Hua University, Hsinchu, Taiwan, in 1997. He joined the
Advanced Module Process Development Division of Macronix
International (MXIC), in 1997 where he has been working on
the process development of chemical mechanical planarization
(CMP). His current works are engaged in advanced diffusion
module process development.
Jurczak, Malgorzata (6C.1)
Malgorzata Jurczak received M.Sc. and Ph.D. in electrical
engineering from the Warsaw University of Technology where
she worked as teaching assistant and research scientist. She was
with NMRC, Ireland and Kyung Hee University, Korea in 1994
and 1997, respectively. In 1998-99 she worked on 0.18 and
0.12µm CMOS and alternative CMOS approaches at CNET,
France Telecom. In 2000 she joined IMEC, Belgium. From 2000
to 2003 she was leading the IMEC-Philips JDP on 90nm and
65nm CMOS. From 2003 to 2007 she coordinated FINFET
project. From 2008 she has been the manager of NVM and
Emerging Memories programs.
K Singh, Pawan (2C.3)
Pawan K Singh received B. Tech. and M. Tech. combined
degrees (2006) from Electrical Engineering department of
the Indian Institute of Technology (IIT) Bombay, India. Since
2006, he is pursuing Ph.D. in Electrical Engineering department
in IIT Bombay. He is an AMAT fellow for PhD in IIT Bombay
since 2006. He has been a graduate intern at Applied Materials,
Santa Clara, CA from June 2007 - July 2008. His research
interests include technology development, physics, and
reliability characterization of non-volatile memories. He is
currently working on metal nanocrystal based non-volatile
memories for NAND application. He is a student member of the
IEEE.
Kaczer, Ben (2A.3, XT.10, XT.13)
Ben Kaczer received the M.S. degree in physical electronics from
Charles University, Prague, Czech Republic, in 1992 and the M.S.
and Ph.D. degrees in physics from Ohio State University (OSU),
Columbus, in 1996 and 1998, respectively. For his Ph.D. research on
the ballistic-electron emission microscopy of SiO2 and SiC films, he
received the OSU Presidential Fellowship and support from Texas
Instruments, Inc. Since 1998, he has been with the reliability group
of IMEC, Leuven, Belgium, where his activities have included the
research of the degradation phenomena and reliability assessment of
SiO2, SiON, high-k, and ferroelectric films, planar and multiple-gate
FETs, circuits, and characterization of Ge/III-V and MIM devices.
He is the author or a coauthor of more than 100 journal and
conference papers and has presented eight invited presentations and
two International Reliability Physics Symposium (IRPS) tutorials.
Dr. Kaczer is the recipient of Best and the Outstanding Paper
Awards at IRPS and the Best Paper Award at IPFA. He has served
or is serving at various functions at the International Electron
Devices Meeting (IEDM), IRPS, IEEE Semiconductor Interface
Specialists Conference (SISC), and Conference on Insulating Films
on Semiconductors (INFOS).
Kalya, Shubhakar (4A.1, BD.2)
Shubhakar K received his B.E (Electronics and Communication,
2000) and M.E (Microelectronics, 2007) from NMAMIT Nitte,
Mangalore and Indian Institute of Science (I.I.Sc), Bangalore
respectively. He is currently pursuing his Ph.D. at the Division of
Microelectronics, School of EEE, Nanyang Technological
University working on reliability physics and degradation
mechanisms in novel high-κ dielectric materials using scanning
tunneling microscopy (STM) and conductive atomic force
microscopy (CAFM) technique.
Kamino, Takeshi (PI.1)
Takeshi Kamino received his B.E. and M.E. in materials physics and
engineering from Osaka University, Osaka, Japan in 1992 and 1994,
respectively. He joined Sumitomo Metal Industries, Ltd., Osaka,
Japan in 1994 and worked on the development of magnetic thin-film
heads for hard disk drives. In 2000, he joined Mitsubishi Electric
Corp., Hyogo, Japan and was then transferred to Renesas
Technology Corp. (now Renesas Electronics Corporation), Hyogo,
Japan in 2003. He has been engaged in the research and
development of deep-submicron CMOS devices and process
integration. He is working on the research and development of
advanced SoC technology.
Kang, Han-Byul (3C.3)
Han-Byul Kang received the Ph. D. degree in advanced material
science & engineering from Sungkyunkwan University, Korea, in
2004. His thesis topic was interfacial reaction between
environmental friendly solder and Ni-P UBM by using analytical
transmission electron microscopy. He is currently with Technology
Reliability, Q&R team in SYSTEM LSI division, Samsung
Electronics as a senior engineer and is involved in package level
reliability. He has authored/coauthored over 30 international papers
and patents.
Kang, Jinfeng (MY.4)
Kang Jinfeng received his B.S. degree in physics from Dalian
University of Technology in 1984, and M.S. and Ph.D degrees in
solid-state electronics from Peking University in 1992 and 1995
respectively. Next, he joined Institute of Microelectronics in Peking
University as a post-doctoral fellow. In 1997 he joined the faculty
first as an associate professor then professor in 2001. He is the
author of a book and more than 100 conference and journal
papers. Currently his research interests are in the areas of novel
memory technology, high-k/metal gate technology and MOS
device physics, as well as solar cell technology.
Kang, Min-gu (RM.3)
Min-gu Kang was born in Seoul, Korea, in 1981. He received
the M. S. degree in the electrical and electronic engineering
from Yonsei University, Seoul, Korea, in 2009. Currently, He is
working in SAMSUNG Semiconductor. His current research
interests is FinFET SRAM circuitary.
Kato, Koichi (4C.2)
Koichi Kato, received the B.S., M.S., and Ph.D. degrees in
physics from the University of Tokyo, Japan, in 1977, 1979, and
1982, respectively. He joined Toshiba Research & Development
Center from 1982. His early activiy includes SOI device
technology of body floating effects and thin body effects. He
joined the Atom Technology national project from 1993 to 1997
in Tsukuba. His careers have moved to more fundamental
technologies including layer-by-layer oxidation, novel SiON
films, high-k insulating films, and dipole comforting Schottky
barriers mostly through a theoretical viewpoint, but including an
experimental viewpoint. His current research interest is interface
engineering with atom manipulation. He is a member of the
Japan Society of Applied Physics and a member of the Physical
Society of Japan.
Katsuji, Ono (4A.5)
Katsuji Ono received the M.S. degree in electrical engineering
from The University of Electro-Communications, Tokyo, Japan
in 1987, where his research focused on Liquid-phase selective
epitaxial growth of GaAs for Junction FET. He joined
Compound Semiconductor Devices Laboratory of Fujitsu
laboratories, Kanagawa, Japan in 1987. He is currently working
on characterizing CMOS devices for advancing device
performance and fabrication technologies in Fujitsu
Microelectronics Limited (FML).
Katsuto, Tanahashi (4A.5)
Katsuto Tanahashi was born in Gifu, Japan, in December 1964.
He received the B.S. and M.S. degrees in materials science from
the Nagoya Institute of Technology, Aichi, Japan, in 1992 and
1994, and Ph.D. degree in Physics from Osaka Prefecture
University, Osaka, Japan, in 2001. He was a Research
Fellowship for Young Scientist of Japan Society for the
Promotion of Science in 2001 and 2001. He joined Fujitsu
Laboratories Ltd., Atsugi, Japan, in 2001, where he studied
physical analysis of semiconductor devices using FT-IR,
photoluminescence, light scattering. Since 2010, he has been
studying failure analysis of semiconductor devices.
Katsuya, Shiga (PI.3)
Katsuya Shiga received the B.S. (1994) and M.S. (1996) in
electronics engineering from Kansai Univ., Osaka, Japan. He
joined Mitsubishi Electric Corporation in 1996 (Renesas
Technology Corporation from 2003) and he has been engaged in
development of reliability engineering for ULSI devices.
Katsuyuki, Horita (PI.3)
Katsuyuki Horita received the B.S. and M.S. degrees in
electronics from Waseda University in 1993 and 1995,
respectively.In 1995, he joined the ULSI Laboratory of
Mitsubishi Electric Corporation, where he was engaged in the
research and development of CMOS device and process
technology. He is now with Renesas Technology Corporation,
continuing the research and development of CMOS.
Kauerauf, Thomas (6A.3, XT.9, XT.13)
Thomas Kauerauf received his degree in electrical engineering from
the Technical University of Ilmenau, Germany, in 2001 and the
Ph.D. degree from the Katholieke Universiteit Leuven, Belgium, in
2007. In 2006 he joined imec, Leuven, Belgium, where he is
currently working in the Device Reliability and Electrical
characterization group focusing on high-k gate stacks and the impact
of Cu contacts on the FEOL reliability. From 1999 to 2000 he stayed
several months at Bell Laboratories, Murray Hill, USA. Thomas
Kauerauf has authored or co-authored more than 50 publications and
received the IEEE SISC Ed Nicollian Award for the best student
paper in 2001.
Kazuyoshi, Torii (PI.3)
Dr. Torii received B.S and M.S degrees in physics from Keio
University,Tokyo, Japan, in 1986 and 1988, and a Ph.D. degree in
engineering from Tokyo Institute of Technology, Tokyo, Japan, in
1998. From 1988 to 1999, he was with Central Research Laboratory,
Hitachi, Ltd., Tokyo, Japan. He worked on process and integration
of capacitor dielectrics for DRAM and FeRAM. From 2000 to 2004,
he was working on high-k gate dielectrics for CMOS. In 2002, he
joined Semiconductor Leading Edge Technology, Inc (SELETE).
Dr. Torii is a member of the Japan Society of Applied physics and
IEEE.
Kees, Beenakker (3F.3)
Kees Beenakker studied chemistry and physics at Leiden University,
the Netherlands. He received the Ph.D. degree at the FOM-Institute
for Atomic and Molecular Physics, Amsterdam, the Netherlands, in
1974. In 1974, he joined Philips’ Research Laboratories, Eindhoven,
the Netherlands. In 1982, he moved to the Philips Semiconductor
Division, Nijmegen, the Netherlands. In 1987, he co-founded
Eurasem, a European hi-rel IC Assembly Company. Since 1990, he
has been a full Professor, Faculty of Electrical Engineering,
Mathematics and Computer Science (EEMCS), Delft University of
Technology, Delft, the Netherlands and Chairman of the Department
of Microelectronics.
Keiji, Takahisa (3A.5)
Keiji Takahisa received the B.S. degree from the Hokkaido
University, in 1986, and the M.Sc. and Ph.D. degrees in physics
from Tohoku University, in 1988 and 1991, respectively. In 1991,
he began work on nuclear physics in RCNP, Osaka University. He is
currently Radiation Handling Supervisor, Division of Radiation
Security Control, RCNP, Osaka University.
Keita, Nishigaya (4A.5)
Keita Nishigaya is an engineer in Si processes development
department at Fujitsu microelectronics limited and is involved in
gate dielectrics Reliability of 45nm technologies. He received his
Bachelor's degree and Master's degree in engineering from
Tokyo Institute of Technology.
Keller, Robert (2F.4)
Robert Keller received his Ph.D. in Geophysics from the Ludwig-
Maximilians University in Munich in 1998. Since that time he is
working at Infineon Technologies Munich.
Ken, Shono (3A.5)
Ken Shono received M.S Degree in Applied Physics from Osaka
university, Japan in 1979. He joined Fujitsu in 1979 and he has
been managed reliability-related activities in technology
development of deep submicron MOSFET and multi-layer
metallization system. He is also interested in mitigation of soft
errors in LSI.
Ker, Ming-Dou (EL.6)
Ming-Dou Ker is now served as Chair Professor and Vice
President of I-Shou University, Kaohsiung, Taiwan. On the
topic of reliability and quality design for integrated circuits, he
has published over 380 technical papers in international journals
and conferences, and has been granted with 154 U.S. patents and
146 R.O.C. (Taiwan) patents. He was selected as the
Distinguished Lecturer in the IEEE Circuits and Systems
Society (2006–2007) and in the IEEE Electron Devices Society
(2008-2010). In 2008, he has been elevated as an IEEE Fellow.
He was the President of Foundation in Taiwan ESD Association.
Kerber, Andreas (2B.1, 4A.3)
Andreas Kerber was born in Schnann, Austria, in 1973. He
received his Diploma in physics from the University of
Innsbruck, Austria, in 2001 and a PhD in electrical engineering
from the TU-Darmstadt, Germany in 2004 (granted with honor).
He worked as intern at Bell Laboratories, Lucent Technologies,
Murray Hill, NJ, USA (1999-2000), at IMEC in Leuven,
Belgium (2001-03) as Infineon Technologies assignee to
International SEMATECH, for the Reliability Methodology
Department at Infineon Technologies in Munich, Germany
(2004-06), for AMD in Yorktown Heights, NY (2006-09), and
for GLOBALFOUNDRIES in Yorktown Heights, NY (since
2009). Much of his work centered around Front-End-Of-Line
(FEOL) reliability research with focus on metal gate / high-k
CMOS technologies. He has co-authored 65 papers in Journals
and Conferences.
Kerst, Uwe (IC.2)
Dr.-Ing. Uwe Kerst is heading the electronic devices failure
analysis lab at Berlin University of Technology. Additionally he
is lecturing Quality Management and Reliability in the
Semiconductor Industry. Before joining the University he
worked for Infineon Technologies in the LDA alliance East
Fishkill subsequently in the Fiber Optics division. His Ph.D.
thesis (2000) covered the integrated series interconnection in
thin film solar cells.
Killat, Nicole (4F.3)
Nicole Killat received the Dipl. Ing. degree in technical physics
from the Ilmenau University of Technology, Germany, in 2008.
She is currently working towards the Ph.D. degree at the
Applied Spectroscopy Group, University of Bristol. Her current
research interests include studying thermal and electrical
properties of GaN-based devices using micro-Raman and
electroluminescence spectroscopy.
Kim, Dae Mann (2C.4)
Received his B. S. degree from Seoul National University,
Seoul, Korea and M.S. and Ph. D. degrees from Yale University,
New Haven, CT, all in physics. He was a research associate at
the Massachusetts Institute of Technology, MA, and taught at
three levels of professorship with the Department of Electrical
and Computer Engineering, Rice University, Houston, TX from
1970 to 1984. After working as a Principal Scientist at
Tektronix, Inc., he became a professor with the Department of
Electronics and Electrical Engineering, Pohang University of
Science and Technology, serving as the Chairman of the
department and the Dean of the Graduate School. Currently he is
a professor in the Computational Sciences Division, Korea
Institute for Advanced Study and a visiting professor in the
department of electrical engineering, Seoul National University,
Seoul, Korea. His current research interests are in nano-CMOS
devices, flash memory technology, and Schottky contacts in
molecular and CNT devices. He is a member of American
Physical Society and a fellow of Korean Academy of Science
and Technology.
Kim, Daesig (6C.4)
Daesig Kim received the B.S. degree in metallurgical engineering
from Hanyang University, Seoul, Korea in 1982. He received the
M.S. and Ph.D. degrees in materials science and engineering from
Stevens Institute of Technology, Hoboken, New Jersey, in 1991.
From 1991 to 2001, he was with Samsung Advanced Institute of
Technology, Korea, as a principal researcher in Material and Device
Division working on the development of new thin film materials and
thin film processes. He joined Ramtron International Corporation,
Colorado Springs, CO, in 2004 as a senior reliability engineer and
has been working on the reliability of high density FeRAM.
Kim, SangBum (2C.5)
SangBum Kim received the B.S. degree from Seoul National
University, Seoul, Korea, in 2001, and the M.S. degree from
Stanford University, Stanford, CA, in 2005, all in electrical
engineering. He is currently working toward the Ph.D. degree in
electrical engineering at Stanford University, Stanford, CA, USA.
His current research focuses on fabrication and characterization of
novel phase-change memory (PCM) structures with reduced
programming power and cell size, and measurement of phase-
change material properties to understand how they can affect PCM
operation.
Kim, Seong Soo (5C.1)
Seong Soo Kim was born in Busan, Korea, on May 22, 1974. He
received the M.S. and the Ph. D. degree
in physics from Seoul National University, Seoul, Korea in 2001
and 2006, respectively. He has been working for Samsung
electronics since 2006 as a member of Flash Memory Process
Architecture team. His main activities have been in TCAD
simulation and analysis of device operation.
Kim, Yong Seok (5C.1)
Yong Seok Kim was born in Seoul, Korea, on July 16, 1969. He
received Ph.D. degrees in electronic engineering from Seoul
National University, Seoul, Korea, in 2004. Since 2005, he has been
working in device engineering of the NAND Flash memories at
Samsung Electronics Corporation, Korea. His current interests
include reliability issues and the scaling of floating type NAND
Flash memories.
Kimura, Shin'ichiro (XT.2)
Shin'ichiro Kimura received the B.S. and M.S. degrees in materials
science from Tohoku University, Sendai, Japan, in 1978 and 1980,
respectively, and the Ph.D. degree from the University of Tokyo,
Japan, in 1989. Since 1980, he has been with the Central Research
Laboratory, Hitachi, Ltd.. During 1988 to 1989, he was a Visiting
Research Associate at the University of Warwick, Coventry, U. K.
Currently, he is a Chief Senior Researcher. His current research
interests include new submicrometer MOSFET devices and
processes. Dr. Kimura is a member of the Japan Society of Applied
Physics and the IEEE Electron Devices Society.
King, Sean (IC.13)
Dr. Sean King is a Senior Technical Contributor for Intel
Corporation’s Portland Technology Development (PTD) Division.
Dr. King received a B.S. degree in Materials Engineering from
Virginia Tech in 1991, and a Ph.D. in Materials Science and
Engineering from North CarolinaStateUniversity in 1997. Since
joining Intel in 1997, Dr. King has held a variety of technical
positions in the development of Intel’s 0.35 mm - 22 nm
technologies. Currently, Dr. King is leading development of low-k
dielectrics for 16 nm Cu interconnects. Dr. King’s research interests
include thin film deposition, diffusion barriers, and electrical
properties of interfaces.
Köck, Helmut (4C.5)
Helmut Köck studied communication engineering at the
Carinthia University of Applied Science, Klagenfurt, Austria.
He received the M.S. degree in 2007. He is currently working
toward the Ph.D. degree at the Technical University of Vienna,
Vienna, Austria. Since 2006 he has been with Infineon
Technologies and KAI GmbH, Villach, Austria, respectively.
His research involves the development of optical methods for
device characterization and reliability studies on smart power
semiconductors.
Koh, Yohwan (MY.7)
In 1989, he joined Hyundai Electronics Industries Co., Ltd
(changed to “Hynix” after merging with LG semiconductor in
2001), Korea where he has been engaged in Advanced DRAM
device and process architecture development for 64M DRAM to
256M DRAM until 2002. During his R&D period, he and his
team developed the world’s 1st fully functional SOI 64Mb
DRAM in 1996, and then the SOI 1Gb DRAM with 0.18um
technology in 1997. From 2002, he worked in Manufacturing
Fab. in Eugene, OR where he was Vice President of Device
Engineering group until 2005. He was project manager for 80nm
DRAM development. He also took care of ProMOS foundry
business and Graphics/Mobile DRAM development with 80nm
& 66nm technologies. From the end of 2007, He moved his
position to Flash Development Division. He also developed
41nm 32Gb, 32nm 32Gb and 26nm 64Gb NAND Flash. He is
now Senior VP and Head of Flash Development Division.
Koichi, Hashimoto (4A.5)
Koichi Hashimoto received B.S. degree in applied chemistry and
M.S. degree in chemical energy engineering from the University
of Tokyo, Tokyo, Japan, in 1983 and 1985, respectively. In
1985, he joined Fujitsu Ltd., Kawasaki, Japan, where he
engaged in the research and development of dry etching
technology and DRAM process technology. Since 2002, he has
been engaged in the research and development of high
performance CMOS logic devices for CPU applications, such as
SPARC64™ series.
Kopf, Rose (FA.5)
Rose F. Kopf is a Member of the Technical Staff at Alcatel-
Lucent Technologies, Bell Labs, in the High-Speed Electronics
and Optoelectronics Research Dept.. She is also a Member of
The Alcatel-Lucent Technical Academy. She received a B.S
degree in chemistry from Northeastern University in Boston,
MA in 1982, and M.S. and Ph.D. degrees in materials science
and engineering from Steven Institute of Technology in
Hoboken, NJ in 1987 and 1991, respectively. Since 1992, she
has been involved in process development and integration for
HBT high-speed circuits and optoelectronic integrated circuits.
She has over 200 publications and holds 20 patents.
Kota, Funayama (PI.3)
Kota Funayama received B.E. and M.E. degrees in materials
science from Tohoku University, Sendai, Japan, in 1995 and
1997, respectively. He joined Hitachi Ltd., Tokyo, Japan, in
1997. Since 2003, he has been working as an engineer for
Renesas Technology Corporation (present Renesas Electronics
Corporation), Ibaraki, Japan, where he is currently engaged in
the research and development of advanced MCU technology.
Koyama, Shin (4C.1)
Received BS and MS degree of physics from Tohoku University
in 1995 and 1997, respectively. He joined NEC in 1997, had
worked on the development of gate dielectric process. He is now
participating in JDA with IBM from 2009, and working on the
gate dielectric and metal electrode for 32nm/28nm node and
beyond.
Krause, Jonathan (3A.1)
Jon Krause coordinates the design, verification, and release of
Standard Cell Libraries for several Intel Server Development Group
Processors. Jon has been involved in the implementation, backend
circuit verification, and full chip integration of multiple high-
performance microprocessors, including the Digital Alpha 21264
and 21364 processors. Jon obtained a BSEE from the University of
Cincinnati in 1998.
Krick, John (5E.5)
John joined Texas Instruments in 1993 and is currently the Director
of Advanced CMOS SPICE Models and Design Kits.
Krishnan, Anand (4A.6, 5E.5, XT.18)
Anand T. Krishnan received his Bachelor of Technology degree in
Metallurgical Engineering from Institute of Technology, BHU,
Varanasi, India in 1994, and M.S. and Ph.D degrees in Materials
from The Pennsylvania State University in 1997 and 2000,
respectively. In 2000, he joined the Silicon Technology
Development Group at Texas Instruments, where he is currently
working as a Reliability Engineer. His interests and activities are in
the areas of negative bias temperature instability, dielectric
breakdown physics and plasma charging damage. He has served in
the technical program committee for the International Reliability
Physics Symposium (IRPS), Integrated Reliability Workshop (IRW)
and for the Plasma Process-Induced Damage Symposium (P2ID)
and as a Guest Editor for IEEE Transactions on Device and
Materials Reliability. He has authored or co-authored more than 50
papers, including 10 at IEDM/VLSI, and holds 12 patents.
Krishnan, Srikanth (5F.3, 6A.1, XT.18)
Srikanth Krishnan received his B.Tech in Electrical Engineering
from the Indian Institute of Technology (IIT) in 1985, M.S. and
Ph.D from Pennsylvania State University (PSU) in 1988 and 1992.
He is a Distinguished Member of Technical Staff and Manager,
responsible for Analog Technology Reliability at Texas Instruments.
Srikanth has published or presented 60 papers. He serves on the
IRPS Management committee. He has received 3 Outstanding Paper
awards and 1 Best Paper award at IRPS, as a co-author and mentor.
He is a Centennial Fellow of the Penn State Engineering Science
Department.
Ku, Shaw-Hung (5D.3)
Shaw-Hung Ku was born in Taipei, Taiwan, R.O.C. 1977. He
received the M.S. and Ph.D. degree in electronics engineering from
the National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in
2001 and in 2006. Then, he joined Macronix International
Company, Ltd. and is responsible for the developement of nitride-
based and floating-gate storage memories.
Kuang-Chao, Chen (5D.4)
Kuang-Chao Chen received the M.S. degrees in chemistry from the
National Chong-Shan University, Taiwan, in 1987. From 1989 to
1995, he joined Electronic Research and Service Organization
(ERSO), Hsinchu, Taiwan, where he has been involved in the
development of BEOL planarization process technology. From 1995
to 1998, he was with Mosel-Vitelic International Co., Ltd, Hsinchu,
Taiwan. He performed yield improvement in manufacturing line. In
1998, he joined Vanguard International Semiconductor Co., Ltd,
Hsinchu, Taiwan, as a department manager. He was responsible for
thin film module development. In 2000, he joined Macronix
International (MXIC), where he worked on advanced module
development. He is currently Executive Director of Technology
Development Center.
Kuball, Martin (2E.5, 4F.3)
Received his Ph.D. from the Max-Planck Institute for Solid State
Physics, Stuttgart, Germany in 1995. After a two year stay at Brown
University, Providence, USA as Feodor-Lynen Postdoctoral Fellow,
he joined the faculty of the University of Bristol (UK) in 1997,
where he is presently Professor in Physics and Director of the
CDTR. His current research interests include the optical,
thermal, and electrical study of advanced electronic and
optoelectronic materials and devices, especially of III-nitride,
GaAs, and boron-based structures, with focus on reliability
physics and engineering. He is author or co-author of more than
150 scientific publications.
Kufluoglu, Haldun (5E.5)
He obtained his B.S., M.S., and PhD in 2001, 2003, and 2007,
respectively from Purdue University. His research interests
include MOSFET reliability, characterization and modeling of
semiconductor devices. His PhD research focus was
measurements and theoretical modeling of MOSFET
degradation mechanisms such as NBTI, HCI and TDDB, and
their implications on VLSI design. He also participated in off-
state transistor reliability assessment. In 2006, he held a summer
internship at Intel Corporation, LTD FE Q&R, Hillsboro, OR,
on experimental NBTI reliability and recovery modeling. He is
now with Texas Instruments and working on parametric
reliability modeling with EDA focus.
Kulkarni, Pranita (XT.14)
Pranita Kulkarni received her B. Engg. in Materials Science and
Engineering from University of Pune, India in 1999, and M.S.
and Ph.D. degrees in the same discipline from Carnegie Mellon
University (CMU), Pittsburgh in 2006 and 2008, respectively.
Prior to joining CMU for graduate studies, she worked at
General Electric Co., Niskayuna NY (2003) and Cosmo Films
Ltd., India (2000) as Polymer Engineer. Since 2008 she is a
Research Staff Member at IBM Corp., NY where she performs
process and device modeling of electronic devices that would
meet the scaling requirements of future generation(s) of
semiconductor chips.
Kumashiro, Shigetaka (5F.4)
Shigetaka Kumashiro received his B.E. and M.E. degrees from
the University of Tokyo in 1981 and 1983, respectively, and his
Ph.D. degree from Carnegie Mellon University in 1992. He
joined NEC Corporation in 1983 and has been working in the
field of the modeling and simulation of ULSI process and
device. Now he is a Chief Engineer of Core Development
Division, NEC Electronics Corporation. In 2007, he was
appointed as theme leader of Environmental Variability Tolerant
Device Technology Program of MIRAI project. Dr. Kumashiro
is a senior member of the Institute of Electrical and Electronics
Engineers.
Kuper, Fred (2D.2)
Fred G. Kuper starting working in the field of wafer level
reliability in 1987 with Philips Semiconductors, working on
GOI, EM, ESD etc. In 1996 he received the outstanding paper
award of the IRPS for his paper on the relation between yield
and reliability. In 2002 Fred joined the automotive division of
Philips that is now part of NXP Semiconductors. First as quality
manager and since 2008 in an automotive quality and reliability
specialist position. Furthermore, since 1998 Fred Kuper is an
extraordinary professor at the University of Twente in the field
of Integrated Circuit Reliability.
Kuroda, Rihito (5F.2)
Rihito Kuroda (S’05) was born in Tokyo, Japan, on July 23,
1982. He received the B.S. degree in electronic engineering and
the M.S. degree and Ph. D. degree in the Graduate School of
Engineering, Tohoku University, Sendai, Japan in 2007 and
2010, respectively. He is engaged in researches on advanced
semiconductor device and process technologies, such as novel-
structure SOI CMOS developments; silicon surface processing,
such as flattening, cleaning, and high-integrity gate insulator film
formation; compact MISFET modeling developments for circuit
simulation; and reliability characterization, including negative-bias-
temperature and hot-carrier instabilities. Dr. Kuroda was the
recipient of the IEEE Electron Devices Society Japan Chapter
Student Award in 2005.
Labat, Nathalie (2E.3)
Nathalie LABAT joined the University of Bordeaux, France in
1987. She received the Ph.D. degree in Electronics in 1990 and the
dissertation “Habilitation à Diriger des Recherches” in 1999, all
from the University of Bordeaux, France. She is currently Professor
in IMS Laboratory in the Department of Electronics Engineering at
the University of Bordeaux and head of the Doctoral School on
Physical Sciences, Electronics and Mechanical Engineering. Her
research interests include the reliability of microwave technologies
using the finite element simulation, electrical and physical analysis
and low frequency noise characterization.
Lacaita, Andrea Leonardo (5C.2, 5D.1, 6C.3, MY.5, MY.6)
Prof. Andrea L. Lacaita. Full Professor of Electronics at the
Politecnico di Milano. Scientist since 1987, he has been Visiting
Professor at the AT&T Bell Laboratories, Murray Hill, NJ (1989-
90), IBM T.J. Watson Research Center, Yorktown Heights, NY
(1999). 2009 IEEE Fellow. He has contributed to study quantum
effects as well as experimental characterization techniques and
numerical models of non-volatile memories, both Flash and
emerging (PCM,RRAM). He is co-author of more than 200 papers,
patents and several educational books in Electronics.
Lai, Sheng-Chih (MY.1)
Sheng-Chih Lai was born in Taichung, Taiwan in 1976. He received
his B.S., M.S. and Ph.D. degrees in department of materials science
and engineering from National Tsing-Hua University, Taiwan, in
1999, 2001 and 2008, respectively. He joined Emerging Central
Laboratory (ECL) in Macronix International (MXIC) in 2001, where
his current research is engaged in reliability studies of nitride
trapping Flash memories, especially incorporated with high-K and
metal gate.
Lamontagne, Patrick (IC.8)
Patrick Lamontagne received the engineering degree in Materials
and Nanotechnologies from the Institut National des Sciences
Appliquées de Rennes, Rennes, France and M.S. degree of Physic
from the Université de Rennes 1, Rennes, France in 2007. He is
currently working toward the Ph.D. degree with the Electrical
Characterization and Reliability Group at STMicroelectronics,
Crolles, France. His research field is the electromigration issues in
advanced copper interconnects.
Langer, Eckhard (IC.2)
Eckhard Langer received his PhD in electrical engineering & micro
systems technology from the Technical University of Chemnitz,
Germany. He started his professional carrier at the Fraunhofer
Institute of Mechanics of Materials Halle, where he worked in the
field of microelectronics and materials analysis. In 1997 Eckhard
Langer joined Advanced Micro Devices (AMD) in Dresden (today
Globalfoundries). As a senior member of technical staff he is
responsible for the electron microscopy group (SEM, TEM, FIB.)
and Failure Localization. He is member of the EUFANET board.
Larcher, Luca (4A.4, 4F.4, 6C.1)
Luca Larcher graduated in Electronics Engineering from University
of Padova in 1998. He received the PhD degree in 2001 from the
University of Modena and Reggio Emilia, where he is currently
Associate Professor of Electronics. His research interests are
twofold. He focused on the experimental characterization, reliability
and modeling non-volatile memories and logic devices. He worked
on the characterization, reliability and design of both RF Integrated
Circuits for telecommunications and circuits for energy
harvesting from renewable sources in CMOS technology. He
authored and co-authored a book, more than 85 technical papers
published on international journals and conferences.
Laurin, Luca (5C.4)
Luca Laurin was born in Monza, Italy on 10/02/1982. He
received the master degree in physics from Bicocca university,
Milan, Italy in 2008. He studied, in an atomistic approach,
Boron diffusion and clustering during his Master thesis work. In
2008, he joined Numonyx Corp., in Agrate, Italy, to work in
TCAD simulation team, dealing with the develop of innovative
PCM memory technology.
Lavizzari, Simone (6C.3)
Simone Lavizzari was born in 1982. He took his first level
Laurea (Bachelor) degree in 2004, and the second level Laurea
(Master) degree in 2006, both in electronic engineering with 1st
class honors at the Politecnico di Milano, Italy, where he was
also awarded with the best student medal within his course. He
worked on Phase Change Memories (PCMs) within the
Department of Electrical Engineering of Politecnico di Milano,
where he achieved his PhD degree in 2009 working on PCMs
and design of VLSI analog instrumentation. At the moment he is
employed in Numonyx R&D working on PCM products.
Lee, Byoungil (2C.5)
Byoungil Lee received the B.S. degree in Electrical Engineering
from the Korea Advanced Institute of Science and Technology
(KAIST) in 2005. He received the M.S. degree in Electrical
Engineering from Stanford University in 2007. He is currently
pursuing the Ph.D. degree in Electrical Engineering at Stanford
University. He is a recipient of the Samsung Scholarship since
2005. His research interests are on resistive non-volatile
memories including metal-oxide memory and phase change
memory.
Lee, Chi Kyoung (5C.1)
Chi Kyoung Lee was born in Seoul, Korea, on March 08, 1971.
He received the B.S. degree in electronics engineering from
Korea Aerospace University, Gyunggi-Do, Korea, in 1995 and
the M.S degree in electronics engineering from Korea
University, Seoul, Korea, in 2004. He has been working at
Samsung electronics, Gyunggi-Do, Korea since 1995. he has
been in a Flash Memory Process Architecture team and his main
research is fail analysis for yield & cell characteristic
improvement. His current work is for the reliability
improvement of high-density NAND flash memories sub 30nm
technology, and research interests are NVM reliability, cell
technology, cell characteristic modeling.
Lee, Dong Jun (5C.1)
Dong Jun Lee was born in Seoul, Korea, on August 18, 1976.
He received the B.S.degree in materials science and engineering
from Yonsei University, Seoul, Korea, in 2001 and the M.S
degrees in materials science and engineering from Pohang
University of Science and Technology, Pohang, Korea, in 2003.
He has been working at Samsung electronics, Gyunggi-Do,
Korea since 2003. From 2003 to 2010, he was a Flash Process
Architecture team and worked on 120nm 1Gb NAND, 90nm
4Gb NAND, 51nm 16Gb NAND, 42nm 16Gb NAND, and
35nm, 32nm, 27nm 32Gb NANDs.
Lee, Dong-Kyu (MY.7)
Dong-Kyu Lee received the B.S. degree and the M.S. degree in
electrical engineering from Sungkyunkwan University, Korea in
1994 and in 2002 respectively. Since he joined Hynix
semiconductor Inc. in 2008, he has been working in process
integration and reliability improvement in advanced NAND
Flash technologies. Prior to joining Hynix, he had worked at Leadis
technology, Inc. and Samsung Electronics, Co. in Korea, where he
was involved in product engineering and process integration of
EEPROM embedded display driver IC, and NAND and NOR Flash
respectively for 14 years.
Lee, Hsiao-Heng (3A.3)
Hsiao-Heng Kelin Lee received his B.Eng in Computer Engineering
from McGill University, Montréal, Canada, in 2000 and his M.S. in
Electrical Engineering from Stanford University, Stanford CA, in
2002, where he is currently pursuing his Ph.D. in the Department of
Electrical Engineering. His research interests include low
power/high performance digital circuits, digital signal processing
algorithms and soft error resilient circuits. While at Stanford, Mr.
Lee was supported by the National Sciences and Engineering
Research Council of Canada (NSERC) Postgraduate Scholarship
from 2000 to 2002.
Lee, Jeong-Soo (2C.4)
Received the B.S. (1991), M.S. (1993) and Ph.D (1996) in
electronics engineering from the Pohang University of Science and
Technology (POSTECH), Pohang, Korea. His main research is
related to fabrication and characterization of nano-CMOS devices
and its reliability issues.
Lee, Sang-Hyun (2C.4)
Received the B.S. (2009) in electronics engineering from the Pohang
University of Science and Technology (POSTECH), Pohang, Korea.
He is currently in M.S. and Ph.D. integrative program course at
POSTECH. His main research is related to nanowire FET.
Lee, S-C (IC.10)
S.C. Lee received the B.S. (1994) in physics from National Sun Yat-
Sen Univ., Kaohsiung, TW, and M.S. (1996) from Institute of
Electro-Optical Engineering of National Chiao-Tung Univ., Hsin-
chu. In 1998, he joined TSMC where he work on Cu/Low-k
interconnect reliability including Cu electromigration and Low-k
dielectric reliability breakdown physics.
Lee, Y.H. (2F.3)
Yung-Huei Lee (S’82-M’86-SM’06) received Ph.D. in EE from
Ohio State University. He is a 23 years veteran of Intel and has
worked in the development of various CPU, RF/analog, and Flash
technology generations. He is currently a Technical Director at
TSMC. Dr. Lee holds 2 US patents and has published over 60
technical papers.
Lenahan, Patrick (2A.5, IC.13, XT.11, XT.18)
Patrick Lenahan earned a B.S. from Notre Dame and a Ph.D. from
Illinois and did a brief post-doc at Princeton. From 1980-1985, he
was with Sandia. Since 1985, he’s been at Penn State where he is
Distinguished Professor of Engineering Science. In 2001, he was
Visiting Professor of Electronics and Computer Engineering at
Nihon University. He served as Technical and General Program
Chairman of the IEEE IIRW in 2008 and 2009 respectively. He’s
authored about 130 journal articles which have been cited
approximately 3500 times. He is a fellow of IEEE.
Leu, Lii-Cherng (CD.3)
Lii-Cherng Leu received received his Ph.D. in Materials Science and
Engineering at University of Florida in 2008 with an emphasis on
electronic thin film materials processing and characterization. After
his postdoctoral work with Dr. Pearton and Dr. Ren on the failure
mechanism of InGaAs/InAlAs and AlGaN/InGaN based HEMTs, he
joined the Department of Materials Science and Engineering at
Boise State University to continue his postdoctoral research in
August, 2009. His current research is focusing on structural analysis
of functional oxide ceramics and minerals using JEOL2100 TEM.
Li, Xiang (MY.4)
Li Xiang received his B.Eng in Electrical and Electronics
Engineering (EEE) from Nanyang Technological University
(NTU) Singapore in 2005. He is currently pursuing his PhD
degree in EEE, NTU working on failure analysis of advanced
gate stacks. His research interest includes device reliability and
nano-scale characterization using transmission electron
microscopy and electron energy loss spectroscopy. Since 2006,
he has been a student member of IEEE.
Lian, Nan-Tzu (MY.1)
Nan-Tzu Lian was born in Kaohsiung, Taiwan in 1969. He
received his M.S in material science and engineering from
National Taiwan University (NTU), Taiwan, R.O.C., in 1993.
He joined Macronix International (MXIC) since 1995. He is
currently a project deputy division manager of the advanced
module process development division in Technology
Development Center.
Liang, James (5A.3)
James Laing received his B.S. (1992) in Ceramic Engineering
from Rutgers University and M.S. (1994) in Material Science
from New Jersey Institute of Technology. He joined United
Microelectronics Corp. in 2002 and has been involved in the
quality and reliability of CMOS process. Currently he is a staff
engineer of reliability department.
Liang, Zhongning (2D.2)
Zhongning Liang received the MSc (1987) in Solid States
Physics from ZhongShan University, Guangzhou, China and the
PhD (1994) from Groningen University of the Netherlands. He
joined Philips Semiconductors in 1995 as a process reliability
engineer and currently is the reliability manager in a business
line at NXP semiconductors. He is a member of the Automotive
Electronic Council Technical Committee, with broad and deep
interests in automotive requirements and quality.
Lilja, Klas (3A.3)
Klas Lilja is CEO and co-founder of Robust Chip Inc. (RCI).
Prior to founding RCI, he was CEO and VP Engineering of
Integrated Systems Engineering and Head of TCAD at Avant!
Corporation. He received his M.S. and Ph.D. in Physics, from
Chalmers University of Technology, Gothenburg, Sweden, and
the Swiss Federal Institute of Technology, Zurich, Switzerland,
respectively. At RCI, Dr. Lilja has lead the development and
market introduction of the company’s new simulation and
design tools. In the area of soft-error hardened design, he is
working on layout techniques and on RCI’s single event
simulation for cross-section and error-rate prediction.
Lim, Phyllis Shi Ya (XT.4)
Phyllis S.Y Lim received the B.Eng. (hons) degree in electrical
and electronic engineering from the National University of
Singapore (NUS) in 2007. She is now working towards a Ph.D.
degree at NUS under the NUS Graduate School for Integrative
Sciences and Engineering (NGS) scholarship. Her research
interests include nanofabrication and CMOS device physics,
high mobility channel materials and advanced junction
engineering
Lim, Yeow Kheng (5B.3)
Yeow-Kheng Lim received Bachelor (Hons.), Master and Ph.D.
degrees in Electrical and Electronic Engineering from Nanyang
Technological University, Singapore in 1999, 2001 and 2008
respectively. He works in Technology Development
Department of Global Foundries Singapore (formerly Chartered
Semiconductor Manufacturing Ltd) for more than 9 years.
Yeow-Kheng is a senior member of IEEE and the Executive
Committee Member and Treasurer of the Singapore IEEE
REL/CPMT/ED Chapter in 2009 and 2010 respectively. He is the
Organizing Committee Member, Co-chair of Technical Sub-
committee and Technical Co-chair of IPFA 2008, 2009 and 2010
respectively; and the Technical Sub-committee Member of IRPS
2009 - 2010.
Lin, Chung-Hsun (CD.1, XT.14)
Chung-Hsun Lin received the B.S. and M.S. degrees in electrical
engineering from National Taiwan University, Taipei, Taiwan,
R.O.C., in 1999 and 2001, and the Ph.D. degree in electrical
engineering from the University of California, Berkeley, in 2007. He
joined the IBM Thomas J. Watson Research Center in 2008 as a
Research Staff Member in the area of CMOS technology and device
modeling for 22nm node and beyond. He has authored or coauthor
of more than 50 technical papers. He is currently a Reviewer of the
IEEE TRANSACTIONS ON ELECTRON DEVICES and
ELETRON DEVICE LETTERS.
Lin, Hung Sung (FA.1, FA.2, FA.3)
Hung-Sung Lin was born in Hsinchu, Taiwan in 1972. He received
the M.S. in MEMS from National Tsing Hua University, Hsinchu,
Taiwan in 1997. He joined Micro System Laboratory, ITRI,
Hsinchu, Taiwan in 1999 where he worked on the research of
advanced MEMS devices and process development. In March 2000,
he joined Product Engineering Division, UMC, Hsinchu, Taiwan.
He is a section manager of Logic&MM group and presently in
charge of failure analysis of Logic and MM products. He has
published 13 papers at international conferences, and he received
UMC ten best composing invention disclosure Award in 2006 and
2008 for the contribution on composing patents in Microelectronic
Device.
Lin, Mingte (5A.3)
Mingte Lin received his B.Eng. (1987) in Power Mechanical
engineering and M.S. (1992) in Physics from Tsing Hua University
Taiwan. He joined United Microelectronics Corp. in 1997 and has
been involved in the quality and reliability of CMOS process.
Currently he is a staff engineer of reliability department.
Lin, Shang-Wei (5D.3)
Shang-Wei Lin was born in Kaohsiung, Taiwan, ROC., on July 5,
1979. He recieved the M.S. degree in Electronics Engineering from
National Central University, Taoyuan County, Taiwan, in 2004. He
joined Macronix International Company, Ltd., Hsinchu, in 2005, as
a Process Integration Engineer in technology development center.
Since 2005, he has been engaged in the development and integration
for the nitride-based NBit technology at Macronix.
Lin, Shihuan (NA. 1)
Shihuan Lin recevied B.E. degree in electrical engineering from
Beijing Insititute of Technology, Beijing, China, in 2001. Since
2006, has been a research student in Nanyang Technology
University, research interests are nano device physics and modeling.
Ling-Wu, Yang (5D.4)
Ling-Wu Yang received the M.S. degrees in material science and
engineering from the University of National Sun Yat-Sen, Taiwan,
R.O.C., in 1996. From 1996 to 1999, he joined Vanguard
International Semiconductor Co., Ltd, Hsinchu, Taiwan, R.O.C., as
a process engineer. In 2000, he joined Macronix International
(MXIC) for advanced diffusion module development. He is
currently a Project Deputy Director of Advanced Module Process
Development Division in Technology Development Center.
Linscott, Ivan (3A.3)
Ivan Linscott is a Senior Research Associate in the Space
Telecommunications and Radio Science Laboratory, in the
Electrical Engineering Department of Stanford University. Dr.
Linscott received his Ph.D. in Elementary Particle Physics from the
University of California, Berkeley CA, in 1974, and after a Post-
Doctoral residence at Syracuse University, and the Brookhaven
National Laboratory, transitioned to radio astronomy at the
Arecibo National Observatory before accepting a National
Academy of Sciences Fellowship with the SETI Project at the
NASA/Ames Research Center, Moffett Field CA, to develop
high performance signal processing systems. He has been at
Stanford since 1984.
Lipp, Dieter (4A.3)
Dieter Lipp was born in Goerlitz, Germany, in 1972. From the
Technical University of Dresden he received his Diploma in
physics in 1997 and a PhD (Dr. rer. nat.) in physics in the field
of thermal low temperature properties of superconductors in
2002. From 2002 till 2004 he worked as scientific staff memeber
at the University of Dresden were he worked on Tantalum based
barriers against copper diffusion in CMOS copper damascene
technologies. From 2004 until 2007, Dieter worked at AMD as
manufacturing engineer in chemical mechanical planarisation
(CMP) operations. Since November 2007, Dieter has been
working as reliability engineer at AMD from 2007 till 2009 and
since 2009 at GLOBALFOUNDRIES with focus on Front-End-
of-Line reliability (gate oxide reliability/TDDB) for CMOS
technologies. He has co-authored 13 papers in Journals and
conferences.
Liu, Bin (XT.4)
Bin Liu received the B.Eng. degree in electrical engineering
from the National University of Singapore (NUS) in 2008,
where he is currently working toward a Ph.D. degree at the
Silicon Nano Device Laboratory (SNDL) with the NUS
Graduate School for Integrative Sciences and Engineering
(NGS) scholarship. His research interests include strained-
silicon MOSFETs and reliability physics of CMOS device
Liu, Chien-Chih (2F.3)
Chien-Chih Liu received the M.S. degree in Materials Science
and Engineering from National Chiao-Tung University,
Hsinchu, Taiwan, R.O.C.in 1995. He joined the Taiwan
Semiconductor Manufacturing Company (TSMC) , Hsinchu,
Taiwan, R.O.C. in 2000. He has worked on the development for
several logic technologies in R&D, and then moved to FEOL
reliability department for HV device reliability qualification.
Currently, he is the HV reliability section manager in
Technology Quality and Reliability Division.
Liu, Tsu-Jae King (XT.17)
Tsu-Jae King Liu received her Ph.D. degree in Electrical
Engineering from Stanford University. She joined the Xerox
Palo Alto Research Center as a Member of Research Staff in
1992. In August 1996 she joined the faculty of the University of
California at Berkeley, where she is now Conexant Systems
Distinguished Professor of Electrical Engineering and Computer
Sciences and Associate Dean for Research in the College of
Engineering. Her awards include the DARPA Significant
Technical Achievement Award (2000) for development of the
FinFET and the 2010 IEEE Kiyo Tomiyasu Award for
contributions to nanoscale MOS transistors, memory devices,
and MEMs devices.
Liu, Ziyuan (4C.1)
Received the B. S. (1982) and the M. S. (1985) in Materials
science and engineering from Beijing Institute of Aeronautics,
China, and the Dr. Sc. (1994) in Material Science from Tokyo
Institute of Technology, Japan. From 1996 to 1997, she worked
as a frontier researcher in RIKEN (The Institute of Physical and
Chemical Research). Since 1997 she joined NEC Corporation,
and was engaged in the development of device analysis
technology. She is working on the development of gate oxide
reliability in Logic and Flash devices from 2002 at NEC Electronics
Corp. She is currently interested in chemistry and physics of
hydrogen at surfaces and interfaces contained in the MOS stacks.
Liu, Wei (5B.3, IC.5)
Wei Liu received his B.E. (2000) and M.E. (2003) in physical
electronics and optoelectronics from Huazhong University of
Science and Technology, China, and Ph.D. (2009) in
microelectronics from Nanyang Technological University,
Singapore. He has been working on the advanced back-end-of-line
process integration and technology qualification in the Technology
Development department of GLOBALFOUNDRIES Singapore
since Oct 2007.
Lo, Chien-Fong (CD.3)
Chien-Fong Lo received the B.Sc. and the M.Sc. degrees from the
Chemical Engineering Department, National Taiwan University, and
then joined the Department of Chemical Engineering, University of
Florida, in 2007 for the Ph.D. degree pursuing. He has been working
on the research in AlN/GaN high electron mobility transistors
(HEMTs) and InGaAsSb based double heterojunction bipolar
transistors (DHBTs).
Lofrano, Melina (5B.4, 6A.3)
Melina Lofrano received the BSc degree in Physics in 2001 and the
MSc in Mechanical Engineering in 2003 at the University of São
Paulo, Brazil. From 2003 until 2006 she worked in research and
product development, where she was responsible for the mechanical
modeling and analysis. From 2006 she was involved with several
CAE research projects at Katholieke Universiteit Leuven, Belgium.
In 2008 she joins IMEC modeling and reliability team.
Lu, Chih-Yuan (5D.2, 5D.3, MY.1, MY.3)
Chih-Yuan Lu received B.S. degree from National Taiwan
University in 1972, and Ph.D. degree in physics from Columbia
University, NYC, in 1977. In Dr. Lu has been a professor in
National Chiao-Tung Univ. and with AT&T Bell Labs from 1984-
1989; later joined ERSO/ITRI in 1989 as a Deputy General Director
responsible for the MOEA grand Submicron Project. This project
successfully developed Taiwan first 8-inch manufacturing
technology with high density DRAM/SRAM. He was therefore
granted the highest honor prize--National Science & Technology
Achievement Award by the Prime Minister of ROC, due to his
leadership and achievement in this Submicron Project. In 1994, Dr.
Lu becomes the co-founder of Vanguard International
Semiconductor Corporation, which is a spin-off memory IC
Company from ITRI’s Submicron Project. He was the VP of
Operation, VP of R&D, and later President from 1994-99. Dr. Lu
now is the founding chairman and CEO of Ardentec Corp. a VLSI
testing service company; and also serves Macronix International as a
Senior VP/CTO, and now the President. Dr. Lu led MXIC’s
technology development team to successfully achieve the state of
the art nonvolatile memory technology and now responsible for
MXIC’s overall operation. Dr. Lu has published more than 300
papers and has been granted 140 worldwide patents, and was elected
a Fellow of IEEE, and a Fellow of APS. He also received IEEE
Millennium Medal, and the most prestige semiconductor R&D
Award in Taiwan from Pan Wen Yuan Foundation.
Lu, Chi-Pin (MY.1)
Chi-Pin Lu was born in Hsinchu, Taiwan, R.O.C., in 1978. He
received the B.S. degree in mechanical engineering from the
National Central University, Taoyuan, Taiwan, in 2001, and the
M.S. degree in material science and engineering from the National
Tsing-Hua University, Hsinchu, Taiwan, in 2003. Since 2003, he
has been with the Technology Development Center, Macronix
International (MXIC), where his current works are engaged in
advanced diffusion module process development as well as the
dielectric characteristics studies of the nitride-trapping non-
volatile memories.
Lu, Lei (TF.1)
Lei Lu was born in Xuzhou, China, in 1985. He received the
B.S. degree in microelectronics in 2007 from Soochow
University, Suzhou, China, where he is currently working
toward the M.S. degree in the Department of Microelectronics.
His current research work is about charge pumping and substrate
current of poly-Si TFTs.
Lu, Wen-Pin (5D.3)
Wen-Pin Lu was born in I-Lan, Taiwan, R.O.C. on December
20, 1967. He received the B.S. degree in electronics engineering
from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C.
in 1990 and the M.S. degree in electrical engineering from
National Taiwan University, Taipei, Taiwan, R.O.C. in 1992. He
joined Macronix International Co., Ltd., Hsinchu, Taiwan, in
1994 as a device engineer. From 1994 to 1999, he has worked
on device analysis of non-volatile memory, especially in
floating-gate flash memory. Since 2000, he has been engaged in
the development of PACAND Flash memory technology, and
has accomplished 0.18mm and 0.15mm of delivering. He is
presently responsible for the Nitrite-based NBit technology and
also floating gate NOR flash development at Macronix.
Lu, Xiaowei (TF.1)
Xiaowei Lu was born in Suzhou, China, in 1986. He received
the B.S. degree in microelectronics in 2009 from Soochow
University, Suzhou, China, where he is currently working
toward the M.S. degree in the Department of Microelectronics.
His main research interests include charge pumping of poly-Si
TFTs and device noise models.
Lue, Hang-Ting (5D.25D.3, MY.1)
Hang-Ting Lue was born in Hsinchu, Taiwan in 1975. He
received his B.S and M.S degrees in physics from National
Tsing-Hua University (NTHU) in 1997 and 1999, respectively,
and Ph.D degree in electrical engineering in National Chiao-
Tung University (NCTU) in 2002. He joined Emerging Central
Lab. (ECL) in Macronix International. Co., Ltd. (MXIC) in
2003. Currently he is the project manager of BE-SONOS NAND
Flash and 3D TFT Memory. From 2004 he has published more
than 30 papers in the premier semiconductor conferences
including IEDM, VLSI and IRPS, and a total of more than 75
technical papers in IEEE journal/letter/conference. In 2007, he
received the “Outstanding Young Innovator Award of the
Industrial Technology Advancement Awards” by Taiwan’s
government. Currently, he is the chair of IRPS 2010 memory
subcommittee, and committee member in VLSI-TSA.
Lwin, Zin Zar (2C.3)
Zin Zar Lwin received B.Eng degree from Nanyang
Technological University, Singapore, in 2009. She is currently
pursuing her Ph.D in Electrical and Electronic Engineering at
Nanyang Technological University, Singapore. Her research
interests include physics and reliability characterization of
memory devices. She is a student member of IEEE.
M, Sivatheja (NA.2)
Siva Theja M is pursuing B. Tech. and M. Tech. combined
degrees from Electrical Engineering department of the Indian
Institute of Technology (IIT) Bombay, since 2004. His research
interests include semiconductor device modeling and simulation.
He is currently working on metal nanocrystal based non-volatile
memories.
Ma, Huan-Chi (MY.3)
Huan-Chi Ma was born in Tainan, Taiwan, R.O.C., in 1981. He
received the B.S. and M.S. degrees in electronics engineering from
National Chiao-Tung University, Hsinchu, Taiwan, in 2003 and
2005, respectively, where he is currently working toward the Ph.D.
degree. His research interests include negative bias temperature
instability degradation, nonvolatile memory reliability issues, and
flicker noise characterization.
Ma, Zhe (SE.1)
Zhe ma received his Ph.D. in E.E. from K.U.Leuven, Belgium in
2006. Since then he has been working in the Digital Component
group at IMEC, Leuven as a senior researcher. His main research
activies focus on the optimization of embedded systems design.
Maconi, Alessandro (MY.5)
Alessandro Maconi was born in Carate Brianza, Italy, in 1983. He
received the Laurea degree in electronics engineering from the
Politecnico di Milano, Milano, Italy, in 2008, where he is currently
working toward the Ph.D. degree in the Dipartimento di Elettronica
e Informazione. He is also with the Italian University Nano-
Electronics Team, Milano, Italy. His research activities mainly
involve characterization and modeling of advanced nonvolatile
memories, with particular interest to TANOS memories.
Mahapatra, Souvik (2C.3NA.2, XT.15)
Souvik Mahapatra received his PhD in Electrical Engineering from
the Indian Institute of Technology (IIT) Bombay, India, in 1999. He
was at Bell Laboratories, Murray Hill, NJ, USA during 2000-2001.
Since 2002 he is with the Department of Electrical Engineering, IIT
Bombay, India, and presently holds the position of Professor. His
research interests are in the area of characterization, modeling and
simulation of CMOS and Flash memory devices, and device
reliability. He has published more than 90 papers in peer reviewed
journals and conferences, delivered invited talks at leading
international conferences in the USA, Europe and Asia-pacific
including at the IEEE IEDM, delivered reliability tutorials at the
IEEE IRPS, and acted as a reviewer of several international journals
and conferences. He also holds an honorary graduate faculty
position at Purdue University, USA, is a distinguished lecturer of
IEEE EDS and senior member of the IEEE.
Maheta, Vrajesh (XT.15)
Vrajesh D. Maheta received the B.E. degree in Electronics
Engineering from Sardar Patel University, Gujarat, India, in 1993,
the M.E. degree in Microelectronics from Birla Institute of
Technology and Science, Pilani, India, in 2002, and the Ph.D.
degree in electrical engineering from Indian Institute of Technology
(IIT) Bombay, Mumbai, India, in 2009. From 1998 to 2009, he was
with G. H. Patel College of Engineering & Technology, as a regular
faculty. Since 2010, he has been with Middle East College of
Information Technology, Muscat, Oman, where he is currently
working as an Associate Professor in the department of electronics
and communication engineering. His research interests are in the
field of semiconductor device physics and simulation, modeling and
characterization of CMOS silicon devices
Mairena, Andrew (XT.17)
Andrew Mairena is a fourth year undergraduate in the Electrical
Engineering and Computer Sciences Department at the University of
California, Berkeley. For the past two years, his research interests
have included reliability issues in SRAM such as HCI, NBTI, PBTI,
and RTS.
Makabe, Kazuya (2D.4)
Kazuya Makabe received the B.S. degree in physics from Chuo
University, Tokyo, Japan, in 1983. He joined Hitachi ULSI
Engineering Corp., Japan, in 1983. He engaged in process
development of bipolar devices, DRAM devices, and so on. He is
now with Renesas Technology Corp. Currently, he engaged in
the process reliability of BEOL. He is a member of the Japan
Society of Applied Physics.
Makabe, Mariko (4C.1)
Received the B.S. (1990), and the M.S. (1992) in physics from
Tokyo University of Science, Japan. Since 1992 she has been
engaged in development and manufacturing technology of
FEOL at NEC Corporation. From 2002 she was in charge of
gate oxide process and reliability in Logic and Flash devices at
NEC Electronics Corporation.
Malbert, Nathalie (2E.3)
Nathalie Malbert received the Ph.D. degree in Electronics in
1996; and the professoral dissertation (Habilitation à Diriger des
Recherches) in 2004, all from the University of Bordeaux,
France. She is currently Full Professor in IMS Laboratory in the
Department of Electronics Engineering at the University of
Bordeaux. Since 2007, she is head of the team “Characterisation
and Reliability of microwave technologies” in the
Nanoelectronic group. Her research topics covered electrical
characterization, modelling, physical simulation and reliability
assessment of compound semiconductor based HEMT such as
GaN HEMT.
Mandich, Mary (FA.5)
Mary Mandich is a Distinguished Member of Technical Staff in
the Reliability Physics Group in the Chief Technology Office
Reliability Engineering organization of Alcatel-Lucent. Her
current work is focused on reliability and failure mode analysis
of wireline and wireless telecommunication systems. Previous
research areas include high speed electrical and optical
backplanes, and low cost optical platforms for high capacity
optical networks. Mandich is the Alcatel-Lucent project leader
for this research effort and contributes technically to the
collaborative ALU-EPA-DHS program to assess the impact of
biodecontamination agents on electronic equipment. Mandich
has a Ph.D. in Physical Chemistry from Columbia University.
Marathe, Amit (2D.3, 4C.6, 5A.4)
Amit P. Marathe earned his M.S. and Ph.D. in Materials Science
and Engineering from the University of California, Berkeley in
May 1991 and August 1996 respectively. His research work was
in the field of high temperature superconductor thin film
processes for integrated circuits with emphasis on high-Tc
SQUIDs and Josephson Junctions. After graduating from
Berkeley, he joined Analog Devices, Inc. in Santa Clara, CA
where he was working on the process development and
integration of BiCMOS Integrated circuits technology for over a
year. Since joining AMD in Sunnyvale CA in October of 1997,
he has led the reliability development of interconnect
metallization for AMD’s memory and microprocessor
technologies. Currently, he is the Department Manager of the
Technology Reliability Development Group at
GLOBALFOUNDRIES. His group is involved with
development of reliability methodologies and modeling failure
mechanisms of ultra thin gate dielectrics, advanced transistor
structures as well as Cu/low-k metallization. He has co-authored
over 40 technical research publications. He is also a co-inventor
of over 15 patents granted and over 50 pending US patents in the
area of technology & reliability development.
Marcon, Denis (2E.4)
Denis Marcon was born in Conegliano, Italy, on March 12,
1981. He received a M.S. degree in computer science with the
thesis entitled “Assessment of trap mechanisms in in-situ
passivated Si3N4/AlGaN/GaN HEMTs by means of pulse IV
measurements: impact of field-plate and passivation technology”
from the University of Padova in 2006. Since 2007, he is
working toward a Ph.D. investigating potential reliability issues of
GaN-based devices both for RF and switching applications at the
Catholic University of Leuven and imec, Leuven, Belgium.
Marshall, Andrew (5E.5)
Andrew Marshall is an analog and digital process verification
expert, working on leading edge and future technologies, including
sub-45nm processes and SOI. He is a Distinguished Member of
Technical Staff at Texas Instruments Incorporated, Dallas, TX. Dr.
Marshall has authored/co-authored approximately 50 patents and 60
papers. He is co-author of the book ‘SOI Design: Analog, Memory
and Digital Techniques’ and sole author of “Mismatch and Noise in
Modern IC Processes”. Dr. Marshall is a Fellow of both the IEEE
and Institute of Physics.
Masaharu, Mizutani (PI.3)
Masaharu Mizutani received the B.S. (2000) and the M.S. (2002) in
electrical engineering science from the University of Osaka, Japan.
He joined the Process Development Dept, MITSUBISHI Ltd.,
Hyougo, Japan in 2002. In 2003, he moved to Process Development
Dept., RENESAS Technology Corp., Hyogo, Japan. Throughout his
career at MITSUBISHI and RENESAS, he has been working on
research and development of advanced CMOS devices with high-
k/metal gate stacks.
Masao, Inoue (PI.3)
Masao Inoue received the B.S., M.S. and Ph.D. degrees in electrical
engineering from Osaka University, Osaka, Japan, in 1993, 1995
and 1997, respectively. In 1997, he joined Mitsubishi Electric Co.
He has been working on research and development of gate oxide,
tunnel oxide and high-k/metal gate CMOS devices. He is currently
with Process Development Department in Renesas Technology Co.
Masataka, Kase (4A.5)
Masataka Kase joined Fujitsu Limited, Kawasaki, Japan in 1986,
where he has been engaged in development of advanced Si LSI
processes. Since 2008, he has been deputy general manager in the
device development division of Fujitsu microelectronics limited. His
present activities include the advanced process development of LSI
device technologies, especially, which are including leading edge
technology and science of ion implantation, msec annealing, gate
dielectric formation, gate dielectric reliability, and stress control. He
has served as committee of several international technology
conferences. He has authored or coauthored more than 50 articles.
Mascellino, Evelyne (MY.5)
Evelyne Mascellino was born in Petralia Sottana, Italy, in 1982. She
received the Bachelor Degree in Electronics Engineering from the
Politecnico di Milano, Italy, in 2005. She's currently working on her
Master Degree thesis on Charge-Trap Memories, collaborating with
the Dipartimento di Elettronica e Informazione, Politecnico di
Milano, Milano, Italy, and the R&D Technology Development of
Numonyx, Agrate Brianza, Italy.
Massengill, Lloyd (3A.2, 6E.2)
Lloyd Massengill received the Ph.D. degree in solid state circuits
from North Carolina State University, Raleigh, in 1987. He is
currently a Professor with the Department of Electrical Engineering
and Computer Science, Vanderbilt University, Nashville, TN, where
he teaches microelectronic circuit analysis and design, and studies
the effects of radiation on the operation of integrated circuits,
particularly the modeling of circuit-level soft errors. He also serves
as the Director of Engineering for the Vanderbilt Institute for Space
and Defense Electronics, Nashville.
Masuduzzaman, Muhammad (XT.7)
Muhammad Masuduzzaman received the B.S. degree in Electrical
and Electronic Engineering (EEE) from Bangladesh University of
Engineering and Technology (BUET), Dhaka, Bangladesh, in 2004.
During 2005-2006, he worked as a Lecturer in the Department
of EEE, BUET. He is currently enrolled in direct Ph.D. program
at the Department of Electrical and Computer Engineering,
Purdue University, West Lafayette, IN, USA. His research
interest includes physics, simulation and characterization of
nanoscale devices. Currently he is working on reliability issues
in ferro-electric and high-κ devices.
Mauri, Aurelio (MY.5)
Aurelio Mauri was born in 1969. He received the M.S. degree in
plasma physics (cum laude) from the University of Milano,
Milano, Italy, in 1995. In 1996, he started to work for a
semiconductor company focused on the chemistry treatment of
silicon surfaces. In 2004, he joined the nonvolatile technology
development of STMicroelectronics in the TCAD group
working particularly on NOR/NAND memories and then with
the same function in the R&D—Technology Development,
Numonyx, Agrate Brianza, Italy. He is a coauthor of more than
20 scientific conference papers on different physics topics.
Mendenhall, Marcus (4B.2, SE.3)
Marcus Mendenhall received his PhD from Caltech in 1983. He
has been involved with ion-beam analytical techniques and
computational methods for ion scattering and transport. He
served as the associate director for operations of the Vanderbilt
Free Electron Laser, and was the physics lead on a project to
develop the first practical tunable Compton Xray source. His
current work at Vanderbilt is in computer modeling of radiation
effects in solids, numerical computing methods, and
development of new xray sources for radiobiological
applications.
Meneghesso, Gaudenzio (3F.2, 4F.2)
Gaudenzio Meneghesso graduated in Electronics Engineering at
the University of Padova in 1992 working on the failure
mechanism induced by hot-electrons in GaAs MESFETs and
HEMTs. His research interests include Electrical
characterization, modeling and reliability of microwave and
optoelectronic devices like compound semiconductors HEMTs
and MESFETs, RF-MEMS switches, and organic
semiconductors devices. He is also developing ESD protection
structures. Within these activities he published over 350
technical papers (of which more than 35 Invited). He is reviewer
of several international journals and he is Associate Editor of the
IEEE Electron Device Letter for the compound semiconductor
devices area since 2007.
Meneghini, Matteo (4F.2)
Matteo Meneghini received the degree in electronics
engineering from the University of Padova, Italy. In 2008 he
received the PhD in Electronic and Telecommunication
Engineering (University of Padova), working on the
optimization of GaN-based LED and laser structures. He is now
Research Fellow at the Department of Information Engineering
of the University of Padova. His main interest is the
characterization, reliability and simulation of compound
semiconductor devices. On these (and related) subjects, he has
coauthored approximately 80 papers published in international
journal and conference proceedings, and a number of invited
papers
Meng, Lei (4E.4)
Lei Meng received her B.Eng. degree in Electrical Engineering
from National University of Singapore in 2009. She worked as
an Associate Engineer in GLOBALFOUNDRIES Singapore
from 2005 to 2006 and an intern in Seagate Technology,
Bloomington MN USA for a period of three months during her
B. Eng. program in 2008. She is currently a Master student at
the Centre for Integrated Circuit Failure Analysis and Reliability
(CICFAR). Her field of research is in failure analysis techniques and
their potential applications in semiconductor industry.
Mertens, Robert (2E.4)
Robert P. Mertens received the electrical engineering and the Ph.D.
degree from the Catholic University of Leuven, Belgium, in 1969
and in 1972 respectively. Today he is Senior Vice President of imec,
heading the Scientific Leadership Team of imec. He is also
professor at the University of Leuven, teaching courses on
semiconductor devices and on technology of electronic and
optoelectronic systems. In 1995 Robert Mertens was elected Fellow
of the IEEE for contributions to heavily doped semiconductors,
bipolar transistors and silicon solar cells. He has authored or co-
authored more than 450 publications and has received several best
paper awards.
Miccoli, Carmine (5C.2)
Carmine Miccoli was born in Cantù, Italy, in 1984. He received the
Bachelor (BS) and the Master (MS) degrees with full marks (cum
laude) in Electronics Engineering from the Politecnico di Milano,
Milan, Italy, in 2006 and 2009, respectively. Since 2009 he has been
with the Dipartimento di Elettronica e Informazione, Politecnico di
Milano, where he is currently pursuing the Ph.D. degree in
Information Technology. His research activities include
characterization and modeling of ultra-scaled Flash memories.
Milor, Linda (IC.3)
Linda Milor is an associate professor of electrical and computer
engineering at the Georgia Institute of Technology. Her research
interests include yield and reliability modeling, testing, and design-
for-testability of analog and digital circuits. She has a PhD in
electrical engineering from the University of California, Berkeley.
Miranda, Enrique (BD.1)
Enrique Miranda received his Ph.D. degrees in Electronics
Engineering and Physics from Universitat Autònoma de Barcelona
(UAB), Spain and Universidad de Buenos Aires (UBA), Argentina
in 1999 and 2001, respectively. From 1987 to 2003, he was
Associated Professor at the Faculty of Engineering-UBA and from
2001 to 2003, Associated Researcher at the National Council of
Science and Technology (CONICET), Argentina. Since 2004, he is
Professor at the Escola d’Enginyeria-UAB. Dr. Miranda serves as
Editorial Advisor of Microelectronics Reliability and is member of
the Distinguished Lecturer program of the IEEE-Electron Devices
Society. He has served in the technical committees of
INFOS’07&09 and IRPS’08,09&10. His research interests include
dielectric physics and reliability.
Mishra, Rahul (EL.3)
Rahul Mishra received his M.Sc.(Engg.) degree in Instrumentation
in 2004 from Indian Institute of Science , Bangalore, where his
research was focused on synthesis and optimization of ZnO thin-
films with nano-particles for gas sensors. He received his PhD
degree from George Mason University in Electrical Engineering in
2008 with research focus on interaction of ESD, NBTI and HCI in
nano-scale bulk and SOI MOSFETs. During the summer and fall
2006 he worked at IBM Microelectronics on a student internship in
ESD/Latchup Development Group. In summer 2007 he was again at
IBM Microelectronics on a student internship in TCAD Technology
Enablement group where he worked on 3D device simulations for
substrate noise isolation. In 2008, he joined IBM's Semiconductor
Research and Development Center (SRDC) focusing on ESD device
development and compact modeling in 32nm, 28nm and 20nm
CMOS technologies.
Mishra, Umesh K. (2E.5)
Received the M.S. degree in electrical engineering from Lehigh
University, Bethlehem, PA, in 1981 and the Ph.D. degree in
electrical engineering from Cornell University, Ithaca, NY, in 1984.
He is a Professor with the Department of Electrical and
Computer Engineering, University of California, Santa Barbara.
He made major contributions in the area of high-speed field
effect transistors at every laboratory and academic institution
that he was with, including North Carolina State University,
Raleigh, Hughes Research Laboratories, Malibu, CA, University
of Michigan, Ann Arbor, and General Electric, Syracuse, NY.
His research interests include electronics and photonics: high-
speed transistors, semiconductor device physics, quantum
electronics, optical control, design and fabrication of millimeter-
wave devices, in situ processing, and integration techniques.
Mitani, Yuichiro (4C.2)
Yuichiro Mitani received the B. E. and M. E. in material science
and engineering from Tohoku University, Sendai, Japan, in 1990
and 1992, respectively. He received the Ph.D. from the
University of Tokyo in 2009. He joined the R&D Center,
Toshiba Corporation in 1992. His primary works were
concerned in the Si-CVD and the ultra-shallow junction process
technology. Since 1999, he has been with the Advanced LSI
Technology Laboratory, Corporate R&D Center, Toshiba
Corporation, Yokohama, Japan. His present research interests
and activities cover the ultra-thin oxide process technology and
the study of the reliability of ultra-thin gate dielectrics (SiO2,
SiON and High-k) for ULSI technology. He serves (or served)
on the technical committees of International Conference on IC
Design & Technology (ICICDT) and IEEE International
Reliability Physics Symposium (IRPS). He is a member of the
JSAP.
Mitra, Subhasish (3A.3)
Subhasish Mitra is an Assistant Professor in the Departments of
Electrical Engineering and Computer Science at Stanford
University where he leads the Stanford Robust Systems Group.
His research interests include: 1. Robust system design; 2. VLSI
design, CAD, validation and test; 3. Design for emerging
nanotechnologies. Prof. Mitra has co-authored over 125
technical papers, and is the recipient of multiple honors
including the Presidential Early Career Award for Scientists and
Engineers, National Science Foundation CAREER Award,
Terman Fellowship, IEEE CAS/CEDA Donald O. Pederson
Award, ACM SIGDA Outstanding New Faculty Award and the
Intel Achievement Award, Intel’s highest corporate honor.
Mitsuaki, Hori (4A.5)
He received the B.S. degree in Physics from Tokyo University
of Science in 1992. He joined Fujitsu limited,Kawasaki,Japan in
1992, where he has been engaged in development of LSI
processes. He is now working on development of advanced
FEOL such as ultra thin gate dielectrics formation and gate
dielectric reliability at Process development dept. of
Fujitsumicroelectronics limited, Japan.
Mitsuhiro, Fukuda (3A.5)
Mitsuhiro Fukuda received the B.Sc., the M.Sc. and Ph.D.
degrees in physics from Osaka University, Osaka, Japan, in
1983, 1985 and 1988, respectively. From 1988 to 2005, he
worked on the acceleration technologies of cyclotrons and ion
beam irradiation techniques for the related applications at Japan
Atomic Energy Agency. In 2006 he joined Research Center for
Nuclear Physics, Osaka University, and worked in the fields of
accelerator physics. He is currently responsible for upgrading
the RCNP cyclotrons for nuclear physics experiments and
various ion beam applications such as SEU analysis.
Mitsuyama, Yukio (3A.4)
Yukio Mitsuyama received the B.E. and M.E. degrees in
information systems engineering from Osaka University, Osaka,
Japan, in 1998 and 2000, respectively. He is currently an
Assistant Professor with Graduate School of Engineering, Osaka
University. His research interests include reconfigurable architecture
and its VLSI design. Mr. Mitsuyama is a member of IEEE, IEICE,
and IPSJ.
Moise, Ted (5F.3, 6C.4)
Ted Moise (M ’91) earned the B.S. degree in Physics and
Engineering from Trinity College, Hartford, CT, in 1987 and the
Ph.D. degree in electrical engineering from Yale University, New
Haven, CT, in 1992. He joined Texas Instruments in 1992, where
he was responsible for the development of high-performance III-V
quantum-effect devices and circuits. In 1997, he initiated work on
the development of scaled ferroelectric capacitors leading to the first
demonstration of low-voltage, high-density, embedded ferroelectric
memory in 2002. In conjunction with Ramtron International
Corporation, Ted and his team have also produced the first high-
density (4Mb) ferroelectric memory products on an advanced
(130nm) silicon technology node. Ted is a distinguished member of
TI’s technical staff and is currently the non-volatile memory
department manager within TI’s Analog Technology Development
organization. Ted has authored or co-authored over 60 papers,
served as conference and session chair for several international
technical conferences, presented numerous invited lectures, and
holds more than 35 issued patents. Ted was presented with an
outstanding achievement award at the 2008 ISIF conference.
Monaco, Gianni (3F.2)
Gianni Monaco received the Laurea degree in Material Science in
2004, and a Ph.D. in Material Science and Engineering in 2009, both
from the University of Padova - Italy. He is currently a research
assistant at LUXOR Laboratory of the National Institute of
Nanophotonics (CNR-INF). His research is focused on deposition
of thin films for optical applications (from Soft-X ray to Infrared)
by means of Pulsed Laser Deposition (PLD) and e-beam. He is
working on thin films analysis by studying the optical constants (in
the Soft X-ray), Atomic Force Microscope (AFM) and spectroscopic
measurements using synchrotron light.
Monzio Compagnoni, Christian (5C.2, MY.5, MY.6)
Christian Monzio Compagnoni received the Laurea degree (cum
laude) in Electronics Engineering and the Ph.D. degree in
Information Technology from the Politecnico di Milano, Milan,
Italy, in 2001 and 2005, respectively. Since 2002, he has been with
the Dipartimento di Elettronica e Informazione, Politecnico di
Milano, where he became an Assistant Professor in 2006. His
research activities include characterization and modeling of
advanced non-volatile memories and MOS devices. Dr. Monzio
Compagnoni received the Outstanding Paper Award at the IRPS in
2008 and was a member of the memory committee of the IRPS in
2009 and 2010.
Mora, Pascal (4A.2)
Pascal Mora Ph.D, STMicroelectronics, Hopewell Junction, NY
Dr. Mora received his Engineering degree from "L' Ecole Nationale
Supérieure de Physique de Grenoble", M.S.E.E. from "L'Institut
National Polytechnique de Grenoble", and Ph.D. in Micro and Nano
Electronics from "L'Institut National Polytechnique de Grenoble",
Grenoble, France. His doctoral research studied the Reliability of
Embedded Non-Volatile Memories in Advanced CMOS and Bi-
CMOS technologies. He has been a direct contributor for the
qualification of several of STMICROELECTRONICS’s most
advanced technologies and has actively worked in Semiconductor
reliability for 7 years.
Morassi, Luca (4A.4, 4F.4)
Morassi Luca, received in 2009 his academic master degree in
Electronic Engineering from University of Modena e Reggio Emilia,
Italy. During 2009 he collaborates with University of Modena and
Reggio Emilia with a research activity focused on electrical
characterization of high-k material for NVM devices. Since 2010 he
is a PhD student at ICT Electronics & Telecommunications
Doctorate School, Modena, Italy. Currently his research activity
is based on III-V compound semiconductor FETs
characterization.
Morin, Pierre (3C.2)
Pierre Morin was born in France in 1965. He received the Ph.D.
degree in electronics in 1995 from Pierre & Marie Curie
University, Paris. From 1995 to 2000 he was with Phillips,
involved in electron optics and physical processes developments
for cathode ray tubes. He joined ST Microelectronics in 2000 to
work on thin film processes development. He was then in charge
of the integration of low thermal budget deposition processes in
FEOL CMOS flows and of stressor modules in 65nm and 45nm
CMOS technology nodes. He is member of the R&D technical
staff, in charge of FEOL processes for CMOS and Flash
memories and has managed the project dedicated to solve the
pattern effects issues in the 45/40nm node. He has authored or
co-authored more than 50 publications or conferences
presentations in the microelectronics field and owns 3 patents.
Morita, Yusuke (XT.2)
Yusuke Morita received the B.S. and M.S. degrees in materials
engineering from Shonan Institute of Technology, Kanagawa,
Japan, in 1999 and 2001, respectively, and the Ph.D. degree
from the Tokyo Institute of Technology, Tokyo, Japan, in 2004.
He joined the Central Research Laboratory, Hitachi, Ltd. in
2005 where he has been working on the research and
development of CMOS devices including SOI MOSFETs. Dr.
Morita is a member of the Japan Society of Applied Physics.
Mottadelli, Riccardo (5C.2)
Riccardo Mottadelli was born in Seregno, Italy, in 1985. He
received the Laurea degree in Physics Engineering from the
Politecnico di Milano, Milan, Italy in December 2009. Since
2009 he has been working on the reliability of Flash memories
and multilevel products.
Mukherjee, Shubu (3A.1)
Shubu Mukherjee is a Principal Engineer and Director in Intel's
Microprocessor and Graphics Architecture Group. His interests
include computer architecture, fault tolerance, and innovation
"confluencing." He is the winner of the 2009 Maurice Wilkes
award, a Fellow of IEEE, and has written a book titled,
"Architecture Design for Soft Errors."
Mukhopadhyay, Gautam (NA.2)
Gautam Mukhopadhyay received M.Sc.(Physics), with 1st rank
from IIT-Kharagpur, India (1966); BARC Training School
(1967) with 2nd rank, Bombay, India; Ph.D.(1973) in Solid
State Theory from Theory Group, Tata Institute of Fundamental
Reasearch (TIFR), Bombay, India; International Atomic Energy
Agency (IAEA) Fellow (Jan-July, 1973) at International Centre
for Theoretical Physics (ICTP), Trieste, Italy; Visiting Scientist
(March, 1973- September 1978) in Institute of Theoretical
Physics, Chalmers University of Technology, Gothenburg,
Sweden; Assistant Professor (1978-1987) at Physics
Department, IIT-Bombay; Associate of ICTP, Trieste (1980-85);
Senior Solid State Fellow (1985-87) at ICTP, Trieste, Italy;
Professor of Physics (1987-) at IIT-Bombay. He has worked on
various areas of Theoretical Condensed Matter Physics, like
electronic energy band calculations for Ce, electron correlations
for homogeneous and inhomogeneous electron systems, surface
physics, Magnetism in Rare Earth Iron Garnets (RIG), optical
properties of dielectric and magnetic nanoparticles, etc. He has
more than 100 papers in peer reviewed journals and conference
Proceedings.
Murakami, Eiichi (2D.4)
Eiichi Murakami received the B.S./M.S./Ph.D. degree in applied
physics from Waseda University, Tokyo, Japan, in 1981/1983/1995,
respectively. He joined the Central Research Laboratory, Hitachi,
Ltd. Japan, in 1983. He worked on Si-SPE, SiGe, ultrashallow-
junction, and MOSFET’s design & characterization studies. He is
now the manager of Process & Device Analysis Engineering
Development Department in Renesas Technology Corp. His current
interest is in reliability and failure physics in Si-LSI. Dr. Murakami
is a member of the Japan Society of Applied Physics and the IEEE
EDS. He served as a sub-committee member of CMOS and
Interconnect Reliability in IEDM 2004,05.
Myny, Kris (4F.2)
Kris Myny was born in Hasselt, Belgium on July 26, 1980. He
received the master degree at the Katholieke Hogeschool Limburg in
Diepenbeek, Belgium in 2002. He joined imec in Leuven in 2004 as
a member of the Large Area Electronics group. In 2008, he started a
PhD on the design of organic circuits. His main research interests
are the design, fabrication and optimization of digital organic
circuits for, amongst others, organic RFID tags and AMOLED-
backplanes
Nagalingam, Dayanand (4E.4)
Dayanand Nagalingam received his B.E from Anna University,
India in 2006 and then M.Sc from National University of Singapore
in 2009. He worked as an intern in Advanced Micro Devices for a
period of 7 months during his M.Sc program. Currently he is
working in National University of Singapore as a Research Engineer
since 2009. His field of research is Characterization of Solar Cells.
Nagarajan, Raghavan (4A.1, BD.2)
Nagarajan Raghavan was born in Bangalore, India in 1985. He
received his B.Eng, 1st Class Honors, (Electronics Engineering,
2007), S.M. (Advanced Materials for Micro & Nano Systems, 2008)
and M.Eng (Materials Science and Engineering, 2008) from
Nanyang Technological University (NTU), National University of
Singapore (NUS) and Massachusetts Institute of Technology (MIT)
respectively. He was the recipient of the prestigious Nanyang
Scholarship, NTU President Research Scholar and Singapore-MIT
Alliance (SMA) Graduate Fellowship awards. He is also one of the
five recipients to be bestowed with the IEEE Reliability Society
Graduate Scholarship award in 2008 for his research
accomplishments in reliability and its application to nanoelectronics.
He is currently pursuing his Ph.D at the Division of
Microelectronics, School of EEE, NTU focusing on reliability
modeling and statistical characterization of novel high-κ dielectric
materials in nanodevices. He serves on the review committee for
IEEE Transactions on Device and Materials Reliability (TDMR). He
is currently a Graduate Student Member of IEEE (2005-present).
Nakamura, Hideyuki (5F.4)
Hideyuki Nakamura received the B.S. and M.S. degrees in
electronic engineering from University of Electro-Communications,
Tokyo, Japan, in 1991 and 1993, respectively. He joined NEC
Corporation in 1993. He has been working in NEC Electronics
Corporation from its establishment in 2002. He has been working on
development of soft error reliability technologies of SRAM and
logic circuits on SoC. He joined Environmental Variability Tolerant
Device Technology Program of MIRAI project in 2007.
Nakamura, Tomonori (FA.4)
Tomonori Nakamura received the Master's and Doctor's degree in
Engineering from the Tohoku University in 2001 and 2004. He has
been working at system department of Hamamatsu Photonics K.K.
Japan. Currently, He is in charge of reserching and developping
semiconductor circuits failure analysis systems.
Nakasaki, Yasushi (4C.2)
Yasushi Nakasaki, received the B.E. (1983) and M.E. (1985) in
nuclear engineering from Kyoto University, Kyoto, Japan. He
joined the ULSI Research Labs, Research & Development
Center, Toshiba Corp., Kawasaki in 1985. Since 1996, he joined
the Advanced LSI Technology Lab, Research & Development
Center, Toshiba Corp., Kawasaki. He has been engaged in the
research on metallization and dielectrics in both frontend and
back-end process technology using first principles calculations.
Naoyoshi, Tamura (4A.5)
He received the B.S. in Physics from Yokohama City University
in 1985. He also joined FUJITSU LIMITED working on
Advanced FEOL such as New Rapid Thermal technologies,
Reliability of ultra thin gate dielectrics and Advanced process
induced strained technologies for 20 years (He joined Fujitsu
Laboratories from 2003 to 2008 in order to research embedded
SiGe technologies) Now He is working on the classification of
1/f noise and Random Telegraph Signal originated Si/SiO2
interface and improvement of interface on Advanced RF/Mixed
Signal device. He is a member of the Japan Society of Applied
Physics.
Narasimham, Balaji (3A.2)
Balaji Narasimham received the B.E. degree in electrical
engineering from the University of Madras, Chennai, India, in
2003 and the M.S. and Ph.D. degrees in electrical engineering
from Vanderbilt University, Nashville, TN, in 2005 and 2008,
respectively. He is currently a Staff Reliability Scientist with
Broadcom Corporation, Irvine, CA, where his work focuses on
device- and circuit-level reliability and characterization of soft
errors for memory and logic circuits. He was with Intel
Corporation, Hillsboro, OR, and IBM T. J. Watson Research
Center, Yorktown Heights, NY, where he held a graduate level
cooperative position. Dr. Narasimham's research interests
include CMOS circuit design, radiation effects and reliability of
semiconductor devices and circuits. He has authored or co-
authored over 30 papers related to his research and has authored
a book chapter on single-event transients. He has served in the
technical committee of IRPS and is the recipient of the Best
Paper Award at the 2007 RADECS conference.
Nardi, Federico (5D.1)
Federico Nardi was born in 1984 in Milano, Italy. He received
his Bachelor degree (BS) in 2006 and his Master degree (MS) in
2008, both in Electronic Engineering from Politecnico di
Milano, Italy. For his first level graduation thesis he worked on
organic non volatile memories and for his second level
graduation thesis he succeeded in studying resistive-switching
effects in oxide-based memories (RRAMs). He is currently
pursuing his Ph.D degree in Information Technology
Engineering in the Dipartimento di Elettronica ed Informazione,
Politecnico di Milano, Italy. He is also with the Italian
Universities Nanoelectronics Team, Politecnico di Milano.
Nassif, Nevine (3A.1)
Nevine Nassif is a member of the Massachusetts Microprocessor
Design Center at Intel, Massachusetts, and is responsible for full
chip physical integration. She also focused on the design of
sequential circuits that are resilient to soft errors. Throughout
her career at Digital Equipment Corporation, Compaq, Hewlett
Packard and Intel, she has worked on several vax, alpha, x86,
and itanium microprocessor designs. Her major contributions
are in the area of timing, including algorithm development,
methodology, and modeling for which she has been awarded 7
patents. She holds a Ph.D. in Electrical Engineering from
McGill University
Nelhiebel, Michael (XT.6, XT.8)
Michael Nelhiebel received the M.Sc. degree in physics from the
Vienna University of Technology, Austria, and the PhD degree in
solid state physics from Ecole Centrale Paris, France, working on
interferometry in electron energy loss spectrometry. In 1999, he
joined Infineon Technologies Austria as a Reliability Engineer of
the silicon wafer production. He is currently a Senior Staff Engineer
with the quality department of the Automotive Business Division,
responsible during the development phase for technology related
product reliability. He has coordinated the qualification of major
automotive technology platforms and participates in research
activities of Infineon Technologies Austria targeting technology
reliability.
Nelson, Tan (SE.5)
Received the B.S. degree in chemical engineering and the M.S. and
Ph.D. degrees in EECS from the University of California, Berkeley,
in 1984, 1989, and 1991, respectively. At UC Berkeley, his research
was on the characterizing and modeling of optical resists under
electron-beam lithography. In 1991, he joined Intel Corporation,
Santa Clara, CA, where he worked on the development of phase
shifting mask (PSM). In 1997, he joined the Enterprise Processor
Division as a Quality and Reliability Engineer focusing on
microprocessor reliability issues. His research interests include
simulation and experimental techniques for determining radiation
effects on microprocessors. He joined Marvell Semiconductor, Inc.
in 2006 as a Principle Reliability Engineer focusing on soft error
reliability issues in various ASIC and SoC devices.
Ney, David (IC.8)
David Ney is a graduate of the engineering school of Physics of
Grenoble, France (ENSPG) in 2003. In 2006, he received his PhD in
Microelectronics from INPG (Institut National Polytechnique de
Grenoble, France). His graduate work focused on electromigration
issues in advanced copper interconnects. Since 2006, he is working
on interconnect reliability issues at Central R&D labs of
STMicroelectronics, Crolles.
Ngan, Paul (2D.2)
Paul Ngan is Reliability Manager of Regional Quality Center at
NXP Semiconductors, San Jose. He holds a BS, MS in Physics and
MBA in Finance. His previous works include qualifying BiCMOS
technologies for RF and championed the implementation of
knowledge-based qualification. He is a member of JC14.1 and 14.3
subcommittee and various task groups, including JEP122 working
group. His primary research interest is in reliability circuit
simulation and ESD robustness design techniques (especially for
RF). Occasionally when he is taking a break from reliability, you
will see him “playing” with general relativity, quantum field theory
and quantitative finance.
Nicollian, Paul (4A.6)
Paul E. Nicollian received the B.S. degree in Physics from The
Pennsylvania State University in 1983, the M.S. degree in Physics
from The University of Texas at Dallas in 1990, and the Ph.D.
degree in Electrical Engineering from The University of Twente
(The Netherlands) in 2007. He was employed by Mostek
Corporation in 1984. He joined Texas Instruments in 1985 and is
currently a Senior Member of the Technical Staff in the Advanced
CMOS Technology-Design Integration department. His research
interests include the reliability physics of dielectric materials. He
has co-authored 32 publications and is a recipient of the 2000 IRPS
Best Paper Award. He has served on the IEDM and IRPS Technical
Program Committees. Dr. Nicollian is a Senior Member of the
IEEE.
Nicolosi, Piergiorgio (3F.2)
Piergiorgio Nicolosi is full professor at University of Padua
since 2004. His research activity has been mainly devoted to
plasma and atomic spectroscopy, spectroscopic studies of laser
generated plasmas, to the development of spectroscopic
instrumentation for laboratory, synchrotron and FEL sources
and space applications, to the development of nano-structured
multilayer coatings for the extreme ultraviolet spectral range.
Nigam, Tanya (4A.3)
Tanya Nigam received her Bachelor’s degree in Physics (Hons.)
from St. Stephens College, Delhi University. She obtained a
M.Sc in Physics from IIT Kanpur and a M.Sc in Electrical
Engineering from the Katholieke Universiteit Leuven in 1995.
Between 1995 and 1999, she obtained Ph.D in the area of ultra-
thin gate oxides at IMEC, Belgium. From 1999 until 2001,
Tanya was a Member of Technical Staff at Bell Labs where she
worked on novel device geometries to overcome sub-50nm
device challenges. From 2001 until 2005, she was with Agere
Systems, formerly the Microelectronics Division of Lucent
Technology. At Agere, she worked on reliability issues for
power LDMOS devices, and HCI/NBTI reliability concerns for
CMOS. From October 2005 till 2007 Tanya worked as a Senior
Staff at Cypress Semiconductor involved in the optimization of
65nm CMOS. In 2008 she was with AMD and since 2009 she is
with GLOBALFOUNDRIES as SMTS working on the
correlation between device and product level degradation. She
has co-authored 30 papers in Journals and Conferences.
Nikolic, Borivoje (XT.17)
Borivoje Nikolic is a Professor of Electrical Engineering and
Computer Sciences at the University of California, Berkeley.
He received the Dipl.Ing. and M.Sc. degrees in electrical
engineering from the University of Belgrade, Serbia, in 1992
and 1994, respectively, and the Ph.D. degree from the
University of California at Davis in 1999. His research activities
include digital and analog integrated circuit design in scaled
technologies and VLSI implementation of communications and
signal processing algorithms.
Nobuyuki, Yoshioka (2D.4)
Nobuyuki Yoshioka received B.S. (1980), M.S. (1982) and Ph.D
(1989) degrees in physics from Collage of Science and
Technology, Nihon University, Tokyo, Japan. In 1982, he
joined LSI research and development laboratory, Mitsubishi
Electric Corp. From 1982 to 2000, he worked on development
of x-ray lithography and photomask technology. From 2000 to
2004, he worked on infrastructure development of photomask
technology in Selete (a consortium for development of
semiconductor technologies in Japan). Currently, He is
responsible for the DFM（Design For Manufacturability）
technology in Renesas Technology Corp..
Oates, Anthony (IC.10)
Tony Oates received his Ph.D. in physics from the University of
Reading, U.K. in 1985. He then joined AT&T Bell Laboratories
in Allentown, PA, as a post-doctoral member of the technical
staff, where his research focused on defects in silicon crystals. In
1987, he joined the VLSI technology development laboratory of
AT&T Bell Laboratories and since then he has studied failure
mechanisms in CMOS technologies. He is currently a member
of the technology development organization of Agere Systems
(formerly the Microelectronics Division of Lucent
Technologies), where he is a technical manager with
responsibility for technology reliability. He has published over
40 papers in the areas of interconnect and circuit reliability. He
is a member of the management committee of the International
Reliability Physics Symposium, serving as the symposium
General Chair in 2001. He is also involved in paper selection
activities for the International Electron Devices Meeting. He has
edited 2 conference proceedings on microelectronics materials
reliability for the Materials Research Society.
Obradovic, Borna (5F.3)
Borna Obradovic was born in Zagreb, Croatia, in 1970. He received
a B.S. degree in Physics in 1993, and MSE and Ph.D. degrees in
Electrical Engineering in 1996 and 1999, from the University of
Texas at Austin. From 1999 to 2006 he was a TCAD engineer at
Intel Corp, working on simulator infrastructure, physical models,
and applications, in particular regarding stress-mobility effects, SiGe
HBTs and Graphene transistors. Since 2006, he has been at Texas
Instruments, developing SPICE models for Non-Volatile Memory
devices.
O'Connor, Eamon (BD.1)
Eamon O’Connor was born in Cork, Ireland in 1980. He received
his B.E. in Electrical and Microelectronic Engineering from
University College Cork in 2002. He was awarded an MEngSc in
2005 for research at the Tyndall Institute (University College Cork)
on the fabrication and characterization of electroluminescent devices
based on organic and inorganic materials. Since 2006 his research
has been focused on the electrical characterisation of MOS device
structures utilising high-k dielectric materials on high-mobility III-V
compound semiconductors. He is currently a PhD student in the
research group of Dr. Paul Hurley at the Tyndall Institute.
Ogasawara, Makoto (2D.4)
Makoto Ogasawara received B.S. (1981) and M.S. (1983) degrees
in electronics from Toyohashi university of technology , Aichi,
Japan. In 1983, he joined Device development center, Hitachi ,Ltd.
From 1983 to 2003, he engaged in process development of DRAM
and gate oxide reliability in MOS devices. He is now with Renesas
Technology Corp. Currently, He is responsible for the process
reliability of FEOL and BEOL
Ohmi, Tadahiro (5F.2)
Tadahiro Ohmi received the B.S., M.S., and Ph.D. degrees in
electrical engineering from Tokyo Institute of Technology, Tokyo,
Japan, in 1961, 1963, and 1966, respectively. Prior to 1972, he
served as a Research Associate in the Department of Electronics,
Tokyo Institute of Technology, where he worked on Gunn diodes
such as velocity overshoot phenomena, multivalley diffusion and
frequency limitation of negative differential mobility due to an
electron transfer in the multi-valleys, high-field transport in
semiconductor such as unified theory of space-charge dynamics in
negative differential mobility materials, Bloch-oscillation-induced,
negative mobility and Bloch oscillators, and dynamics in injection
lasers. In 1972, he moved to Tohoku University, Sendai, Japan,
where he is currently a Professor at the New Industry Creation
Hatchery Center. He is engaged in researches on high-performance
ULSI such as ultrahigh-speed ULSI based on gas-isolated-
interconnect metal-substrate SOI technology, base store image
sensor (BASIS) and high-speed flat-panel display, and advanced
semiconductor process technologies such as low kinetic-energy
particle bombardment processes including high-quality oxidation,
high-quality metallization, very-low-temperature Si epitaxy, and
crystallinity-controlled film growth technologies from single-crystal,
grain-size-controlled polysilicon and amorphous highly selective
CVD, highly selective RIE, and high-quality ion implantation with
low-temperature annealing capability based on ultraclean
technology concept supported by newly developed ultraclean gas
supply system, ultrahigh vacuum-compatible reaction chamber with
self-cleaning function, and ultraclean wafer surface cleaning
technology. His research activities are summarized by the
publication of over 1300 original papers and the application of 1600
patents. Dr. Ohmi serves as the President of the Institute of Basic
Semiconductor Technology-Development (Ultra Clean Society). He
is a Fellow of the Institute of Electricity, Information and
Communication Engineers of Japan. He is a member of the
Institute of Electronics of Japan, the Japan Society of Applied
physics, and the Electrochemical Society. He received the
Ichimura Award in 1979, the Inoue Harushige Award in 1989,
the Ichimura Prizes in Industry-Meritorious Achievement Prize
in 1990, the Okouchi Memorial Technology Prize in 1991, the
Minister of State for Science and Technology Award for the
Promotion of Invention (the Invention Prize) in 1993, the IEICE
Achievement Award in 1997, the Okouchi Memorial
Technology Prize in 1999, the Werner Kern Award in 2001, the
ECS Electronics Division Award, the Medal with Purple Ribbon
from Government of Japan and the Best Collaboration Award
(the Prime Minister’s Award) in 2003.
Ok, Injo (4F.4)
Injo Ok received the B.S. and M.S. degrees in Electrical
Engineering from Changwon National University, Changwon,
Korea in 2000 and 2002, respectively and the Ph.D. degree in
Electrical and Computer Engineering at the University of Texas,
Austin. In April 2008, he joined SEMATECH at Albany,
Albany, NY, where he working on fabrication and
characterization of III-V and SiGe FinFET transistors for 22-nm
node and beyond. He has authored or coauthored more than 47
technical papers.
Olney, Andrew (3B.1)
Andrew Olney is the Director of Reliability, Product Analysis,
Calibration & ESD at Analog Devices, Inc. in Wilmington,
Massachusetts. He received a BS degree from Lehigh
University and an MS degree from Boston University, both in
Electrical Engineering. Andrew is responsible for managing
ADI’s worldwide Reliability, Product Analysis, Calibration, and
ESD labs and associated engineering organizations in Ireland,
the Philippines, and the United States. Andrew has published
several papers and holds several patents related to ESD testing
and on-chip protection. He also represents ADI on the
Semiconductor Industry Association (SIA) Anti-Counterfeiting
Task Force.
Olson, Nicholas (4D.3)
Nicholas Olson received his B.S. degree in electrical
engineering from Iowa State University of Science and
Technology in 2005. He received his MS degree from the
University of Illinois at Urbana-Champaign in 2008 and is
working towards his Ph.D at the same university. His research
is in the field of ESD and he plans to graduate by 2011.
Ong, Yi Ching (4A.4)
Y. C. Ong received the B.Eng. (Hons) and Ph.D. degrees in
electrical and electronics engineering from Nanyang
Technological University (NTU) in 2004 and 2010, respectively.
She is currently a post doctoral fellow in the University of
Tokyo. Her research interest is in the application of scanning
probe microscopy technique on surface and reliability physics.
Onoye, Takao (3A.4)
Takao Onoye received the B.E. and M.E. degrees in electronic
engineering, and the Dr.Eng. degree in information systems
engineering, all from Osaka University, Osaka, Japan, in 1991,
1993, and 1997, respectively. He was an Associate Professor
with the Department of Communications and Computer
Engineering, Kyoto University, Kyoto, Japan. Since 2003, he
has been a Professor in the Department of Information Systems
Engineering, Osaka University. He has published more than 200
research papers in the field of VLSI design and multimedia
signal processing in reputed journals and proceedings of
international conferences. His current research interests include
media-centric low-power architecture and its SoC
implementation. Dr. Onoye has served as a member of the CAS
Society Board of Governors since 2008. He is a member of IEEE,
IEICE, IPSJ, and ITE-J.
Ottogalli, Federica (5C.4)
Federica Ottogalli, since 28-Oct-2007 with Numonyx, Via
C.Olivetti 2, 20041, Agrate Brianza (Milan), Italy. She received the
doctor degree in Physics from the University of Padova, Italy, in
1998 with a thesis on crystallographic characterization by RBS-
Channeling and modeling of III-V compounds. She joined the Non-
Volatile Memory Technology Development Group of the Central
R&D of STMicroelectronics in Agrate Brianza (Milan) in 1999.
Since 2002, she has been working on the process development for
phase-change memories based on chalcogenide materials.
Oualli, Mourad (2E.3)
Mourad Oualli was born in France in 1982. He was graduated from
the Ecole Polytechnique, Palaiseau, France and the Ecole Supérieure
d’Electricité (Supélec), Gif-sur-Yvette, France, in 2007. He then
joined the Alcatel-Thales III-V lab as a research engineer in the
development of the AlGaN/GaN and AlInN/GaN HEMT
technologies. He especially works on the improvement of device
reliability.
Ouchi, Tomohiko (2D.4)
Tomohiko Ouchi received B.S.(1988) and M.S.(1991) degrees in
physics from Ibaraki University, Ibaraki, Japan. He joined the
Hitachi Research Laboratory, Hitachi ,Ltd, in 1991. He worked on
molecular CAD development, Flash memory design and
ferroelectric memory development. He is now with Renesas
Technology Corp. Currently, he is working on the development of
DFM method.
Paccagnella, Alessandro (3F.2, 4B.3)
Alessandro Paccagnella is Full Professor of Electronics and Director
of the Department of Information Engineering at the University of
Padova. He is the author of more than 300 scientific papers, and
about 200 of them have been published on international journals. In
the past, his research has been directed to the study of different
aspects of physics, technology, and reliability of semiconductor
devices. At present, he coordinates the activity of a research group
focused on the study of ultra-thin gate dielectrics in MOS devices
and on Total Ionizing Dose and Single Event Effects induced by
ionizing radiation on integrated circuits.
Padovani, Andrea (4A.4, 4F.4, 6C.1)
Andrea Padovani graduated in Electronics Engineering at the
University of Modena and Reggio Emilia, Italy, in 2005. He
received his Ph.D. in 2009 from the University of Ferrara, Italy. He
is currently a post-doc at the University of Modena and Reggio
Emilia, Italy.His research activity focuses on the reliability and
modeling of logic transistors based on high-k/metal gate technology,
and of innovative non-volatile memories, such as resistive rams
(RRAM) and charge-trapping devices (NROM, TANOS). He
authored and co-authored more that 25 technical papers in
international journals and conference proceedings. He serves as
reviewer for several international journals.
Pan, Liu (3C.5)
Liu Pan was born in Xi’an, Shaanxi province, China, He received
the B.S and M.S degree in material science and technology from the
University of Science and Technology Beijing in 2000 and 2003,
respectively. He is currently working for GLOBALFOUNDRIES
Singapore company and responsible for semiconductor chip failure
analysis. His strength is in transmission electron microscopy (TEM)
sample preparation and image analysis. His interested areas include
chip function failure analysis and reliability assessment. He also is
the author of 8 papers and 2 patents on the failure analysis, material
characterization and TEM sample preparation technique.
Park, Chan-Hoon (2C.4)
Received the B.S. (2008) in electronics engineering from the
Kyungbuk National University, Korea. He received the M.S.
(2010) in electronics engineering from the Pohang University of
Science and Technology (POSTECH), Pohang, Korea. He is
currently in Ph.D. course at POSTECH. His main research
interests include nanowires fabrication.
Park, Hokyung (2B.4)
Hokyung Park received a B.S. (2001) in Avionics from Korea
Aerospace University and M.S. (2003) and Ph. D (2007) in
Material Science and Engineering from Gwangju Institute of
Science and Technology, KOREA. He is device characterization
and reliability engineer at SEMATECH from 2008. His current
research area is characterization of memory devices and high-k
gate dielectric for logic application and reliability evaluation.
Park, Hyun-Kook (RM.3)
Hyun-Kook Park was born in Ik-san, Jeollabuk-do, Korea, in
1983. He received the B. S. degree in the electrical and
electronic engineering from Yonsei University, Seoul, Korea, in
2008. He is studying for M. S degree in Yonsei University. His
current research interests is SRAM stability and FinFET SRAM
design.
Park, Jongwoo (2D.1, 3C.3)
Jongwoo Park received the Ph. D. degree from Lehigh
University, Bethlehem, PA, in 1998. After post doctoral
research at Lehigh University in 1999, he joined Lucent
Technologies as a Member of Technical Staff. His research
projects were packaging and reliability associated with
application and characterization of polymeric materials used for
microelectronic devices and interfacial failure mechanism. In
2002, he joined Princeton Optronics as a Manager of
Quality/Reliability. He was involved in hermetic/nonhermetic
package development and reliability focused on tunable laser
module including pump laser, MEMS and VCSEL. Since 2003,
he is with Technology Reliability, Q&R team in SYSTEM LSI,
Samsung Electronics as a Director responsible for reliability
qualification of CMOS process and product and has contributed
to the development and reliability of 90, 65, 45, and 32nm logic
process technology nodes.
Park, Milim (MY.7)
Milim Park received the B.S. degree in electrical engineering
from Chonbuk National Univercity, Chonjo, Korea, in 2005.
From 2005 to 2010, she is with the Flash Device Team, Hynix
Semiconductor Inc., Korea. She is currently focusing on triple
level cell technology development in Nand Flash Memeory.
Park, Suk-Kwang (MY.7)
Suk-Kwang Park received the B.S. degree in Physics from Dong
A University, Busan, Korea, in 1999, and the M.S. degrees in
Physics from Pusan National University Busan, Korea, in 2002 ,
Since joining the hynix Semiconductor Inc. Ichon,Korea, in
2002, he has been working on device and process integration of
high density memory as well as deep submicron devices. From
2002 to 2005.He and his team developed hynix’s first MLC
product ,the world’s first commercial 16MB 3bits NAND flash
in 2008, He is currently working on the development 3bits
NAND.
Park, Young-Joon (6A.1)
Young-Joon Park received his BS from Seoul National
University in 1986, and MS.D. and Ph.D. in material science
and engineering from KAIST in 1988 and 1995. He was a post
doctoral associate in MIT during 1995-1996. Young-Joon joined
Texas Instruments (TI) in 2002 and is a Senior Member of
Technical Staff, working in the BEOL reliability area. Prior to
TI, He had researched on various topics in Korean governmental
research institutes: 1988-1991 in ETRI and 1996-2002 in KIST.
Young-Joon has authored or co-authored 70+ papers/presentations
and holds 10+ patents issued or filed.
Pavan, Paolo (4F.4, 6C.2)
Paolo Pavan graduated in Electrical Engineering at the University of
Padova, Italy, in 1990. He received his PhD in 1994 from the same
University. From 1992 to 1994 he was at the University of
California at Berkeley. He is currently Full Professor of Electronics
at the University of Modena and Reggio Emilia. He is the President
of the IU.net Consortium. His research activity deals with electrical
characterization, modeling and reliability of integrated circuits and
nonvolatile memory devices. He also works on "By-wire" systems
for automotive and wireless embedded systems. He has been
involved in the technical committees of international conferences
(IEDM, ESREF). He authored and co-authored many papers, one
book and two chapters in edited books.
Pei, Yi (2E.5)
Received the B.S. degree in Electrical Engineering from Peking
University, Beijing, China, in 2000, the M.S. and Ph.D. degrees in
Electrical Engineering from University of Santa Barbara, USA, in
2005 and 2009, respectively. He joined in Dynax Semiconductor,
Inc. in 2009. His research interests focus on design, fabrication, and
characterization and applications of compound semiconductors,
especially in Nitride-based devices. Dr. Pei has authored and co-
authored more than 50 papers in technical journals and conferences.
Pendharkar, Sameer (HV.1)
Graduated from The University of Wisconsin-Madison in 1996. In
1996, he joined Texas Instruments Inc. where he worked on
developing more than 5 generations of BiCMOS-DMOS (LBCTM)
technologies. His primary focus was on developing highly efficient,
robust and cost efficient integrated high voltage and high power
semiconductor devices. He is currently a TI Fellow and manages the
High Voltage Component Development Group at Texas Instruments
Inc.
Petitprez, Emmanuel (IC.8)
Emmanuel Petitprez received the Engineering degree in solid state
physics from the Institut National des Sciences Appliquées,
Toulouse, France, in 1994, and the Ph.D. degree in materials science
from the University of São Paulo, Brazil, in 2001. He was with
Serma Technologies, Grenoble, France, as a Characterization
Engineer. In 2005 he moved to Freescale Semiconductor, Crolles,
France working on interconnect reliability issues in SOI
technologies. Since 2007, he has been with the STMicroelectronics
Central R&D Laboratory, Crolles, France where he works on the
reliability of interconnects for advanced CMOS technology.
Pey, Kin Leong (2C.3, 4A.1, 4A.4, 5B.3, BD.2, MY.4)
Kin Leong Pey received his Bachelor of Engineering (1989) and
Ph.D. (1994) in Electrical Engineering from the National University
of Singapore (NUS). He has held various research positions in the
Institute of Microelectronics, Chartered Semiconductor
Manufacturing, Agilent Technologies and National University of
Singapore. He is currently a Visiting Professor at Nanyang
Technological University (NTU) and an Associate Provost of
Singapore University of Technology and Design (SUTD), Singapore
and also holds a concurrent Fellowship appointment in the
Singapore-MIT Alliance (SMA). He has published more than 150
international refereed publications and 160 technical papers at
international meetings/conferences and holds 33 US patents. Dr. Pey
is a senior member of IEEE and an IEEE EDS Distinguished
Lecturer.
Phang, Jacob Chee Hong (3C.4, 4E.4)
Jacob CH Phang received both his BA and PhD degrees from
the University of Cambridge in 1975 and 1979 respectively. He
joined the National University of Singapore in 1979 where he is
now Professor at the Centre for Integrated Circuit Failure
Analysis and Reliability (CICFAR), Faculty of Engineering. His
field of research is in microelectronic device failure analysis and
reliability. He is also Executive Chairman of SEMICAPS
Corporation, an NUS spin-off company he co-founded in 1988
to commercialise the technologies developed at CICFAR for
world-wide distribution.
Piazza, Michele (2E.3)
Michele Piazza was born in Pordenone, Italy, in 1981. He
graduated in Electronic Engineering at the University Of Padova
(Italy) in 2008. He's currently a research Engineer at Alcatel-
Thales 3-5 Lab and registered as PhD student at X-LIM, France.
He works on GaN HEMTs reliability within the Thales
Microelectronics Group.
Pickholtz, Jeffrey (3A.1)
Jeffrey Pickholtz joined Intel in 2003 where he contributed to
the design of multiple Itanium microprocessors. He is currently
an engineering manager working on a next generation
microprocessor. Prior to joining Intel, Jeffrey worked for Digital
Equipment, Compaq and HP where he contributed to a variety
of VAX and Alpha microprocessor designs
Pinato, Alessandro (4F.2)
Alessandro Pinato was born in Piove di Sacco (Padova), Italy, in
1982. In 2007 he received the degree (summa cum laude) in
Electronics Engineering at the University of Padova, working on
the development of an Ion Sensitive Field Effect Transistor
(ISFET) based on organic electronics. He is currently working
toward the Ph.D. degree in Information Engineering at the
University of Padova. His main interests are the characterization
and reliability analysis of organic semiconductor devices, in
particular OLEDs and organic photovoltaic solar cells.
Pirovano, Agostino (5C.4)
Agostino Pirovano was born in Italy in 1973. He received the
Laurea degree in electrical engineering in 1997, and the Ph.D.
degree at Politecnico di Milano, Italy, in 2000. He joined the
Department of Electrical Engineering in 2000, working on the
modeling and characterization of transport properties in
MOSFET devices. In 2001 and 2002 he was a consultant for
STMicroelectronics. From 2002 he teaches 'Optoelectronics' at
the Politecnico di Milano, where he was a lecturer from 1999. In
2003 he joined the Non-Volatile Memory Technology
Development Group of STMicroelectronics, working on the
modeling and characterization of phase-change memory devices.
From 2008 he is with Numonyx, R&D Technology
Development, being in charge for the investigation of emerging
NVM technologies.
Pobegen, Gregor (XT.8)
Gregor Pobegen received his BSc degree in technical physics
from the Graz University of Technology, Austria, in 2007. He is
currently working toward his MSc degree at KAI GmbH in
cooperation with Infineon Technologies Austria. His master
thesis focuses on the electrical characterization of NBTI induced
oxide defects.
Pogany, Dionyz (4D.4)
Dionyz Pogany received his Dipl. - Ing. degree in solid state
engineering from the Slovak Technical University in Bratislava
in 1987. In 1994 he received a Ph.D. degree at INSA de Lyon,
France. In 1994-95 he was a postdoc at France Telecom, CNET-
Grenoble. Since 1995 he is with the Institute of Solid State
Electronics, TU Vienna, Austria, where he leads a research team.
Since 2003 he is Associate Professor at TU Vienna. He published on
defect states in semiconductors, low frequency noise and device
reliability physics. His current research interest is in ESD-
phenomena, self-heating effects, current filamentation and thermal
breakdown, power electronics, GaN HEMTs and LEDs, failure
analysis, device reliability and development of new optical methods
for device characterization. He is author or co-author of more than
250 scientific contributions.
Poli, Stefano (HV.1)
Received the Ph.D. degree in Information Technology from the
University of Bologna in 2009. In 2005 he was with the
Interuniversity Micro Electronic Center, Leuven, Belgium, as an
Internship under-graduate student. Since 2006 he is with the ARCES
Research Center, working on the modeling and simulation of ultra-
scaled CMOS, post-CMOS and CNT based device. In 2007 he was
with CEA-LETI, Grenoble, France, as a graduate student. He is
currently involved in the modeling, design and TCAD analysis of
low-Rsp power MOSFETs in the frame of a SRC Project in
collaboration with Texas Instruments (Dallas, Texas).
Puchner, Stefan (XT.6)
Stefan Puchner finished his diploma thesis, concerning thin layer
surface analysis with time of flight secondary ion mass spectrometry
in May 2007 and received his M.S. degree in physics from the
Vienna University of Technology, Austria. Currently he is working
toward his doctor degree at KAI in cooperation with Infineon
Villach and the Institute for Chemical Technologies and Analytics.
Rafik, Mustapha (4A.2)
Mustapha Rafik received the engineering degree in physics from the
Instiut Nationale Polytechnique de Grenoble, and the M.S.E.E
degree from Joseph Fourier University of Grenoble, France, 2005.
In joined STMicroelectronics, Crolles, France in 2005 where he
obtained a PhD degree in micro and nanoelectcronics in 2008. He is
currently a reliability engineer with STMicroelectronics and his
research focus on advanced gate stack reliability.
Raghavan, Nagarajan (5B.3)
Nagarajan Raghavan was born in Bangalore, India in 1985. He
received his B.Eng, 1st Class Honors, (Electronics Engineering,
2007), S.M. (Advanced Materials for Micro & Nano Systems, 2008)
and M.Eng (Materials Science and Engineering, 2008) from
Nanyang Technological University (NTU), National University of
Singapore (NUS) and Massachusetts Institute of Technology (MIT)
respectively.
Ragheb, Tamer (5E.5)
Tamer Ragheb received the Ph.D. degree in electrical and computer
engineering from Rice University, Houston, TX, in 2008. Since
2008, he has been with Texas Instruments Incorporated, Dallas, TX,
where he currently works with Advanced CMOS Technology-
Design Integration Group. His research interests include
interconnect modeling, parasitic extraction, substrate noise
characterization, and the development of circuit designs to evaluate
and verify performance and power metrics for deep submicron
technologies. He has published more than 30 papers in peer
reviewed journal and conference proceedings.
Ragnarsson, Lars-Ake (2A.3, XT.13)
Lars-Åke Ragnarsson received a M.S. degree in 1993 and a Ph.D.
degree in 1999 in Electrical Engineering from Chalmers University
of Technology, Goteborg, Sweden. He did post-doctoral studies at
the IBM T.J. Watson Research Center in Yorktown Heights, NY,
USA between 2000 and 2002, focusing mainly on electrical
characterization of high-k dielectrics. He is since 2002 employed by
IMEC in Leuven, Belgium as a senior research scientist on high-k
dielectrics and metal gates.
Rangoni, Armando (MY.5)
Armando Rangoni was born in 1971 in Piacenza, Italy. In 1996
he graduated in Industrial Chemistry and in 1999 he took the
Specialization in Science of Polymers. In 2000 he was hired
from STMicrolectronics as R&D Process Engineer and after,
from 2004, he worked as R&D SPC Engineer. From 2008, under
Numonyx, he works in the field of NAND memories electrical
characterization and reliability.
Rao, V. Ramgopal (4D.4, EL.2)
V. Ramgopal Rao received the M.Tech. degree from Indian
Institute of Technology (IIT) Bombay, Mumbai, India, in 1991
and Dr. Ingenieur degree from the Faculty of Electrical
Engineering, Universitaet der Bundeswehr Munich, Germany, in
1997. During 1997–1998 and again in 2001, he was a Visiting
Scholar with the Electrical Engineering Department, University
of California, Los Angeles. He is currently a Professor in the
Department of Electrical Engineering, IIT Bombay. His areas of
interest include physics, technology, and characterization of
silicon CMOS devices for logic and mixed-signal application
and Nanoelectronics. He has over 250 publications in these areas
in refereed international journals and conference proceedings
and holds three patents with eight patents currently pending.
Prof. Rao is a Fellow of the Indian National Academy of
Engineering, a Fellow of the Indian Academy of Sciences and a
Fellow of the Institution of Electronics and Telecommunication
Engineers (IETE). He received the Shanti Swarup Bhatnagar
Prize in Engineering Sciences in 2005 for his work on electron
devices. He also received the Swarnajayanti Fellowship Award
for 2003–2004, instituted by the Department of Science and
Technology, Government of India, 2007 IBM Faculty award,
2008 ‘The Materials Research Society of India (MRSI)
Superconductivity & Materials Science Prize’ and the 2009
TechnoMentor award instituted by the Indian Semiconductor
Association. . He is an Editor for the IEEE TRANSACTIONS
ON ELECTRON DEVICES in the CMOS devices and
technology area and is a Distinguished Lecturer (DL), IEEE
Electron Devices Society. Prof. Rao was the organizing
committee Chair for the 17th International Conference on VLSI
Design and the 14 th International Workshop on the Physics of
Semiconductor Devices and serves on the program/organizing
committees of various international conferences including the
International Electron Devices Meeting (IEDM), IEEE Asian
Solid-State Circuits Conference, 2006 IEEE Conference on
Nano-Networks, ACM/IEEE International Symposium on Low
Power Electronics and Design, 11 th IEEE VLSI Design & Test
Symposium among others. He was Chairman, IEEE AP/ED
Bombay Chapter during 2002-2003 and currently serves on the
executive committee of IEEE Bombay Section besides being the
vice-chair, IEEE Asia-Pacific Regions/Chapters Subcommittee.
Recchia, Charles (3A.1)
Dr Charles Recchia is currently senior product reliability
engineering manager at Intel Corporation, having previously
focused on microlithography process development for next-
generation silicon technologies with Portland Technology
Development. Dr Recchia holds a doctorate in condensed
matter physics from Ohio State University, holding 3 patents
and author on over twenty technical publications spanning
fundamental research, technology development and
microprocessor reliability.
Redaelli, Andrea (5C.4)
Andrea Redaelli was born in Italy in 1978. He received the
Laurea (cum laude) and Ph.D. degrees in electronic engineering
from the Politecnico di Milano, Italy, in 2003 and 2007
respectively. During the Ph.D. thesis he worked on Phase
Change Memories in the Department of Electrical and
Electronic Engineering, Politecnico di Milano. His research
interests include the modeling and characterization of transport
properties and phase-change transition of chalcogenide-based
devices. From 2007, he joined STMicroelectronics working on
advanced technologies for non volatile memories and since 2008 he
is employed in the emerging non volatile memory group of
Numonyx. From 2005 to 2009, he cooperated with Politecnico di
Milano, in holding master’s classes on electronics and signal
conditioning.
Reddy, Vijay (5E.5)
After receiving the Ph.D. (1994) in Electrical Engineering from the
University of Texas at Austin, Vijay Reddy joined Texas
Instruments and has worked on several topics concerning transistor,
circuit reliability and product qualification methodologies. He is
currently a Distinguished Member Technical Staff and is focusing
on the digital, analog, and RF spaces. He has served on the
IRPS/IEDM program committees and has presented papers at
IRPS/IEDM and invited tutorials at IRPS/ICTMS/VLSI Test.
Symposium. He received the 2002 IRPS Outstanding Paper Award,
2004 IRPS Outstanding Paper Award, and the 2002 ESD/EOS
Symposium Best Paper/Best Presentation Awards. He has received
eleven patents with several pending along with more than 26
publications.
Reed, Robert (4B.2, SE.3)
Robert A. Reed received his M.S. and Ph.D. degrees in Physics from
Clemson University in 1993 and 1994. After completion of his
Ph.D. he worked as a post-doctoral fellow at the Naval Research
Laboratory and later worked for Hughes Space and Communication.
From 1997 to 2004, Robert was a research physicist at NASA
Goddard Space Flight Center where he supported NASA space
flight and research programs. He is currently a Research Associate
Professor at Vanderbilt University. His radiation effects research
activities include topics such as single event effect and displacement
damage basic mechanisms and on-orbit performance analysis and
prediction techniques.
Reents, William (FA.5)
William Reents is a Consulting Member of Technical Staff and
director of the Reliability Physics Group in Murray Hill, NJ. He
joined Bell Laboratories in 1980, working in several areas of
research and root cause analysis. His areas of specialty include
package hermeticity, organic contamination and gas and particle
contamination issues.
Reggiani, Susanna (HV.1)
Received the B.S. and Ph.D. degrees in electrical engineering from
the University of Bologna, Bologna, Italy, in 1997 and 2001. Since
April 1997, she has been working with the Department of
Electronics (DEIS), University of Bologna, in the field of numerical
simulation of semiconductor devices. She became a Research
Associate in 2001 and is currently with the ARCES Research
Center. Since 1999, she has been working on the simulation of
electron transport in nanoscale devices such as silicon nanowires,
carbon nanotubes and graphene nanoribbons. She is currently
involved in a SRC project in collaboration with Texas Instruments.
Regolini, Jorge Luis (3C.2)
Jorge Luis Regolini received his M.Sc. from Centro Atomico
Bariloche (Argentina) and graduated from Strasbourg University
(France) with a Thesis in Solid State Physics. He was then with the
Atomic Energy Commission in Argentina as a researcher on
Semiconductor Physics and Technology. At the EE Dept. (Stanford
University - USA) he worked as a post-doctoral fellow in laser
processing for silicon recrystalisation and silicide formation. From
1986 he was with France Telecom CNET-CNS involved on
RT/RPCVD for the selective deposition of epitaxial Si/SiGeC and
silicides. He has presented several invited papers on those fields,
concerning material fabrication and characterisation, kinetics and
kinematics aspects of reduced pressure single wafer reactors.
From 2000 he was with STMicroelectronics (Crolles-France) as
Senior Staff Engineer on Advanced Dielectrics for new
generations of DRAMs and gate stacks, and circuit passivation
issues. He is now R&D expert and he has participated to the
development of new Image Sensors Technologies. He holds
several patents and more than 100 publications in these fields.
Reifenberg, John (2C.5)
John P. Reifenberg received the B. S. degree in mechanical
engineering from Carnegie Mellon University in 2003, and the
M. S. and Ph. D degrees in mechanical engineering from
Stanford University in 2006 and 2010, respectively. His
graduate research developed models and measurements of
nanoscale thermal transport phenomena in phase change
memory data storage devices. He is a recipient of the National
Defense Science and Engineering Graduate (NDSEG)
Fellowship and an Honorary Stanford Graduate Fellowship
(SGF).
Reisinger, Hans (2A.1, 2A.3, 2F.4)
Hans Reisinger received his diploma in physics (1979) and his
Ph.D. (1982) both from the Technical University of Munich. In
1982/83 he was with the IBM T.J.Watson Research Ctr. in
Yorktown Heights working on electronic properties of 2d-
systems. In 1986 he joined the Siemens Semiconductor
Department (now Infineon). His work was focused on the study
of thin dielectrics and interfaces in DRAMs and NVMs.
Currently he is with the Infineon Central Reliability
Methodology group and mainly works on threshold instabilities
of MOSFETs.
Relangi, Prasanthi (3A.3)
Prasanthi Relangi received her B.E. in Electrical and Electronic
Engineering with Honors from Birla Institute of Technology and
Science (BITS), Pilani, India in 2005 and her M.S. in Electrical
Engineering from Stanford University, Stanford CA, in 2007,
where she is currently pursuing her Ph.D. in the Department of
Electrical Engineering. Her research interests include erratic bit
errors, soft errors and digital circuits.
Remack, Keith (6C.4)
Keith Remack (IEEE M’81) was born in Chicago, IL. He
received the B.Sc. degree in Electrical Engineering from The
Milwaukee School Of Engineering, Milwaukee, WI. He
currently works in the Medical Business Unit of Texas
Instruments, Inc., Dallas, TX. His current research interests are
the development of product and reliability test methods for
embedded FRAM memory arrays. Mr. Remack is a registered
Professional Engineer in the state of Texas and has authored or
coauthored over 20 technical papers.
Ren, Fan (CD.3)
Fan Ren is Charles Stokes Professor of Chemical Engineering at
the University of Florida, Gainesville, FL, USA. He joined UF
in 1997 after 12 years as a Member of Technical Staff at AT&T
Bell Laboratories, where he was responsible for high speed
compound semiconductor device development. He is a Fellow
of ECS. APS and AVS.
Renard, Sophie (2B.2)
Sophie Renard received the PhD degree in microelectronics
from the Université de Provence, Marseille, France in 2003
working on EEPROM memories reliability through the
collaboration between STMicroelectronics, Rousset, France and
the L2MP laboratory, Marseille, France. Afterwards, she joined
the reliability group of STMicroelectronics Central R&D,
Crolles, France where she has been working on Front-end
Reliability, and more specifically on Hot-Carriers Injection
mechanism. Since 2008, she has been Technical Leader of the Non
Volatile Memories Reliability.
Ribes, Guillaume (4A.2)
Guillaume Ribes received the engineer degree in electrical
engineering from the ISEN (Institut Supérieur d’Electronique et du
Numérique, France), in 2002. He obtained in 2005, the Ph.D degree
in microelectronics from INPG (Institut National Polytechnique de
Grenoble). He worked as a reliability engineer at
STMicroelectronics in the area of advanced devices reliability. He
works now for ISDA as ST assignee in the field of High-K and Low
K reliability. He has published 40 papers and 20 as first author. He
serves the IRPS Technical program committee in 2006 and 2007 for
High-K and in the 2010 for BEOL dielectrics & Interconnects.
Riedlberger, Eva (2F.4)
Eva Riedlberger obtained her Diploma in Physics from the
Technical University Munich in 2007, where she worked on the
growth of III-V based heterostructures by Selective Area Epitaxy at
the Walter-Schottky-Institute. She is currently pursuing a Ph.D.
degree in Electrical Engineering from the Bundeswehr University in
Neubiberg, to graduate by Sept. 2010. She is with Infineon
Technologies since 2007 and is working on the modeling of the
degradation of Lateral DMOS Transistors due to Hot Carrier
Injection.
Robl, Werner (IC.6)
Werner Robl received his PhD in Physics from the University of
Regensburg in 1994. After his degree he joined Infineon (former
Siemens Semiconductors). Since then he has been working on
development of new metallization schemes in Regensburg and
Munich, Germany and East Fishkill, NY. Currently, he is working
as a Principal for Metallization on new metalliza¬tion schemes for
semiconductor devices and chip packaging. He is a member of the
German Physical Society.
Roche, Philippe (4B.4)
Philippe Roche received the M.S. (1995) and Ph.D. (1999) in
semiconductor physics from the University of Montpellier, France.
From 1995 to 1999, he worked consecutively at the University of
Eindhoven, the Netherlands, at the French Atomic Energy
Commission, Military applications centre at Bruyères-le-Chatel, at
the University of Montpellier and in the Radiation Effects Group at
Vanderbilt University, USA. Since 1999, he has been with
STMicroelectronics, Central CAD and Design Solutions, Crolles
France, as senior expert and manager of a group in charge of both
SER safety/reliability aspects and subthreshold (~0.3V) IP designs.
His primary research activities are Single Event Effects and Total
Ionizing Dose, as well as Ultra Low Voltage IPs, on sub-0.25µm
commercial technologies down to CMOS 20nm. He has been
serving in conferences since 1997, as session chairman and short
course instructor, in 10 international conferences, such as IRPS,
NSREC, IOLTS, RADECS and SOI conference. Philippe has
coauthored 90 papers and has filed 19 patents and 3 trade marks in
radiation hardening.
Rodriguez, John (5F.3, 6C.4)
Dr. Rodriguez is a Senior Member of the Technical Staff in the
Analog Technology Development Reliability group at Texas
Instruments, Dallas, where he has focused on FRAM technology
since 2001. He earned his BS, MS and PhD ('99) degrees at Rice
University, all in Electrical and Computer Engineering. He joined
TI's advanced process development lab in Houston in 1993 as a
summer intern, where he contributed TCAD and SPICE modeling
for submicron modular merged technology components including
high voltage, analog, non-volatile memories and ESD. He has co-
authored over 25 conference and journal publications and has been
awarded 11 US patents.
Rodriguez Latorre, Jose (6C.4)
Jose A. Rodriguez was born in Moca, Puerto Rico on June 21,
1983. He received the B.S. degree in Electrical Engineering
from the University of Puerto Rico at Mayaguez in 2007.
Currently, he is a Research Assistant at the University of Puerto
Rico at Mayaguez and working toward his M.S. degree. Jose
has worked at Texas Instruments as a summer intern since 2007
mostly focusing on product engineering and test development.
Rosenbaum, Elyse (4D.5, EL.1)
Elyse Rosenbaum received the B.S. degree (with distinction)
from Cornell University in 1984, the M.S. degree from Stanford
University in 1985, and the Ph.D. degree from the University of
California, Berkeley in 1992. All of these degrees were in
electrical engineering. From 1984 through 1987, she was a
Member of Technical Staff at AT&T Bell Laboratories in
Holmdel, NJ. She is currently a Professor in the Department of
Electrical and Computer Engineering at the University of Illinois
at Urbana-Champaign. Dr. Rosenbaum’s present research
interests include design, testing, modeling and simulation of
ESD protection circuits, design of high-speed circuits with ESD
protection, and latch-up. She has presented tutorials on
reliability physics at the International Reliability Physics
Symposium, the EOS/ESD Symposium, and the RFIC
Symposium. She has authored or co-authored over 100 technical
papers and is an editor for IEEE Transactions on Device and
Materials Reliability. Dr. Rosenbaum has been the recipient of a
Best Student Paper Award from the IEDM, a Technical
Excellence Award from the SRC, an NSF CAREER award, an
IBM Faculty Award, and a UIUC Bliss Faculty Scholar Award.
Roussel, Philippe J. (2A.3, 6A.3, XT.13)
Philippe J. Roussel was born in Bruges, Belgium, on May 18,
1955. He recei¬ved the diploma in Electrical Engineering from
the Industriële Hogeschool of Ghent, Belgium, in 1983. In 1984,
he joined the ESAT labo-ratory of the KULeuven, Belgium as
an assistant in a reli¬ability research project on plastic
en¬capsulation. From 1987, he assisted in a gov¬ernment
funded project on electromigration at imec, Leuven, which also
resulted in a maxi¬mum likelihood fitting program for the
assessment of statistical distributions and acceleration models
from reliability test data. From 1991 till 2000, he worked on
analysis techniques like microprobe, TEM and Spectroscopic
Ellipsometry (SE) in the PT/MCA group, while continuing his
research on Reliability Statistics, SPC and Data Analysis in the
PT/DRE group. At present he also works in a multi¬disciplinary
team on the statistics required for Technology Aware Design
(TAD). He co-authored papers in fields as diverse as scientific
handheld programming, virology, SE, ESD, oxide and
interconnect reliability, and TAD.
Roy, David (2B.2)
David Roy received the BS (1997) in physics, the M.S.(1998) in
Physics (from the Institut National Polytechnique de Grenoble
(INPG) and the Magistere (1998) of Physics Research from
University Joseph Fourier de Grenoble. He worked for the CEA-
Grenoble on the 3D-optical micro-system in the “Laboratoire d
Electronique et des Technologies de l’information” (LETI) in
1999. In 1999, he joined STMicroelectronics as a reliability
engineer, working on oxide and device reliability. Since 2007,
he is in charge of the Front-end Reliability team. His current
research interests include transistor reliability as well as low k
interconnect reliability.
Ruelke, Hartmut (IC.2)
Dipl. Phys. Hartmut Ruelke is a GLOBALFOUNDRIES Fellow
Process Engineer working for Module One LLC&Co KG
Dresden, Germany. He is leading the CVD and PVD projects in
the Thin Films Module at GLOBALFOUNDRIES, former AMD
Fab36 LLC & Co KG, 300mm Micro-Processor Fabrication. During
1996 to 2004 he was the lead CVD Engineer in AMD’s 200mm
fabrication line, responsible for PE-CVD, HDP and Tungsten CVD
processes. Prior joining AMD in 1996 he was working for System
Microelectronic Innovation GmbH Frankfurt (Oder) as Senior
Process Engineer for CVD - Processes and Epitaxy. During 1991 to
1992 Hartmut Ruelke was Head of the Group Doping Processes /
CVD in the Technology Department of Halbleiter Elektronik GmbH
Frankfurt (Oder). From 1979 to 1991 he worked at the
Halbleiterwerk Frankfurt (Oder), a Bipolar and CMOS
Semiconductor Fabrication, as Process Engineer for Diffusion,
Epitaxy and Semiconductor Measurement.Hartmut Ruelke received
his Diploma degree in Physics in 1979 from Technical University of
Magdeburg, Germany and completed postgraduate study of
Semiconductor Technology 1982 at Technical University of Karl-
Marx-Stadt, Germany.
Rumyantsev, Sergey (2B.4)
Sergey L. Rumyantsev received the M.S.E.E. degree from
Leningrad Electrotechnical Institute, Leningrad, USSR, in 1977, the
Ph.D. degree in physics from Leningrad Polytechnical Institute in
1986, and the Doctor of Science (Habilitation) degree from A.F.
Ioffe Institute of Physics and Technology, Lenningrad, in 1996.
From 1999 he is with Rensselaer Polytechnic Institute. He is also a
Research Fellow of A.F. Ioffe Institute of Physics and Technology.
His current research interests include low frequency noise, wide
bandgap semiconductors, terahertz electronics, nanowires and
semiconductor nanotubes, graphene. He published a number of
papers and he is a coeditor of 5 books.
Ryan, Jason (2A.5, XT.18)
Jason T. Ryan (S’04) received the B.S. degree in Physics from
Millersville University, Millersville, PA in 2004. He received the
M.S. degree in Engineering Science and the Ph.D in Materials
Science and Engineering from The Pennsylvania State University,
University Park, PA in 2006 and 2010 respectively. He is currently
employed in the Semiconductor Electronics Division at the National
Institute of Standards and Technology. His current research
involves the atomic-scale mechanisms involved in bias temperature
instabilities and stress induced leakage currents in ultra thin gate
dielectrics.
Ryan, Shawn (FA.5)
Dr. Shawn Ryan is the decontamination research area lead in EPA's
National Homeland Security Research Center's (NHSRC)
Decontamination and Consequence Management Division. His
research includes determining methods for assessing
decontamination efficacy; investigating technologies as a function of
agent and operation; decontaminant-material interactions (demand,
compatibility, by-products). He received his B.S. in Environmental
Engineering, M.S. in Chemical Engineer, and Ph.D. in Chemical
Engineering all from Rensselaer Polytechnic Institute, Troy, NY.
Ryoichi, Ishihara (3F.3)
Ryoichi Ishihara received the Ph.D. degree from the Tokyo Institute
of Technology, Tokyo, Japan, in 1996. Since 1996, he has been with
the Delft Institute of Microsystems and Nanotechnology (DIMES),
Delft University of Technology, Delft, The Netherlands, where he
has been focusing on location control of grains through a novel
excimer-laser crystallization process and fabrication and
characterization of high-performance TFTs inside a single grain. He
is currently an Associate Professor with the Faculty of Electrical
Engineering Mathematics and Computer Science, Delft University
of Technology.
Ryuta, Tsuchiya (PI.3)
Ryuta Tsuchiya received the B.S., M.S., and Ph.D. degrees in
material science from the Tokyo Institute of Technology, Tokyo,
Japan, in 1993, 1995, and 1998, respectively. He joined the Central
Research Laboratory, Hitachi, Ltd., Tokyo, Japan, in 1998,
where he has been engaged in research on fabrication and
characterization of high-performance and low-power MOSFETs
including thin-film SOI and BOX transistors. Dr. Tsuchiya is a
member of the Japan Society of Applied Physics.
Sagong, Hyun Chul (2C.4)
Received the B.S. (2008) in electronics engineering from the
Pusan National University (PNU), Pusan, Korea. He is currently
in M.S. and Ph.D. integrative program cource at the Pohang
University of Science and Technology (POSTECH), Pohang,
Korea. His main research interests include CMOS devices and
RF measurement.
Sahhaf, Sahar (XT.9)
Received the M.Sc. degree in electrical engineering from the
Catholic University of Leuven, Belgium, in 2006. Currently, she
is working toward the Ph.D. degree at the KULeuven university
(Belguim) and IMEC. The main focus of her work is on the
reliability of high-κ gate dielectrics and metal gates.
Salman, Akram (4D.3)
He received his B.Sc. from Alexandria University, M.Sc. from
AAST, Egypt, and Ph.D. from George Mason University,
Fairfax, VA. He held several positions in the semiconductor
industry at IBM and AMD. In 2008 he joined Texas Instruments
as and ESD specialist working on the ESD development for
various analog technologies. He is an author/co-author of more
than 38-refereed publications; he holds 5 U.S patents with 4
more pending. Dr. Salman was awarded, the distinguished
academic achievement award from GMU, the IBM co-operative
fellowship and the best paper award from the 2005 SOI
conference.
San, Tamer (5F.3)
Tamer San received the B.S. degrees in electrical engineering
and physics from Bogazici University, Istanbul, Turkey. He
received the M.S and Ph.D. degrees in electrical engineering in
1991 and 1994, respectively, from Yale University. He joined
Texas Instruments in 1994 where he worked on memory
technology development. He was involved in development of
nonvolatile memory (Flash) technology at various technology
nodes and SRAM technology at 90nm node. From 2005 to 2007,
he was at IMEC as an assignee from TI and worked on
MUGFET (multi-gate) devices. Since 2009, he is leading FRAM
development at 180nm node. Since 1996, he has been a member
of technical committee of non-volatile semiconductor memory
workshop. He is currently serving as the technical program chair
of international memory workshop.
Sandhya, C. (NA.2)
C. Sandhya (S’07) received the M.Tech. degree in
microelectronics in 2006 and Ph.D. degree in electrical
engineering in 2010 from the Indian Institute of Technology
Bombay, Mumbai, India. During her graduation, she was a
recipient of the SRC (GRC) fellowship. Since November 2009,
she is working with Samsung Semiconductor R&D Center,
South Korea. Her research interests are in the field of Flash
memory optimization through device characterization and
understanding device physics through modeling, design, and
simulation.
Sasse, Guido (CR.3)
Guido Sasse received the M.Sc and Ph.D degree, both in
electrical engineering, from the University of Twente, The
Netherlands, in 2003 respectively 2008. He performed his Ph.D.
research at the MESA+ Institute for Nanotechnology, where he
studied RF CMOS reliability, reliability simulation, and
advanced CMOS characterization techniques. In 2008 he joined
NXP Semiconductors, where he works on wafer level reliability. His
current activities have a focus on RF reliability and reliability
simulation. He received the IRPS 2006 best poster award.
Sato, Motoyuki (4C.2)
Motoyuki Sato received the B.S. and M.S. degrees in applied
physics of engineering from the University of Tokyo, Tokyo, Japan,
in 1996 and 1998, respectively, and the Ph.D. degree in engineering
from University of Tsukuba in 2008. He joined Toshiba
Corporation, Yokohama, Japan in 1998, and has been engaged in the
research for semiconductor device fabrication and its physics. He
joined the Semiconductor Leading Edge Technologies Inc.(Selete)
since 2006, and moved to Toshiba in 2010. He received the best
paper award in International Workshop on Dielectric Thin Film
(IWDTF) 2008. His current interests and activities include the study
of the reliability physics in high-k gate dielectrics. Dr. Sato is a
member of technical program committee member in IRPS since
2008.
Schlünder, Christian (2A.1)
Dr. Christian Schlünder has received his Dipl.-Ing. (1999) in
electrical engineering and his doctoral degree in engineering science
(2006) accompanying his regular work (both from the Technical
University of Dortmund, Germany). From 1998-1999 he worked in
a cooperative program between Siemens Corporate Research Labs
in Munich and the Technical University of Dortmund. 1999 he
joined Infineon as a member of the Corporate Research Department,
where he was active in research on hot carrier stress in analog and
mixed signal applications. Since 2000 he works in the Corporate
Reliability Methodology Group. There he manages technology
qualification and quality assurance for various state-of-the-art
CMOS-Technologies and technology transfers to silicon foundries.
Furthermore he evaluates the device reliability of innovative
technologies. He leads the NBTI-research for Infineon. His current
work is focussed on recovery phenomena. Christian Schlünder has
published some 30 papers in various conference proceedings and
microelectronic journals. Additionally, he has presented invited talks
and tutorials at many conferences such as ‘IRPS’, ‘ESSDERC’ or
“ZuE”. He is frequently a member of the Technical Program
Committee of the IEEE-conferences ‘IRPS’, ‘IRW’ and referee of
several microelectronic journals. Moreover he is involved in the
JEDEC NBTI standard development.
Schmitt-Landsiedel, Doris (CR.2)
Doris Schmitt-Landsiedel received the Dipl. Ing. degree in electrical
engineering from the Technical University of Karlsruhe, the diploma
in physics from the University of Freiburg and the Dr. rer. nat.
degree from the Technical University of Munich. She joined the
Corporate Research and Development Department of Siemens AG,
Munich, Germany, in 1981. There she worked on scaling problems
in MOS devices and on the design of high speed logic and SRAM
circuits. Since 1989 she has been manager of a research section with
projects in future generation memory design, analog and digital
CMOS and BICMOS circuits and design-based yield analysis. Since
1996 she is a professor of electrical engineering and director of the
Institute for Technical Electronics at the Technical University of
Munich. Her research interests are in robust CMOS circuit design
and reliability as well as in circuits with novel devices and
nanomagnetic computing.
Schneider, Jens (4D.4, EL.2)
Jens Schneider received his diploma in physics (Dipl. Phys.) in 1995
from the University of Kaiserlautern working on the condensation of
quasi-particles in field theories. He then moved to Munich where he
he received his Ph.D. from Ludwig-Maximilians-University in 2001
in the filed of atom lasers and Bose-Einstein condensation. Since
then he is working with Infineon Technologies, first in the field of
modelling of process effects in photomask lithography. Since 2003
he is working in the Infineon ESD/LU group where is involved with
process and device simulation of ESD phenomena and with the
development of HV CMOS ESD protection concepts.
Schrimpf, Ron (SE.3)
Ron Schrimpf received his BEE, MSEE, and Ph.D. degrees from
the University of Minnesota in 1981, 1984, and 1986,
respectively. He is currently a Professor of Electrical
Engineering at Vanderbilt and he previously was a Professor at
the University of Arizona. Ron's research deals with the effects
of radiation on semiconductor devices and integrated circuits.
Current projects include use of high performance parallel
computing to simulate single-event effects and soft errors in
integrated circuits, atomic-scale modeling of radiation-induced
defects, and design techniques for reliable integrated circuits.
Ron is the director of the Institute for Space and Defense
Electronics.
Schrimpf, Ronald (4B.2, 6E.2)
Ron Schrimpf is the Orrin Henry Ingram Professor of Electrical
Engineering at Vanderbilt University and the Director of
Vanderbilt’s Institute for Space and Defense Electronics (ISDE).
He received his B.E.E., M.S.E.E., and Ph.D. degrees from the
University of Minnesota in 1981, 1984, and 1986, respectively,
and served as a Professor of Electrical and Computer
Engineering at the University of Arizona prior to joining
Vanderbilt in 1996. Ron’s research activities focus on radiation
effects and reliability in microelectronics and semiconductor
devices. He has served as General Chairman and Technical
Chairman of the IEEE Nuclear and Space Radiation Effects
Conference and Chairman of the IEEE Radiation Effects
Steering Group.
Scozzari, Claudia (MY.5)
Claudia Scozzari graduated in physics from the University of
Trieste Italy (2005). In 2006 she joined the STMicroelectronics
in Agrate Brianza (Italy) working in the Non-Volatile Memory
Process Development group within the Dielectric Reliability
group of Central R&D. She is coauthored 10 papers published in
journals or presented in international conferences. Recently, the
memory section of STMicroelectronics has been separated
forming a new company, Numonyx, and she joined the new
company.
Seetharaman, Sridhar (HV.1)
Received the B.Tech degree from the Indian Institute of
Technology in Madras, India, and MS and PhD degrees in
Electrical engineering from North CarolinaStateUniversity in
Raleigh. He joined Texas Instruments Inc. in 1996 where he
worked as a process integration engineer in developing 4
generations of deep submicron CMOS. Since 2007 he has been
working in the areas of power component design and BCD
process integration. He is currently a Distinguished Member of
Technical staff at TI and a BCD development manager.
Seifert, Norbert (3A.1)
Norbert Seifert currently heads all radiation effects efforts in the
Manufacturing Technology Group at Intel Corporation. Prior to
joining Intel in 2003, he worked in the fields of compact
modeling, device reliability and digital design in the Alpha
Development Group (DEC, CPQ, HP). He received Diplom
Ingenieur and Ph.D. degrees in physics from the Technical
University of Vienna, Vienna, Austria, in 1990 and 1993,
respectively. He also holds an M.S. degree in physics from
Vanderbilt University (Nashville, TN, May 1994).
Sekine, Katsuyuki (4C.2, MY.2)
Katsuyuki Sekine was born in Saitama, Japan, in 1970. He
received the B.S., M.S., and Ph.D. degrees in electronic
engineering from Tohoku University, Sendai, Japan in 1995,
1997, and 2000, respectively. In 2000, He joined Process and
Manufacturing Engineering Center, Toshiba Corporation,
Semiconductor Company, Yokohama, Japan, where he worked on
development of advanced gate dielectric film formation process for
CMOS device. He is currently engaged in development of dielectric
film for nonvolatile memory device in Advanced Memory
Development Center, Semiconductor Company, Toshiba
Corporation, Yokkaich, Japan
Shao, Ingrid (4E.5)
Ingrid Shao is a research staff member at IBM T.J. Watson Research
Center. She got her Ph.D. in materials science and engineering
department at Johns Hopkins University in 2002. She joined IBM
Research soon after graduation. She has worked in research related
to hard disk drive, CMOS interconnect, Phase change memory, and
currently working on Si photovoltaics. Ingrid has won a graduate
student gold medal from Materials Research Society in 2001.
Sheldon, Douglas (6E.1)
Doug Sheldon is currently the VLSI Reliability Center Lead at the
Jet Propulsion Laboratory. Dr. Sheldon has been at JPL for 7 years
and involved in a wide variety of electronic part reliability and
radiation issues. He is also a principal investigator on several
NASA and JPL R&D projects regarding new FPGA and memory
technology applications to spacecraft. Prior to coming JPL Dr.
Sheldon had 20 years experience in various engineering and
management positions in the commercial integrated circuit industry
including Lattice Semiconductor, Ramtron, and Inmos. Dr. Sheldon
has a bachelor and master’s degrees in physics from the University
of Colorado and the University of Oregon respectively and a
doctorate degree in management from Colorado Technical
University.
Shi, Quan (3A.1)
Quan Shi received M.S. from Beijing Normal University in Radio
Frequency Electronics in 1986 and Ph.D. degree from University of
New Mexico in Electrical Engineering in 2000. From 1998 to 2002,
he worked as a design engineer and Research Assistant Professor
with NASA Institute of Advanced MicroElectronics to design
Radiation Tolerant special purpose processors for NASA
applications. He joined Intel in 2002. He is currently working in
standard cell library team focusing on library reliability and cell
architecture related issues. His research interests include radiation
hardened sequential design, circuit electromigration and standard
cell layout architecture.
Shih, J.R. (2F.3)
Jiaw-Ren Shih received his M.S. and Ph.D. from National Tsing-
Hua University, Taiwan, in 1992 and 2000, respectively. All are
with Electrical Engineering. Dr. Shih is the Academician in TSMC
Academy now, and also serves as the manager of Advanced
Reliability Development Program and Mainstream Technology
Quality and Reliability Department at Technology Quality and
Reliability Division. Prior to joining reliability division in 2000, he
served as the transistor designer at device department of R&D since
1992. Dr. Shih has served on the IRPS Technical Committee in
2002, 2004 ~ 2009 for Transistor, Process Integration and Dielectric
Sections, respectively. He holds 53 U.S. patents and 40 Taiwan
patents, and also published more than 41 technical papers.
Shin, Changhwan (XT.17)
Changhwan Shin received the B.S. degree with top honors in
electrical engineering from Korea University, Seoul, Korea, in 2006.
Since 2004, he has received a fellowship from the Korea Foundation
for Advanced Studies (KFAS). He is currently working toward the
Ph.D. degree in electrical engineering in the Department of
Electrical Engineering and Computer Sciences, University of
California, Berkeley, CA. He won the Best Paper Award and the
Best Student Paper Award at the 2009 IEEE International SOI
Conference. His research interests include non-conventional
advanced CMOS device designs and their applications to
variation-robust SRAM cell.
Shinosky, Mike (5A.5)
Mike Shinosky received an Associate of Engineering degree in
Electronic Engineering from A.T.E.S. Technical Institute of
Niles, Ohio in 1982. Mike joined IBM in 1982, where he was
responsible for building and running Soft Error Rate testers for
DRAM Memory products. In 1985 he began T2 Functionality
Qualification testing of DRAM memory cards for large scale
server applications. In 1999 Mike transferred to an ASICS
department doing book level Physical Design Mask Layout
work. In 2003 Mike joined Technology Reliability Engineering,
where he is currently and primarily responsible for TDDB
testing of BEOL Dielectric technologies.
Shrivastava, Mayank (4D.4, EL.2)
Mayank Shrivastava was born in Lucknow, India, in 1984. He
received the B.S. degree in engineering from Rajiv Gandhi
Technical University, Bhopal, India, in 2006. He is currently
working toward the Ph.D. degree with the Center for Excellence
in Nanoelectronics, Department of Electrical Engineering,
Indian Institute of Technology (IIT) Bombay, Mumbai, India In
July 2006, he joined IIT Bombay as a Research Fellow. He was
a Visiting Research Scholar with Infineon Technology AG,
Munich, Germany, from April 2008 to October 2008. His
current research interest includes ESD- and HCD-aware I/O
device design, ESD-aware technology development, FinFET and
UTB-Planar SOI devices, nonvolatile analog memories, and
electrothermal modeling and simulation. He has five U.S.
patents and one Indian patent pending in the fields of ESD, I/O
devices, FinFETs, and nonvolatile analog memory. Mr.
Shrivastava was a recipient of the Intel’s 2008 Asia Academic
Forum (AAF’08) Best Research Paper Award in the circuit
design category. He also served as a Reviewer for the IEEE
TRANSACTIONS ON ELECTRON DEVICES, the 2009 IEEE
International Electron Devices Meeting (IEDM’09), and the
2010 International Conference on VLSI Design (VLSI’10).
Shukla, Vrashank (4D.5)
Vrashank Shukla received his B.E. degree from the National
Institute of Technology, Karnataka in 2001. He is currently
working towards a PhD degree in Electrical Engineering at
University of Illinois Urbana Champaign. He worked at Texas
Instruments, Bangalore, India from 2001 to 2007 in the ASIC
CAD group. He worked on the development of EDA tools for
reliability analysis of circuits.
His current research focus is on full-chip and package modeling
for electro-static discharge (ESD) simulations, in particular,
simulation of charged device model of ESD. He works in the
ESD group of Co-ordinated Science Laboratory at University of
Illinois Urbana Champaign.
Shur, Michael (2B.4)
Michael Shur received MSEE degree (with honors) from LETI,
PhD and Dr. Sc. degrees from Ioffe Institute. He is Patricia W.
and C. Sheldon Roberts Professor, Acting Director of Center for
Integrated Electronics and Director of the NSF I/UCRC at RPI.
He is also co-founder and Vice-President of Sensor Electronic
Technology, Inc. His area of expertise is physics of
semiconductor devices. Dr. Shur is Foreign Member of the
Lithuanian Academy of Sciences and Fellow of IEEE, APS,
IET, ECS, MRS, and AAAS. He received IEEE and other
awards and holds Honorary Doctorate from St. Petersburg
Technical State University.
Sierawski, Brian (4B.2, SE.3)
Brian Sierawski is a Staff Engineer at the Institute for Space and
Defense Electronics. He joined ISDE in January 2005 where his
efforts include modeling of semiconductor devices using
Technology Computer Aided Design (TCAD) simulations and
developing tools for the prediction of single event error rates. He
earned a BSE in Computer Engineering and MSE in Computer
Science and Engineering from the University of Michigan in 2002
and 2004 respectively and is currently pursuing his Ph.D. in
Electrical Engineering at Vanderbilt University.
Simms, Richard J.T. (2E.5)
Received the M.S. degree in physics in 2006 from the University of
Bristol, Bristol, U.K., where he is currently working toward the
Ph.D. degree at the CDTR group. His current research interests
include studying electrical effects in AlGaN/GaN HFET devices
using dc and time-resolved micro-Raman spectroscopy,
electroluminescence and electrical characterisation techniques.
Simoen, Eddy (2A.3)
Eddy Simoen obtained his Masters ('80) and Doctoral Degree ('85)
in Engineering from the University of Gent (Belgium). His doctoral
thesis was devoted to the study of trap levels in high-purity
germanium by deep-level transient spectroscopy. In 1986, he joined
imec to work in the field of low temperature electronics. His current
interests cover the field of device physics and defect engineering in
general, with particular emphasis on the study of low-frequency
noise, low-temperature behavior and of radiation defects in
semiconductor components and materials. He is an imec Researcher
currently involved in the study of defect and strain engineering in
high-mobility and epitaxial substrates and defect studies in
germanium. In these fields, he has (co-) authored over 1000 Journal
and Conference papers.
Singh, Pawan (NA.2)
Pawan Singh received B. Tech. and M. Tech. combined degrees and
PhD from Electrical Engineering department of the Indian Institute
of Technology (IIT) Bombay, India in 2006 and 2010 (January)
respectively. He was the recipient of Applied Materials fellowship
during his PhD in IIT Bombay.. He worked as a graduate intern at
Applied Materials, Santa Clara, CA from June 2007 - July 2008.
Since February 2010 he is with CEA-LETI-MINATEC at Grenoble,
France. His research interests include technology development,
physics, and reliability characterization of non-volatile memories
and metal/high-k integration.
Smout, Steve (4F.2)
Steve Smout was born in Leuven, Belgium on March 17, 1984. He
received the bachelor degree at the Katholieke Hogeschool Leuven
in Leuven, Belgium in 2007. He joined imec in Leuven in 2007 as a
member of the Large Area Electronics group. His main focus is the
development of new transistor of foil technologies, both for organic
and oxide semiconductor device concepts.
Song, Du Heon (5C.1)
Du Heon Song received the Ph.D. degree in electronics engineering
from Seoul National University. He joined Samsung Electronics in
2000. Since 2009, he has been working on the process integration of
NAND flash memories. His current interests include sub-30nm
NAND flash memory development and reliability.
Song, Jai Hyuk (5C.1)
Jai Hyuk Song was born in Seoul, Korea, on August 3, 1967. He
received Ph.D. degrees in electronic engineering from Seoul
National University, Seoul, Korea, in 1996. Since 1996, he has been
working in device engineering of sub-micron DRAM & sub-60nm
NAND Flash memories at Samsung Electronics Corporation, Korea.
His current interests include reliability issues and operation
optimization and scaling of floating type NAND Flash memories.
Song, Seung-Chul (RM.3)
Seung-Chul Song received Ph.D in Solid State Electronics from
the Univeristy of Texas at Austin in 2000. Since then, he had
been in engineering and managemental positions in various
organizations including Motorola, Samsung and Sematech.
Since 2007, he has been with Qualcomm, leading projects of
28nm HK/MG technology enablement and advanced transistor
technology development for future technology nodes.
Song, Seung-Hyun (2C.4)
Received the B.S. (2004) and Ph.D (2010) in electronics
engineering from the Pohang University of Science and
Technology (POSTECH), Pohang, Korea. His main research is
related to CMOS devices.
Soo Sien, Seah (3C.5)
Seah Soo Sien received his bachelors in Materials Engineering
from Nanyang Technological University, and is a Engineer in
Quality Reliability Assurance Failure Analysis at Global
Foundries of Singapore.
Spessot, Alessio (MY.6)
Alessio Spessot received the Laurea degree (cum laude) in
Physics from the University of Triest (Italy) and the Ph.D.
degree in Solid State Physics from the University of Modena
(Italy), in 2003 and 2006, respectively. In 2006 he joined the
Non-Volatile Memory Process Development Group, Central
Research and Development department of STMicroelectronics
(now Numonyx), Agrate Brianza, Milano, Italy. His research
activities include characterization and modeling of MOS devices
and advanced non-volatile memories. He published more than
30 papers in device physics and solid state physics. Dr. Alessio
Spessot received the Best Paper Award at the EMRS in 2006.
Spinelli Sottocornola, Alessandro (5C.2, MY.5, MY.6)
Alessandro S. Spinelli is a Full Professor of electronics with the
Politecnico di Milano. He has conducted experimental and
theoretical research in electronics instrumentation and
microelectronics, co-authoring more than 130 papers published
in international journals or presented at international
conferences, and serving in the technical committees of the
IEDM and IRPS conferences. His current research interests
include experimental characterization and modeling of non-
volatile memory cells performance and reliability, development
of innovative non-volatile memory technologies and circuit
design for biological signal readout.
Spitzer, Andreas (2F.4)
Andreas Spitzer received his Diploma in Physics in 1979 and the
Ph.D. in 1982 from the Technical University Aachen, Germany.
From 1982 to 1984, he specialized there on adsorption on single
crystal surfaces and on GaAs Schottky contacts. In 1984, he
joined Siemens AG Corporate Research and Development in
Munich, where his research activities have focused on the
physics of dielectrics with a special emphasis on multilayer
films. From 1999 to 2006 he was with the Memory Products
Division of Infineon Technologies AG as head of the process
and device simulation department. In 2006, he joined the
Automotive Division of Infineon. He is now responsible for the
device development and simulation of the technology
development in Munich.
Srividya, Vidya (XT.9)
Earned a B.S. in Chemical Engineering from Anna University in
Chennai, India and a Ph.D. in Chemical Engineering in 1997
from Clarkson University in Potsdam, New York. After
graduating, she worked at CVC as a Process engineer
developing PVD and CVD metal films. She joined Micron
Technology, Boise in 2001 as a CVD Process engineer. She has
worked on CVD/ALD deposition of various metal and high-k films
for DRAM capacitor module application. For the past 3 years, she
has been working on DRAM- and flash-related programs at IMEC,
Belgium where she is on an international assignment, representing
Micron Technology.
Stathis, James H. (2B.1, BD.3, XT.14)
Jim Stathis received the bachelor’s in physics from Washington
University in St. Louis (1980), and the Ph.D. in physics from the
Massachusetts Institute of Technology (1986), joining the IBM
Research Division the same year. At IBM the focus of his work has
been the electrical properties of point defects in SiO2, including
basic studies of defect structure using magnetic resonance and
electrical measurement techniques, and the role of defects in
wearout and breakdown. He is the author or coauthor of more than
100 research papers and over 60 invited talks. From November 2005
to February 2007 he served as Technical Assistant to the Vice
President for Science and Technology, IBM Research Division. In
February 2007 he became manager of High-k/Metal-Gate
Characterization and Reliability, IBM Research. Jim has served on
technical program committees for SISC, INFOS, IRPS, ESREF,
IPFA, MIEL and other conferences, served as Chair of the
dielectrics sub-committee for the 2003 IRPS in Dallas, and is on the
IRPS management committee. He was the Technical Program Chair
for IRPS 2009 and is Vice-General Chair for IRPS 2010. He has
presented tutorials on CMOS reliability at IRPS, ESREF, MRS, and
IPFA and is an Associate Editor of the journal Microelectronics
Reliability. He is a Senior Member of IEEE and a Fellow of the
American Physical Society.
Stecher, Matthias (2F.4, 4D.1)
Matthias Stecher studied Electrical and Electronic Engineering at
the VaTech (USA) and at the Rheinisch-Westfälische Technische
Hochschule Aachen (Germany) where he received his PhD in 1995.
Between 1998 and 1994 he was involved in the development of
device and circuit simulation tools. He joined Infineon Technologies
in 1994 and has been project manager for several Smart Power
Technologies of Infineon. Since 2003 he has been involved in the
thermo-mechanical optimization of chip-package systems.
Currently, he holds the position of a technical advisor in the fields of
power technology and package development. He holds more than 20
patents and has published more than 70 papers in technical journals
and conferences.
Stellari, Franco (4E.5)
Franco Stellari received M.S. and Ph.D. degrees in electronics
engineering from the Politecnico di Milano, Italy, in 1998 and 2002
respectively. He subsequently joined IBM Watson Research Center
as a PostDoc becoming a Research Staff Member in 2004. His major
interests are the development and use of new optical methodologies
for testing VLSI circuits. He has more than 55 international
publications, 9 granted patents and several more pending. He has
won the IEEE EDS Paul Rappaport Award for the best Trans. on
Electron Devices of 2004, and two Best Paper Awards at the ESREF
conference in 2002 and 2004.
Steve, Pearton (CD.3)
Steve Pearton is Distinguished Professor and Alumni Chair of
Materials Science and Engineering at the University of Florida,
Gainesville, FL, USA. He has a Ph.D in Physics from the University
of Tasmania and was a postdoc at UC Berkeley prior to working at
AT&T Bell Laboratories from 1994-2004 . His interests are in the
electronic and optical properties of semiconductors. He is a Fellow
of the IEEE, AVS, ECS, MRS, TMS and APS.
Su, K.C. (5A.3)
K C Su received the B.S. degree (1986) and M.S. degree (1988) in
Electrical Engineering from National Cheng Kung university,
Taiwan, ROC. Then, he joined United Microelectronic Corp.
(UMC) and worked with process technology development
division for over 10 years. He is currently focusing on reliability
technology & methodology development. His main interests are
reliability engineering, device engineering and logic technology
development.
Sugawa, Shigetoshi (5F.2)
Shigetoshi Sugawa received his M.S. in 1982 in Physics from
Tokyo Institute of Technology and his Ph.D. in 1996 in
Electrical Engineering from Tohoku University. In 1982-1999
he worked in Canon Inc., where he researched high S/N ratio
solid-state imaging devices, high performance amorphous
silicon devices, high-speed low power SOI devices and high-
density liquid crystal display devices. In 1999 he moved to
Tohoku University and he is presently a professor at Graduate
School of engineering, Tohoku University. He is currently
engaged in researches on CMOS image sensors, high-
performance ULSI's and advanced displays such as high-
performance, high-speed and low-power circuits/devices, and
advanced semiconductor process technologies related to high-
quality low-temperature oxidation, nitridation, CVD and etching
process using microwave-exited high-density plasma. Dr.
Sugawa is a member of the IEEE, the Institute of Image
Information and Television Engineering of Japan.
Sugii, Nobuyuki (XT.2)
Nobuyuki Sugii received the B.S., M.S., and Ph.D. degrees in
applied chemistry from the University of Tokyo in 1986, 1988,
and 1995, respectively. He joined the Central Research
Laboratory, Hitachi, Ltd. in 1988 where he had engaged in R&D
of oxide superconducting materials and devices until 1996.
Since 1996, he has been working in CRL, Hitachi on R&D of
CMOS devices including SOI and strained-silicon MOSFETs.
Since 2004, he also serves as a visiting professor for the Tokyo
Institute of Technology. Dr. Sugii is a member of the Japan
Society of Applied Physics and the IEEE Electron Devices
Society.
Suh, Kang-Deog (5C.1)
Kang-Deog Suh was born in Gyunggi-Do, Korea, on October 2,
1956. He received the B.S. degree in electrical engineering
from Seoul National University, Seoul, Korea, and the M.S. and
Ph.D. degrees from the Korea Advanced Institute of Science and
Technology (KAIST), Daejeon, Korea, in 1979, 1981, and 1991,
respectively. He joined Samsung Electronics Company,
Gyunggi-Do, Korea, where he was engaged in the CMOS logic
IC design. Since 1991, he has been developing EEPROMs, flash
memories, and MaskROMs. From 2009, he was a professor of
information and communication engineering in SungKyunKwan
University, Gyunggi-Do, Korea.
Summerfelt, Scott (5F.3, 6C.4)
Dr. Summerfelt is DMTS in Analog Technology Development
at Texas Instruments. He has two BS degrees in 1984 from
Iowa State University (Metallurgical Engineering, double major
Physics and Mathematics) and MS and Ph.D. degree (1990)
from Cornell University in MS&E. He joined Texas
Instruments in 1990 to work on (Ba,Sr)TiO3 for DRAM and
later Pb(Zr,Ti)O3 for FRAM. His research interests are
ferroelectric materials for electronics including electrical
properties, electrode materials, processing, design rules, cell
design, ferroelectric spice models and integration issues. He is
an author of over 34 refereed, 40 proceeding publications, two
book chapters and 130 US patents
Sun, Kai (TF.1)
Kai Sun was born in Taizhou, China, in 1987. He received the
B.S. degree in microelectronics in 2009 from Soochow
University, Suzhou, China. He is currently working toward the
M.S. degree in the Department of Microelectronics. His current
research work is about Hall effect devices and sensors.
Suñé, Jordi (BD.4)
Jordi Suñé is Professor of Electronics at the Universitat Autònoma
de Barcelona (UAB) and IEEE Fellow. He has (co)authored more
than 280 papers in international journals and relevant conferences,
among which and 5 tutorials on oxide reliability at IRPS. He has
served in technical subcommittees of IRPS, IEDM, and INFOS. He
has received the the IBM Faculty award (2008) and the ICREA
ACADEMIA award (2010). His main interests are oxide reliability
physics and statistics, and the modeling of novel nanoelectronic
devices. He coordinates NANOCOMP research group at the UAB.
Sury, Charlotte (2E.3)
Charlotte Sury was born in Bordeaux, France, in 1981. She
obtained both her master degree at the University of Bordeaux and
her engineer diploma at the “Ecole Nationale Supérieure
d’Electronique, d'Informatique, et de Radiocommunication de
Bordeaux" (ENSEIRB)” in 2006. She is currently working as a PhD
student in the team “Characterisation and Reliability of microwave
technologies” in the Nanoelectronic group of the IMS Laboratory of
Bordeaux. Her thesis was supported by the DGA and takes part in
the ANR project CARDYNAL, which is centered on the parasitic
effects and the degradation mechanisms of AlGaN/GaN HEMTs
designed for microwave power applications.
Suzuki, Hiroyoshi (5F.2)
Hiroyoshi Suzuki was born in Sendai, Japan on May 16, 1986. He
received the B.S. degree in electronic engineering from Tohoku
University, Sendai, Japan in 2010. He is currently working toward
the M.S. degree in the Graduate School of Engineering, Tohoku
University.
His reserch interest is fabrication technologies of ultra low-noise
MOSFETs which have structures to suppress low-frequency noise
and Random Teregraph Signal (RTS) noise.
Tahone, Yang (5D.4)
Tahone Yang received the B.S. degree in chemistry from Fu Jan
Catholic University, Taipei, Taiwan, in 1989, and the M.S. degree in
chemistry from National Tsing-Hua University, Hsinchu, Taiwan, in
1991. In 1991, he was with FAB1, Macronix International (MXIC),
working on the start-up and manufacturing of Etching /Lithography
Department. In 1999, he transferred to Technology Development
Center. Currently, he is leading the division of advanced module
process development for nonvolatile memory devices. He has
publications and holds patents in the areas of lithography, OPC,
etching, thin film, diffusion, yield improvement and nonvolatile
memory processing.
Taiki, Uemura (3A.5)
Taiki Uemura received M. S. degrees in chemical engineering from
Yamagata University, Japan, in 2004. He joined Fujitsu Laboratories
in 2004. He is currently a staff of LSI Quality Assurance in Fujitsu
Microelectronics. He has worked on developing SER mitigation
technologies and SER evaluation methodology on LSI, CPU for
HPC and ASIC. He joined Environmental Variability Tolerant
Device Technology Program of MIRAI project in 2008.
Takashi, Hashimoto (PI.3)
Takashi Hashimoto received B.E. and M.E. degrees in applied
chemistry from Tohoku University, Sendai, Japan, in 1983 and
1985, respectively. He joined Hitachi Ltd., Tokyo, Japan, in 1985.
Since 2003, he has been working as an engineer for Renesas
Technology Corporation (present Renesas Electronics Corporation),
Ibaraki, Japan, where he is currently engaged in the research and
development of advanced MCU technology.
Takeuchi, Kan (5F.4)
Kan Takeuchi is a group manager of Renesas Technology Corp.,
after some experiences as a researcher at the Central Research
Laboratory, Hitachi, Ltd. Renesas was established in 2003,
merging two semiconductor department of Hitachi and
Mitsubishi. He is now working on the SoC reliability design
methodology at Renesas Technology Corp. He joined
Environmental Variability Tolerant Device Technology Program
of MIRAI project in 2008. He was a visiting researcher at the
Cavendish Laboratory, University of Cambridge, U. K., from
April 1990 to March 1991.
Tan, Juan Boon (5B.3)
Juan-Boon Tan received his B.Eng. with Honours in
Engineering Science (Electrical) from the University of Exeter,
UK, and Ph.D. in Opto-Electronics from the University of
Oxford, UK. He is currently the BEOL Integration Deputy
Director of Technology Development of GlobalFoundries,
Singapore.
Tanaka, Katsuhiko (5F.4)
Katsuhiko Tanaka received the B.S. and M.S. degrees in applied
mathematics from University of Tokyo, Japan, in 1984 and
1986, respectively. In 1986, he joined NEC Corp., Sagamihara,
Japan, and transferred to NEC Electronics Corp., Sagamihara,
Japan, in 2008. He has been engaged in the research of silicon
MOS devices and development of three dimensional mesh
generation system. In 2007, he joined Environmental Variability
Tolerant Device Technology Program of MIRAI project. His
research interest is in the analysis of advanced CMOS devices
through 2D/3D process and device simulations.
Tang, Zhao (3F.4)
Dr. Zhao Tang was born in Xi’an, Shaanxi, P.R. China. He
received B.S. degree in Electronics from Peking University in
2001, M.S. degree and Ph.D. degree in Electrical Engineering
from the State University of New York, University at Buffalo in
2003 and 2010, respectively. He is a student member of IEEE,
Society of Information Display (SID) and American Association
for the Advancement of Science (AAAS). His current research
interests included the thin film transistors based on amorphous
Si, polycrystalline Si, organic and amorphous oxide, thin film
solar cells and reliability issues.
Tanimoto, Hisanori (PI.1, PI.2)
Hisanori Tanimto received his Ph. D. in engineering from Osaka
University, Osaka, Japan in 1990. He gained a position at the
University of Tsukuba, Ibaraki, Japan in 1990 and is now an
Associate Professor. His main scientific interest is the properties
of nanostructured materials such as nanocrystalline metals, thin
metal films and ultrafine metal particles. Dr. Tanimoto is a
member of The Physical Society of Japan and of The Japan
Institute of Metals.
Tao, Chen (3F.3)
Tao Chen received the Bachelor of Science degree in
microelectronics from Fudan University, Shanghai in 2005. And
he got Master of Science degree (cum laude) in electrical
engineering from Delft University of Technology, Netherlands,
in April 2007. After completing his master thesis with the
Faculty of Electrical Engineering Mathematics and Computer
Science, Delft University of Technology, he continued to work
as a Phd student with Delft Institute of Microsystems and
Nanotechnology, Delft University of Technology. His research
interests include low temperature (<100oC) high performance
TFTs on flexible substrate, laser crystallization of IGZO and
location and orientation controlled single grain TFT.
Ťapajna, Milan (2E.5)
Received the M.S. and Ph.D. degrees in 2003 and 2007,
respectively, in electrical engineering form Slovak University of
Technology, Bratislava (Slovakia). In 2004, he joined Slovak
Academy of Sciences, Bratislava (Slovakia). Currently he is a post-
doctoral research assistant in the Center for Device Thermography
and Reliability (CDTR) at University of Bristol (UK). His research
interest includes electrical and optical study of advanced electronic
structures and devices, especially III-nitride and Si-based structures
with focus on defect characterization and reliability.
Tatsunori, Kaneoka (PI.3)
Tatsunori Kaneoka received the B.S. and M.S. degrees Electrical
and Electronic Engineering in from Toyohashi University of
Technology in 1985 and 1987, respectively. He joined Mitsubishi
Electric Corp. where he was engaged in the research and
development of the gate dielectrics . He is presently with RENESAS
Technology Corp. where he works on the development of the gate
dielectric and process integration for the CMOS and embedded
Flash devices.
Taylor, Bill (2B.4, 4A.4)
Bill Taylor earned a PhD in Mechanical Engineering and Materials
Science at Duke University in 1992. He then joined Motorola's
Advanced Products R&D Labs, spending 4 years in the process and
device simulation group, and 11 years on front-end materials
development. He joined Sematech in 2008, with responsibilities in
front-end integration, and electrical & physical characterization. He
has authored or co-authored over 60 papers, and holds 12 patents in
these areas
Tazzoli, Augusto (3F.2, 4F.2)
Augusto Tazzoli (IEEE Member) was born in Padova, Italy, in 1978.
He graduated in Electronics Engineering at the University of Padova
in 2003, and he received the Ph.D. degree in Electronics and
Telecommunications Engineering from the same University in 2006
working on the reliability of silicon, compound and MEMS devices.
He currently holds a post-doc position, working on the develop of
measurement systems in genre, ESD phenomena, HV systems,
compound and MEMS devices. In his career he has coauthored
about 80 papers, awarded with 3 best paper awards. He serves as
reviewer of several International Journals and in Symposia TPCs.
Teo, Zhiqiang (XT.5)
Z. Q.Teo received the B.Eng. (Hons.) degree from the School of
Electrical and Electronic Engineering, Nanyang Technological
University, Singapore, where he is currently working toward the
Ph.D. degree under a GLOBALFOUNDRIES Singapore-NTU
Graduate Research Scholarship. His research project is on the
characterization of bias-temperature instability in state-of-the-art P-
MOSFETs.
Teramoto, Akinobu (5F.2)
Akinobu Teramoto (M’02) received the B.S. and M.S. degrees in
electronic engineering from Tohoku University in 1990 and 1992,
respectively and Ph.D. in 2001 in Electrical Engineering from
Tohoku University. In 1992-2002, he worked Mitsubishi Electric
Corporation, Hyogo, Japan, where he has been engaged in the
research and development of thin silicon dioxide films. In 2002, he
moved to Tohoku University and he is presently an associate
professor at New Industry Creation Hatchery Center, Tohoku
University. He is currently engaged in an advanced semiconductor
device technologies and process technologies, such as SOI MOS
transistors, accumulation-mode transistors, variation and noise of
transistors, high-quality low-temperature oxidation, nitridation, and
CVD process using microwave-exited high-density plasma. Dr.
Teramoto is a member of the IEEE, the Electrochemical Society, the
Japan Institute of Electronics Packaging, Information and
Communication Engineers of Japan and the Japan Society of
Applied Physics.
Tessariol, Paolo (MY.5)
Paolo Tessariol received his PhD in Physics from University of
Padova, Padova, Italy in 1997. In 1998 he joined the INFM
institute, Meran, Italy. From 1999 to 2008 he has been with ST
Microelectronics Non Volatile Memory Group of Central R&D
(Agrate Brianza, Italy) working on NOR and NAND Flash
memory process development down to 45nm node. Since 2008
he is with Numonyx appointed NAND Flash memory Manager,
working in the development of high density NAND memories
with particular emphasis in Charge Trap technologies. He is
Technical Coordinator and Member of Strategic Board of EC
FP7 “GOSSAMER” project.
Tobimatsu, Hiroshi (PI.2)
Hiroshi Tobimatsu received his B.E. and M.E. in industrial
chemistry from Kyushu Institute of Technology, Fukuoka, Japan
in 1985 and 1987, respectively.
He joined Mitsubishi Electric Co., Ltd. in 1987, and then joined
Renesas Technology Corp., engaged mainly in developing
insulation and metal film deposition technology for DRAM and
logic devices. Since 2010 he has been working for Renesas
Electronics Corporation, where he is engaged in the planning of
value engineering.
Toh, Seng Oon (XT.17)
Seng Oon Toh received the B.S. degree (highest honors) in
computer engineering from the Georgia Institute of Technology,
Atlanta, in 2002. He received the M.S. degree in electrical
engineering from the University of California at Berkeley in
2008, where he continues to work towards the Ph.D. degree. His
research emphasis is on power-performance optimization as well
as robust design of nanoscale SRAM, with emphasis on dynamic
stability, RTS, and BTI. Mr. Toh was awarded an IBM Ph.D.
fellowship in 2010.
Tőkei, Zsolt (5A.1, 5A.2, 5B.4, 6A.3)
Zsolt Tőkei is program director for the advanced interconnect
program. He joined IMEC in 1999 and since then he is working
in the field of copper low-k interconnects. He obtained his M.S.
(1994) in physics from the University Kossuth in Debrecen,
Hungary. In the framework of a co-directed thesis between the
Hungarian University Kossuth and the French University Aix
Marseille-III, he earned his PhD (1997) in materials science.
From 1998 he worked at the Max-Planck Institute of Düsseldorf,
Germany, as a post-doctorate researcher. In 1999, he joined the
Interuniversity Microelectronics Center (IMEC), Belgium,
where he has worked on a range of interconnect issues such as
metallization, process development, electrical performance,
interconnect scaling and dielectric reliability. He has authored or
co-authored more than 100 publications in international
scientific journals and in international scientific proceedings.
Tomohiro, Kubo (4A.5)
Tomohiro Kubo received the B.S. and M.S. degree in physics
from Nagoya University, Nagoya, Japan in 1991 and 1993,
respectively. In 1993, he joined Fujitsu Ltd., Kawasaki, Japan,
where he was engaged in research and development of ultra
shallow junction technology. He is now mainly workings on
development of millisecond anneal technology.
Tortorelli, Innocenzo (5C.4)
Innocenzo Tortorelli, since 28-Oct-2007 with Numonyx, Via
C.Olivetti 2, 20041, Agrate Brianza (Milan), Italy. He received
the Laurea degree in Electronic Engineering in 2002 from the
Politecnico di Torino, Italy, with a thesis on smart antennas and
relative beamforming algorithms for UMTS. In 2004 he joined
Central R&D department of STMicroelectronics in Agrate Brianza
(Italy) and since then he has been working in process development
and electrical characterization of phase-change memories based on
chalcogenide materials. He has authored papers and patents on
phase-change memories.
Toshiaki, Iwamatsu (PI.3)
Toshiaki Iwamatsu received the M.S. degree from Kyushu
University, in 1989, and the Ph.D. degree from Osaka University, in
1998. In 1989, he joined the ULSI Development Center, Mitsubishi
Electric Corporation, Itami, Japan, where he has been engaged in
SOI process and device technology research. Since 2003 he has been
with the Advanced Technology Development Div., Renesas
Technology Corp., Itami, Japan. Presently, he is responsible for the
research and development of the advanced MOSFETs. He has also
been a Visiting Professor at Osaka University since 2007. Dr.
Iwamatsu is a Member of the Japan Society of Applied Physics.
Toshifumi, Mori (4A.5)
Mori Toshifumi joined Fujitsu Limited in 1989. He has been
engaged in development of advanced Si LSI processes, such as CVD
(poly-Si and WSix for gate electrode, dielectric films for side-wall
spacer, and stress control) of FEOL. His present activities are the
process development of High Performance LSI device technologies,
which are including gate dielectric formation and reliability, Si and
SiGe epitaxial films.
Tous, Santi (BD.4)
Santi Tous is a Ph. D. student in the NANOCOMP research group of
the Universitat Autònoma de Barcelona. He graduated in Physics in
1996 and in Electronic Engineering in 2008, both at the UAB.
Master in Micro and Nanoelectronics Engineering from the UAB in
2008. He’s been working towards Ph.D. on oxide reliability for
MOS gate applications since 2005. He has published several papers
on the modelling of progressive breakdown and high-K stack
insulator breakdown.
Truong, Connie (5A.5)
Connie Truong received her B. S. in Chemical Engineering from the
University of Massachusetts in 1988, her M.S. in Materials Science
from Columbia University in 1994, and her M.B.A. degree from
Marist College in 2001. She is also a PMP® certified by PMI and
IBM since 2001. Connie started working for IBM since 1988,
where she held various process engineering positions in IBM East
Fishkill Ceramic packaging manufacturing between 1988 and 1999.
In 1999, Connie took on a management assignment and
subsequently managed various manufacturing process engineering
departments in IBM System & Technology Group. In 2006, Connie
joined the IBM Semiconductor Research and Development Center
as manager of Development Manufacturing Engineering department
enabling the technology process transfer from Development to
Manufacturing FAB. Since 2007, Connie has been managing the
Unit Process Development Engineering department of IBM and
Alliance engineers focussing on developing Surface Prep, Plating,
and CMP processes for advanced CMOS technologies.
Tseng, Joshua (XT.13)
Joshua Tseng received the Ph.D. degree in materials science and
engineering from National Taiwan University, Taipei, Taiwan, in
1998. His study was focused on materials, processes and electrical
properties of BaTiO3 based dielectrics with Ni electrode. In 2000,
he joined Taiwan Semiconductor Manufacturing Company (TSMC),
Hsinchu, Taiwan as a process engineer for CVD, PVD and CMP
processes. From 2002, he moved to TSMC's R&D group for
advanced technologies related to clean, control, low k film and then
HK/MG as a technical manager. In 2007, he began his work as a
TSMC assignee to the Interuniversity Microelectronics Center
(IMEC), Leuven, Belgium, focusing on process and integration of
high-k and metal gates with Si or high mobility channel.
Tsuchiya, Ryuta (XT.2)
Ryuta Tsuchiya received the B.S., M.S., and Ph.D. degrees in
material science from the Tokyo Institute of Technology, Tokyo,
Japan, in 1993, 1995, and 1998, respectively. He joined the
Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan, in
1998, where he has been engaged in research on fabrication and
characterization of high-performance and low-power MOSFETs
including thin-film SOI and BOX transistors. Dr. Tsuchiya is a
member of the Japan Society of Applied Physics.
Tsukamoto, Yasumasa (XT.17)
Yasumasa Tsukamoto received his Ph. D. degree in Applied
Physics from Osaka University, Japan. After his graduation in
2001, he entered Mitsubishi Electric Corporation and was
transferred to Renesas Technology Corp in 2003. He has been
engaged in the research and development of the embedded
SRAM design using advanced CMOS processes. Since 2008, he
has been a visiting industrial fellow at the University of
California at Berkeley, where he is conducting research on the
variability and reliability issues on the advanced SRAM design
as well as the new device application to the SRAM memory
cells.
Tsunehisa, Sakoda (4A.5)
Tsunehisa Sakoda received the B.S. (1999) and M.S. (2001)
degrees in physical electronics from Tokyo Institute of
Technology, Tokyo, Japan. He joined Fujitsu Laboratories Ltd.
in 2001 and has been engaged in the research and development
of semiconductor technologies. His present activities are the
process development of High Performance LSI device
technologies, which are including reliability of gate dielectric in
Fujitsu Microelectronics Ltd.He is a member of the Japan
Society of Applied Physics.
Tuyoshi, Arigane (PI.3)
Tsuyoshi Arigane was born in Ibaraki, Japan, on July 30, 1971.
He received the B.E, M.E., and D.E. degrees in 1995, 1997, and
2000, respectively, from the University of Tohoku, Miyagi,
Japan. In 2000, he joined Hitachi Ltd., Tokyo, Japan, where he
has been engaged in the research and development of non-
volatile memory and high-k MOSFETs.
Udayakumar, K.R. (6C.4)
K. R. Udayakumar earned his Ph.D. in Solid State Science from
Pennsylvania State University. He joined TI in 1995 where he
was involved in the development of monolithic un-cooled
infrared detectors for TI’s Defense Systems & Electronics
Group. From 2000, he has been working on process integration
of embedded ferroelectric memories. Udayakumar has
published extensively in the area of energetics of point defects in
alkaline earth titanates through atomistic simulation,
thermodynamic phenomenology of perovskites, piezoelectrics
for MEMS, pyroelectric detectors, and FRAMs. His other
interests are in comparative literature and political science.
Uemura, Taiki (5F.4)
Taiki Uemura received M. S. degrees in chemical engineering
from Yamagata University, Japan, in 2004. He joined Fujitsu
Laboratories in 2004. He is currently a staff of LSI Quality
Assurance in Fujitsu Microelectronics. He has worked on
developing SER mitigation technologies and SER evaluation
methodology on LSI, CPU for HPC and ASIC. He joined
Environmental Variability Tolerant Device Technology Program
of MIRAI project in 2008.
Uznanski, Slawosz (4B.4)
Slawosz Uznanski received the Engineer Degree and the M.Sc.
degree in microelectronics from Technical University of Lodz,
Poland, and from University of Nantes, France, both in 2008. He
is currently working towards the Ph.D. degree at
STMicroelectronics Crolles, France, and the Institute of Materials,
Microelectronics and Nanosciences of Provence, Marseille, France.
His research interests include modeling of Single Event Effects in
commercial ultra-deep sub-micrometer CMOS technologies in
terrestrial and space environments.
Van den bosch, Geert (6C.1)
Geert Van den bosch received the M. Sc. (1987) and Ph. D. (1993)
in applied sciences from the Katholieke Universiteit Leuven,
Belgium. He is with imec in Leuven since 1987. As a Senior
Researcher, he has made contributions to the fields of hot-carrier
degradation, plasma and process induced damage in ultrathin oxides,
back end - front end of line interaction, and smart power devices.
Since 2007 his activity moved to charge trap Flash memory. He has
(co-)authored more than 80 international journal publications and
conference contributions, and served as program committee member
of P2ID, ICICDT, and IRPS.
van Dijk, Kitty (2D.2)
Kitty van Dijk received her MSc (1992) and PhD (1997) degree in
Solid State Physics from the Technical University of Delft, and from
the University of Nijmegen, respectively, both in The Netherlands.
In 1998 she joined the Research and Development group of ASMI at
IMEC in Leuven, Belgium, working on gate-oxide quality. In 2000
she moved to NXP (former Philips) Semiconductors in Nijmegen,
where she started in non-volatile memory reliability, eventually
broadening to process and product reliability in general. She now
works on the interaction between process and product reliability,
with a focus to Automotive and extreme mission profile
qualifications.
Van Houdt, Jan (6C.2)
Jan Van Houdt received a Ph.D. from the Katholieke Universiteit
Leuven in 1994. During his PhD work, he invented the HIMOS™
Flash memory, which he transferred to several industrial production
lines. In 1999 he became responsible for Flash memory at IMEC
and as such was the driving force behind the expansion of IMEC's
memory program. Today he is IMEC's Memory Device Design
Group Manager and Flash Memory Program Manager. He has
published more than 160 papers in international journals (incl. 2
book chapters) and accumulated more than 140 conference
contributions (incl. about 30 invited papers and panel contributions).
He has filed about 50 patent applications and served on the program
committees of 10 major conferences.
Van Hove, Marleen (2E.4)
Marleen Van Hove obtained her degree in Physics from the Catholic
University of Louvain in 1980. She continued research at the
Institute of Nuclear and Radiation Physics group at the Physics
Department of the same university and obtained her PhD in 1985.
After this, she joined imec, Leuven, Belgium. She specialised in
GaAs and InP III-V processing in the period between 1986 and
1997. Afterwards she was responsible for CMOS back-end
integration in imec. At the end 2006 she returned to compound
semiconductor research, being responsible for the development of
high-power GaN switching devices.
Vandelli, Luca (6C.1)
Vandelli Luca was born in Reggio Emilia, Italy, in 1985. He
received the Master degree in electronic engineering from the
University of Modena and Reggio Emilia Italy, in 2009. Since 2010,
he has been pursuing the Ph.D. degree at the Department of
Engineering Sciences and Methods of the University of Modena and
Reggio Emilia. His work focuses on modeling and characterization
of thin gate oxides in nonvolatile memory devices and MOS
transistors.
Vandevelde, Bart (6A.3)
Bart Vandevelde received his Masters degree in mechanical
engineering from the Catholic University of Leuven (Belgium)
in June 1994. In March 2002, he received a PhD degree at imec
in the field of thermo-mechanical modeling for electronic
systems. Currently, he is team leader for the packaging
reliability activities at imec and internal project coordinator for
several Flemish and European projects. He is co-founder and
member of the organisation committee for the Eurosime
conference. Dr. Vandevelde is author and co-author of about
100 publications in international conferences and journals.
Vayshenker, Alex (4A.3)
Alex Vayshenker received masters degree in opto-electronic
engineering from Moscow Institute of Geodesy (1972 - 1978).
He worked as an engineer in Moscow State Optical Enterprise
qualifying hybrid opto-electronic components (1978 - 1981). He
joined IBM Technology group in 1984 and held several
engineering positions in the fields of Quality and Reliability of
semiconductor components/technology. Most recently he
worked on reliability of ultra-thin gate dielectrics. He co-
authored several papers on this subject.
Veksler, Dmitry (2B.4, 4F.4)
Dmitry Veksler received his B.S. in 1996 and M.S. in 1998 from
Nizhniy Novgorod State University and Ph.D. in Physics in
2007 from Rensselaer Polytechnic Institute, Troy, NY. From
1998 till 2003 he was with Institute for Physics of
Microstructures, Nizhniy Novgorod (Russian Academy of
Sciences) investigating optical and transport phenomena in low-
dimensional semiconductor hetero structures. During 2003-2008
he was with Rensselaer Polytechnic Institute working on plasma
wave electronics for THz spectroscopy and imaging
applications. In 2009 he joined SEMATECH Inc., Albany, NY.
His current research focus is on characterization/reliability of
high-k and alternative substrate MOSFETs.
Velamala, Jyothi Bhaskarr (5E.2)
Jyothi Bhaskarr Velamala received his Bachelor of Technology
degree in Electronics and Communications Engineering from
Indian Institute of Technology (IIT), Guwahati, India in 2008.
He is currently working towards his Masters degree in Arizona
State University. His research interests include reliability effects
in scaled CMOS technology and circuits; design and test
solutions for resilience.
Ventrice, Domenico (6C.2)
Domenico Ventrice was born in Italy in 1979. He received the
Laurea degree in electrical engineering from the Politecnico di
Milano, Italy, in 2006. He is currently working as a process
development engineer at Numonyx R&D. His research interests
include the modeling of electrical and phase-change properties
in PCM devices.
Vereecke, Bart (5B.4)
Bart Vereecke received a Ph. D. degree in nuclear particle
physics in 2001 at the Catholic University of Leuven, Belgium.
In 2002, he started working in a development aid project as
computer advisor for the Zambian ministry of education. In
2007, he joined IMEC, Leuven, where he works on the
development of Cu/low-k integration projects.
Vermunt, Frank (SE.1)
Frank Vermunt received his B.Sc. degree in computer
technology in 1987 at the ‘Hogere Technische School’ in Venlo.
In 1989 he joined AT&T in Hilversum, and in 1996 Philips in
Eindhoven, both in The Netherlands. Since November 1999 he
is with NXP Semiconductors, which is a former division of
Philips. Frank is currently working as a system architect at Car
Entertainment’s development department for Car DSPs, where his
focus is on system infrastructure for next generation software
defined analogue and digital radios. He has a special interest in
assessing and addressing the perceived impact of SER for (end-
)users.
Verzellesi, Giovanni (4F.4)
Giovanni Verzellesi, “Laurea” degree from the Univ. of Bologna,
Italy, in 1989, PhD in Electrical Engineering from the Univ. of
Padova, Italy, in 1994, Full Professor of Electronics with the Univ.
of Modena and Reggio Emilia, Italy, since 2006. His research
activity has dealt with: (i) impact-ionization effects in silicon BJTs;
(ii) silicon optical, chemical, and ionizing radiation sensors; (iii)
compound-semiconductor FETs. He has coauthored more than 130
papers in international journals and conference proceedings. He is,
or has been, member of the technical program committee of IEDM,
IRPS, ESREF. He is member of the steering committee of
HETECH. He is Senior Member of the IEEE.
Vincent, Huard (2A.4, 2B.2, 5E.3)
Vincent Huard received the B.S. (1996) in physics and the M.S.
(1997) in electrical engineering from the Institut National
Polytechnique de Grenoble (INPG). He worked for the CEA-
Grenoble on the MBE growth of II-VI based doped heterostructures
and their magneto-optical and electrical characterizations. He
received his Ph.D. (2000) in physics from the university of
Grenoble. In 2000 and 2001, he was a Visiting Scholar at the
University of California, where he worked on devices made of
ferromagnetic materials on top of semiconductors. In 2002, he
joined Philips Semiconductors as a reliability engineer, working on
oxide and device reliability. Since 2007, he is at STMicroelectronics
as Design-in Reliability project leader, working on device and
circuit reliability modeling and product qualification tests. His
current research interests include NBTI and hot carrier degradation
both at wafer and product levels as well as Design for reliability. He
authored and co-authored more than 70 regular papers, several
invited papers and is IRPS 2009 Circuit Reliability Chairman.
Visalli, Domenica (2E.4)
Domenica Visalli obtained her degree in Electronic Engineering
from the University of Messina in Italy in 2006. She joined imec in
2005 where she worked on the development of a new methodology
for the characterization of advanced Cu/low k interconnects.
Afterwards, in 2007, she started the PhD program at the Catholic
University of Leuven and she joined the group of GaN in imec. She
is currently working on the simulation and characterization of GaN-
based devices for power switching applications.
Visconti, Angelo (4B.3, 5C.2)
Angelo Visconti (M’07) received the Laurea degree in physics (cum
laude) from the University of Milano, in 1997. The same year he
joined the Non-Volatile Memory Process Development Group,
R&D department of STMicroelectronics (now Numonyx), Agrate
Brianza, Italy. Since that, he has been involved in the developments
of ten-generations of Flash Memory Process. His current research
interests include reliability, radiation effects, and multilevel
applications of Flash cells. He is co-author of more than 100
scientific publications and 14 patents. He is a Lecturer on NVM
Reliability and Radiation Effects on Flash Memory with the
University of Padova and Politecnico di Milano. Since 2005, he has
been the ST-rapresentative, and chair from 2009, within the JEDEC
14.3 task-group on NVM reliability. Finally, he was member of the
IEDM-CIR committee, IRPS-PIR committee, IRPS-Memory
committee and co-chair in 2010. Mr. Visconti won the IRPS 2008
“Outstanding Paper Award” and the JEDEC 2010 Team Award.
Volf, Paul (2D.2)
Paul A. J. Volf (M’93) received his MSc degree in 1994, and his
PhD degree in 2002 for his research work on data compression, both
in electrical engineering from the Eindhoven University of
Technology, The Netherlands. In 2000 he joined Philips
Semiconductors, now NXP Semiconductors, where he started as
DfM-engineer, followed by product engineering positions in
operations and in the automotive business line. Currently he
holds a product engineering position in the central department
for process development and foundry interfacing. His activities
cover the process and product qualifications and product
introductions in internal specialty processes and advanced
CMOS foundry processes.
Wang, Li (6C.4)
Li Wang received her Ph. D. in physics from the Colorado
School of Mines. She joined Texas Instruments in 1997 and is
currently working as a product engineer in the Analog
Technology Development group. Her interests are in the area of
FeRAM functional and reliability testing and product yield
improvement.
Wang, Miaomiao (XT.14)
Miaomiao Wang Received her B.S. in Electrical Enginnering
from Peking University, China in 2003, and M.S. and Ph.D.
degrees in the same discipline from Yale University in 2005 and
2008 respectively. She is Currently a Research Staff Member at
IBM Research @Albany Nanotech, Albany, NY. She is working
on Electrical Characterization and Reliability for a variety of
high-k metal gate MOS devices including SOI, FINFET,
ETSOI and etc.
Wang, Mingxiang (TF.1)
Mingxiang Wang (M’07) received the B.S. degree in Physics
and Ph.D. degree in Condensed Matter Physics from Nanjing
University, Nanjing, China, in 1993 and 1998, respectively.
From 1998 to 2001, he was a Postdoctoral Research Associate
with the Department of Electrical and Electronic Engineering,
the Hong Kong University of Science and Technology, Hong
Kong. Afterwards, he joined Semiconductor Manufacturing
International Corporation (Shanghai), as a member of technical
staff in process reliability engineering. Currently he is with the
Department of Microelectronics, Soochow University, Suzhou,
China. His research interests include thin-film materials and
devices, semiconductor device physics and device reliability.
Wang, Szu-Yu (5D.2, MY.1)
Szu-Yu Wang was born in Kauhsiung, Taiwan in 1974. He
received his B.S and M.S degrees in material science and
engineering from National Tsing-Hua University (NTHU) in
1996 and 1998, respectively. Now he is pursuing his Ph.D
degree in electronic engineering in National Tsing-Hua
University (NTHU). In 2000, he joined Technology
Development Center in Macronix International. Co. Ltd., where
his current work is focused on dielectric characterizations in
nitride trapping Flash Memories.
Wang, Tahui (MY.3)
Tahui Wang (S'84-M'85-SM'94) was born in Taoyuan, Taiwan,
R.O.C., on May 3, 1958. He received the B.S.E.E. degree from
National Taiwan University, Taipei, Taiwan, in 1980, and the
Ph.D. degree in electrical engineering from the University of
Illinois at Urbana–Champaign, Urbana, in 1985. From 1985 to
1987, he was with Hewlett-Packard Laboratories, Palo Alto, CA,
where he was engaged in the development of GaAs HEMT
devices and circuits. Since 1987, he has been with the
Department of Electronics Engineering, National Chiao-Tung
University, Hsinchu, Taiwan, where he is currently a Professor.
His research interests include hot-carrier phenomena
characterization and reliability physics in very large scale
integration (VLSI) devices, RF CMOS devices, and nonvolatile
semiconductor devices. Dr. Wang was given the Best Teacher
Award by Taiwan’s Ministry of Education. He has served as
technical committee member of many international conferences,
among them International Electron Devices Meeting, International
Reliability Physics Symposium, and VLSI Technology, Systems,
and Applications.
Wang, Zhongrui (MY.4)
Wang Zhongrui received his B.Eng in Electrical and Electronics
Engineering (EEE) from Nanyang Technological University (NTU)
Singapore in 2009. He is currently pursuing his PhD degree in EEE,
NTU working on metal oxide based resistive random access
memory device simulation and characterization.
Warren, Kevin (4B.2, SE.3)
Kevin Warren received the B.S. degree in Chemistry from
Tennessee Technological University in 1994 and his M.S. in
Chemistry at Vanderbilt University in 1997. He received his M.S. in
Electrical Engineering from Vanderbilt University in 1999. From
1998-2000 he worked for Raytheon ITSS as a contractor at the
Marshall Space Flight Center where he supported the component
group as a radiation effects engineer for the International Space
Station and the Space Shuttle Programs. From 2000-2003 he worked
at the Johns Hopkins University Applied Physics Laboratories as a
specialist in the testing and qualification of electronic parts. In 2003,
he joined the Institute for Space and Defense Electronics where he
has focused on modeling the soft error response of microelectronics
for terrestrial and space applications.
Watabe, Shunichi (5F.2)
Shunichi Watabe was born in Japan, on September 9, 1982. He
received the M.S. degree and Ph. D. degree in the Graduate School
of Engineering, Tohoku University, Sendai, Japan in 2007 and 2010,
respectively.
His research interests are the variability of characteristics in
MOSFETs and the development of device and fabrication processes
to suppress the variability.
Wei, Jun (5B.3)
Jun Wei received the Ph.D. degree from Tsinghua University in
Materials Science and Engineering. He is currently a Group
Manager and Senior Scientist at Singapore Institute of
Manufacturing Technology. Currently, he is working on
microsystems and nanosystems fabrication and packaging, low
temperature wafer/substrate bonding, advanced interconnection
materials, packaging for electronics and optoelectronics,
nanofabrication, nanocomposites as well as advanced
characterization techniques. He is serving several international
conference committees. He has published more than 250 technical
papers in the areas of micro/nano-interconnection, electronics,
nanotechnology, microsystems and nanosystems and solid oxide
fuel oxide, and currently holds 30 patents and technology
disclosures.
Weller, Robert (4B.2, SE.3)
Robert A. Weller received his Ph.D. in physics from Caltech in
1978, and is now a Professor of Electrical Engineering at Vanderbilt
University. His research interests include the computational analysis
of radiation effects in electronics, device physics, radiation effects in
materials, and applications of the techniques of nuclear physics.
Wen, Shi-Jie (SE.3, SE.5)
Shi-Jie Wen received his Ph.D in Material Engineering from
University of Bordeaux I in 1993. He joined Cisco Systems Inc.,
San Jose, CA in 2004, where he has been engaged in IC component
technology reliability assurance. His main interest is in silicon
technology reliability, such as SEU, WLR, and complex failure
analysis, etc. He is a member of DFR, SEU core teams in Cisco.
Before Cisco, he worked in Cypress Semiconductor where he was
involved in the area of product reliability qualification with
technology in 0.35u, 0.25u, 0.18u, 0.13u and 90nm.
Wen, Yong-Ru (EL.6)
Yong-Ru Wen received the B.S. degree from the Department of
Mechenical Engineering, National Chiao-Tung University,
Hsinchu, Taiwan, R.O.C., in 2007, and the M.S. degree from the
Institute of Electronics, National Chiao-Tung University,
Hsinchu, Taiwan, R.O.C., in 2009. He is currently with military
service in the Chinese Army.
Wen Hu, Liu (4A.1, BD.2)
LIU WENHU was born in Shandong, China in 1986. He
received his B.Eng, 1st Class Honors (Electrical and Electronics
Engineering) from Nanyang Technological University (NTU) in
2008. He is currently pursuing his Ph.D. at the Division of
Microelectronics, School of Electrical and Electronic
Engineering in NTU. His project is focusing on electrical
characterization and reliability of novel high-κ gate dielectrics in
nano-scale MOSFETs. He is currently a Graduate Student
Member of IEEE (2008-present).
Werner, Christoph (CR.2)
Christoph Werner received the Ph.D. degree from Technical
Unversity Munich in 1980. From 1980 until 2007 he was with
Siemens/Infineon working in research and development of
advanced CMOS devices and processes and circuits. Since 2007
he has been with Technical University Munich as a senior
scientific consultant. He has published more than 50 scientific
papers and has filed 20 patent applications. His current research
include Low Power digital CMOS systems, CMOS long term
degradation effects as well as future device concepts beyond
CMOS.
Wie, Chu-Ryang (3F.4)
Chu Ryang Wie received Ph.D. degree in Applied Physics from
Caltech in 1985. Ever since, he was Professor of Electrical
Engineering at State University of New York at Buffalo. His
research was on developing analysis methods of III-V
heterostructures such as strained buried quantum wells and
barriers and lattice-mismatched structures and the strain
relaxation, by high resolution x-ray diffraction techniques; and
on the effects of lattice strain and relaxation on the device
characteristics such as strained resonant tunneling diodes, laser
diodes and p-n junctions. Recently, he is interested in thin film
device and reliability physics He also developed “The
Semiconductor Applet Service” website during 1996-2000
period for semiconductor education.
Wilde, Markus (4C.1)
Obtained master and doctoral degrees in Physical Chemistry
from the University of Bochum, Germany, and is currently
Associate Professor at the Institute of Industrial Science,
University of Tokyo (Japan). He investigates the reactive
behavior of hydrogen (H) on surfaces, in shallow surface-bulk
transition regions and at thin film interfaces, combining surface
science techniques with quantitative high-resolution H depth
profiling by nuclear reaction analysis (NRA). Current research
focuses on H-absorption and surface/subsurface H exchange at
transition metal single crystals and nanoparticles. Other interests
include H impurities at MOS electrode/dielectric interfaces,
surface hydroxylation and hydrophilicity of oxides, and
semiconductor H-passivation.
Wilson, Christopher J. (5B.4, 6A.3)
Christopher J. Wilson (S’07) received the M.Eng. degree (first
class honors) in Electronics and Ph.D. degree in interconnect
reliability and mechanical stress in thin films from Newcastle
University, Newcastle upon Tyne, U.K. in 2006 and 2009
respectively. Between 2007 and 2008 he spent 16 months as Marie
Curie APROTHIN Fellow and Visiting Scholar in the Advanced
Interconnect Program at the Interuniversitair Micro-Elektronica
Centrum (IMEC). He was an Institution of Electrical Engineers
Robinson Research Scholar and held an Institution of Electrical and
Electronic Engineers Reliability Society Scholarship. Dr. Wilson is
now the International Mobility Post-Doctoral Fellow in IMEC's
Interconnect Process Technology unit, where he is working on
advanced metallization integration and reliability.
Wise, Rick (HV.1)
Received the B.S. degree in chemical engineering from the
University of Arkansas, Fayetteville and the M.S. and Ph.D. degrees
in engineering and applied science from Southern Methodist
University, Dallas, Texas. He joined Texas Instruments (TI)
Incorporated, Dallas, as a process engineer in 1983. He has worked
on the development of semiconductor device fabrication front-end
processes utilizing his expertise in CVD and silicon materials. He
currently works on external research & consortia projects for the
Analog Technology Development group. He was elected Texas
Instruments Fellow in 1998.
Witulski, Arthur (3A.2)
Arthur F. Witulski received the Ph.D. degree in electrical
engineering from the University of Colorado, Boulder in 1988. He
has worked in analog electronics, power electronics, and
microelectronics in industry and academia. He has held positions as
design engineer at Storage Technology in Colorado, Associate
Professor at the University of Arizona, and currently as Senior
Research Engineer at the Institute for Space and Defense Electronics
at Vanderbilt University, where he also holds an appointment as
Research Associate Professor. His technical interests include single
event radiation effects in sub-100 nm CMOS technologies, as well
as power devices and power electronics
Wong, H.-S. Philip (2C.5)
H.-S. Philip Wong joined Stanford University as Professor of
Electrical Engineering in September, 2004. From 1988 to 2004, he
was with the IBM T.J. Watson Research Center. He held various
positions from Research Staff Member to Manager, and Senior
Manager. While he was Senior Manager, he had the responsibility of
shaping and executing IBM’s strategy on nanoscale science and
technology as well as exploratory silicon devices and semiconductor
technology. His present research covers a broad range of topics
including carbon nanotubes, semiconductor nanowires, self-
assembly, exploratory logic devices, nanoelectromechanical relays,
device modeling, and novel memory devices such as phase change
memory and metal oxide resistance change memory. He is a Fellow
of the IEEE and served on the Electron Devices Society AdCom as
elected member (2001 – 2006). He served as the Editor-in-Chief of
the IEEE Transactions on Nanotechnology in 2005 – 2006, sub-
committee Chair of the ISSCC (2003 – 2004), General Chair of the
IEDM (2007), and is currently a member of the Executive
Committee of the Symposia of VLSI Technology and Circuits (2007
– 2009). He received the B.Sc. (Hons.), M.S., and Ph.D. from the
University of Hong Kong, Stony Brook University, and Lehigh
University, respectively.
Wong, Richard (SE.3, SE.5)
Richard Wong received his M.S. degree in electrical engineering
from Santa Clara University in 1988 and his B.S. degree in chemical
engineering from UC Berkeley in 1982. He joined Cisco Systems
Inc., San Jose, CA in 2006. He is engaged in IC component
technology reliability assurance in issues such as SEU, ESD, WLR,
failure analysis and reliability modeling. Prior to Cisco, he had
worked on ASICs, FPGAs, TCAMs and memories.
Woo, Seung-Han (RM.3)
Seung-Han Woo was born in Seoul, Korea, in 1983. He received
the B. S. degree in the electrical and electronic engineering from
Yonsei University, Seoul, Korea, in 2009. He is studying for M.
S degree in Yonsei University. His current research interests is
process variation tolerant circuit design.
Wouters, Yves (IC.8)
Yves Wouters is Professor of chemistry at the University of
Grenoble (France). After a PhD from the Grenoble Institute of
Technology, he joined the technical centre of Juelich (Germany)
in 1996 in the team of Dr W.J. Quaddakers. In 2000 Yves
Wouters joined the SIMaP (the Materials and Processes Science
and Engineering Laboratory). His main research topic concerns
the preparation, forming, assembly and properties of materials
for structural and functional applications and in particular the
durability of metallic materials (energy, microelectronics, etc.).
Wrachien, Nicola (3F.2, 4F.5)
Nicola Wrachien was born in Treviso, Italy, in 1982. He
received the degree (magna cum laude) in electronic engineering
in 2006 from the University of Padova, Italy, and the PhD in
Information Engineering in 2010, working on advanced non-
volatile memories. He currently holds a post-doc position
working on organic semiconductor devices and on III-V
MOSFETs.
Wu, Ernest (BD.4)
Ernest Y. Wu is a senior technical staff member in Technology
Reliability Department at Semiconductor Research and
Development Center (SRDC) in IBM Microelectronics Division
in IBM System and Technology Group. He received M.S. and
Ph.D. degrees in physics from University of Kansas in 1986 and
1989, respectively. Dr. Wu joined IBM Microelectronics
Division in 1994 at Essex Junction, Vermont after transferring
from IBM Rochester, Minnesota.
Wu, Kenneth (2F.3)
Dr. Kenneth Wu is the Director of Technology Quality &
Reliability at Taiwan Semiconductor Manufacturing Company
(TSMC), responsible for technology reliability characterization
and qualification. Prior to join TSMC in 2002, Dr. Wu worked
at Intel Corporation since 1982 in technology development and
reliability qualification. Dr. Wu has published more than 50
papers on a variety of technology and reliability subjects; and
received IRPS The Best Paper Award in 1990. Dr. Wu received
his B.S from National Taiwan University in 1975, an M.S. from
Northwestern University in 1978 and his Ph.D. from Princeton
University in 1982; all are in Electrical Engineering.
Wu, Ling (MY.4)
Wu Ling received his B.Eng in Electrical and Electronics
Engineering (EEE) from Nanyang Technological University
(NTU) Singapore in 2008. He is currently pursuing his PhD
degree in EEE, NTU working on High-k/Metal gate of advanced
gate stacks.
Wu, Ming-Tsung (MY.1)
Ming-Tsung Wu was born in Hualien, Taiwan in 1977. He
received the M.S. degree in Institute of Environmental
Engineering & Science from Feng Chia University (FCU),
Taiwan, R.O.C., in 2002. He is currently a project manager of
Etch Process Development Department in Technology
Development Center in Macronix International (MXIC).
Wu, Mong Sheng (FA.1, FA.3)
M.S. Wu, born in Chia-yi in 1982, is a engineer in UMC
Corporation. Wu received a bachelor degree from National
Tsing Hua University in Taiwan. Now, he has been a FA
engineer for 4 years.
Wu, Xing (4A.1, BD.2)
Xing Wu was born in Xi’an, China in 1984. She received the B.E.
degree in Electronic Science and Technology in 2008 from Xi’an
Jiaotong University, People’s Republic of China. She was an
international exchange student at Osaka University from 2006 to
2007. She is currently pursuing her Ph.D. degree at the Division of
Microelectronics, School of Electrical and Electronic Engineering,
Nanyang Technological University (NTU), Singapore. Her current
research interests include reliability study of novel high-κ dielectric
materials in nanodevices using atomistic simulations and
transmission electron microscopy (TEM) analysis. She is currently a
graduate student member of the IEEE (2008-present).
Xiang, Li (4A.1, BD.2)
Xiang Li received his B.Eng in Electrical and Electronics
Engineering (EEE) from Nanyang Technological University (NTU),
Singapore in 2005. He is currently pursuing his PhD degree in EEE,
NTU working on failure analysis of advanced gate stacks. His
research interests include front-end device reliability and nano-scale
characterization using transmission electron microscopy (TEM) and
electron energy loss spectroscopy (EELS). Since 2006, he has been
a student member of IEEE.
Xu, Chen (FA.5)
Dr. Chen Xu is a reliability engineer with Alcatel-Lucent Reliability
Enginerring Department. He has extensive experience in the fields
of semiconductor and electronic packaging, electronic
manufacturing, surface finishes and coatings, failure mode analysis
and reliability assessment. Chen Xu received his BS Degree in
Chemistry from Tongji University in Shanghai, China and his Ph.D.
in Physical Chemistry from Ruhr-University Bochum, Germany.
Prior to joining Alcatel-Lucent, he was a Senior Scientist with
Enthone, Cookson Electroncis. Dr. Xu’s career also includes the
position of project leader/MTS with Lucent Technologies and R&D
positions at Hoechst Research and Technology Center.
Yamamoto, Hirohiko (PI.1, PI.2)
Hirohiko Yamamoto received his B.E. in industrial chemistry from
Kumamoto University, Kumamoto, Japan in 1981. He joined
Hitachi Microcomputer Engineering, Ltd. (now Hitachi ULSI
systems, Co., Ltd.), Tokyo, Japan in 1981, where he worked on
developing and improving CVD technology for mass production. He
then worked at Trecenti Technologies, Inc., Ibaraki, Japan from
2000 to 2004. Since 2005, he has been working at the Naka Sector
of Renesas Technology Corp. (now Renesas Electronics
Corporation), Ibaraki, Japan. He is a chief engineer of the Wafer
Process Manufacturing Technology Dept. 2.
Yamauchi, Toyohiko (FA.4)
Mr. Yamauchi graduated with Bachelor's and Master's degrees in
Engineering from the University of Tokyo in 2002 and 2004,
respectively. He has been working at Hamamatsu Photonics K.K.
(Japan) since 2004 as a researcher in the central research group. He
has also been a visiting researcher for a collaborative study at the
MIT Spectroscopy Laboratory since 2008. He is engaged in research
on biomedical sensing with interference optics.
Yang, Ling-Wu (MY.1)
Ling-Wu Yang received the M.S. degrees in material science and
engineering from the University of National Sun Yat-Sen, Taiwan,
R.O.C., in 1996. From 1996 to 1999, he joined Vanguard
International Semiconductor Co., Ltd, Hsinchu, Taiwan, R.O.C., as
a process engineer. In 2000, he joined Macronix International
(MXIC) for advanced diffusion module development. He is
currently a Project Deputy Director of Advanced Module Process
Development Division in Technology Development Center.
Yang, Tahone (MY.1)
Tahone Yang received the B.S. degree in chemistry from Fu Jan
Catholic University, Taipei, Taiwan, in 1989, and the M.S.
degree in chemistry from National Tsing-Hua University,
Hsinchu, Taiwan, in 1991. In 1991, he was with FAB1,
Macronix International (MXIC), working on the start-up and
manufacturing of Etching /Lithography Department. In 1999, he
transferred to Technology Development Center. Currently, he is
leading the division of advanced module process development
for nonvolatile memory devices. He has publications and holds
patents in the areas of lithography, OPC, etching, thin film,
diffusion, yield improvement and nonvolatile memory
processing.
Yang, Yang (EL.3)
Yang Yang received the B.Sc. (2004) in electrical engineering
from Beijing University of Aeronautics and Astronautics,
Beijing, China and the M.Sc. (2005) in electronics from Queen’s
University Belfast, Belfast, UK. He is currently a Ph.D. student
at George Mason University, VA, USA. His research focuses on
the design & optimization of field-effect-diode (FED) and ESD-
like stress on the gate dielectric reliability of nano CMOS. From
Jan. 2009 to Dec. 2009, he was at IBM Microelectronics-System
and Technology Group, SRDC, on a student internship in
ESD/Latchup Development Group.
Yasuda, Naoki (MY.2)
Naoki Yasuda received the B.S., M.S., and Ph.D. degrees in
electronic engineering from Osaka University, Japan. He joined
Toshiba Corporation in 1992, where he was engaged in the
research on SiO2 in Si MOSFETs. From 1998 to 1999, he was a
visiting scientist at Rutgers University, NJ, where he studied the
stabilities of high-k dielectrics. When he returned to Toshiba, he
was engaged in silicon oxynitride in CMOS devices. From 2001
to 2004, he worked for MIRAI Project, Tsukuba, Japan, as a
researcher in High-k Gate Stack Group. Since 2005, he has been
working in the area of non-volatile memories.
Yasuhiro, Shimamoto (PI.3)
Yasuhiro Shimamoto received the Ph.D. degrees in physical
engineering from The University of Tokyo, Tokyo, Japan, in
1996. He joined the Central Research Laboratory, Hitachi Ltd.,
Tokyo, in 1996, where he was engaged in the development of
FeRAM, DRAM capacitors and high-k gate dielectrics. From
2002 to 2004, he was an Industrial resident in the Interuniversity
Microelectronics Center (IMEC), Leuven, Belgium, where he
studied on high-k gate dielectrics and metal gate. He is currently
working on reliability of gate dielectrics for non-volatile
memory.
Yasuo, Nara (4A.5)
Yasuo Nara received the B.S. (1980), M.S. (1982), and Ph.D
(1985) degrees in physical electronics from Tokyo Institute of
Technology, Tokyo, Japan. He joined Fujitsu Laboratories Ltd.
in 1985 and has been engaged in the research and development
of Si-based semiconductor technologies. He is currently in
charge of advanced Si LSI technology development in Fujitsu
Microelectronics Ltd. He is the author or coauthor of more than
270 journals and international conference papers in the field of
semiconductor research. Dr. Nara is a member of the Japan
Society of Applied Physics, the Institute of Electronics,
Information and Communication Engineers, and IEEE Electron
Devices Society.
Yau, Anthony (2D.2)
Anthony Yau received the B.E. in Material from Cheng Kung
University, Tainan, Taiwan. He has joined Taiwan
Semiconductors Manufacturing Company on product reliability
engineering since 2000.
Ye, Chen (3C.5)
Chen Ye is an Engineer in Quality Reliability Assurance Failure
Analysis at Global Foundries of Singapore. She received his
bachelors in Materials Engineering from Nanyang Technological
University,Singapore.
Yeh, Teng-Hao (5D.3)
Teng-Hao Yeh was born in I-Lan, Taiwan, ROC., on January 8,
1981. He recieved the BS and MS degree in Material Science and
Engineering from National Tsing Hau University, Hsinchu, Taiwan,
in 2003 and 2005. He joined Macronix International Company, Ltd.,
Hsinchu, in 2006, as a Process Integration Engineer in technology
development center. Since 2006, he has been engaged in the
development and integration for the nitride-based NBit technology
at Macronix.
Yeo, Yee-Chia (XT.4)
Y.-C. Yeo received the B. Eng and M. Eng degrees from National
University of Singapore (NUS), and the M.S. and Ph.D degrees
from UC Berkeley, all in Electrical Engineering. He was with
TSMC in 2001-2003. He is now an Assistant Professor of Electrical
and Computer Engineering at NUS and a Program Manager for a
nanoelectronics research program at the Agency for Science,
Technology, and Research, Singapore. His research interests
include strained-silicon MOSFETs, compound semiconductor
transistors, and transistors with steep subthreshold swing. He co-
authored ~330 papers, and has 82 US Patents.
Yew, Kwang Sing (4A.4)
K. S. Yew received the B.Eng. (Hons) degree in electrical and
electronics engineering from the University of Technology,
Malaysia (UTM) in 2007. From 2007 to 2009, he was with Altera
Corporation, Penang, Malaysia as a Backend Device Modeling
Engineer. He is currently working toward the Ph.D. degree in high-к
gate stacks electrical characterization by scanning probe microscopy
at Nanyang Technological University (NTU) at Singapore.
Yiang, Kok-Yong (2D.3, 5A.4)
Kok-Yong Yiang received his Ph.D in Electrical Engineering from
the National University of Singapore. He joined Advanced Micro
Devices (Sunnyvale CA) in 2005 as a BEOL reliability engineer,
and is currently with GLOBALFOUNDRIES (Sunnyvale CA) as a
Member of Technical Staff. His main interest is in BEOL and
middle-of-line (MOL) TDDB reliability. Before joining the
semiconductor industry, Kok was a military engineer in the
procurement of extreme-damage missile systems, and a software
engineer involved in high-security smartcard encryption and
authentication technologies.
Yoann, Mamy Randriamihaja (2B.2)
Yoann Mamy Randriamihaja was born in Grenoble, France, in 1985.
He received the M.S. degree in micro- nano- electronic from
University Joseph Fourier and the Engineering degree in 2009 from
the Ecole Nationale Supérieure d'Electronique et de Radioélectricité
de Grenoble (ENSERG) of the Institut National Polytechnique de
Grenoble (INPG). Since 2009, he is pursuing the Ph.D. degree in
micro- and nanoelectronic through a collaboration between the
Institut Matériaux Microélectronique Nanosciences de Provence
(IM2NP), Toulon, and the Electrical Characterization and Reliability
Department of STMicroelectronics Crolles. His Ph.D. work focuses
on the improvement of electrical characterization techniques of
oxide defects, and the understanding of physical phenomena
observed in advanced MOSFETs.
Yokogawa, Shinji (6A.4)
Shinji Yokogawa recieved the B.S.(1992), M.S.(1994), and
Ph.D(2008) in engineering from The University of Electro-
Communications, Tokyo, Japan. In 1994 he joined NEC Corp.,
Japan. He is currently with the Advanced Device Development
Division, NEC Electronics Corporation, Kawasaki, Japan.
Currently, he serves as a leading engineer of advanced
technology qualification in NEC Electronics. He is a member of
the Japan Society of Applied Physics and Reliability
Engineering Association of Japan.
Yoshiharu, Tosaka (3A.5, 4A.5)
Yoshiharu Tosaka was born in Akita, Japan, in April 1962. He
received B. S., M. S. and Ph. D. degrees in physics from Niigata
University, Japan, in 1985, 1987, and 1990, respectively. He
joined Fujitsu Laboratories Ltd in 1990. His current research
interests are in the reliability physics of VLSI devices, especially
for soft-error reliability. Dr. Tosaka is a member of the Japan
Society of Applied Physics and the Physical society of Japan.
Yoshimoto, Hiroyuki (XT.2)
Hiroyuki Yoshimoto received the B.S., M.S., and Ph.D. degrees
in solid state physics from Waseda University in 2000, 2002,
and 2006, respectively. In 2006, he joined the Central Research
Laboratory, Hitachi, Ltd., Tokyo, Japan. Since then, he has been
working on research and development of CMOS devices
including SOI and high-k MOSFETs. Since 2009, he has also
been working on research and development of power electronics
devices.
Young, Chadwin (2B.4, 4A.4)
Chadwin D. Young received his B.S. degree in Electrical
Engineering from the University of Texas at Austin in 1996. He
then went on to receive a M.S. and Ph.D. from the North
Carolina State University in 1998 and 2004, respectively. He
has held several internships during this time until 2001 when he
joined SEMATECH. Here, he completed his dissertation
research on high-k gate stacks. He now continues this research
at SEMATECH as a Member of the Technical Staff working on
electrical characterization and reliability methodologies for the
evaluation of high-k gate stacks, and he has authored or co-
authored 150+ journal and conference papers.
Yu, Hongyu (MY.4)
Yu Hongyu obtained his BEng degree from Tsinghua
University, MASc degree from University of Toronto and PhD
from National University of Singapore respectively. From June
2004 to January 2008, he worked as a Senior Researcher in
IMEC, Belgium. He joined the School of EEE starting from
January 2008, receiving the inaugural Nanyang Assistant
Professorship. His research is on sustainable Si-based Nano
electronic device, e.g. emerging memories / sub-22nm CMOS
devices for green IC; advanced solar cell / nano-photonic
devices. He has authored / co-authored more than 150 peer-
reviewed international papers. He also has published / been
granted with > 20 USA/EU patents. His research achievements
have gained international recognition. He has received many
awards including NUS president graduate fellowship, IEEE EDS
PhD fellowship, Nanyang Assistant Professorship, Tan Chin
Tuan Academic Exchange Fellowship, and one high-light paper
in Tech. Sym. VLSI (2007).
Yuichiro, Mitani (3D.4)
Yuichiro Mitani received the B. E. and M. E. in material science
and engineering from Tohoku University, Sendai, Japan, in 1990
and 1992, respectively. He received the Ph.D. from the
University of Tokyo in 2009. He joined the R&D Center,
Toshiba Corporation in 1992. His primary works were
concerned in the Si-CVD and the ultra-shallow junction process
technology. Since 1999, he has been with the Advanced LSI
Technology Laboratory, Corporate R&D Center, Toshiba
Corporation, Yokohama, Japan. His present research interests
and activities cover the ultra-thin oxide process technology and
the study of the reliability of ultra-thin gate dielectrics (SiO2,
SiON and High-k) for ULSI technology. He serves (or served) on
the technical committees of International Conference on IC Design
& Technology (ICICDT) and IEEE International Reliability Physics
Symposium (IRPS). He is a member of the JSAP.
Yuko, Kobayashi (4A.5)
Yuko Kobayashi received the B.S. degree in Materials Property, and
the M.S. degree in Materials Processing and Characterization from
Tohoku University, Miyagi, Japan, in 2003 and 2005, respectively.
She joined Fujitsu Ltd. in 2005. Her currently work is reliability
technology for ULSI devices.
Yumi, Kakuhara (6A.4)
Yumi Kakuhara received the B.E. degree from Aoyama Gakuin
University, Tokyo, Japan, the M.E. degree from Shinshu University,
Nagano, Japan, and Ph.D (2010) in engineering from Shibaura
Institute of Technology, Tokyo, Japan. She was with the
Semiconductor Group, NEC Corporation, Sagamihara, Japan. She is
currently focused on reliability issues in advanced Cu./Low-k
interconnect. She is currently with the Advanced Device
Development Division, NEC Electronics Corporation, Kawasaki,
Japan.
Zhang, Lijuan (5B.2)
Lijuan Zhang is a graduate student in the Department of Electrical
Engineering at The University of Texas at Austin. She received her
M.S. degree in solid state physics from the Institute of Physics,
Chinese Academy of Sciences (CAS) in 2004 and her B.S. degree in
physics from Peking University in China in 2001. She joined The
University of Texas at Austin in fall 2004 and pursued her PhD in
the Interconnect and Packaging group under the supervision of Prof.
Paul Ho. Zhang’s research focuses on the BEOL reliability issues
such as electromigration and stress migration reliability of Cu
damascene interconnects.
Zhao, Kai (2B.1)
Kai Zhao received the bachelor's and master 's in physics from
University of Science and Technology of China in 2000 and 2002
respectively and the Ph.D. from Physics department at University of
California, San Diego in 2008. In the same year, he joined IBM
research division as a postdoctroal researcher, working in the
reliability and characterization group. At IBM research, he is
focused on understanding the fundamental reliability aspects of
advanced Field Effect Transistors, including HKMG FETs and
Carbon Nanotube Transistors.
Zhao, Larry (5A.2)
Larry Zhao joined Intel Corporation in 2002 and is currently
working at IMEC as an assignee from Intel. He has more than 10
years of experience in the research and development of Cu
interconnects and holds 6 U.S. patents. He has also co-authored
more than 40 scientific publications. Larry Zhao received his B.S.
degree in Materials Science from Shanghai Jiaotong University in
1984 and M.S. degree in Engineering from Dartmouth College,
Hanover, NH in 1993. He studied for Ph.D. at Columbia University,
NYC from 1993 to 1997.
Zheng, Rui (5E.2)
Rui Zheng received Bachelor of Science from School of EECS,
Peking University, China in 2008.He is a master student in Arizona
State University since 2008. Currently researching in circuit
reliability modeling and prediction.
Zhi Qiang, Mo (3C.5)
Mo Zhi Qiang is Manager of failure analysis operations group in
Global Foundries Singapore Pte Ltd. He has been working in
microelectronics failure analysis area for more than 18 years. His
areas of interest includ surface analysis, materials/chemical analysis
and physical analysis. Prior to join Chartered, he was Assistant Vice
President in TUV-SUD-PSB Corp Singapore and worked as
Senior Research Engineer in Institute of Microelectronics (IME)
Singapore. He received his Bachelor and Master's degree in
electronic engineering from Tsinghua University, Beijing in
1987 and 1993 respectively
Zhou, Carl (6C.4)
Carl Zhou has worked at Texas Instruments since 1999. He has
developed yield enhancement tools such as critical area analysis
and logic mapping. He also works on Non-Volatile Memory,
flash and FRAM, testing, characterization, and reliability study.
Prior to joining TI, Carl Zhou has worked in several companies,
including Integrated Device Technology, Inc. and SunPower. He
received his Ph.D in Physics at Stanford University.
Zhou, Jiping (5B.2)
J. P. Zhou is a Research Scientist and Facility Manager in Texas
Materials Institute in the University of Texas at Austin. His
research career is covered to high Tc superconductors,
semiconductors, nano-materials and their syntheses, fabrications
and characterizations. Recently, he is engaged in the area for
nano-materials structures, defects and properties, corresponding
to crystal orientations by using Diffraction-Scanning
Transmission Electron Microscope (D-STEM) and Precession
Microscope.
Zhou, Xing (NA. 1)
Xing Zhou received the B.E. degree from Tsinghua University
in 1983 and the M.S. and Ph.D. degrees in electrical engineering
from the University of Rochester in 1987 and 1990,
respectively. Since 1992 he has been a faculty of the School of
Electrical and Electronic Engineering, Nanyang Technological
University, Singapore. He was a visiting professor with
Stanford University in 1997 and 2001 and with Hiroshima
University in 2003. He is a distinguished lecturer of the IEEE
EDS and an editor for the IEEE Electron Device Letters. His
research focuses on development of compact models for circuit
simulation for nanoscale MOS devices.
Zhu, Goujun (NA. 1)
Guojun Zhu was born in China in 1984. He received the B.E.
degree (Hons.) in electrical and electronic engineering in 2007
from Nanyang Technological University, Singapore, where he is
currently working toward the Ph.D. degree at the School of
Electrical and Electronic Engineering. His current research interests
include unified compact modeling of bulk/SOI/DG/GAA and
Schottky-barrier MOSFETs. From July to December 2005, he was
an Intern with Chartered Semiconductor Manufacturing Ltd.,
Singapore, where he worked on electrical testing.
Zhu, Vivian (4B.2)
Xiaowei (Vivian) Zhu received her Ph.D. in Electrical Engineering
from Vanderbilt University. She joined Texas Instruments, Inc. in
2002 as a Reliability Engineer in the Silicon Technology
Development group. Dr. Zhu has published several papers in the
field of radiation induced single event upset, served as technical
session chair for IEEE Nuclear and Space Radiation Effects
Conference, and International Conference on the Application of
Accelerators in Research and Industry. She also served as a
committee member and section author of JEDEC JESD89A
standard, and is a frequent reviewer for IEEE TNS, European
Conference on Radiation and Its Effects on Components and
Systems, and Microelectronics Reliability.
Zous, Nian-Kai (5D.3)
Nian-Kai Zous received the Ph.D. degree in electronics engineering
from National Chiao-Tung University (NCTU), Hsin-chu, Taiwan,
R.O.C., in 2002. He joined the Macronix International Co., Ltd.
(MXIC) in Hsinchu, Taiwan, in 2003, working in the advanced
device group of the Device Technology Division and his research
activities include the study of reliability and scaling issues in nitride
storage devices. From 2005 to 2007, he is working in the NBIT
Flash Tech. Dept. II of MXIC and is responsible for the reliability
issue on NBIT product. Since 2007, he has been engaged in the
methodologies for technology development and yield enhancement .
Zschech, Ehrenfried (5B.1, 5B.2)
Ehrenfried Zschech is Division Director at Fraunhofer Institute for
Nondestructive Testing in Dresden, which he joint in 2009. His
responsibilities include micro- and nanoanalysis. He received his Dr.
degree from Dresden University of Technology. Ehrenfried Zschech
gathered experience in industry, during 17 years in several technical
and management positions at Airbus and AMD. He has published
three books and more than 100 papers in scientific journals. He is an
honorary professor for nanomaterials at the Brandenburg University
of Technology in Cottbus, Germany. In 2009, Ehrenfried Zschech
was elected as Vice President of the Federation of European
Materials Societies (FEMS).