Noise in Digital Integrated Circuits

Lecture 4
V DD
v(t)
The CMOS Inverter i(t)

Peter Cheung
Department of Electrical & Electronic Engineering
Imperial College London

(a) Inductive coupling (b) Capacitive coupling (c) Power and ground
noise
URL: www.ee.ic.ac.uk/pcheung/
E-mail: p.cheung@ic.ac.uk

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DC Operation: Voltage Transfer Characteristic DC Transfer Curve: Load line

‹ Consider a simple inverter

• When Vin = 0 Vout = Vdd
• When Vin = Vdd Vout = 0
‹ In between, Vout depends on current through
transistors as determined by transistor width
and length
‹ By KCL, steady state condition is:
• Idsn = |Idsp|
•
‹ Find transfer function by solving equations, but
better insight using graphical method

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 DC Transfer Curve Operating Regions

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Effect of beta ratio on switching thresholds Noise Margins

‹ Extract switching point depends on βp/ βn

‹ If βp/ βn = 1, switching occurs at around Vdd/2
‹ Otherwise:

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 Maximize Noise Margins Voltage Transfer Characteristic of Real Inverter
5.0
‹ Select logic levels at unity gain point of DC transfer
characteristic
4.0 NM L

3.0

Vout (V)
2.0
VM
NM H
1.0

0.0 1.0 2.0 3.0 4.0 5.0

V in (V)
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The Regenerative Property Delay Definitions

V in
...
v0 v1 v2 v3 v4 v5 v6

(a) A chain of inverters. 50%

v 1, v 3 , ... v 1 , v 3, ...
t
f(v) finv(v)
t t
pHL pLH
V out
finv(v) f(v) 90%

50%

v 0 , v 2, ... v 0, v 2 , ...
10% t
tf tr
(b) Regenerative gate (c) Non-regenerative gate

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 Ring Oscillator Power Dissipation

v0 v1 v2 v3 v4 v5

v0 v1 v5

T = 2 × tp × N
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Delay Estimation RC Delay Models

‹ Need to estimate delay without circuit simulation e.g. SPICE ‹ For each MOS transistor
• Not as accurate as simulation • Assume ideal switch + capacitance + ON resistance
• But easier to ask “What if?” • Unit nMOS has resistance R, gate capacitance C
‹ The step response usually looks like a 1st order RC response • Unit pMOS has resistance 2R, gate capacitance C
with a decaying exponential • Capacitance ∝ width
• ON resistance ∝ 1/width
‹ Use RC delay models to estimate delay
• C = total capacitance on output node
• Use effective resistance R so that t pd = RC
‹ Characterize transistors by finding their effective R depends on
average current as gate switches

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 Computing the Capacitances Computing the Capacitances

V DD VD D

M2
C db2 C g4 M4
C gd12
V in V out V out2

C db1 Cw C g3
M1 M3
Interconnect

Fanout
V in V out
Simplified
Model CL

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Impact of Rise Time on Delay Delay as a function of VDD

0.35
28

0.3 24 Assuming Vdd = 5V

tpHL(nsec)

20

Normalized Delay
0.25
16
0.2
12

8
0.15
0 0.2 0.4 0.6 0.8 1
tr is e (nsec) 4

0
1.00 2.00 3.00 4.00 5.00
V DD (V)
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 Where Does Power Go in CMOS? Dynamic Power Dissipation

‹ Dynamic power Vdd

• charging and discharging capacitors

‹ Short circuit currents Vin Vout

• short circuit path between power rails during switching

CL
‹ Leakage power
• Leaking diodes and transistors
Energy/transition = C L * V dd 2

Power = Energy/transition * f = C L * V dd 2 * f

Not a function of transistor sizes!

Need to reduce C L , V dd , and f to reduce power.

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Short Circuit Currents Leakage

Vdd Vdd

Vin Vout

CL Vout

Drain Junction
Leakage
0 .15

0 .10 Sub-Threshold
IVDD (mA)

Current
0 .05

0. 0 1.0 2.0
Vin (V)
3.0 4.0 5.0
Sub-Threshold Current Dominant Factor
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 Sub-Threshold in MOS How to reduce power?

‹ Prime choice: Reduce voltage!

z Recent years have seen an acceleration in supply voltage
reduction
z Design at very low voltages (0.6 … 0.9 V by 2010!)
z Maintaining performance by threshold scaling leads to
increased leakage
‹ Reduce switching activity
‹ Reduce physical capacitance

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