R.M.K.

ENGINEERING COLLEGE
RSM Nagar, Kavaraipettai – 601 206
Date : 03.08.2020
First Internal Assessment Test – August 2020 (Online Test - through Google Classroom)
Third Semester B.E. / B.Tech
Computer Science and Engineering / Information Technology
CS8351 - Digital Principles and System Design
COs Course Outcome : The students, after the completion of the course, are expected to ….
CO1 Design Digital Circuits using simplified Boolean functions
CO2 Analyze and Design Combinational Circuits
CO3 Analyze and Design Synchronous Sequential Circuits
CO4 Analyze and Design Asynchronous Sequential Circuits
CO5 Implement designs using Programmable Logic Devices
CO6 Write HDL code for Combinational and Sequential Circuits
Time : 3 Hours Answer ALL Questions Max. Marks : 100
Part-A (10 x 2 = 20 Marks)
1. Find the Octal equivalent to Hexadecimal number (AB.CD)10
2. State the principle of duality.
3. Convert ( 428)10 to binary.
4. State Consensus Theorem.
5. Implement AND gate using NOR gate.
6. What is the disadvantage of ripple carry adder?
7. What is Combinational Circuit?
8. What is the need for code conversion? Give two commonly used codes.
9. Give the applications of Demultiplexer.
10. What is logic synthesis in HDL?
Part – B ( 5 x 13 = 65 Marks)
11.a. Simplify the following Boolean expression to minimum number of literals (7+6)
(x+y+z) (x’+y’+z) (b) (A+B)’ (A’+B’)’
Or
11.b. (i) Subtract 748 from 963 using 10’s complement (7)
(ii)Find (22)10-(11)10 using 9’s complement (6)

12.a. Simplify the following Boolean expression in SOP and POS using KMAP (13)
AC' +B'D+A'CD+ABCD
Or
12.b. Simplify the Boolean function F(w,x,y,z)=∑(2,3,4,6,7,11,12,13,14) with don’t care conditions
d(1,5,15) and implement using NOR gates. (13)

13.a. Explain the gray code to binary converter with necessary diagram. (13)
Or
13.b. Design a carry look ahead adder. (13)

14.a. Design and explain a 3 to 8 line decoder using combinational circuits. (13)
Or
14.b. i) With suitable block diagram explain binary multiplier. (5)
ii) Write a detailed note on carry propagation. (8)

15.a. Simplify the Boolean function F= x’z+ w’xy’+ w(x’y+xy’) and implement a logic circuit using
NAND gates. (13)
 Or
15.b. Explain HDL models for combinational circuits. (13)
Part – C ( 1 x 15 = 15 Marks)
16.a. Simplify the Boolean Function F = Σ (0, 2, 3, 5, 7, 8, 11, 13, 17, 19, 23, 24, 29, 30) using K-
map. (15)
Or
16.b. Construct a BCD Adder circuit and write a HDL program module for the same. (15)
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Knowledge Level ( Blooms Taxonomy)

K1 Remembering (Knowledge) K2 Understanding (Comprehension) K3 Applying (Application of Knowledge)
K4 Analysing (Analysis) K5 Evaluating (Evaluation) K6 Creating (Synthesis)

Knowledge Level and Course Outcome – Question wise Mapping

Part Part A
Question 1 2 3 4 5 6 7 8 9 10
K Level K2 K1 K2 K1 K2 K2 K1 K2 K2 K1
CO CO1 CO1 CO1 CO1 CO1 CO2 CO2 CO2 CO2 CO2
Part Part B Part C
Question 11 (a) 11(b) 12 (a) 12 (b) 13 (a) 13 (b) 14 (a) 14 (b) 15 (a) 15 (b) 16 (a) 16 (b)
K Level K3 K3 K4 K4 K3 K4 K4 K3 K2 K3 K2 K3 K4
CO CO1 CO1 CO1 CO1 CO2 CO2 CO2 CO2 CO1 CO2 CO1 CO2