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ch06 PDF
ch06 PDF
ch06 PDF
Jin-Fu Li
Advanced Reliable Systems (ARES) Laboratory
Department of Electrical Engineering
National Central University
Jungli, Taiwan
Outline
Basics
Fault Modeling
Design-for-Testability
Customer’s need
Determine requirements
Write specifications
Test development
Fabrication
Manufacturing test
Chips to customer
Cost: cents/transistor
1 Source: SIA
0.1
0.01 Si capital/transistor
0.001
0.0001
0.00001 Test capital/transistor
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
Specification
Netlist
Test Manufacturing
Silicon
a c a c
b b
---11 10---
---01 00---
…… Circuit under test ……
---00 01---
---10 10---
Stored
Correct Comparator
Responses
Test result
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24
Cost of Test
Design for testability (DFT)
Chip area overhead and yield reduction
Performance overhead
Software processes of test
Test generation and fault simulation
Test programming and debugging
Manufacturing test
Automatic test equipment (ATE) capital cost
Test center operational cost
(CUT)
Internal Bus
Pin Generators
Pin
Pin
Pin
Electronics
Pin System
Electronics
Pin
Electronics
Pin
Electronics
Electronics Controller
Electronics
Electronics Analyzers
Disk
Workstation
STIL 1.0;
Pattern
Test
Memory Program
Input Compare
Drivers Expected
Response Output
Pass/Fail
Input
Stimulus Actual
CUT Response
Local
Per-Pin
Memory
mortality
Time
Good chips
Faulty chips
Defects
Wafer
Wafer yield = 12/22 = 0.55 Wafer yield = 17/22 = 0.77
1
1
0 (1)
1 s/1
0
POWER Output
Shorted
to 1
OUT
IN
GROUND
0 0
B
C
0 1(Z)
VDD
pMOS IDDQ path in
faulty circuit
A
1 Stuck-on
0
B Good circuit state
C
0 (X)
nMOS
Faulty circuit state
Density
A1 Y
n2 n3
A0 A1
A0
n1
n2
n3
Y
Minimum set:
Test Example
SA1 SA0
A3 {0110} {1110}
A2 A3
A2
n1
A1
Y
n2 n3
A0
A1
A0
n1
n2
n3
Y
Minimum set:
Test Example
SA1 SA0
A3 {0110} {1110}
A2 {1010} {1110} A3
A2
n1
A1
Y
n2 n3
A0 A1
A0
n1
n2
n3
Y
Minimum set:
Test Example
SA1 SA0
A3 {0110} {1110}
A2 {1010} {1110}
A1 {0100} {0110} A3 n1
A2
A0 Y
n1
n2 n3
A1
A0
n2
n3
Y
Minimum set:
Test Example
SA1 SA0
A3 {0110} {1110}
A2 {1010} {1110}
A1 {0100} {0110}
A3 n1
A2
Y
A0 {0110} {0111} A1
n2 n3
n1 A0
n2
n3
Y
Minimum set:
Test Example
SA1 SA0
A3 {0110} {1110}
A2 {1010} {1110}
A3 n1
A1 {0100} {0110} A2
Y
A0 {0110} {0111} A1
n2 n3
n1 {1110} {0110} A0
n2
n3
Y
Minimum set:
Test Example
SA1 SA0
A3 {0110} {1110}
A2 {1010} {1110} A3 n1
A1 {0100} {0110} A2
Y
A0 {0110} {0111} A1
n2 n3
n1 {1110} {0110} A0
n2 {0110} {0100}
n3
Y
Minimum set:
Test Example
SA1 SA0
A3 {0110} {1110}
A2 {1010} {1110} A3 n1
A1 {0100} {0110} A2
Y
A0 {0110} {0111} A1
n2 n3
n1 {1110} {0110} A0
n2 {0110} {0100}
n3 {0101} {0110}
Y
Minimum set:
Test Example
SA1 SA0
A3 {0110} {1110}
A2 {1010} {1110} A3
A2
n1
A1 {0100} {0110} Y
n2 n3
A0 {0110} {0111} A1
A0
n1 {1110} {0110}
n2 {0110} {0100}
n3 {0101} {0110}
Y {0110} {1110}
Flop
SI Q
D
Normal mode: flip-flops behave as usual
Scan mode: flip-flops behave as shift register
can be scanned
Flop
Flop
Flop
out and new
Flop
Flop
Flop
values scanned inputs
Logic
Cloud
Logic
Cloud outputs
in Flop
Flop
Flop
Flop
Flop
Flop
scanout
Scannable Flip-flops
SCAN
SCAN CLK
Q
D
D 0 X
Flop
Q Q
SI 1 SI
(a)
(b)
d
D
d Q
SCAN
d X
Q
s
s
SI
(c)
s
Built-in Self-test
Built-in self-test lets blocks test themselves
Generate pseudo-random inputs to comb. logic
Combine outputs into a syndrome
With high probability, block is fault-free if it
produces the expected syndrome
PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop
Flop
Flop
D D D
1
2
3
4
5
6
7
PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop
Flop
Flop
D D D
1 110
2
3
4
5
6
7
PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop
Flop
Flop
D D D
1 110
2 101
3
4
5
6
7
PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop
Flop
Flop
D D D
1 110
2 101
3 010
4
5
6
7
PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop
Flop
Flop
D D D
1 110
2 101
3 010
4 100
5
6
7
PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop
Flop
Flop
D D D
1 110
2 101
3 010
4 100
5 001
6
7
PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop
Flop
Flop
D D D
1 110
2 101
3 010
4 100
5 001
6 011
7
PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop
Flop
Flop
D D D
1 110
2 101
3 010
4 100
5 001
6 011
7 111 (repeats)
BILBO
Built-in Logic Block Observer
Combine scan with PRSG & signature analysis
C[0]
C[1]
Q[2] / SO
Flop
Flop
Flop
SI 1
0 Q[0]
Q[1]
PackageInterconnect
CHIP B CHIP C
CHIP A CHIP D
Serial Data In
Boundary Scan Interface
Boundary scan is accessed through five pins
TCK: test clock
TMS: test mode select
TDI: test data in
TDO: test data out
TRST*: test reset (optional)