Mixed-Signal-Electronics

PD Dr.-Ing. Stephan Henzler

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 Chapter 6
Nyquist Rate
Analog-to-Digital Converters

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 Pipelined ADC 2

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 High-Speed ADC: Pipeline Processing

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 Robertson Diagram with Threshold Error

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 Impact of Comparator Offset on
ADC Performance

As soon as the residue leaves

the convergence region the
result suffers from major errors

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 Impact of Comparator Offset on
ADC Performance

Comparator offset reflects in

non-linearity of ADC characteristic

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 Impairments in SAR Algorithms
 Finding:
Each error in the amplifier gain or quantizer threshold causes
divergence of the convergence algorithms and thus major
conversion error

 How can we make SAR algorithms more robust

 Redundancy
 Redundant SAR algorithms

Architecture implications

 Subranging ADC  Pipeline ADC

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 How can we Strengthen the Algorithm?
 Gain and offset errors shift the algorithm out of the
convergence window.
 Does an additional threshold help?

 No, not necessarily. Important is that the residue is not

scaled back fully.

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 Redundant SAR Algorithms

 Stage quantizer with B bit  Stage quantizer with B bit

(here B=2) (here B=2)
 Gain factor = 2B  Gain factor < 2B
 Sensitive to thresh. var.  redundant SAR
 not sensitive to thres. var.
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 Redundant Pipeline ADC Algorithm
 Redundant algorithm
– Two thresholds
– Gain ( = 2 ) does not scale
residue back to full scale

 Stage resolution 1 bit

 Information contained
in bi is 1.5 bit
 Redundancy

 Residue stays in
convergence box even
with strong gain and
offset variations

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 Subranging Principle

quantization error

 Principle: Coarse quantization in frontend ADC and fine

quantization of residue in backend ADC
 Pipelining possible (s&h between frontend and backend
 Generalization to multi-stage ADC ( pipeline ADC)

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 Model of Frontend ADC

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 Linear Model of Subranging ADC

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 What is the “Digital Result Combiner“?
 Output of forward and backward ADC from last slide:

 Multiply result of backend ADC by 1/a and add to Bout,1

 Overall quantization error only depends on quantization error

of backend ADC
 Quantization error of backend ADC is scaled by 1/a
 Resolution:

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 Linear Model of Subranging ADC

 Effective resolution of frontend ADC is ld(a)

 not necessarily the same as the number of bits of Bout,1
 Analog and digital gain must match, otherwise leakage of
quantization error of frontend ADC

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 Reconstruction of Signal

matching
 Error free reconstruction requires matching between analog
gain a and digital gain ad
In the context of variations this requires calibration

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 General Pipeline SAR ADC

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 General Pipeline SAR ADC II
 As long as analog and digitals gains match all intermediate
terms vanish

 Resolution R:

Gain elements determine resolution, not the stage quantizers

 Effective stage resolution:

 Last stage must not saturate under all circumstances!

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 Background Calibration for Stage Gain

Digital gain is
continuously
adjusted, i.e. even
slow transient
variations are
corrected

Li et al., Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy, TCAS II, 9/2003.
Fu et al., A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters, JSSC, 12/1998
Liu et al., A 15b 40MS/s CMOS Pipelined ADC with Digital Background Calibration, JSSC, 5/2005
many more …

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 Classification of Callibration Techniques
 Calibration comprises two phases
– Error estimation
– Error correction
 Analog approach  additional analog components, noise,
power, distortion, etc.
 Digital approach: Works on reults only, i.e. does not interfere
with analog signal processing

Calibration

Foreground Background

Virtual True
Ginés et al., A Survey on Digital Background Calibration of ADCs, ECCTD, 2009.

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 Summary Pipeline ADC
 Stage errors can be tolerated if the residue stays inside the
convergence region
– Minimum requirement is that the residue is back in the convergence region
before the final quantizer)
– Take care for nonlinearity which is not revealed by the linear model
 Trade-off sampling frequency – resolution – latency
 Number of stages, i.e. number of elements grows linearly
with resolution (not exponentially, ref flash ADC)
 Accurate sample-and-hold elements required
(That’s the reason why pipelined time-to-digital converters do not exist)

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 Nyquist Rate Analog-to-Digital Converters

– Flash Converter –

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 Flash Converter
 Generate all switching thresholds in parallel
and compare them to input voltage in parallel
 very fast, but high effort in terms of
power, area, noise generation, clock
distribution, input buffering
 high speed applications with moderate
resolution

implemented
as parallel
connection
of 2 unit resistors
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 Properties of Flash ADC
 Advantages
– parallel processing  very fast
– no analog post-processing

 Disadvantages:
– Huge hardware effort and power consumption (2N)
– high input capacitance
– synchronous routing of clock signal

 Good for high-speed converters with low # of bits

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 thermometer code
one-hot code Flash Converter
 Thermometer-to-binary
decoder often
implemented in 2 steps
– thermo  one-hot
– one-hot  binary

 Allows for insertion of

bubble correction in
between decoders

transition detector
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 Bubble Correction in Flash Converter

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 Bubble Correction in Flash Converter
 Bubbles in flash converters:
0 0 0 0 0 0 1 1 1 1 1 1
0 0 0 1 0 0 1 1 1 0 1 1

 Source of bubbles:
– noise
– meta-stability
– x-talk
– mismatch
–…
 Basic bubble correction with 3-input NAND gate: transition
only detected if more than one high signal occurs.
 More complex encoders require to eliminate long distance
errors
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 Interpolating Flash Converter
 Preamp. with moderate
gain to provide smooth
transition region
 Latch for sign detection
 Resistive interpolation
to create additional
transition curves in
between 2 regular ones

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 Interpolating Flash Converter

 Interpolation does not work at

boarders
 Overrange amplifiers required

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 Interpolating Flash Converter (cont)
additional series resistors to balance
delays in high-speed interpolating
flash converters

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 Kickback Effect
 Especially in flash converters
 Clocked comparators produce lots of
noise at their inputs when toggling
from track to latch mode.
 Different impedance seen from both
comp inputs
(input drive vs. resistor ladder)
 Differential error that may corrupt
next conversion
 Decay of error sets max sample rate

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