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  • Cmos Digital Vlsi Design: Sequential Logic Design-VII

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    The document discusses various register styles for sequential logic design in CMOS digital VLSI circuits. It describes dual edge registers that sample data on both clock edges, allowing lower clock frequencies. True single phase clocked registers are also discussed that use a single clock phase. Alternative styles include pulse registers that generate short pulses around clock edges for sampling and sense amplifier based registers that amplify small input signals. The document recaps advantages and disadvantages of different approaches for implementing registers in sequential digital circuits.

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    Lecture notes VLSI design

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    lec31

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    The document discusses various register styles for sequential logic design in CMOS digital VLSI circuits. It describes dual edge registers that sample data on both clock edges, allowing lower clock frequencies. True single phase clocked registers are also discussed that use a single clock phase. Alternative styles include pulse registers that generate short pulses around clock edges for sampling and sense amplifier based registers that amplify small input signals. The document recaps advantages and disadvantages of different approaches for implementing registers in sequential digital circuits.

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    46 views11 pages

    Cmos Digital Vlsi Design: Sequential Logic Design-VII

    Uploaded by

    vivek j
    The document discusses various register styles for sequential logic design in CMOS digital VLSI circuits. It describes dual edge registers that sample data on both clock edges, allowing lower clock frequencies. True single phase clocked registers are also discussed that use a single clock phase. Alternative styles include pulse registers that generate short pulses around clock edges for sampling and sense amplifier based registers that amplify small input signals. The document recaps advantages and disadvantages of different approaches for implementing registers in sequential digital circuits.

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    © All Rights Reserved
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    of 11

    CMOS DIGITAL VLSI DESIGN

    Sequential Logic Design-VII


    SUDEB DASGUPTA
    DEPARMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

    1
    Dual Edge Register-
    • It is possible to design a sequential circuit
    which samples the data on both the edges
    of clock.
    • The advantage of this scheme is that a
    lower frequency clock is distributed for
    the same functional throughput, resulting
    in power saving.
    • It consists of two parallel master-slave
    edge-triggered registers, whose outputs
    are multiplexed by using tri-state drivers.
    Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

    2
    True Single Phase Clocked Register (TSPCR)-
    • It is possible to design a register that only use a single phase clock.
    • For the positive latch, when CLK is high then the latch is in
    transparent mode and corresponds to two cascaded inverters; the
    latch is non-inverting and propagates the input to the output.
    • A register can be constructed by cascading positive and negative
    latches.

    Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

    3
    Cont…
    • TSPC offers an additional advantage of embedding logic functionality
    into the latches.

    Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

    4
    Cont…
    • TSPC can further be designed with less complexity as only the first
    inverter is controlled by the clock.
    • This reduce the clock load but having a disadvantage that all node
    voltages will not experience the full logic swing.

    Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

    5
    Alternative Register Styles
    Pulse Register-
    • The idea is to construct a short
    pulse around the rising or
    falling edge of the clock. So,
    the data sampling takes place
    over the short window.
    • The combination of glitch-
    generation circuitry and the
    latch results in a positive edge
    triggered register.
    Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

    6
    Cont…
    • Another version of pulsed register is shown below-

    • This circuit uses a pulse generator which is integrated into the


    register itself.
    • In this circuit the setup time is negative.
    Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

    7
    Sense Amplifier based Register-
    • Sense Amplifier circuits accept small input signals and amplify them
    to generate rail-to-rail swings.

    Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

    8
    • The need of shorting transistor M4 Cont…

    Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

    9
    Recapitulation
    • The sequential logic circuit with a idea of temporary storage of charge
    on parasitic capacitors comes into the category of dynamic logic.
    • Dynamic Transmission Gate Edge Triggered Registers is suffered from
    the clock overlapping while C2MOS is insensitive to overlap.
    • Dual Edge Registers can reduce the clock frequency by half of the
    original rate.
    • The disadvantage of TSPCR is the slight increase of transistor count in
    the circuit.

    10
    Thank You

    11

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