Birla Institute of Technology & Science, Pilani

Work-Integrated Learning Programmes Division

Second Semester 2018-2019
Comprehensive Examination (EC-3 Make-up)
Course No. : ENGG ZC112
Course Title : ELECTRICAL AND ELECTRONICS TECHNOLOGY
Nature of Exam : Open Book
Weightage : 40% No. of Pages =3
Duration : 3 Hours No. of Questions = 8
Date of Exam : 12/05/2019 (AN)
Note:
1. Please follow all the Instructions to Candidates given on the cover page of the answer book.
2. All parts of a question should be answered consecutively. Each answer should start from a fresh page.
3. Assumptions made if any, should be stated clearly at the beginning of your answer.
Q.1. Consider the circuit shown in Fig Q1. The resistance of 40 Ω in the circuit is the load
resistor.
(a) Determine Norton’s equivalent circuit. [2]
(b) Using part (a) above, determine Thevinin’s equivalent circuit. [1]
(c) Determine the power drawn by the load resistor. [1]
(d) If an additional load of 40 Ω resistance is connected across the load terminals, then
determine the load current drawn by the combined (parallel combination) load. [1]

Fig. Q1

Q.2. Consider the circuit shown in Fig. Q2.

(a) Determine the current through 20 Ω resistor using nodal analysis. [2]
(b) Determine the voltage across 6 Ω resistor using mesh analysis. [2]
(c) Calculate the total current supplied by the 20 V supply. [1]

Fig. Q2

ENGG ZC112 (EC-3 Make-up) Second Semester 2018-2019 Page 1 of 3

ENGG ZC112 (EC-3 Make-up) Second Semester 2018-2019 Page 2

Q.3. Consider the circuit shown in Fig. Q3. The supply frequency is 50 Hz.
(a) Determine the total load impedance. [1]
(b) Determine the currents through the capacitor and the current through the inductor. [2]
(c) Draw a neat sketch of the phasor diagram showing the supply voltage, total current, the
current through the capacitor and the voltage across the capacitor. [1]
(d) Calculate the total active power supplied by the AC supply. [1]

Fig. Q3

Q.4. A 2.2 MVA, 6.6 kV, three-phase, star-connected synchronous generator has armature
resistance of 0.6 Ω per phase and a synchronous reactance of 6 Ω per phase. Assume that
the speed and the exciting current remain unaltered.
(a) Calculate the emf generated in the armature, if half the rated load is connected to its
terminals at the rated voltage and at 0.8 power factor leading. [2]
(b) Draw a neat sketch of the phasor diagram showing the terminal voltage, the load current,
and the generated emf. [2]
(c) Calculate the percentage voltage regulation at unity power factor. [1]

Q.5. A 440 V, 60 Hz, two pole, three phase induction motor is connected to its rated supply. The
frequency of the rotor currents at the rated load is 2.4 Hz.
(a) Calculate the rotor speed (in rpm) at the rated load. [2]
(b) If the frequency of the rotor currents at some other load is 3 Hz, then calculate the rotor
speed (in rpm). [1]
(c) If the same motor is connected to a supply at 50 Hz and is running at 2940 rpm, then
calculate the percentage slip. [2]

Q.6. A four pole, 1500 rpm, lap wound, 240 V DC shunt generator has 48 armature slots with 8
conductors per slot. It delivers a load current of 14.04 A at the rated terminal voltage. The
armature resistance and the field resistance are 0.5 Ω and 250 Ω, respectively. Neglect the
rotational losses.

(a) Calculate the emf generated in the armature and the power developed in the armature.
[2]
(b) Calculate the efficiency of the generator. [2]
(c) Calculate the useful flux per pole. [1]

ENGG ZC112 (EC-3 Make-up) Second Semester 2018-2019 Page 2 of 3

ENGG ZC112 (EC-3 Make-up) Second Semester 2018-2019 Page 3

Q.7. A full wave rectifier with a center-tapped transformer and two diodes is fed from a single
phase, 50 Hz, 240 V supply (vs (t)). A resistive load of 100 Ω is connected across the output
of the rectifier.

(a) Calculate the average voltage across the load and the average current through the load.
[2]
(b) Sketch the following waveforms on the same plot: supply voltage vs(t), the voltage across
the load, current through the load, voltage across one of the diodes and the current
through the same diode. [3]

Q.8. Consider a three-input logical function with inputs A, B and C, and the output F. The output
(F) is 1, when more than half of the inputs are 1.

(a) Prepare the truth table of the function showing the inputs (A, B, and C), and the output
(F). [2]

(b) Prepare the truth table of a logical function F1 = AB + AC + BC showing the inputs (A,
B, and C), and the output (F1). Compare the truth table in part (a) with that of in part (b).
[2]

(c) Implement the function F1 using two-input AND gates and two-input OR gates. [1]

***********

ENGG ZC112 (EC-3 Make-up) Second Semester 2018-2019 Page 3 of 3