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Birla Institute of Technology & Science, Pilani

Work-Integrated Learning Programmes Division


Second Semester 2018-2019

Comprehensive Examination
(EC-3 Regular)

Course No. : ENGG ZC112


Course Title : ELECTRICAL AND ELECTRONICS TECHNOLOGY
Nature of Exam : Open Book
Weightage : 40% No. of Pages =3
Duration : 3 Hours No. of Questions = 8
Date of Exam : 05/05/2019 (AN)
Note:
1. Please follow all the Instructions to Candidates given on the cover page of the answer book.
2. All parts of a question should be answered consecutively. Each answer should start from a fresh page.
3. Assumptions made if any, should be stated clearly at the beginning of your answer.

Q.1. Consider the circuit shown in Fig Q1. The resistance of 15 Ω in the circuit is the load
resistor.
(a) Determine Thevenin’s equivalent circuit as seen from the load terminals. [2]
(b) Using part (a) above, determine Norton’s equivalent circuit. [1]
(c) Determine the power drawn by the load resistor. [1]
(d) Determine the maximum power that can be delivered by this circuit. [1]

Fig. Q1

Q.2. Consider the circuit shown in Fig. Q2.


(a) Determine the current through 20 Ω resistor using superposition theorem. [2]
(b) Determine the voltage across 10 Ω resistor using nodal analysis. [2]
(c) Using the results obtained in part (b) above, determine the current through 15 Ω
resistor. [1]

Fig. Q2

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ENGG ZC112 (EC-3 Regular) Second Semester 2018-2019 Page 2

Q.3. Consider the circuit shown in Fig. Q3. The supply frequency is 50 Hz.
(a) Determine the total impedance of the circuit. [1]
(b) Determine the current through the capacitor and the current through 15 Ω resistor. [2]
(c) Determine the total current drawn from the supply of 100 V and the power factor. [1]
(d) Draw a neat sketch of the phasor diagram showing the supply voltage, total current,
the current through the capacitor and the voltage across the capacitor. [1]

Fig. Q3

Q.4. A 2650 kVA, 6.6 kV, three-phase, star-connected synchronous generator has a per phase
synchronous impedance of (0.65 + j 7.5)Ω. Assume the speed and the exciting current
remain unaltered. A rated load at 0.85 lagging power factor is connected to its terminals at
the rated voltage.
(a) Calculate the emf generated in the armature. [2]
(b) Draw a neat sketch of the phasor diagram showing the terminal voltage, the load current,
and the generated emf. [2]
(c) Calculate the voltage regulation of the generator at this load. [1]

Q.5. A 415 V, 50 Hz, four pole, 1440 rpm, three phase induction motor is energized with a 415 V,
50 Hz three phase AC supply.
(a) Calculate the synchronous speed of the motor. [1]
(b) Calculate the percentage slip at the rated load. [1]
(c) If the slip is 0.035 at a certain load, then calculate the rotor speed (in rpm) at that load. [1]
(d) Suppose that the supply frequency is changed to 55 Hz. If the motor runs at 1440 rpm at a
certain load, then calculate the slip. [2]

Q.6. A four-pole, lap wound, 220 V DC shunt motor has 400 armature conductors. The useful flux
per pole is 0.025 Wb. The resistance of the armature circuit is 0.8 Ω and that of the field
winding is 250 Ω. The armature current is 15 A.
(a) Calculate the speed (in rpm) [2]
(b) Calculate the power developed in the machine. [1]
(c) Calculate the torque in N m. [1]
(d) Calculate the current drawn from the supply. [1]

Q.7. In the circuit shown in Fig. Q7, Vm = 230 V, R = 100 Ω and VB = 115 V. The supply
frequency is 50 Hz.
(a) Find the peak current assuming that the diode is ideal. [1]
(b) Sketch vs(t), i(t) and the voltage across the resistor. [2]
(c) Determine the average value of the load voltage and the load current, assuming VB to be
zero. [2]

ENGG ZC112 (EC-3 Regular) Second Semester 2018-2019 Page 2 of 3


ENGG ZC112 (EC-3 Regular) Second Semester 2018-2019 Page 3

Fig. Q7

Q.8. A logical function is described as


F = NOT (F1 OR F2)
where
F1= A AND B, and F2 = B OR C.
Here, A, B and C are the inputs, and F is the output. Further, NOT, OR and AND denote the
logical operations (functions).
(a) Prepare the truth table of the function showing the inputs, F1, F2 and the output F. [3]
(b) Implement this function, F, using two-input AND gates, two-input OR gates and a NOT
gate. [2]
***********

ENGG ZC112 (EC-3 Regular) Second Semester 2018-2019 Page 3 of 3

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