INVITED
PAPER
Analog and RF Interference
Mitigation for Integrated
MIMO Receiver Arrays
This paper describes how directional and spectral interference mitigations
in the analog and RF domain are achieved through innovative
beamforming architectures.
By Harish Krishnaswamy, Member IEEE, and Linxiao Zhang, Student Member IEEE
ABSTRACT | Over the past decade, we have witnessed the
maturation of silicon-based phased array technology, which
has started to make an impact on commercial and military
wireless applications. Over the next decade, driven by the
development of next-generation wireless communication
networks, we will see the maturation and impact of large-
scale multiple-input–multiple-output (MIMO) technology.
MIMO receiver arrays exploit digital array signal processing,
and consequently are exposed to interference in the analog
and radio-frequency (RF) front ends. The absence of analog/
RF interference mitigation in traditional digital MIMO receiver
arrays results in designs with high-dynamic-range and power-
hungry analog and RF receiver front ends and analog-to-
digital converters. This paper describes recently developed
techniques for spatio–spectral interference mitigation in
the analog and RF domain for digital MIMO receivers. The
techniques proposed are flexible; tunable across operating
frequency; scalable; present low cost, size, and power con-
sumption overheads; and are experimentally validated
through a 0.1–1.7-GHz four-element receiver front-end array
integrated circuit (IC) prototype in 65-nm complementary
metal–oxide–semiconductor (CMOS) technology.
KEYWORDS | Antenna arrays; complementary metal–oxide–
semiconductor (CMOS) integrated circuits; integrated circuits
(ICs); interference cancellation; interference suppression;
multiple-input–multiple-output (MIMO); phased arrays; radio
frequency (RF); receivers; receiving antennas
Manuscript received December 29, 2015; revised January 18, 2016; accepted
January 18, 2016. Date of current version February 17, 2016. This work was
supported by the Defense Advanced Research Projects Agency (DARPA) under the
Arrays at Commercial Timescales (ACT) program.
The authors are with the Department of Electrical Engineering, Columbia University,
New York, NY 10027 USA (e-mail: harish@ee.columbia.edu).
Digital Object Identifier: 10.1109/JPROC.2016.2519885
0018-9219 Ó 2016 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/
redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
I. INTRODUCTION
Phased array transmission was perhaps first shown in
1905 by the Nobel-Prize-winning scientist Karl Ferdinand
Braun, who shared the 1909 Nobel Prize in Physics with
Guglielmo Marconi for “contributions to the development
of wireless telegraphy.” Subsequently, during World War
II, the Nobel laureate Luis Alvarez used phased arrays to
develop electronically steerable radars for aircraft landing
assistance. Phased arrays were later applied to radio as-
tronomy for aperture synthesis by Nobel laureates Antony
Hewish and Martin Ryle, leading to the discovery of pul-
sars in 1967.
The past decade has seen the maturation of silicon-
based phased array transceivers and systems [1]–[25].
Research efforts on silicon-based phased arrays were mo-
tivated by the interest in silicon-based millimeter-wave
systems targeting commercial wireless communication
and vehicular radar applications at 24, 60, and 77 GHz
[1]–[11]. In these efforts, phased array technology was
primarily leveraged for overcoming the high path losses
at millimeter-wave frequencies through the spatial-
power-combining benefits offered to transmitters, and
signal-to-noise ratio benefits offered to receivers. Inter-
ference mitigation was not a significant motivating factor
due to the relatively quiet nature of the millimeter-wave
spectrum.
The promise of silicon-based high-speed circuits led
to active research on radio-frequency (RF) and millimeter-
wave phased arrays in silicon for military communica-
tions and radar applications [12]–[15]. The ability to
integrate the entire phased array beamformer into a single
integrated circuit (IC), potentially with the frequency con-
verters, analog and digital baseband circuitry, analog-to-
digital converters, and analog biasing and digital control
Vol. 104, No. 3, March 2016 | Proceedings of the IEEE 561
Krishnaswamy et al.: Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays
Fig. 1. Integrated silicon-based phased arrays reported at the
IEEE International Solid-State Circuits Conference over
2004–2015, including recent wideband and reconfigurable
phased arrays.
circuitry, leads to significant reductions in cost, size and
weight of military wireless systems. Power consumption is
also reduced due to the reduction of chip-to-chip and mod-
ule-to-module interfaces that typically require controlled
impedance levels that are power hungry to drive. Silicon-
based technologies also allow the integration of built-in
self-test (BIST) and calibration functionalities for phased
arrays [16], further reducing size, weight, and cost.
Recently, there has been extensive research on com-
plementary metal–oxide–semiconductor (CMOS) phased
arrays operating in the low-RF range that utilize wide-
band and reconfigurable design principles enabled by
CMOS technology scaling, allowing operation in a
tunable fashion across wide frequency ranges and com-
pact implementations that avoid inductors and other
frequency-limiting passive elements [17]–[19]. These
works represent the evolution of recent research on wide-
band and reconfigurable software-defined single-element
radios. Fig. 1 captures this trend by depicting integrated
silicon-based phased arrays reported at the IEEE Interna-
tional Solid-State Circuits Conference over 2004–2015,
including recent wideband and reconfigurable phased ar-
rays. There has also been significant work on integrated
true-time-delay-based arrays for instantaneously ultrawi-
deband systems [20]–[24].
Through these research efforts, several candidate
phased array architectures were explored, including RF
phase shifting [Fig. 2(a)], local-oscillator (LO) phase
shifting [Fig. 2(b)], and analog baseband phase shifting
[Fig. 2(c)]. While LO and analog baseband phase shifting
were explored as a means to overcome the cost, noise
and linearity limitations of RF phase shifters and com-
biners operating at high frequencies, the improved per-
formance of silicon transistors with technology scaling
has eliminated the RF phase shifter as the performance
bottleneck. Consequently, the RF phase shifting ap-
proach has emerged as the popular choice due to its
562 Proceedings of the IEEE | Vol. 104, No. 3, March 2016
power-efficient nature, given the fact that a single-
frequency conversion and analog baseband path is re-
quired for the entire array. RF phase shifting also sup-
presses spatial interference prior to the frequency
conversion and analog and digital baseband, easing their
dynamic range requirements and power consumption.
However, phased arrays are multiple-input–single-
output (MISO) systems that merely scratch the surface
of the potential of multiple antenna systems. While the
simple phased array forms a single beam, multiple simul-
taneous beams enable tracking of multiple targets in ra-
dar, and multifunctional apertures that can be used for
communications and radar. Multiple-input–multiple-
output (MIMO) communication systems exploit multiple
antennas to extract spatial diversity gain [26], [27] or
spatial multiplexing gain [28] to establish reliable com-
munication links or increase data rate, respectively, in
the presence of heavy multipath. While MIMO has been
exploited in WiFi and third-generation (3G) and fourth-
generation long–term evolution (4G-LTE) cellular since
2006, there has been significant recent interest in mas-
sive MIMO for future fifth-generation (5G) communica-
tion networks, where an extremely large number of
antennas is employed at the base station to realize enor-
mous increases in spectral efficiency [29], [30]. In this
context, the interested reader is directed to another pa-
per in this special issue of the PROCEEDINGS OF THE IEEE
[31]. Inspired by MIMO communication systems, such
techniques are also under exploration for MIMO radars
to reduce false alarms, enable extraction of more infor-
mation from the scene being imaged, and in certain situ-
ations, enable radar imaging with fewer array elements
[32]–[34].
MIMO systems require space-time array signal pro-
cessing that can practically only be implemented in the
digital domain. Therefore, conventional MIMO systems
use digital array processing architectures [Fig. 2(d)] that
eschew analog/RF spatial filtering. Digital array process-
ing also offers new opportunities for digital array calibra-
tion [35], [36]. For additional details, the reader is
directed to another paper in this special issue of the PRO-
CEEDINGS OF THE IEEE [37]. However, such architectures
typically sacrifice analog/RF spatial interference mitiga-
tion capabilities, and consequently require high-dynamic-
range receiver front ends and analog-to-digital (A/D)
converters that can tolerate the interference before it
may be suppressed through digital signal processing.
While some compensation of weak nonlinearities in-
duced in the analog and RF circuits by the interference
is possible in the digital domain, the front ends must
have sufficient dynamic range (and consequently, power
consumption) to prevent strong nonlinearity or satura-
tion under interference. Despite these challenges, research
efforts to recover analog/RF interference mitigation in digi-
tal receiver arrays have been scant, particularly in inte-
grated settings [38].
 Krishnaswamy et al.: Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays

Fig. 2. Conventional MISO phased array architectures: (a) RF-path phase shifting; (b) LO-path phase shifting; and (c) baseband phase
shifting, along with MIMO receiver array architectures: (d) digital array processing; (e) RF multibeam matrices (the Butler matrix is
shown here); (f) multiple parallel RF phased arrays; and (g) a digital MIMO receiver array with analog/RF spatio–spectral
interference mitigation.

There has been exciting research progress on fully in-
tegrated widely tunable sharp spectral bandpass filters in
silicon [39]–[41] through the revival of the so-called
N-path RF switched-capacitor commutated filter [42],
[43]. This paper describes recent research on a fully inte-
grated widely tunable CMOS-based receiver front-end
MIMO array architecture that combines these recent ad-
vances in tunable spectral bandpass filtering with novel
techniques for spatial notch filtering, thus enabling
spatio–spectral interference mitigation and power-
efficient digital array processing. The architecture is
scalable—multiple array ICs may be tiled on a printed
circuit board (PCB) to exploit the benefits of spatial fil-
tering across the larger array without the need for RF in-
terconnections. The use of wideband and reconfigurable
design approaches enables a compact IC implementation
that avoids inductors and transmission lines. Experimen-
tal results from a 0.1–1.7-GHz four-element MIMO

Vol. 104, No. 3, March 2016 | Proceedings of the IEEE 563

Krishnaswamy et al.: Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays
receiver array implemented in 65-nm CMOS technology
are presented.
The rest of the paper is organized as follows. Section II
reviews the state of the art in analog and RF spatial filter-
ing for MIMO receivers. Section III describes the pro-
posed analog/RF spatio–spectral interference mitigation
architecture. Measurement results from the 65-nm
CMOS 0.1–1.7-GHz four-element MIMO receiver array
prototype mentioned earlier are described in Section IV.
Finally, Section V concludes the paper with a discussion
of open topics for future research.
II. ARCHITECTURES FOR ANALOG/RF
SPATIAL FILTERI NG IN MIMO
RE CEI VERS
As discussed earlier, digital receiver arrays are fully ex-
posed to interference in the receiver front end and A/D.
The goal of analog/RF spatial filtering for digital receiver
arrays is to suppress interference and ease the transition
into the digital domain where more advanced array sig-
nal processing will be performed. Such analog/RF spatial
filters must be flexible in order to adapt to a changing in-
terference profile. They should also result in no informa-
tion loss (i.e., no reduction of the available spatial
degrees of freedom), meaning that it should be possible
to reconstruct the signal corresponding to each antenna
in the digital domain for advanced space-time array sig-
nal processing. In these contexts, prior efforts toward in-
corporating analog/RF spatial filtering in MIMO receiver
arrays are fraught with challenges.
RF multibeam matrices have been investigated that
typically employ passive networks to form multiple si-
multaneous beams from multiple antennas [Fig. 2(e)].
Examples of RF multibeam matrices include the Butler
matrix [44] and the Blass matrix [45]. The separation of
interferers and desired signals across the different beams
(or outputs) relaxes the dynamic range requirements on
the subsequent receiver front-end circuitry and A/D used
on each beam relative to the overall dynamic range seen
at each antenna. In other words, each antenna sees a dy-
namic range that is governed by the most powerful inter-
ferer and the weakest desired signal across all angles of
incidence, but each beam output sees a dynamic range
only limited by the interferer and desired signal along
the particular beam direction. Consequently, lower reso-
lution A/Ds can be used on each beam relative to the
A/Ds that would be used in the digital array processing
architecture of Fig. 2(d), and variable gain can be used
in the various receiver front ends to scale the beam sig-
nals accordingly. Furthermore, if there are as many
beams as there are antenna elements, and the different
beams compute linearly independent combinations of
the various antenna inputs, then no information is lost
across the beam outputs. The different beam outputs can
be recombined in the digital domain to recover each
564 Proceedings of the IEEE | Vol. 104, No. 3, March 2016
antenna signal for more advanced space-time array signal
processing. Despite these features, there are several chal-
lenges associated with RF multibeam matrices. They typi-
cally employ bulky passive components such as hybrids
that do not lend themselves to silicon CMOS implemen-
tations, do not improve in performance with CMOS
technology scaling, and are challenging to reconfigure
and tune across frequency. Furthermore, the beam orien-
tations that are formed are typically fixed, limiting the
flexibility of the analog/RF spatial filtering, and there are
theoretical limitations on the nature of the beams that
can be formed [46], [47]. Despite these challenges, RF
multibeam structures have been explored in CMOS in
[48] and [49], and in [50], where the authors have ex-
plored a spatio–temporal RAKE MIMO radar architec-
ture based on a Butler matrix.
The most flexible approach to analog/RF spatial filter-
ing is to employ multiple parallel phased arrays, each
performing a distinct linear combination of the antenna
inputs [Fig. 2(f)]. The main challenge with this approach
is the severe increase in cost, size, and power consump-
tion, due to the need for N
M RF variable-gain ampli-
fiers and phase shifters and M power combiners, where
N is the number of antenna elements and M is the num-
ber of beams being formed. In order to keep cost, size,
and power consumption in check, the number of beams
being formed must be kept much smaller than the num-
ber of antennas, or analog/RF beamforming must be
performed on a subarray level, with each subarray’s
beamformed output being digitized for digital space-time
array signal processing. Both approaches significantly
sacrifice the spatial diversity or multiplexing gains avail-
able, as the number of outputs is significantly lower than
the number of inputs.
In reviewing the state of the art, there is a clear need
for receiver front-end array architectures that perform
spatial interference mitigation in a manner that is flexi-
ble and tunable across frequency; benefits from CMOS
integration and technology scaling; has low cost, size,
and power consumption overhead; and does not sacrifice
the spatial degrees of freedom available in the array.
Section III describes research in this direction.
I II . A S CALABLE FOUR-ELEMENT MIMO
RECEIVER ARRAY W ITH S PATIO–
SPECTRAL INTE RFERENCE
MITIGATION
Since blockers that are outside the frequency band of in-
terest can be eliminated at analog/RF to some degree
through spectral bandpass filtering, the goal of spatial in-
terference mitigation is to address blockers that are
within the receive band by rejecting them based on their
angle of arrival, or in other words, performing spatial
notch filtering. Therefore, the desired receiver front-end
array depicted in Fig. 2(g) preserves all antenna inputs
 Krishnaswamy et al.: Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays

Fig. 3. SNF concept that performs impedance-domain beamforming at baseband to create spatial notches in input impedance. A
simulation of the incident-angle-dependent input impedance synthesized by the SNF in the prototype described in this paper is
also shown assuming a four-element uniform linear array with =2 antenna spacing.

at the output while imparting spectral bandpass filtering
and spatial notch filtering to them.
At the core of the proposed architecture is a spatial
notch filter (SNF) at baseband (Fig. 3). The SNF produces
an incident-angle-dependent input impedance that is rela-
tively low along a notch direction, and relatively high
along other directions. As will be described later in this
section, this input impedance of the SNF is translated to
the RF antenna interface, so that blockers along the notch
direction are reflected by a low input impedance, while
signals from other directions are absorbed by the array.
The operation of the SNF will now be described for a
notch at broadside incidence, but as will be described
later, the notch can be steered to any angle of incidence.
In the SNF (Fig. 3), in order to create a spatial notch,
the signals arriving from all antennas are tied to a single
node. When signals from all antennas arrive in-phase
with equal magnitude (broadside incidence or
¼ 0 ),
then in each path, a high impedance is seen, equal to N
times the resistive load at the common node, where N is
the number of antennas. However, when signals arrive
from other directions, for instance, endfire incidence
(
¼ 90 ), the signals from the different antennas will
be equal in magnitude but successively 180 out of
phase (assuming =2 spacing in a uniform linear array).
As a result, the common node will become a virtual
ground, and zero impedance is seen in each antenna
signal path. In other words, the impedance seen in each
antenna path (ZLi , i ¼ 1; . . . ; N) is incident-angle-
dependent and has a beam-like or “angle-pass” profile.
Since spatial notch filtering is desired, baseband
gyrators1 based on active circuitry may be employed to
invert the impedance to have a notch-like or “angle-stop”
profile (ZIN1 in Fig. 3). In other words, in the broadside
direction, a relatively low impedance will be seen in
each antenna signal path looking into the SNF, while in
other directions, a relatively high impedance will be
seen. Fig. 3 depicts a simulation of the SNF employed in
the prototype receiver front-end array described later in
this paper, with 510  presented to the first antenna at
baseband in the broadside (notch) direction and 3500 
presented at endfire.
While such an angle-stop impedance is synthesized at
baseband, it is desirable to be able to present such an im-
pedance at RF at the antenna interface so that spatial
blockers may be suppressed early in the receiver chain.
In the recent past, there has been exciting progress on
CMOS passive-mixer-based receivers that exhibit imped-
ance transparency, namely, an RF input impedance that
is dependent on and a translated version of the baseband
impedance [40], [51]. Since the translation is controlled
by the local oscillator (LO) frequency, the RF impedance
is tunable across frequency. Furthermore, a low-pass
baseband impedance with a low corner frequency effec-
tively translates to a high-Q spectral bandpass filter at
RF, enabling spectral blocker suppression at small fre-
quency offsets from the desired receiver band.
1
The gyrator is a circuit element whose input impedance is in-
versely proportional to its load impedance.

Vol. 104, No. 3, March 2016 | Proceedings of the IEEE 565

Krishnaswamy et al.: Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays

Fig. 4. GBMF receiver front-end block diagram along with simulations from the prototype described in this paper of the dependence
of input impedance and conversion gain on the baseband load resistance RBin . As RBin is reduced, due to the impedance transparency of
the passive mixer, the in-band input impedance presented to the antenna ( jZIN j at fLO ) reduces as well. The conversion gain of the front
end also reduces due to multiple factors—reduction of baseband load impedance, reduction of input impedance resulting in reflection
of the incident signal, and reduction of the RF amplifier gain ðAV;RF Þ due to the loading down of the amplifier through feedback.

Consequently, widely tunable receivers with impressive
resiliency to out-of-band spectral blockers have been
demonstrated by eliminating the front-end low-noise am-
plifier, and placing such a transparent passive mixer as
the first block in the receiver chain [40], with the im-
pedance transparency providing the input matching.
Noise-canceling architectures have been investigated
that lower the noise figure (NF) of such mixer-first re-
ceivers to sub-2-dB levels at RF [51]. Such widely tunable
receivers with integrated high-Q spectral filtering
potentially eliminate the fixed-frequency surface-acoustic-
wave (SAW) filters that are employed in conventional
commercial mobile wireless receivers. Recently, a gain-
boosted passive-mixer-first (GBMF) receiver front end
was proposed that places the passive mixer in feedback
around an RF amplifier [52]. The RF amplifier imparts
higher conversion gain to the otherwise completely
passive mixer, suppressing the noise of the subsequent
analog baseband circuitry. It also provides a Miller-
multiplication effect that reduces the required capaci-
tance in the baseband low-pass load impedance for a
given RF filter Q as well as the size of the passive mixer
switches and the associated LO-path power consumption.
Fig. 4 depicts the block diagram of the GBMF re-
ceiver front end used in the prototype described in this
paper, along with simulations of its performance. The in-
band input impedance ( ZIN at fLO , the LO frequency) is
a function of the baseband resistance RBin , indicating the
impedance transparency. The receiver bandwidth is set
by the baseband capacitor Cs ; outside the receiver band-
width, the low impedance of these capacitors translates
to a low input impedance at the antenna input, signifying
the high-Q input spectral filtering achieved through
transparency. Simulations of the spectral filtering are not
shown here, as these concepts are well established [40],
[51], [52]. In addition, conversion gain is also dependent
on the baseband resistance RBin . While conversion gain is
expected to be a function of the baseband load resistance
in a mixer, a low RBin also suppresses the input imped-
ance through the transparency discussed earlier, reflect-
ing the incident signal, and also loads down the RF
amplifier through feedback, reducing the voltage gain
across the amplifier AV;RF .
In the proposed MIMO receiver array architecture
(Fig. 5), each antenna path uses a GBMF receiver front
end loaded with the baseband SNF. The GBMF front
ends accomplish tunable high-Q spectral filtering, and
the incident-angle-dependent input impedance synthe-
sized in the SNF is translated to the antenna input by
the GBMF receiver front ends, accomplishing spatial
notch filtering right at the antenna inputs. Using the
notch-direction and outside-notch-direction input imped-
ance levels of 510  and 3500  from Fig. 3, Fig. 4 indi-
cates that through careful design of the GBMF receiver
front ends and the SNF, an absorptive in-band input im-
pedance of 50  can be provided outside the notch

566 Proceedings of the IEEE | Vol. 104, No. 3, March 2016

 Krishnaswamy et al.: Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays

Fig. 5. Block diagram of the fully integrated MIMO receiver front-end array with analog/RF spatio–spectral interference mitigation.

direction, while a (partially) reflective in-band input im-
pedance of 16.7  is provided in the notch direction.
This corresponds to approximately 6 dB of voltage sup-
pression at the antenna input. However, overall, the
conversion gain of the GBMF front end in Fig. 4 shows
> 10-dB suppression in the notch direction.
The active gyrator in the SNF is implemented using a
baseband operational transconductance amplifier (OTA)
with a feedback resistor ðRFB Þ. The extent of conversion
gain suppression is limited by feedback loop gain
considerations in this active gyrator, which limits the dif-
ference between the notch-direction and outside-notch-
direction input impedance levels. The finite switch re-
sistance and RF amplifier gain in the GBMF receiver
front ends also limit the effectiveness of the impedance
translation. The > 10-dB suppression, while already
substantial, can be increased further by using more ad-
vanced CMOS technology nodes that allow greater loop
gain in the gyrators within stability constraints and
lower switch resistance in the passive mixers for the
same LO-path power consumption. It should also be
noted that this spatial notch suppression is mainly effec-
tive within the receiver bandwidth, as outside the re-
ceiver bandwidth, the baseband capacitors Cs (i.e.,
spectral filtering) dominate the input impedance and
the conversion gain.
What is unique about the approach described here is
that spatial filtering is being achieved in the impedance
domain. This is distinct from conventional microwave
beamformers that are designed with isolation between
the different antenna signal paths (for instance, variable
gain amplifiers and phase shifters driving an isolating
Wilkinson combiner). While isolation is desirable to pre-
vent interactions between the paths, it prevents the input
impedance looking into the beamformer from depending
on the angle of incidence of the wave. The incident-angle-
dependent input impedance achieved in our approach
allows the benefits of spatial filtering to be passed on to

Vol. 104, No. 3, March 2016 | Proceedings of the IEEE 567

Krishnaswamy et al.: Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays

preceding blocks. While spatial notch filtering is common output node of the SNF across chips (on a PCB,
achieved at baseband, the resultant suppression is also for instance), spatial notch filtering would be effectively
translated to the antenna input and the output of the RF achieved across the entire larger array. Since the com-
amplifier in the GBMF receiver front end through im- mon output node is at baseband, it can inherently toler-
pedance transparency. Therefore, all nodes in the re- ate more parasitics in the board-level interconnects than
ceiver front end are protected. an RF node. Therefore, scalability is achieved without RF
The discussion above has focused on a spatial notch interconnections.
at broadside; however, the notch may be steered by
phase shifting the LOs of the different GBMF receiver
front ends relative to each other (Fig. 5). As described I V. MEASUREMENTS
earlier, after impedance inversion by the baseband gyra- A scalable 0.1–1.7-GHz four-element direct-conversion
tors, the SNF presents a low impedance to create a notch MIMO receiver array with spatio–spectral interference
if all the signals arrive at its inputs perfectly in phase. By mitigation has been implemented in TSMC 65-nm CMOS
shifting the phases of the LO signals, phase shifts are im- technology [53]. The block diagram of the chip is shown
posed on the received signals before they reach the SNF, in Fig. 5, and a microphotograph of the IC is shown in
thus steering the notch. The phase shifting of the LO sig- Fig. 6. The receiver array occupies 1.3 mm
1.3 mm of
nals is carried out through on-chip vector-modulator die area. The compact nature of the implemented IC is
phase shifters in the LO paths. Furthermore, while we enabled by the aforementioned design principles that
have focused the discussion on uniform linear arrays, the enable tunable operation over 0.1–1.7-GHz and spatio–
concept is equally applicable to nonuniform 2-D arrays spectral interference mitigation without the use of induc-
as well, as arbitrary phase shifts can be applied in each tors and transmission lines that are traditionally seen in
LO path. conventional microwave beamforming approaches. For
Since the objective is to provide spatial notch filter- all measurements described below, the chip is packaged
ing to interferers that are within the receiver band and in a commercial 64-pin QFN package and mounted on a
see gain throughout the receiver chain, additional sup- custom-designed printed circuit board (PCB).
pression beyond the > 10 dB that is achieved through The incident-angle-dependent input reflection coeffi-
the SNF is desired. To this end, we note that the com- cient of the four-element array is first characterized to
mon output node of the SNF is a node where a beam evaluate the effectiveness of the SNF in reflecting inter-
has been formed that points in the notch direction. In ference at the antenna interface. This input reflection
other words, this node contains the interference signal coefficient is obtained by measuring the two-port
but not the desired signal(s), and can be used to cancel
the interference residue left behind by the SNF. A
feedforward spatial notch canceller (FF SNC) (Fig. 5)
senses the voltage at the common node, scales it with
a tunable attenuator, and cancels the interference resi-
due in a feedforward fashion in each antenna’s base-
band analog signal path. Since the SNF has an
inverting gain to the common node, the phase condi-
tion for cancellation is automatically satisfied. Using
identical cells in the main and cancellation paths that
handle equal residue and replica interference signals
also ensures cancellation of distortion induced by the
residual interference in the cells. Since the FF SNC is
a feedforward canceller, the amount of suppression it
can impart is only limited by the resolution of the tun-
able attenuator and the phase matching condition
across the receiver bandwidth. Based on the required
amount of suppression and the rate at which conditions
such as supply voltage and temperature change, the at-
tenuator setting would need to be calibrated one time
or periodically.
Finally, a unique characteristic of the proposed archi-
tecture is its inherent scalability. Large arrays require
the tiling of multiple array RFICs. It is desirable to Fig. 6. Chip microphotograph of the 0.1–1.7-GHz scalable
achieve spatial filtering benefits across the larger array, four-element MIMO receiver array with spatio–spectral
rather than at a subarray level. By connecting the interference mitigation.

568 Proceedings of the IEEE | Vol. 104, No. 3, March 2016

 Krishnaswamy et al.: Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays

Fig. 7. (a) Incident-angle-dependent input reflection coefficient of the four-element receiver array at 0.602 GHz, assuming a uniform
linear array geometry with =2 spacing at 0.6 GHz and an LO frequency of 0.6 GHz. The SNF is enabled and tuned to broadside.
(b) Input reflection coefficient for broadside and endfire incidence as the LO is tuned across frequency (0.4, 0.6, and 0.8 GHz). The
assumed antenna spacing is also correspondingly changed.

network parameters of the four inputs pairwise, and
then mathematically computing the input reflection co-
efficient for plane waves arriving at the array at differ-
ent angles of incidence. The four elements are assumed
to be excited by a uniform linear array with =2 antenna
spacing at 0.6 GHz. The input signal is at 0.602 GHz,
within the bandwidth of the receiver, the LO signal is at
0.6 GHz, and the notch is tuned to broadside. Fig. 7(a)
shows that incident signal power is (partially) reflected
when the wave is incident from broadside, but is
absorbed for other angles of incidence. As described
earlier, the receiver array reflects spatial blockers by
presenting low impedance to the antenna array, result-
ing in smaller voltage swings at the input nodes and
therefore higher linearity in the notch direction. It
should also be mentioned that omnidirectional anten-
nas are assumed here, as well as in the other measure-
ments presented in this section, except for the wireless
imaging demonstration in Fig. 12, where real radiators
are employed. Fig. 7(b) shows the input reflection coeffi-
cient as the LO is tuned across frequency (the assumed
antenna spacing is also correspondingly changed) for
broadside and endfire incidence, verifying tunable opera-
tion across frequency.
Fig. 8 shows the measured spatio–spectral conversion
gain of the second element in the four-element receiver
array, with the LO frequency set to 0.5 GHz and the
four elements assumed to be excited by a uniform linear
array with =2 spacing at 0.5 GHz. In order to synthe-
size signals at the four inputs representative of an inci-
dent wavefront, a calibrated beamformer implemented
using discrete components on a PCB is used. While
Fig. 8(a) shows the 2-D conversion gain with both SNF
and FF SNC enabled and the notch tuned to broadside,
Fig. 8(b) shows a cross section versus angle of incidence
for in-band frequencies, and with the notch steered to
45 as well. Fig. 8(c) shows a cross section versus RF
input frequency. The measured in-band spatial response
shows a maximum of 32-dB rejection in a steerable notch
direction with both the SNF and FF SNC enabled, of
which 8 dB comes from the feedback-based SNF (close
to the simulated 10 dB). The measured spectral response
in the notch direction shows that the spectral filtering,
SNF, and FF SNC together enable blocker rejection of
more than 19 dB at all frequencies in the notch
direction.
In order to demonstrate scalability, two packaged
RFICs are tiled on a PCB with their baseband beam-
formed nodes tied together as described earlier. The
measured spatial notch suppression at in-band frequen-
cies exhibits the expected improved spatial selectivity of
an eight-element uniform linear array (Fig. 9), clearly
demonstrating the scalability feature.
Fig. 10(a) depicts the measured input-referred third-
order intercept point (IIP3) as a function of the offset of
the first of the two RF tones from the LO frequency. As
before, the four elements are assumed to be excited by a
uniform linear array with =2 spacing at 0.5 GHz. IIP3
measurements are depicted for both signals incident
from broadside and endfire. Both SNF and FF SNC are
enabled with the notch tuned to broadside. In the notch
direction, at in-band frequencies, it can be seen that IIP3
is significantly enhanced by as much as 34 dB. As the
two tone signals migrate to out-of-band frequencies, the
improvement in IIP3 is less substantial as discussed ear-
lier, but is still as high as 7 dB for a first-tone offset of
100 MHz (out-of-band IIP3 improves from þ11 to
þ18 dBm). Fig. 10(b) depicts the linearity as a function
of incidence angle for in-band and out-of-band frequen-
cies. For in-band frequencies, since signals experience
gain throughout the receiver chain, input-referred linear-
ity metrics such as IIP3 depend heavily on the receiver
gain. Therefore, output-referred IP3 (OIP3) is a better
metric that enables comparisons across designs featuring

Vol. 104, No. 3, March 2016 | Proceedings of the IEEE 569

Krishnaswamy et al.: Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays

Fig. 8. (a) Measured spatio–spectral conversion gain of the second element of the four-element receiver array. Both SNF and FF-SNC
are enabled and the notch is steered to broadside. (b) Cross section versus angle of incidence for in-band frequencies. The individual
contribution of the SNF is also shown, as are measurements when the notch is steered to 45 . (c) Cross section versus RF frequency
for broadside and endfire incidence.

different gains. The combination of the SNF and FF SNC In a traditional digital receiver array, the noise signals
improves the in-band OIP3 from þ0 dBm outside the at the outputs of the different receiver front-end ele-
notch angle to þ34 dBm at the notch angle. ments are uncorrelated (assuming that the input noise

Fig. 9. Conversion gain of the second element versus angle of incidence at in-band frequencies for a two-chip tile with (a) SNF enabled,
and (b) FF SNC additionally enabled. The notch is steered to broadside, and the eight elements are assumed to be excited by a uniform
linear array with =2 spacing at 500 MHz. The response of a single chip from Fig. 8 is also shown for comparison purposes.

570 Proceedings of the IEEE | Vol. 104, No. 3, March 2016

 Krishnaswamy et al.: Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays
Fig. 10. Measured two-tone linearity across frequency and angle of incidence, with the four elements assumed to be excited by a
uniform linear array with =2 spacing at 0.5 GHz: (a) measured IIP3 as a function of the offset frequency of the first tone for broadside
and endfire incidence, and (b) measured in-band OIP3 and out-of-band IIP3 as a function of incidence angle. For these measurements,
both SNF and FF SNC are enabled with the notch tuned to broadside.
signals are uncorrelated as well and ignoring the effects
of phase noise from a common LO) as there is no inter-
action between the different receiver front ends. There-
fore, single-element receiver noise figure (NF) can be
easily defined and measured. However, in this four-ele-
ment receiver, it is more tricky to evaluate the noise per-
formance, since the noise signals at the multiple outputs
are partially correlated due to the formation of a spatial
notch across the different elements. Therefore, in order
to define an equivalent single-element receiver NF, we
form a beam in the analog domain using the four array
outputs (away from the notch direction, along the end-
fire direction), and measure NF at the beam output with
respect to one of the array inputs with the other inputs
terminated with reference-impedance terminations. Sub-
tracting 10 log10 N (¼ 6 dB for N ¼ 4) from this mea-
sured array NF yields the equivalent single-element
receiver NF (Fig. 11). The equivalent single-element dou-
ble-sideband noise figure (NFDSB;eq ) ranges from 1.7 to 4.
Fig. 11. Measured equivalent single-element double-sideband
noise figure NFDSB;eq across the operating frequency range.
5 dB over the operating frequency range with both SNF
and FF SNC disabled. Enabling the SNF leads to 2–2.7-
dB NF DSB;eq , while enabling the FF SNC mildly in-
creases the noise figure to 2.2–4.6 dB. It is noteworthy
that aside from the low area and power overhead associ-
ated with the spatial notch filtering proposed in this
paper, the noise penalty is also minimal.
In order to demonstrate the benefits of analog/RF
spatio–spectral interference mitigation in a MIMO re-
ceiver array, a wireless imaging demonstration at
920 MHz is performed (Fig. 12). The receiver array is in-
terfaced with a 2
2 antenna array, and its analog base-
band outputs are digitized using an Agilent InfiniiVision
MSO7054A mixed-signal oscilloscope. The digitized out-
puts are streamed to a laptop computer so that digital
multibeamforming may be performed in MatLab. The an-
tenna array is irradiated with a weak desired signal in the
presence of a spatially distinct in-band 20 dB stronger
blocker. Twenty five simultaneous beams in a 5
5 array
are formed digitally in MatLab, with 30 coverage in each
direction. Note that the large number of beams results in
spatial overlap between them. An image is constructed
using the received signal strength on each beam for pixel
brightness. Without analog spatial rejection (SNF and FF
SNC), the receiver array outputs show clipping due to the
strong blocker. The desired signal cannot be detected on
the image. By enabling the SNF, the saturation of the re-
ceiver is prevented, but the blocker suppression is not suf-
ficient to discern the desired signal in the image.
Further enabling the FF SNC leads to higher blocker sup-
pression. Consequently, the blocker is no longer visible in
the image, and the desired weaker signal is clearly
detected.
Fig. 13 summarizes the performance of the prototype
and compares it to state-of-the-art RF CMOS (single-
output) phased array receivers. In addition to the new
Vol. 104, No. 3, March 2016 | Proceedings of the IEEE 571
Krishnaswamy et al.: Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays
Fig. 12. Wireless imaging demonstration exploiting digital multibeamforming with analog/RF spatial interference suppression.
functionality of preserving all receiver array outputs for
digital array processing while providing spatio–spectral
interference mitigation, this work demonstrates very
high in-band OIP3 after spatial suppression through the
successive SNF and FF SNC. The area and power over-
head associated with interference mitigation are low,
when the prototype is compared with the other single-
output phased arrays. The NF degradation associated
with spatial notch suppression is also notably minimal.
V. CONCLUSION AND T OPICS FOR
FUT URE RE SE ARCH
This paper has described techniques for analog and
RF spatio–spectral interference mitigation in integrated
digital MIMO receiver arrays. The techniques proposed
are flexible, tunable across operating frequency, and
572 Proceedings of the IEEE | Vol. 104, No. 3, March 2016
scalable; present low cost, size, and power consumption
overheads; and do not sacrifice the spatial degrees of
freedom available in the array. Experimental results
have been presented from a 0.1–1.7-GHz four-element
receiver front-end array IC prototype in 65-nm CMOS
technology. Further research on analog and RF interfer-
ence mitigation techniques is critical for the deployment
of cost-effective, power-efficient, large-scale MIMO
technology.
Several topics have been opened for future research.
The architecture presented in this paper is capable of
suppressing signals that arrive at the various antenna
elements with arbitrary phase shifts but equal magni-
tude. Such a signal distribution, specifically equal magni-
tudes with progressive phase difference, is seen for a
plane interference wave impinging on an antenna array;
however, in the presence of multipath, interference may
 Krishnaswamy et al.: Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays

Fig. 13. Performance summary and comparison to state-of-the-art CMOS RF phased array receivers.

appear at the various antenna elements with arbitrary
magnitude. Mutual coupling between antenna elements
may also produce a similar effect. It is therefore desir-
able to be able to suppress signals with arbitrary phase
and magnitude profiles across the different antennas.
Such a capability would also enable the formation of
multiple simultaneous notches for the suppression of
multiple interferers.
The passive-mixer-based approaches described in this
paper that translate the incident-angle-dependent imped-
ance synthesized by the baseband SNF to RF typically
have an upper limit of operating frequency governed by
the CMOS technology employed. The upper limit is a
fraction of the MOSFET switch speed in the CMOS
technology, and is typically around 2 GHz for 65-nm
CMOS. Techniques that extend operating frequency
to around 5 GHz are of interest, as higher frequencies
are likely to be exploited for massive MIMO deploy-
ments given the associated reductions in antenna aper-
ture sizes.
It is also interesting to consider integrated techniques
for self-interference cancellation (i.e., cancellation of
interference arising from the transmitter array of the
same system or platform) in MIMO receiver arrays for
coexistence and emerging full-duplex or simultaneous-
transmit-and-receive (STAR) applications [54]–[60]. h
Acknowledgment
The authors would like to thank DARPA Program
Manager Dr. T. Olsson for valuable discussions and
feedback.

Vol. 104, No. 3, March 2016 | Proceedings of the IEEE 573

Krishnaswamy et al.: Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays
REFERENCES
[1] A. Hajimiri, H. Hashemi, A. Natarajan,
X. Guan, and A. Komijani, “Integrated
phased array systems in silicon,” Proc. IEEE,
vol. 93, no. 9, pp. 1637–1655, Sep. 2005.
[2] A. Natarajan, A. Komijani, X. Guan,
A. Babakhani, and A. Hajimiri, “A 77-GHz
phased-array transceiver with on-chip
antennas in silicon: Transmitter and local
LO-path phase shifting,” IEEE J. Solid-State
Circuits, vol. 41, no. 12, pp. 2807–2819,
Dec. 2006.
[3] A. Babakhani, X. Guan, A. Komijani,
A. Natarajan, and A. Hajimiri, “A 77-GHz
phased-array transceiver with on-chip
antennas in silicon: Receiver and antennas,”
IEEE J. Solid-State Circuits, vol. 41, no. 12,
pp. 2795–2806, Dec. 2006.
[4] A. Natarajan, A. Komijani, and A. Hajimiri,
“A fully integrated 24-GHz phased-array
transmitter in CMOS,” IEEE J. Solid-State
Circuits, vol. 40, no. 12, pp. 2502–2514,
Dec. 2005.
[5] X. Guan, H. Hashemi, and A. Hajimiri,
“A fully integrated 24-GHz eight-element
phased-array receiver in silicon,” IEEE J.
Solid-State Circuits, vol. 39, no. 12,
pp. 2311–2320, Dec. 2004.
[6] H. Krishnaswamy and H. Hashemi,
“A variable-phase ring oscillator and PLL
architecture for integrated phased array
transceivers,” IEEE J. Solid-State Circuits,
vol. 43, no. 11, pp. 2446–2463, Nov. 2008.
[7] H. Krishnaswamy and H. Hashemi,
“A 4-channel 24–27 GHz UWB phased
array transmitter in 0.13 m CMOS for
vehicular radar,” in Proc. IEEE Custom
Integr. Circuits Conf., Sep. 2007,
pp. 753–756.
[8] A. Natarajan et al., “A fully-integrated
16-element phased-array receiver in SiGe
BiCMOS for 60-GHz communications,”
IEEE J. Solid-State Circuits, vol. 46, no. 5,
pp. 1059–1075, May 2011.
[9] A. Valdes-Garcia et al., “A fully integrated
16-element phased-array transmitter in SiGe
BiCMOS for 60-GHz communications,”
IEEE J. Solid-State Circuits, vol. 45, no. 12,
pp. 2757–2773, Dec. 2010.
[10] M. Tabesh et al., “A 65 nm CMOS
4-element sub-34 mW/Element 60 GHz
phased-array transceiver,” IEEE J. Solid-State
Circuits, vol. 46, no. 12, pp. 3018–3032,
Dec. 2011.
[11] B.-H. Ku et al., “A 77–81-GHz 16-element
phased-array receiver with 50 beam
scanning for advanced automotive radars,”
IEEE Trans. Microw. Theory Tech., vol. 62,
no. 11, pp. 2823–2832, Nov. 2014.
[12] K.-J. Koh and G. Rebeiz, “An X- and
Ku-band 8-element phased-array receiver in
0.18-m SiGe BiCMOS technology,” IEEE J.
Solid-State Circuits, vol. 43, no. 6,
pp. 1360–1371, Jun. 2008.
[13] K.-J. Koh, J. May, and G. Rebeiz, “A
millimeter-wave (40–45 GHz) 16-element
phased-array transmitter in 0.18-m SiGe
BiCMOS technology,” IEEE J. Solid-State
Circuits, vol. 44, no. 5, pp. 1498–1509,
May 2009.
[14] C.-Y. Kim, D.-W. Kang, and G. Rebeiz,
“A 44–46-GHz 16-element SiGe BiCMOS
high-linearity transmit/receive phased
array,” IEEE Trans. Microw. Theory Tech.,
vol. 60, no. 3, pp. 730–742, Mar. 2012.
[15] F. Golcuk, T. Kanar, and G. Rebeiz, “A 90–
100-GHz 4
4 SiGe BiCMOS polarimetric
transmit/receive phased array with
simultaneous receive-beams capabilities,”
574 Proceedings of the IEEE | Vol. 104, No. 3, March 2016
IEEE Trans. Microw. Theory Tech., vol. 61, [30] J. Andrews et al., “What will 5G be?” IEEE
no. 8, pp. 3099–3114, Aug. 2013. J. Sel. Areas Commun., vol. 32, no. 6,
pp. 1065–1082, Jun. 2014.
[16] O. Inac, D. Shin, and G. Rebeiz, “A phased
array RFIC with built-in self-test [31] A. Puglielli et al., “Design of energy- and
capabilities,” IEEE Trans. Microw. Theory cost-efficient massive MIMO arrays,”
Tech., vol. 60, no. 1, pp. 139–148, Proc. IEEE, vol. 104, no. 3, Mar. 2016,
Jan. 2012. DOI: 10.1109/JPROC.2015.2492539.
[17] M. Soer, E. Klumperink, B. Nauta, and [32] E. Fishler et al., “MIMO radar: An idea
F. van Vliet, “A 1.0-to-4.0 GHz 65 nm whose time has come,” in Proc. IEEE Radar
CMOS four-element beamforming receiver Conf., 2004, pp. 71–78.
using a switched-capacitor vector modulator [33] E. Fishler et al., “Spatial diversity in radars
with approximate sine weighting via charge models and detection performance,” IEEE
redistribution,” in IEEE Int. Solid-State Trans. Signal Process., vol. 54, no. 3,
Circuits Conf. Dig. Tech. Papers, Feb. 2011,
pp. 823–838, Mar. 2006.
pp. 64–66.
[34] B. Donnet and I. Longstaff, “MIMO radar,
[18] A. Ghaffari, E. Klumperink, F. van Vliet, techniques and opportunities,” in Proc. 3rd
and B. Nauta, “Simultaneous spatial Eur. Radar Conf., 2006, pp. 112–115.
and frequency-domain filtering at the
[35] C. J. Fulton, “Digital array radar calibration
antenna inputs achieving up to þ10 dBm
and performance monitoring techniques for
out-of-band/beam P1dB,” in IEEE Int.
direct conversion and dual polarization
Solid-State Circuits Conf. Dig. Tech. Papers,
architectures,” Ph.D. dissertation, Purdue
Feb. 2013, pp. 84–85.
Univ., West Lafayette, IN, USA, 2011.
[19] M. Soer, E. Klumperink, B. Nauta, and
[36] C. Fulton and W. Chappell, “Calibration
F. van Vliet, “A 1.0-to-2.5 GHz
techniques for digital phased arrays,” in
beamforming receiver with constant-Gm
Proc. IEEE Int. Conf. Microw. Commun.
vector modulator consuming G 9 mW per
Antennas Electron. Syst., Nov. 2009,
antenna element in 65 nm CMOS,” in IEEE
DOI: 10.1109/COMCAS.2009.5385979.
Int. Solid-State Circuits Conf. Dig. Tech.
Papers, Feb. 2014, pp. 66–67. [37] C. J. Fulton et al., “Digital phased arrays:
Challenges and opportunities,” Proc. IEEE,
[20] J. Roderick, H. Krishnaswamy, K. Newton,
vol. 104, no. 3, Mar. 2016, DOI: 10.1109/
and H. Hashemi, “Silicon-based ultra-wideband
JPROC.20152501804.
beam-forming,” IEEE J. Solid-State Circuits,
vol. 41, no. 8, pp. 1726–1739, Aug. 2006. [38] S. Patnaik, S. Kalia, B. Sadhu, M. Sturm,
M. Elbadry, and R. Harjani, “An 8GHz
[21] T.-S. Chu, J. Roderick, and H. Hashemi,
multi-beam spatio-spectral beamforming
“An integrated ultra-wideband timed array
receiver using an all-passive discrete time
receiver in 0.13 m CMOS using a
path-sharing true time delay architecture,”
analog baseband in 65nm CMOS,” in Proc
IEEE Custom Integr. Circuits Conf.,
IEEE J. Solid-State Circuits, vol. 42, no. 12,
Sep. 2012, pp. 1–4.
pp. 2834–2850, Dec. 2007.
[39] A. Ghaffari, E. Klumperink, M. Soer, and
[22] T.-S. Chu and H. Hashemi, “A CMOS UWB
B. Nauta, “Tunable high-Q N-path band-pass
camera with 7
7 simultaneous active
filters: Modeling and verification,” IEEE J.
pixels,” in IEEE Int. Solid-State Circuits Conf.
Solid-State Circuits, vol. 46, no. 5,
Dig. Tech. Papers, Feb. 2008, pp. 120–600.
pp. 998–1010, May 2011.
[23] H. Hashemi, T.-S. Chu, and J. Roderick,
[40] C. Andrews and A. Molnar, “A passive
“Integrated true-time-delay-based
mixer-first receiver with digitally controlled
ultra-wideband array processing,” IEEE
and widely tunable RF interface,” IEEE J.
Commun. Mag., vol. 46, no. 9, pp. 162–172,
Solid-State Circuits, vol. 45, no. 12,
Sep. 2008.
pp. 2696–2708, Dec. 2010.
[24] S. Garakoui, E. Klumperink, B. Nauta, and
[41] N. Reiskarimian and H. Krishnaswamy,
F. Van Vliet, “A 1-to-2.5 GHz phased-array
“Design of all-passive higher-order CMOS
IC based on gm-RC all-pass time-delay
N-path filters,” in Proc. IEEE Radio Freq.
cells,” in IEEE Int. Solid-State Circuits Conf.
Integr. Circuits Symp., May 2015, pp. 83–86.
Dig. Tech. Papers, Feb. 2012, pp. 80–82.
[42] H. Busignies and M. Dishal, “Some
[25] R. Tseng, H. Li, D. H. Kwon, Y. Chiu, and
relations between speed of indication,
A. S. Poon, “A four-channel beamforming
bandwidth, signal-to-random-noise ratio in
down-converter in 90-nm CMOS utilizing
phase-oversampling,” IEEE J. Solid-State
radio navigation and direction finding,”
Proc. IRE, vol. 37, no. 5, pp. 478–488,
Circuits, vol. 45, no. 11, pp. 2262–2272,
May 1949.
Nov. 2010.
[43] L. Franks and I. Sandberg, “An alternative
[26] S. M. Alamouti, “A simple transmit diversity
approach to the realization of network
technique for wireless communications,”
transfer functions: The N-path filter,” Bell
IEEE J. Sel. Areas Commun., vol. 16, no. 8,
Syst. Tech. J., vol. 39, no. 5, pp. 1321–1350,
pp. 1451–1458, Oct. 1998.
1960.
[27] V. Tarokh, N. Seshadri, and A. R. Calderbank,
[44] J. Butler and R. Lowe, “Beam-forming
“Space-time codes for high data rate wireless
matrix simplifies design of electronically
communication: Performance criterion and
scanned antennas,” Electron. Design,
code construction,” IEEE Trans. Inf. Theory,
pp. 170–173, Apr. 1961.
vol. 44, no. 2, pp. 744–765, Mar. 1998.
[45] J. Blass, “Multidirectional antenna—A new
[28] G. J. Foschini, “Layered space-time
approach to stacked beams,” in 1958 IRE
architecture for wireless communication
Int. Conv. Rec., vol. 8, pp. 48–50.
in a fading environment when using
multi-element antennas,” Bell Labs Tech. J., [46] J. Allen, “A theoretical limitation on the
vol. 1, no. 2, pp. 41–59, 1996. formation of lossless multiple beams in
linear arrays,” IRE Trans. Antennas Propag.,
[29] E. Larsson, O. Edfors, F. Tufvesson, and
vol. 9, no. 4, pp. 350–352, Jul. 1961.
T. Marzetta, “Massive MIMO for next
generation wireless systems,” IEEE [47] J. Shelton and K. Kelleher, “Multiple beams
Commun. Mag., vol. 52, no. 2, pp. 186–195, from linear arrays,” IRE Trans. Antennas
Feb. 2014. Propag., vol. 9, no. 2, pp. 154–161,
Mar. 1961.
 Krishnaswamy et al.: Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays

[48] B. Cetinoneri, Y. Atesal, and G. Rebeiz, “An
8
8 butler matrix in 0.13-m CMOS for
5–6-GHz multibeam applications,” IEEE
Trans. Microw. Theory Tech., vol. 59, no. 2,
pp. 295–301, Feb. 2011.
[49] C.-C. Chang, T.-Y. Chin, J.-C. Wu, and
S.-F. Chang, “Novel design of a 2.5-GHz
fully integrated CMOS butler matrix for
smart-antenna systems,” IEEE Trans. Microw.
Theory Tech., vol. 56, no. 8, pp. 1757–1763,
Aug. 2008.
[50] H. Krishnaswamy and H. Hashemi,
“A 4-channel 4-beam 24-to-26 GHz
spatio-temporal RAKE radar transceiver
in 90 nm CMOS for vehicular radar
applications,” in IEEE Int. Solid-State Circuits
Conf. Dig. Tech. Papers, Feb. 2010,
pp. 214–215.
[51] D. Murphy et al., “A blocker-tolerant,
noise-cancelling receiver suitable for
wideband wireless applications,” IEEE J.
Solid-State Circuits, vol. 47, no. 12,
pp. 2943–2963, Dec. 2012.
[52] Z. Lin, P.-I. Mak, and R. Martins, “A
0.028 mm2 11 mW single-mixing
blocker-tolerant receiver with double-RF
Npath filtering, S11 centering, þ13 dBm
OB-IIP3 and 1.5-to-2.9 dB NF,” in Proc.
IEEE Int. Solid-State Circuits Conf., Feb. 2015,
DOI: 10.1109/ISSCC.2015.7062913.
[53] L. Zhang, A. Natarajan, and H. Krishnaswamy,
“A scalable 0.1-to-1.7 GHz spatio-spectral-
filtering 4-element MIMO receiver array with
spatial notch suppression enabling digital
beamforming,” in IEEE Int. Solid-State Circuits
Conf. Dig. Tech. Papers, Feb. 2016,
pp. 166–167.
[54] J. Zhou, A. Chakrabarti, P. Kinget, and
H. Krishnaswamy, “Low-noise active
cancellation of transmitter leakage and
transmitter noise in broadband wireless
receivers for FDD/co-existence,” IEEE J.
Solid-State Circuits, vol. 49, no. 12,
pp. 3046–3062, Dec. 2014.
[55] D. Bharadia and S. Katti, “Full duplex
MIMO radios,” in Proc. 11th USENIX Conf.
Netw. Syst. Design Implement., 2014,
pp. 359–372.
[56] J. Zhou, T.-H. Chuang, T. Dinc, and
H. Krishnaswamy, “Integrated wideband
self-interference cancellation in the RF
domain for FDD and full-duplex wireless,”
IEEE J. Solid-State Circuits, vol. 50, no. 12,
pp. 3015–3031, Dec. 2015.
[57] D.-J. van den Broek, E. Klumperink, and
B. Nauta, “An in-band full-duplex radio
receiver with a passive vector modulator
downmixer for self-interference
cancellation,” IEEE J. Solid-State Circuits,
vol. 50, no. 12, pp. 3003–3014, Dec. 2015.
[58] T. Dinc, A. Chakrabarti, and
H. Krishnaswamy, “A 60 GHz same-channel
full-duplex CMOS transceiver and link
based on reconfigurable polarization-based
antenna cancellation,” in Proc. IEEE Radio
Freq. Integr. Circuits Symp., May 2015,
pp. 31–34.
[59] A. T. Wegener and W. Chappell,
“Simultaneous transmit and receive with
a small planar array,” in IEEE MTT-S
Int. Microw. Symp. Dig., Jun. 2012,
DOI: 10.1109/MWSYM.2012.6259663.
[60] A. Wegener and W. Chappell, “Coupled
antenna scheme using filter design
techniques and tunable resonators to show
simultaneous transmit and receive,” in IEEE
MTT-S Int. Microw. Symp. Dig., Jun. 2013,
DOI: 10.1109/MWSYM.2013.6697668.

ABOUT THE AUTHORS

Harish Krishnaswamy (Member, IEEE) received Linxiao Zhang (Student Member, IEEE) received
the B.Tech. degree from the Indian Institute of the B.S. degree in electrical and electronics engi-
Technology, Madras, India, in 2001 and the M.S. neering from Nanyang Technological University,
and Ph.D. degrees from the University of South- Singapore, in 2011. He is currently working toward
ern California (USC), Los Angeles, CA, USA, in the Ph.D. degree in the Electrical Engineering De-
2003 and 2009, respectively, all in electrical partment, Columbia University, New York, NY, USA.
engineering. He interned at the Institute of Microelectron-
In 2009, he joined the Department of Electri- ics, Singapore, for five months in 2009. In sum-
cal Engineering, Columbia University, New York, mer 2013, he interned at Mediatek. His research
NY, USA, where he is currently an Associate Pro- interests include wideband/software-defined ra-
fessor. His research interests include integrated devices, circuits, and dio with an emphasis on multiple-antenna systems.
systems for a variety of RF, millimeter-wave, and submillimeter-wave Mr. Zhang received the EE MS Award of Excellence from the
applications. Columbia University Electrical Engineering Department in May 2013.
Dr. Krishnaswamy serves as a member of the Technical Program
Committee (TPC) of several conferences, including the IEEE Interna-
tional Solid-State Circuits Conference (2015/2016–present) and the IEEE
RFIC Symposium (2013–present). He was the recipient of the IEEE Inter-
national Solid-State Circuits Conference (ISSCC) Lewis Winner Award
for Outstanding Paper in 2007, the Best Thesis in Experimental Re-
search Award from the USC Viterbi School of Engineering in 2009, the
Defense Advanced Research Projects Agency (DARPA) Young Faculty
Award in 2011, a 2014 IBM Faculty Award, and the 2015 IEEE RFIC Sym-
posium Best Student Paper Award—First Place.

Vol. 104, No. 3, March 2016 | Proceedings of the IEEE 575