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1 Constraints Coding Rules
1 Constraints Coding Rules
1 Constraints Coding Rules
1
Constraints Coding Rules
Introduction
This chapter presents reference information for the rules contained in the Constraints policy
for the Leda Checker tool. This policy specifies general-purpose rules that cover many aspects
of Synopsys Design Constraint (SDC) files and their relationships to the designs that they
constrain. For information on how to use the SDC checker, see the Leda User Guide.
The rules in the Constraints policy are grouped by type into the following rulesets. Each ruleset
imposes constraints on different aspects of SDC file constraints (see Table 2).
Table 2: Constraints Policy Rulesets
Ruleset Description
Rules for consistency and completeness in the usage of constraints defined
with create_clock, create_generated_clock, set_propagated_clock,
Clocks
set_clock_transition, set_input_transition, set_driving_cell, set_clock_latency,
Ruleset
and set_clock_uncertainty SDC file commands used to constrain real and
generated clocks in the design.
Rules to check for consistency in the usage of constraints between the top
TVB Ruleset
block and other sub blocks of a design.
Ruleset includes checks associated with SDC DFT commands, used in test-
DFT Ruleset
mode SDC files.
DRC Ruleset Rules that deal with DRC of the design.
Exceptions Ruleset includes checks related to SDC timing exceptions commands like
Ruleset set_false_path, set_multicycle_path, set_disable_timing etc.
Inputs Rules for consistency and completeness in the usage of set_input_delay,
Ruleset set_input_transition and set_driving_cell SDC commands.
Naming
Rules for naming clocks, ports, and pins.
Ruleset
Outputs Rules for consistency and completeness in the usage of set_output_delay
Ruleset SDC commands.
Power
Rules that deal with power of the design
Ruleset
Structure
Rules that deal with structure of the design.
Ruleset
Miscellaneous Rules that are miscellaneous in nature and that does not fall under any of the
Ruleset above mentioned rulesets.
Objects Rules that deal with objects that should not be used with create_clock and
Ruleset create_generated_clock commands.
Equivalency
Rules that deal with the equivalency of two SDC files.
Ruleset
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Clocks Ruleset
The following rules are from the Clocks ruleset:
SDC_CLK01
Every clock in the design must be defined in the SDC file using either a
create_clock or create_generated_clock command. This information needs to be
passed to synthesis and post-synthesis tools, because clocks are treated as
special nets in the design flow. For example, if you don't specify a definition and
Description
other information on clock nets in your constraint file for DC, the synthesis tool
may treat the clock signal like any other net, thus requiring another iteration
with DC.Leda's output points to the signal inferred as a clock and the Path
Viewer shows a path from this signal to a flip-flop.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows a portion of an SDC file and the associated design file. Leda flags this
combination as a rule violation because the SDC file does not contain a definition for the
second clock in the design. Every clock has to be present in your SDC file. In this case, Leda
infers a clock that has no corresponding constraint in the SDC files checked. If a register has
no clock in the constraint file, Leda cannot verify paths to this register.
// SDC File
create_clock -name CLK1 -period 10 [get_pins clk1]
// Design File
module CLK01(clk1, clk2, in1, in2, out1, out2);
input clk1;
input clk2;
input in1, in2;
output out1, out2;
reg out1, out2;
always @(posedge clk1)
begin
out1 <= in1;
end
always @(negedge clk2)
begin
out2 <= in2;
end
endmodule
SDC_CLK02
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Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows a constraint file that has a create_clock command for a clock that is not
used in the design. Leda flags an error for the unused clock constraint:
// SDC File
create_clock -name CLK -period 2 [get_ports CLKIN]
create_generated_clock -name GCLK1 -source [get_ports CLKIN] -divide_by
2 [get_pins Q0]
create_generated_clock -name GCLK2 -source [get_pins Q0] -divide_by 2
[get_pins Q1]
create_clock -name ECLK -period 2 [get_ports D0]
# SDC_CLK02 violation--ECLK is an extra clock
// Design File
module CLK02(D0, D1, D2, CLKIN, Q);
input D0, D1, D2, CLKIN;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D0;
always @(posedge Q0)
Q1 <= D1;
always @(posedge Q0)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN)
Q <= SR2;
endmodule
SDC_CLK03
Each generated clock should be driven by a master clock in the design. For each
create_generated_clock command in the SDC files you check, Leda traces
backward from the generated clock node in the design until the master clock
Description
node is reached. If it is never reached, Leda flags an error giving the source
position of the create_generated_clock constraint, as well as the master clock
and generated clock full path names.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
Leda flags an error for this example because the generated clock for Q1 is not driven by the
design master clock.
// SDC File
create_clock -name CLK -period 5.0 -waveform {0.0 2.5} [get_ports CLKIN]
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create_clock -name CLK1 -period 7.0 -waveform {0.0 2.5} [get_ports
CLKIN1]
create_generated_clock -name GCLK1 -source [get_ports CLKIN] -divide_by
2 [get_pins Q0]
create_generated_clock -name GCLK2 -source [get_ports CLKIN_1] -
divide_by 2 [get_pins D0]
// Design File
module CLK02(D0, D1, D2, CLKIN, CLKIN_1, Q);
input D0, D1, D2, CLKIN, CLKIN_1;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D0;
always @(posedge Q0)
Q1 <= D1;
always @(posedge Q0)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN_1)
Q <= SR2;
endmodule
The following circuit diagrams illustrate valid and invalid designs using generated clocks. Leda
flags an error for rule SDC_CLK03 when it infers an error case like the one shown below.
SDC_CLK04
This rule makes sure that the pin referred to in the -source option for the
create_generated_clock command is really a clock. If it isn't, Leda flags an error
Description and points to the generated_clock declaration and the master clock (source)
declaration. The Path Viewer shows the path from the generated clock to its
designated master clock.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
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This example causes Leda to flag an error because the driver for GCLK is an input pin, but not
a clock:
// SDC File
create_clock -name CLK -period 5.0 -waveform {0.0 2.5} [get_ports CLKIN]
create_generated_clock -name GCLK -source DATAIN -divide_by 2 [get_pins
FF0/Q]
# SDC_CLK04 violation--driver for GLCK not a clock
// Design File
module CLK04 ( D0, D1, D2, CLKIN, CLKIN1, Q );
input D0;
input D1;
input D2;
input CLKIN;
input CLKIN1;
output Q;
wire Q0, Q1, SR0, SR1, SR2;
GTECH_FD1 Q_reg ( .D(SR2), .CP(CLKIN1), .Q(Q) );
GTECH_FD1 SR2_reg ( .D(SR1), .CP(Q1), .Q(SR2) );
GTECH_FD1 SR1_reg ( .D(SR0), .CP(Q1), .Q(SR1) );
GTECH_FD1 SR0_reg ( .D(D2), .CP(Q0), .Q(SR0) );
GTECH_FD1 Q1_reg ( .D(D1), .CP(Q0), .Q(Q1) );
GTECH_FD1 Q0_reg ( .D(D0), .CP(CLKIN), .Q(Q0) );
endmodule
SDC_CLK06
Message: Overlapping clock trees: path from clock source to leaf cell
clock is not unique
This rule flags if there is more than one path from clock source (obtained from
Description
create_clock/create_generated_clock) to clock pins of sequential elements.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
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// SDC File
create_clock -name CLK -period 10 -waveform {0 5} [get_ports clk]
// Design File
module mid ( c1, c2, d, q );
input c1;
input c2;
input d;
output q;
wire w5;
SDC_CLK07
This rule flags violation if any net in clock tree is connected to output port
Description
without dedicated buffering.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
// SDC File
create_clock -name CLOCK1 -period 10 [get_ports CLK1]
create_clock -name CLOCK2 -period 15 [get_ports CLK2]
create_clock -name CLOCK3 -period 20 [get_ports CLK3]
# SDC_CLK07 violation
// Design File
module mSDC_CLK07 (D, CLK1, CLK2, CLK3, EN, Q1, Q2, Q3, outClk1,
outClk2, outClk3, outClk4);
input D, CLK1, CLK2, CLK3, EN;
output outClk1, outClk2, outClk3, outClk4;
output Q1, Q2, Q3;
reg Q1, Q2, Q3;
wire w1,w2,w3;
assign outClk1 = CLK1 & EN;
always@(posedge outClk1) Q1 <= D;
assign w1 = CLK2 | EN;
always@(posedge w1) Q2 <= D;
assign outClk2 = !w1;
assign w2 = CLK3 & EN;
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buf inst0(outClk3, w2);
buf inst1(w3, outClk3);
always@(posedge w3) Q3 <= D;
endmodule
SDC_CLK08
If a generated clock is a port, then the slope on that port and the delays in the
clock tree depend strongly on the load capacitance of that port. When Leda
finds a violation of this rule, the output shows the generated_clock declaration,
Description
master clock (source) declaration, and the declaration of the port referenced by
the constraint. The Path Viewer shows the path from port identified as a
generated clock to the master clock.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows an SDC file with a generated clock that is a design port.
// SDC File
create_clock -name CLK -period 5.0 -waveform {0.0 2.5} [get_ports CLKIN]
# SDC_CLK08 violation
create_clock -name CLK -period 5.0 -waveform {0.0 2.5} [get_ports CLKIN]
create_generated_clock -name GCLK1 -source [get_ports D2] -divide_by 2
[get_pins CLK08.Q]
// Design File
module clk08(D0, D1, CLKIN, GCLK, Q, Q1);
input D0, D1, CLKIN;
inout GCLK;
output Q, Q1;
reg Q, TMP;
reg Q0, Q1;
SDC_CLK09
If the source pin of a clock GCLK is in the fanout of the source pin of another
clock CLK, then GCLK should be generated by CLK. When Leda flags a violation
of this rule, the output points to the generated_clock declaration, master clock
Description
(source) declaration, and the declaration of the port referenced by the
constraint. The Path Viewer shows the path from the generated clock to the real
master clock (primary input).
Policy Constraints
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Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows valid and invalid circuit diagrams relative to the SDC file.
// SDC File
create_clock -name CLK -period 5.0 [get_ports CLKIN]
create_generated_clock -name GCLK -source CLKIN -divide_by 2 [get_pins
FF0/Q]
SDC_CLK10
In the post-layout timing analysis constraint file, real and generated clocks need
to be set as propagated clocks (this rule does not apply to virtual clocks).
Because the clock tree has already been synthesized, setting propagated clocks
Description
is necessary for accurate timing analysis. With this rule selected, Leda checks
that all real and generated clocks are constrained by set_propagated_clock
commands in the post-layout SDC file.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows a post-layout SDC file that is missing the set_propagated_clock
commands required for accurate timing analysis.
// SDC File
create_clock -name CLKIN -period 10 [get_ports clk1]
create_generated_clock -name GCLK1 -source clk1 [get_pins clk2]
# SDC_CLK10 violation--no set_propagated_clock command in post-layout
//Design File
module clk10(D1, clk1, Q);
input D1, clk1;
output Q;
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reg Q, clk2;
always @(posedge clk1)
clk2 = D1;
always @(posedge clk2)
Q = 1;
endmodule
SDC_CLK11
In a pre-layout SDC file, the clock tree is not yet synthesized, so setting it as
propagated clock is premature. Using set_propagated_clock commands in this
Description mode may cause the timing analysis tool to unnecessarily calculate delays for
an ideal clock network. This rule applies to both real and generated clocks in
pre-layout mode.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
SDC_CLK12
This rule flags violation if the clock is defined on a signal, which is neither port
Description
nor a leaf cell pin.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
// SDC File
create_clock -name CLK1 -period 10 [get_ports CLKIN]
create_clock -name CLK2 -period 10 [get_pins Q3_reg/CP]
create_clock -name CLK3 -period 10 [get_pins inst0/CP]
# SDC_CLK12 violation
create_generated_clock -name CLK4 -source [get_pins inst0/CP] [get_pins
inst1/CP] -divide_by 2
// Design File
module mSDC_CLK12 ( D0, D1, D2, CLKIN, CLKIN1, Q1, Q2, Q3 );
input D0;
input D1;
input D2;
input CLKIN;
input CLKIN1;
output Q1;
output Q2;
output Q3;
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wire Q0;
SDC_CLK13
Message: Virtual clock has no corresponding real clock with the same
period and waveform
Every virtual clock defined in constraint file should have a real clock with same
Description
period and waveform values.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
// SDC File
create_clock -name VCLOCK0 -period 10 -waveform {5 9}
create_clock -name VCLOCK1 -period 15
create_clock -name VCLOCK2 -period 20 -waveform {5 10}
# SDC_CLK13 violation
create_clock -name CLOCK0 -period 10 -waveform {5 10} [get_ports CLK0]
create_clock -name CLOCK1 -period 10 [get_ports CLK1]
create_clock -name CLOCK2 -period 20 -waveform {5 10} [get_ports CLK2]
// Design File
module mSDC_CLK13 (D0, D1, D2, CLK0, CLK1, CLK2, Q);
input D0, D1, D2, CLK0, CLK1, CLK2;
output Q;
reg Q0, Q1, Q2;
always @(posedge CLK0)
Q0 <= D0;
always @(posedge CLK1)
Q1 <= D1;
always @(posedge CLK2)
Q2 <= D2;
assign Q = Q0 | Q1 | Q2;
endmodule
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SDC_CLK14
Constraint file clock definitions should specify the period and waveform of the
Description clock. This information is needed by timing analysis and synthesis tools for their
internal delay calculations.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
SDC_CLK15
Generated clock definitions in SDC files must contain one of the options: -
divide_by, -multiply_by, -invert, -edge_shift or -edge. This defines the
Description relationship between the source and generated clocks. The absence of this
information may lead to incorrect timing results during timing analysis and
synthesis.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
SDC_CLK16
Example
This example causes Leda to flag a warning because the create_generated_clock command is
having -divide_by and -multiply_by options.
// SDC File
create_clock -name CLK [get_ports CLKIN] -waveform {5 10} -period 15
# SDC_CLK16 violation
create_generated_clock -name GCLK1 -source [get_ports CLKIN] Q0
-divide_by 2
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create_generated_clock -name GCLK2 -source Q0 -divide_by 2 Q1
-multiply_by 3
// Design File
module mSDC_CLK16 (D0, D1, D2, CLKIN, Q);
input D0, D1, D2, CLKIN;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D0;
always @(posedge Q0)
Q1 <= D1;
always @(posedge Q0)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN)
Q <= SR2;
endmodule
SDC_CLK17
Example
This example causes Leda to flag a warning because the create_generated_clock command is
having -edges option.
// SDC File
create_clock -name CLK [get_ports CLKIN] -waveform {5 10} -period 15
# SDC_CLK17 violation
create_generated_clock -name GCLK1 -source [get_ports CLKIN] Q0 -edges
{1 3 5}
create_generated_clock -name GCLK2 -source Q0 -divide_by 2 Q1
// Design File
module mSDC_CLK17 (D0, D1, D2, CLKIN, Q);
input D0, D1, D2, CLKIN;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D0;
always @(posedge Q0)
Q1 <= D1;
always @(posedge Q0)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN)
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Q <= SR2;
endmodule
SDC_CLK18
Example
This example causes Leda to flag an error because the create_generated_clock command is
having -add and -master_clock option.
// SDC File
create_clock -name CLK [get_ports CLKIN] -waveform {5 10} -period 15
# SDC_CLK18 violation
create_generated_clock -name GCLK1 -source [get_ports CLKIN] -divide_by
2 Q0 -add
create_generated_clock -name GCLK2 -source Q0 -divide_by 2 Q1 -
master_clock [get_ports CLKIN]
// Design File
module mSDC_CLK18 (D0, D1, D2, CLKIN, Q);
input D0, D1, D2, CLKIN;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D0;
always @(posedge Q0)
Q1 <= D1;
always @(posedge Q0)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN)
Q <= SR2;
endmodule
SDC_CLK20
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SDC_CLK23
Example
This example causes Leda to flag an error because create_clock command is not having -
period option.
// SDC File
# SDC_CLK23 violation
create_clock -name VCLK
create_clock -name CLK [get_ports CLKIN] -waveform {5 10}
create_generated_clock -name GCLK1 -source [get_ports CLKIN] -divide_by
2 Q0
create_generated_clock -name GCLK2 -source Q0 -divide_by 2 Q1
// Design File
module mSDC_CLK23 (D0, D1, D2, CLKIN, Q);
input D0, D1, D2, CLKIN;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D0;
always @(posedge Q0)
Q1 <= D1;
always @(posedge Q0)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN)
Q <= SR2;
endmodule
SDC_CTR01
In RTL and pre-layout modes, clock transition values must be defined in the
constraint file using set_clock_transition commands. Because a clock tree is
ideal, the clock transition should be supplied using set_clock_transition
Description command for timing analysis. Without information about clock transition values,
you may get incorrect results in timing analysis and a design that does not
optimize properly during synthesis. This rule fires for real clocks and generated
clocks.
Policy Constraints
Ruleset Clocks
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Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows an SDC file for an RTL or pre-layout design that does not contain the
required set_clock_transition commands:
// SDC File
create_clock -name CLK -period 10 [get_ports clk]
create_generated_clock -name GCLK -source [get_ports clk] -divide_by 2
[get_pins clk1]
set_propagated_clock { CLK GCLK }
# SDC_CTR01 violation for CLK
// Design File
module CTR01(in1, in2, clk, out);
input in1, in2, clk;
output out;
reg out;
reg clk1;
SDC_CTR02
Example
This example shows an RTL or pre-layout SDC file that uses a set_clock_tansition command on
a design object that is not a clock:
// SDC File
create_clock -name CLK -period 10 [get_ports clk]
create_generated_clock -name GCLK -source [get_ports clk] -divide_by 2
[get_pins clk1]
set_propagated_clock { CLK GCLK }
set_clock_transition 0.0 -rise {in1}
# SDC_CTR02 violation--use of set_clock_transition on object that is not
a clock
SDC_CTR04
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Get all the clock pins of leaf level cells. For each clock pin if the constraint
Description
set_annotated_transition is not set on it then flag a violation.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
SDC_CTR06
Example
This example shows part of an SDC file for post-layout mode. This SDC file causes Leda to flag
an error.
// SDC File
create_clock -name CLK -period 10 [get_ports clk]
create_generated_clock -name GCLK -source [get_ports clk] -divide_by 2
[get_pins clk1]
# SDC_CTR06 violation--no set_input_transition command for real clock
SDC_CTR08
In post-layout mode, the clock tree is synthesized and net transition values can
be calculated from the synthesized netlist. Therefore, only external port
transition values need to be set in post-layout mode. After the clock tree
network is synthesized, the clock port needs to be treated like any other port,
Description
using set_input_transition commands to set transition values instead of
set_clock_transition commands.Note that if there are both set_input_transition
and set_clock_transition commands in the SDC file, this rule fires on the
set_clock_transition command.
Policy Constraints
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Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This post-layout SDC file example causes Leda to flag an error, because the clock port
transition values in this mode should be set with set_input_transition commands, not
set_clock_transition commands.
// SDC File
create_clock -name CLK -period 10 [get_ports clk]
set_clock_transition 0.0 CLK
# SDC_CTR08 violation--set_clock_transition for clock signal in post-
layout mode.
SDC_CTR09
Generally, during the pre-layout stage, the clock net is ideal. So, using the
set_input_transition and set_driving_cell commands for the clock is not
recommended. Instead, use set_clock_transition commands. Leda checks this
Description rule for both real and generated clocks in pre-layout mode. When Leda finds
violations of this rule, the output points to set_input_transition and
set_driving_cell commands for clocks defined using create_clock or
create_generated_clock commands.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows the use of a set_input_transition command for a clock in pre-layout
mode, which causes Leda to flag an error.
// SDC File
create_clock -name CLK -period 10 clk
set_input_transition 1.0 clk
# SDC_CTR09 violation--set_input_transition for clock in pre-layout
mode.
SDC_CTR10
Description In post-layout mode, Leda fires for this rule when it finds real or generated
clocks set with the set_driving_cell command. The output points to
set_input_transition and set_driving_cell commands for clocks defined using
create_clock or create_generated_clock commands. In post-layout mode it is
better to use the set_input_transition commands.Setting a drive on a clock port
can create problems. With an ideal clock there is a 0 ns propagation delay and
thus the drive strength is ignored; however, there is a transition delay. Since the
load on the clock is large, the transition delay is huge. The non-linear delay
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model tables in the library are not characterized to handle such huge transition
delays. As a result, there might be a negative propagation delay. Moreover, the
nonlinear delay model allows a cell's output pin transition to depend on the
transition on the input. The set_driving_cell command does not specify what
input transition to use when calculating the port delay. Leda assumes a zero
transition. This means that the port delay will be slightly optimistic for driving
cells where output transition depends on input transition.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
SDC_CTR11
In RTL or pre-layout mode, clock transitions should be specified using both the
max and min values and both the rise and fall values to give more information
Description to the timing analysis and synthesis tools. This rule applies to clocks and
generated clocks. When Leda flags a violation of this rule, the output points to
the set_clock_transition command with incomplete options.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example SDC file for a pre-layout design shows the use of a min value without also
specifying a max value for the clock.
// SDC File
create_clock -name CLK -period 10 [get_ports clk]
set_clock_transition 0.0 -min CLK
# SDC_CTR11 violation--no max specified for clock
This next example SDC file for a pre-layout design shows the use of a rise value without also
specifying a fall value for the clock.
// SDC File
create_clock -name CLK -period 10 [get_ports clk]
set_clock_transition 0.0 -rise CLK
# SDC_CTR11 violation--no fall specified for clock
SDC_CTR12
In post-layout mode, clock input transitions should be specified using both the
max and min values and both the rise and fall values to give more information
Description to the timing analysis and synthesis tools. This rule applies to clocks and
generated clocks. When Leda flags a violation of this rule, the output points to
the set_input_transition command with incomplete options.
Policy Constraints
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Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
SDC_CTR13
This rule will flag violation if min value specified in clock transition is greater
Description
than max.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to flag an error because the min value is greater than the max
value in set_clock_transition and set_input_transition command.
// SDC File
create_clock -name CLK -period 10 [get_ports CLKIN]
create_generated_clock -name GCLK -source [get_ports CLKIN]
-divide_by 2 Q1
// Design File
module mSDC_CTR13 (D1, D2, D3, D4, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3, D4;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2&D4;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_CTR14
Description This rule will flag violation if -clock or -clock_fall options are specified in
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set_input_transition.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to flag an error because -clock and -clock_fall options are present.
// SDC File
create_clock -name CLK -period 10 [get_ports CLKIN]
create_generated_clock -name GCLK -source [get_ports CLKIN]
-divide_by 2 Q1
# SDC_CTR14 violation
set_input_transition 2.5 [get_clocks CLK] -clock_fall
set_input_transition 1.5 [get_clocks GCLK] -clock [get_clocks CLK]
// Design File
module mSDC_CTR14 (D1, D2, D3, D4, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3, D4;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2&D4;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_CTR15
Description This rule flags violation if the value specified in clock transition constraint is < 0.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to flag an error because the value specified in set_clock_transition
command is negative.
// SDC File
create_clock -name CLK -period 10 [get_ports CLKIN]
create_generated_clock -name GCLK -source [get_ports CLKIN] -divide_by 2
Q1
#RTL & G-pre
# SDC_CTR15 violation
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set_clock_transition -2.5 [get_clocks GCLK]
#G-Post
set_input_transition -1.5 [get_ports CLKIN]
set_input_transition -1.6 [get_ports D1]
// Design File
module mSDC_CTR15 (D1, D2, D3, D4, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3, D4;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2&D4;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_LAT01
Message: Undefined clock latency or zero clock latency for real clocks:
%s
In RTL or pre-layout mode, the clock latency for real clocks cannot be zero or
left unspecified. To model the propagation of the clock signal through the clock
Description tree from the root pin to the leaf pins, a latency must be defined for every
clock. This is mandatory to ensure alignment between ideal and propagated
clock timing analysis and the optimization environment.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This SDC file example shows a properly specified clock latency, as illustrated in the following
circuit diagram.
// SDC File
create_clock -name CLK -period 5.0 [get_ports CLKIN]
set_clock_latency 1.5 [get_clocks CLK]
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SDC_LAT02
Setting clock latencies on design objects that are not clocks may cause
Description
problems for timing analysis and synthesis tools.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This SDC file contains examples of valid and invalid create_clock commands. Leda flags the
invalid cases as errors and points to them in the Checker output.
// SDC File
create_clock -name CLK -period 10 [ger_ports clk]
set_clock_latency 1.0 [get_clocks clk]
set_clock_latency 1.0 [get_clocks d] #Error, d is not a clock
# SDC_LAT02 violation--clock latency set for object that is not a clock
// Design File
module ITR07 (clk, d, q);
parameter nb_bit = 8;
input clk;
input [1: nb_bit] d;
output [1: nb_bit] q;
reg [1: nb_bit] q;
SDC_LAT03
The latency of a generated clock has to be greater than its source clock latency.
Description Otherwise, Leda flags an error because this can cause poor quality of results
from timing analysis and synthesis tools.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This SDC file example shows a properly specified clock latency for a generated clock, as
illustrated in the following circuit diagram.
// SDC File
create_clock -name CLK0 -period 5.0 -waveform {0.0 2.5} [get_ports
CLKIN]
create_generated_clock -name CLK -source [get_ports CLKIN] -divide_by 2
[get_pins FF0/Q]
create_generated_clock -name GCLK -source [get_pins FF0/Q] -divide_by 2
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[get_pins FF1/Q]
set_clock_latency -source 1.0 [get_clocks CLK]
set_clock_latency -source 2.0 [get_clocks GCLK]
SDC_LAT05
The rule will flag violation if set_clock_latency is used in constraint file for post-
Description
layout analysis.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
// SDC File
create_clock -name CLK0 -period 5.0 -waveform {0.0 2.5} [get_ports
CLKIN]
create_generated_clock -name GCLK1 -source [get_ports CLKIN]
-divide_by 2 Q0
create_generated_clock -name GCLK2 -source Q0 -divide_by 2 Q1
set_clock_latency 2.5 [get_clocks CLK0]
set_clock_latency -source 4.0 [get_clocks GCLK1]
set_clock_latency -source 2.1 [get_clocks GCLK2]
# SDC_LAT05 violation
// Design File
module mSDC_LAT05 (D, CLKIN, CLKIN1, Q, EN);
input CLKIN, CLKIN1, EN;
input [0:2]D;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D[0];
wire tmp;
assign tmp = Q0 & EN;
always @(posedge tmp)
Q1 <= D[1];
always @(posedge Q0)
SR0 <= D[2];
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN1)
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Q <= SR2;
endmodule
SDC_LAT06
The latency for a generated clock cannot be zero; it has to be greater than the
Description latency of its source clock. Specifying a latency for generated clocks greater
than their source clocks produces better timing analysis and synthesis results.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This SDC file example shows properly specified generated clocks, as illustrated in the following
circuit diagram.
// SDC File
create_clock -name CLK -period 5.0 -waveform {0.0 2.5} [get_ports CLKIN]
create_generated_clock -name GCLK -source [get_ports CLKIN] -divide_by 2
[get_pins FF0/Q]
set_clock_latency -source 1.8 [get_clocks GCLK]
SDC_LAT07_A
SDC_LAT07_B
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SDC_LAT07_C
When the -source option is not used used with set_clock_latency commands,
Description Leda flags an error. The output points to the incomplete command in the SDC
file checked.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
SDC_LAT08_A
Leda flags an error is the minimum clock latency is greater than the maximum
Description clock latency. Leda points to the incorrect set_clock_latency command in the
output.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
SDC_LAT08_B
Leda flags an error is the -early option is greater than the -late option in the
Description set_clock_latency command. Leda points to the incorrect set_clock_latency
command in the output.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
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SDC_LAT09
Clocks should not be specified with negative latencies. Check for typos. Leda
Description flags these errors and points to the incorrect set_clock_latency command in the
output.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
SDC_UNC01
For every real clock, the clock uncertainty must not be zero. Otherwise, Leda
flags an error. In Primetime, the hold clock uncertainty models the sum of the
clock tree's inherent skew, the uncertainty on insertion delays, and a hold
Description
margin. The setup clock uncertainty models the sum of the clock tree's inherent
skew, the uncertainty on insertion delays, a setup margin, and the clock's input
jitter. See the following circuit diagram.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows an SDC file that is missing a set_clock_uncertainty command for CLK2:
// SDC File
create_clock -name CLK1 -period 1.0 clk1
create_clock -name CLK2 -period 1.0 clk2
set_clock_uncertainty 1.0 CLK1
# SDC_UNC01 violation--no clock uncertainty set for CLK2
// Design File
module simple_reg (clk1, clk2,d1,d2, q1,q2);
parameter nb_bit = 8;
input clk1,clk2;
input [1: nb_bit] d1,d2;
output [1: nb_bit] q1,q2;
reg [1: nb_bit] q1,q2;
always @(negedge clk1) q1 = d1;
always @(negedge clk2) q2 = d2;
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endmodule
SDC_UNC02
This rule checks that all design objects specified with set_clock_uncertainty
commands are real or generated clocks. If not, Leda flags an error and points to
Description
the faulty command in the output. Setting clock uncertainty for design objects
that are not clocks causes problems for timing analysis and synthesis tools.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows an SDC file that uses a set_clock_uncertainty command on a design
object (in1), which is not a clock.
// SDC File
create_clock -name CLK -period 10 [get_ports clk]
set_clock_uncertainty -setup 0.65 in1
# SDC_UNC02 violation--design object not a clock
// Design File
module UNC02(in1, in2, clk, out);
input in1, in2, clk;
output out;
reg out;
reg clk1, clk2;
always @(posedge clk)
clk1 <= in1;
always @(negedge clk)
clk2 <= in2;
always @(posedge clk1 or posedge clk2)
out <= in1;
endmodule
SDC_UNC04
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Description This rule flags violation when any of rise, fall or setup, hold option is used but
the counterpart options are not present for inter-clocks.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to flag an error because -rise and -fall options are not present for
the -hold option.
// SDC File
create_clock -name CLK0 -period 5.0 -waveform {0.0 2.5} [get_ports
CLKIN]
create_clock -name CLK1 -period 7.0 -waveform {0.0 2.5} [get_ports
CLKIN1]
// Design File
module mSDC_UNC04(D0, D1, D2, CLKIN, CLKIN1, Q2, Q3);
input D0, D1, D2, CLKIN, CLKIN1;
output Q2, Q3;
reg Q0, Q1, Q2, Q3;
always @(posedge CLKIN)
Q0 <= D0;
always @(posedge Q0)
Q1 <= D1;
always @(posedge Q1)
Q2 <= D2;
always @(posedge CLKIN1)
Q3 <= Q2;
endmodule
SDC_UNC05
Specifying negative clock uncertainty values causes problems for timing analysis
Description and synthesis tools. Leda flags these as errors and points to the faulty
set_clock_uncertainty commands in the output.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows an SDC file that specified a negative clock uncertainty value.
// SDC File
create_clock -name CLK -period 10 [get_ports clk]
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set_clock_uncertainty -setup -0.65 CLK
# SDC_UNC05 violation--negative clock uncertainty
// Design File
module UNC05(in1, in2, clk, out);
input in1, in2, clk;
output out;
reg out;
reg clk1, clk2;
always @(posedge clk)
clk1 <= in1;
always @(negedge clk)
clk2 <= in2;
always @(posedge clk1 or posedge clk2)
out <= in1;
endmodule
TVB Ruleset
The following rules are from the Top versus Block (TVB) ruleset:
SDC_TOP01
Message: Block level clock constraint is inconsistent with top level clock
constraint
This rule checks if the top level clock constraint has a period equal to the period
associated with the corresponding block level clock constraint. It also checks if
Description the top-level waveform is exactly equivalent to the corresponding block-level
waveform. This rule also takes into consideration the divide_by and multiply_by
options on a create_generated_clock command.
Policy Constraints
Ruleset TVB
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to issue an error message because the period of the top-level clock
constraint is not the same as the period of the block-level clock constraint.
// SDC File
//Top-level constraints:
create_clock -name "CLK_t" -period 5.0 [get_ports CLK_t]
create_generated_clock -name "CLK_g" -divide_by 2 -source CLK_t
[get_pins div/clk]
SDC_TOP02
Message: Block level I/O delay constraint is inconsistent with top level
delay constraint
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This rule checks that the input constraints at the block-level are consistent with
top-level constraints. The input delay for block must be greater than or equal to
Description any input delay for a top-level port in the fanin cone of that block input. The
output delay for block must be greater than or equal to any output delay for a
top-level port in the fanout cone from that block output.
Policy Constraints
Ruleset TVB
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to issue an error message because the input delay and output delay
constraints of top-level and block-level are inconsistent.
// SDC File
//Top-level constraints:
create_clock -name "CLK_t" -period 5.0 -waveform {0 2.5} [get_ports
CLK_t]
create_generated_clock -name "CLK_g" -divide_by 2 -source CLK_t
[get_pins div/clk]
set_input_delay 2.5 -clock CLK_t [et_ports IN1]
set_output_delay 2.5 -clock CLK_g [get_ports OUT1]
SDC_TOP03
Message: Block level false path constraint is inconsistent with top level
false path constraint
This rule checks that the top-level false path constraint is consistent with the
Description block-level false path constraint. A path that is defined as false at the block-
level should also be a false path at the top level.
Policy Constraints
Ruleset TVB
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows a test case that does not violate this rule.
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// SDC File
//If a clock is specified in the false_path at the block level, then the
//top-level should also have a similar constraint and the top-level
//clock should drive the block-level clock.
SDC_TOP04
This rule checks that the top-level multicycle path constraint is consistent with
Description the block-level multicycle path constraint. A path that is defined as multicycle at
the block-level should also be a multicycle path at the top level.
Policy Constraints
Ruleset TVB
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows a test case that does not violate this rule.
// SDC File
SDC_TOP20
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Ruleset TVB
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows a test case that does not violate this rule.
// SDC File
// Top-level constraint
// Block-level constraint:
// Assume the top-level port goes through instance BA of block and the
// block has the following constraint
DFT Ruleset
The following rules are from the DFT ruleset:
SDC_DFT01
Example
This example causes Leda to flag a warning because undefined test_scan_enable ports are
present.
// SDC File
create_clock -name CLK1 -period 10 [get_ports clk1]
create_clock -name CLK2 -period 10 [get_ports clk2]
// Design File
module mSDC_DFT01 ();
endmodule
SDC_DFT02
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Example
// SDC File
create_clock -name CLK1 -period 10 [get_ports clk1]
create_clock -name CLK2 -period 10 [get_ports clk2]
# SDC_DFT02 violation
set_scan_configuration -existing_scan true
set_signal_type "test_scan_enable" in1
#set_signal_type "test_scan_in" in2
set_signal_type "test_scan_out" in1
// Design File
module mSDC_DFT02(clk1, clk2, in1, in2, out1, out2, out3, out4, out5,
out6, out7);
input clk1;
input clk2;
input in1, in2;
output out1, out2,out3, out4, out5, out6 , out7;
reg out1, out2,out3, out4, out5, out6, out7;
wire w2;
assign w2 = clk2;
always @(posedge clk1)
begin
out1 <= in1;
end
always @(negedge clk2)
begin
out2 <= in2;
end
always
out3 <= clk1;
always
out4 <= ~clk2;
BUF U1(clk1,out5);
always@(w2)
out6 <= w2;
always@(w2)
out7 <= clk2;
endmodule
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SDC_DFT03
Example
// SDC File
create_clock -name CLK1 -period 10 [get_ports clk1]
create_clock -name CLK2 -period 10 [get_ports clk2]
# SDC_DFT03 violation
set_scan_configuration -existing_scan true
set_signal_type "test_scan_enable" in1
set_signal_type "test_scan_in" in2
#set_signal_type "test_scan_out" in1
// Design File
module mSDC_DFT03(clk1, clk2, in1, in2, out1, out2, out3, out4, out5,
out6, out7);
input clk1;
input clk2;
input in1, in2;
output out1, out2,out3, out4, out5, out6 , out7;
reg out1, out2,out3, out4, out5, out6, out7;
wire w2;
assign w2 = clk2;
always @(posedge clk1)
begin
out1 <= in1;
end
always @(negedge clk2)
begin
out2 <= in2;
end
always
out3 <= clk1;
always
out4 <= ~clk2;
BUF U1(clk1,out5);
always@(w2)
out6 <= w2;
always@(w2)
out7 <= clk2;
endmodule
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out1 <= w1;
endmodule
SDC_DFT04
Example
// SDC File
create_clock -name CLK1 -period 10 [get_ports clk1]
create_clock -name CLK2 -period 10 [get_ports clk2]
# SDC_DFT04 violation
#set_scan_configuration -existing_scan true
set_signal_type "test_scan_enable" in1
set_signal_type "test_scan_in" in2
set_signal_type "test_scan_out" in1
// Design File
module mSDC_DFT04(clk1, clk2, in1, in2, out1, out2, out3, out4, out5,
out6, out7);
input clk1;
input clk2;
input in1, in2;
output out1, out2,out3, out4, out5, out6 , out7;
reg out1, out2,out3, out4, out5, out6, out7;
wire w2;
assign w2 = clk2;
always @(posedge clk1)
begin
out1 <= in1;
end
always @(negedge clk2)
begin
out2 <= in2;
end
always
out3 <= clk1;
always
out4 <= ~clk2;
BUF U1(clk1,out5);
always@(w2)
out6 <= w2;
always@(w2)
out7 <= clk2;
endmodule
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always @(w1)
out1 <= w1;
endmodule
DRC Ruleset
The following rules are from the DRC ruleset:
SDC_IDR01
Example
// SDC File
create_clock -name CLK -period 5.0 -waveform {0.0 2.5} [get_ports CLKIN]
create_clock -name CLK1 -period 15.0 -waveform {0.0 2.5} [get_ports
CLKIN1]
# SDC_IDR01 violation
set_max_capacitance 2.5 D0
set_input_delay 2.5 D1 -clock [get_clocks CLK]
// Design File
module mSDC_IDR01 (D0, D1, D2, CLKIN, CLKIN1, Q, EN, SR2);
input CLKIN, CLKIN1, EN;
input D0, D1, D2;
output Q, SR2;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D0;
wire tmp;
assign tmp = Q0 & EN;
always @(posedge tmp)
Q1 <= D1;
always @(posedge Q0)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN1)
Q <= SR2;
endmodule
SDC_ODR01
Description This rule will flag violation if set_max_capacitance is not constraint on an output
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or inout port.
Policy Constraints
Ruleset DRC
Language VHDL/Verilog
Type SDC
Severity Warning
Example
// SDC File
create_clock -period 5.0 -waveform {0.0 2.5} [get_ports CLKIN]
create_generated_clock -name Q0 -source CLK0 -divide_by 2 Q0
create_generated_clock -name GCLK2 -source GCLK1 -divide_by 2 Q1
set_clock_latency -source 2.5 [get_clocks CLK0]
set_clock_latency -source 4.0 [get_clocks GCLK1]
set_clock_latency -source 2.1 [get_clocks GCLK2]
# SDC_ODR01 violation
set_max_capacitance 2.5 Q
// Design File
module mSDC_ODR01 (D, CLKIN, CLKIN1, Q, EN, SR2);
input CLKIN, CLKIN1, EN;
input [0:2]D;
output Q, SR2;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D[0];
wire tmp;
assign tmp = Q0 & EN;
always @(posedge tmp)
Q1 <= D[1];
always @(posedge Q0)
SR0 <= D[2];
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN1)
Q <= SR2;
endmodule
Exceptions Ruleset
The following rules are from the Exceptions ruleset:
SDC_CMB01
This rule will flag violation if a combinational path is not constrained using
Description
set_max_delay and set_min_delay.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity Error
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Example
This example causes Leda to flag an error because input/output delay values is not specified
for a combinational path.
// SDC File
create_clock -name CLK1 -period 5.0 -waveform {0.0 2.5} CLKIN
create_clock -name CLK2 -period 5.0 -waveform {0.0 2.5} [get_ports Q0]
# SDC_CMB01 violation
set_input_delay 2.0 [get_ports sel]
set_input_delay 2.0 [get_ports D2]
set_output_delay 2.0 [get_ports Q]
set_max_delay 5.0 -from [get_ports sel] -to [get_ports Q]
set_max_delay 5.0 -from [get_ports D2] -to [get_ports Q]
// Design File
module mSDC_CMB01 (D4, D0, D1, D2, sel, CLKIN, Q);
input D0, D1, D2, CLKIN, sel, D4;
output Q;
wire Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
assign Q = muxwirebar;
endmodule
SDC_CMB02
This rule will flag violation if set_min_delay > set_max_delay value for a
Description
combinational path.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to flag an error because set_min_delay value is greater than
set_max_delay for a combinational path.
// SDC File
create_clock -name CLK1 -period 5.0 -waveform {0.0 2.5} CLKIN
create_clock -name CLK2 -period 5.0 -waveform {0.0 2.5} Q0
# SDC_CMB02 violation
set_min_delay 5.0 -from [get_ports D0] -to [get_ports Q]
set_max_delay 4.0 -from [get_ports D0] -to [get_ports Q]
set_min_delay 5.0 -from [get_ports D1] -to [get_ports Q]
set_max_delay 6.0 -from [get_ports D1] -to [get_ports Q]
set_min_delay 4.0 -from [get_ports D1] -through {tmp} -to [get_ports Q]
set_max_delay 5.0 -from [get_ports D1] -through [get_ports tmp] -to
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[get_ports Q]
set_max_delay 5.0 -to [get_ports tmp]
set_min_delay 7.0 -through [get_ports Q0]
set_min_delay 8.0 -from {D1 CLKIN} -to {tmp Q}
set_max_delay 6.0 -from {CLKIN D1} -to {Q tmp}
set_max_delay 10.0 -from [get_clocks CLK1] -to [get_ports Q]
set_min_delay 11.0 -from [get_clocks CLK1] -to {Q}
// Design File
module mSDC_CMB02 (D4, D0, D1, D2, sel, CLKIN, Q);
input D0, D1, D2, CLKIN, sel, D4;
output Q;
wire Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
assign Q = muxwirebar;
endmodule
SDC_CMB03
Example
// SDC File
create_clock -name CLK1 -period 5.0 -waveform {0.0 2.5} [get_ports
CLKIN]
create_generated_clock -name CLK2 -multiply_by 2 -source CLKIN Q0
create_generated_clock -name CLK3 -divide_by 2 -source CLKIN [get_ports
CLKIN1]
create_generated_clock -name CLK4 -divide_by 2 -source CLKIN1 [get_ports
CLKIN2]
// Design File
module mSDC_CMB03 (D4, D0, D1, D2, sel, CLKIN, CLKIN1, CLKIN2, Q);
input D0, D1, D2, CLKIN, CLKIN1, CLKIN2, sel, D4;
output Q;
wire Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
assign Q = muxwirebar;
endmodule
SDC_CMB04
This rule will flag violation if -fall option is not used along with -rise option while
Description
specifying input delay and output delay for a combinational path.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to flag an error because -fall is not used with -rise option for a
combinational path.
// SDC File
create_clock -name CLK1 -period 5.0 -waveform {0.0 2.5} CLKIN
create_clock -name CLK2 -period 5.0 -waveform {0.0 2.5} Q0
set_min_delay 5.0 -rise -from [get_ports D0] -to [get_ports Q]
set_min_delay 5.0 -fall -from [get_ports D0] -to [get_ports Q]
set_min_delay 5.0 -fall -from [get_ports D1] -to [get_ports Q]
set_min_delay 5.0 -rise -from [get_ports D1] -to [get_ports Q]
set_min_delay 5.0 -rise -from [get_ports D1] -through {tmp} -to
[get_ports Q]
set_min_delay 5.0 -fall -from [get_ports D1] -through [get_ports tmp] -
to [get_ports Q]
set_min_delay 5.0 -rise -from [get_ports CLKIN] -to [get_ports Q]
set_min_delay 5.0 -fall -from [get_ports CLKIN] -through [get_ports tmp]
-to [get_ports Q]
set_min_delay 5.0 -rise -to [get_ports tmp]
set_min_delay 5.0 -fall -through [get_ports Q0]
set_min_delay 5.0 -rise -from {D1 CLKIN} -to {tmp Q}
set_min_delay 5.0 -fall -from {CLKIN D1} -to {Q tmp}
set_max_delay 5.0 -rise -from [get_ports D0] -to [get_ports Q]
set_max_delay 5.0 -fall -from [get_ports D0] -to [get_ports Q]
set_max_delay 5.0 -fall -from [get_ports D1] -to [get_ports Q]
set_max_delay 5.0 -rise -from [get_ports D1] -to [get_ports Q]
set_max_delay 5.0 -rise -from [get_ports D1] -through [get_ports tmp] -
to [get_ports Q]
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set_max_delay 5.0 -fall -from [get_ports D1] -through [get_ports tmp] -
to [get_ports Q]
set_max_delay 5.0 -rise -from [get_ports CLKIN] -to [get_ports Q]
set_max_delay 5.0 -fall -from [get_ports CLKIN] -through [get_ports tmp]
-to [get_ports Q]
set_max_delay 5.0 -rise -to [get_ports tmp]
set_max_delay 5.0 -fall -through [get_ports Q0]
set_max_delay 5.0 -rise -from {D1 CLKIN} -to {tmp Q}
set_max_delay 5.0 -fall -from {CLKIN D1} -to {Q tmp}
set_max_delay 5.0 -rise -from [get_clocks CLK1]
set_min_delay 5.0 -rise -from [get_clocks CLK2]
# SDC_CMB04 violation
set_max_delay 6.0 -fall -from [get_clocks CLK1]
// Design File
module mSDC_CMB04 (D4, D0, D1, D2, sel, CLKIN, Q);
input D0, D1, D2, CLKIN, sel, D4;
output Q;
wire Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
assign Q = muxwirebar;
endmodule
SDC_CMB05
Example
This example causes Leda to flag an error because set_min_delay and set_max_delay
constraint command is used for sequential path.
// SDC File
create_clock -name CLK -period 5.0 -waveform {0.0 2.5} CLKIN
// Design File
module mSDC_CMB05 (D4, D0, D1, D2, sel, CLKIN, Q);
input D0, D1, D2, CLKIN, sel, D4;
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output Q;
reg Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
always @(posedge Q0)
Q <= muxwirebar;
endmodule
SDC_DIS03
Example
This example causes Leda to flag an error because the object referred in set_disable_timing
command is not present in the design.
// SDC File
# SDC_DSC03 violation
create_clock -name CLK1 -period 5.0 -waveform {0.0 2.5} CLKIN
set_disable_timing {A1}
#none of the points exist
set_disable_timing [get_ports Q]
// Design File
module mSDC_DIS03 (D4, D0, D1, D2, sel, CLKIN, Q);
input D0, D1, D2, CLKIN, sel, D4;
output Q;
reg Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
always @(posedge Q0)
Q <= muxwirebar;
endmodule
SDC_DIS04
Description set_disable_timing arc is part of clock net, so it will disturb timing calculations
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SDC_FLP01
In all modes, false paths specified with set_false_path commands must refer to
Description real design signals, and should be specified with from and to points so that the
timing analysis and synthesis tools have all the needed information.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity Error
SDC_FLP02
Description None.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity Error
Example
// SDC File
create_clock -name CLK1 -period 5.0 -waveform {0.0 2.5} CLKIN
create_clock -name CLK2 -period 5.0 -waveform {0.0 2.5} {INST1/INST/D}
# SDC_FLP02 violation
set_false_path -from {D0} -to {Q} -through {tmp}
set_false_path -from [get_ports D0] -to [get_ports D2] -through {tmp}
set_false_path -from {D4} -to {Q} -through {muxwire}
set_false_path -from {D0 D4} -to {Q} -through {tmp}
set_false_path -from {D0 D4} -to {Q} -through {andwire}
set_false_path -from {D0 D4} -to {Q}
// Design File
module mymodule (D, Q, CLK);
input D, CLK;
output Q;
reg Q;
initial
begin
Q <= D;
end
endmodule
SDC_FLP06
This rule is a parameterized rule where user needs to explicitly specify which
clocks are asynchronous using the parameter ASYNC_CLOCKS. The default
value of the rule parameter is {CLK, CLK1}.rule_set_parameter -rule
SDC_FLP06 -parameter ASYNC_CLOCKS -value {CLK, CLK1}You can overwrite
this rule parameter to specify the asynchronous clock set. When there are
several asynchronous clocks in the design for example, CLK1, CLK2, CLK3, CLK4
then the parameter value can be specified as follows:rule_set_parameter -rule
SDC_FLP06 -parameter ASYNC_CLOCKS -value {CLK1, CLK2, CLK3,
Description
CLK4}When there are several synchronous and asynchronous clocks for
example, a set of clocks CLK1, CLK2, CLK3, CLK4 CLK1 <-> CLK2 -
synchronousCLK1 <-> CLK3 | CLK4 - asynchronous CLK2 <-> CLK3 | CLK4 -
asynchronousCLK3 <-> CLK4 - asynchronousthen the parameter value can be
specified as shown below:rule_set_parameter -rule SDC_FLP06 -parameter
ASYNC_CLOCKS -value {{CLK1, CLK3, CLK4}, {CLK2, CLK3, CLK4}}This rule
expects a false path to be set between all asynchronous clocks irrespective of
data crossing exists or not.
Policy Constraints
Ruleset Exceptions
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Language VHDL/Verilog
Type SDC
Severity Error
Example
// SDC File
create_clock -name CLK -period 5.0 -waveform {0.0 2.5} [get_ports CLKIN]
create_generated_clock -name CLK1 -divide_by 2 -source CLKIN [get_ports
Q]
create_clock -name CLK2 -period 5.0 -waveform {0.0 2.5} [get_ports
CLKIN1]
create_generated_clock -name CLK3 -divide_by 2 -source CLKIN1 [get_ports
sel]
# SDC_FLP06 violation
set_false_path -from [get_clocks CLK] -to [get_clocks CLK1]
set_false_path -from {CLK2} -to {CLK3}
// Design File
module mSDC_FLP06 (D4, D0, D1, D2, sel, CLKIN, CLKIN1, Q);
input D0, D1, D2, CLKIN, CLKIN1, sel, D4;
output Q;
reg Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0, Dim;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
always @(posedge CLKIN1)
Dim <= muxwirebar;
always @(posedge Q0)
Q <= Dim;
endmodule
SDC_FLP21
Message: False path has been set between registers belonging to same
clock domain
Example
// SDC File
create_clock -name CLK1 -period 5.0 -waveform {0.0 2.5} [get_ports
CLKIN]
create_generated_clock -name CLK2 -divide_by 2 -source CLKIN {Q0}
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create_generated_clock -name CLK3 -divide_by 3 -source CLKIN [get_ports
CLKIN1]
# SDC_FLP21 violation
set_false_path -from [get_clocks CLK1] -to tmp
set_false_path -from [get_ports CLKIN] -to tmp
set_false_path -from Q0 -to [get_ports Q]
set_false_path -from tmp -to muxwirebar
set_false_path -from Q0 -to tmp
set_false_path -from tmp1 -to Q1
// Design File
module mSDC_FLP21 (D4, D0, D1, D2, sel, CLKIN, CLKIN1, Q);
input D0, D1, D2, CLKIN, CLKIN1, sel, D4;
output Q;
reg Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0, Dim;
reg tmp1, Q1;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
always @(posedge CLKIN1)
Dim <= muxwirebar;
always @(posedge Q0)
Q <= Dim;
always @(posedge tmp1)
Q1 <= D4;
endmodule
SDC_FLP22
Derived clocks are clocks which are related to each other. Generally false path is
Description set between registers belonging to different domains (asynchronous clocks).
Hence this check.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity Error
Example
// SDC File
create_clock -name CLK1 -period 5.0 -waveform {0.0 2.5} [get_ports
CLKIN]
create_clock -name CLK2 -period 5.0 -waveform {0.0 2.5} {Q0}
create_generated_clock -name CLK3 -divide_by 2 -source CLKIN [get_ports
CLKIN1]
create_generated_clock -name CLK4 -divide_by 4 -source CLKIN [get_ports
D1]
create_clock -name CLK5 -period 5.0 -waveform {0.0 2.5}
# SDC_FLP22 violation
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set_false_path -from [get_ports CLKIN] -to [get_ports CLKIN1]
set_false_path -from [get_ports CLKIN] -to {Q0}
set_false_path -from [get_clocks CLK3] -to [get_clocks CLK4]
set_false_path -from [get_clocks CLK5] -to [get_clocks CLK5]
// Design File
module mSDC_FLP22 (D4, D0, D1, D2, sel, CLKIN, CLKIN1, Q);
input D0, D1, D2, CLKIN, CLKIN1, sel, D4;
output Q;
reg Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0, Dim;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
always @(posedge CLKIN1)
Dim <= muxwirebar;
always @(posedge Q0)
Q <= Dim;
endmodule
SDC_HFN01
Example
// SDC File
create_clock -name CLK -period 5 [get_ports CLKIN]
create_clock -name CLK1 -period 5.0 -waveform {0.0 2.5} [get_ports
CLKIN1]
create_clock -period 5.0 -waveform {0.0 2.5} [get_ports Q0]
create_clock -period 5.0 -waveform {0.0 2.5} [get_ports Q1]
create_clock -period 5.0 -waveform {0.0 2.5} [list [get_ports SR0]
[get_ports SR1]]
create_generated_clock -name CLK3 -divide_by 2 -source CLKIN [get_ports
SR2]
create_generated_clock -name CLK4 -divide_by 2 -source CLKIN [get_ports
SR3]
# SDC_HFN01 violation
set_dont_touch_network [get_clocks CLK]
set_dont_touch_network [get_ports CLKIN1]
set_dont_touch_network [get_ports Q1]
set_dont_touch_network [list [get_ports SR0] [get_ports SR1]]
set_dont_touch_network [get_clocks CLK3]
// Design File
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module mSDC_HFN01 (D0, D1, D2, CLKIN, CLKIN1, Q);
input D0, D1, D2, CLKIN, CLKIN1;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2, SR3, SR4, SR5;
always @(posedge CLKIN)
Q0 <= D0;
always @(posedge Q0)
Q1 <= D1;
always @(posedge Q1)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge SR0)
SR2 <= SR1;
always @(posedge SR1)
SR3 <= SR2;
always @(posedge SR2)
SR4 <= SR3;
always @(posedge SR3)
SR5 <= SR4;
always @(posedge CLKIN1)
Q <= SR5;
endmodule
SDC_HFN02
SDC_HFN06
To verify that set_ideal_transition value with "-min" option does not exceed the
Description
value with "-max" option.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity Error
SDC_HFN07
Description If the command has "-min" option then there should be a counter part
command with "-max" option. Similar for options "-rise" and "-fall.
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Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity Error
SDC_HFN08
To verify that set_ideal_transition value with "-min" option does not exceed the
Description
value with "-max" option.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity Error
SDC_HFN09
If the command has "-min" option then there should be a counter part
Description
command with "-max" option. Similar for options "-rise" and "-fall".
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity Error
SDC_HFN10
SDC_HFN11
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At RTL and prelayout level, clock is treated as ideal net, hence you should use
set_ideal_latency command to set latency. It sets ideal latency on top-level
Description
ports and leaf-cell pins of the ideal network, ideal nets or auto disable drc nets.
Specifies latency on ideal network.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to flag an error because ideal net latency is not specified for CLK1.
// SDC File
create_clock -name CLK -period 5 [get_ports CLKIN]
create_clock -name CLK1 -period 5 [get_ports CLKIN1]
// Design File
module mSDC_HFN11 (D0, D1, D2, CLKIN, CLKIN1, Q);
input D0, D1, D2, CLKIN, CLKIN1;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2, SR3, SR4, SR5;
always @(posedge CLKIN)
Q0 <= D0;
/*always @(posedge Q0)
Q1 <= D1;
always @(posedge Q1)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge SR0)
SR2 <= SR1;
always @(posedge SR1)
SR3 <= SR2;
always @(posedge SR2)
SR4 <= SR3;
always @(posedge SR3)
SR5 <= SR4;*/
always @(posedge CLKIN1)
Q <= Q0;
endmodule
SDC_HFN12
At RTL and prelayout level, clock is treated as ideal net, hence you should use
set_ideal_transition command to set transition. It sets ideal transition on top-
Description
level ports and leaf-cell pins of the ideal network, ideal nets or auto disable drc
nets. Specifies transition on ideal network.
Policy Constraints
Ruleset Exceptions
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Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to flag an error because ideal net transition is not specified for
CLK1.
// SDC File
create_clock -name CLK -period 5 [get_ports CLKIN]
create_clock -name CLK1 -period 5 [get_ports CLKIN1]
// Design File
module mSDC_HFN12 (D0, D1, D2, CLKIN, CLKIN1, Q);
input D0, D1, D2, CLKIN, CLKIN1;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2, SR3, SR4, SR5;
always @(posedge CLKIN)
Q0 <= D0;
/*always @(posedge Q0)
Q1 <= D1;
always @(posedge Q1)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge SR0)
SR2 <= SR1;
always @(posedge SR1)
SR3 <= SR2;
always @(posedge SR2)
SR4 <= SR3;
always @(posedge SR3)
SR5 <= SR4;*/
always @(posedge CLKIN1)
Q <= Q0;
endmodule
SDC_HFN20
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Example
// SDC File
create_clock -name CLK -period 5 [get_ports CLKIN]
# SDC_HFN20 violation
set_max_fanout 1.0 [get_ports D0]
set_max_fanout 99999.0 [get_ports CLKIN]
set_max_fanout 100001.0 [get_ports D1]
// Design File
module mSDC_HFN20 (D0, D1, D2, CLKIN, CLKIN1, Q);
input D0, D1, D2, CLKIN, CLKIN1;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2, SR3, SR4, SR5;
always @(posedge CLKIN)
Q0 <= D0;
/*always @(posedge Q0)
Q1 <= D1;
always @(posedge Q1)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge SR0)
SR2 <= SR1;
always @(posedge SR1)
SR3 <= SR2;
always @(posedge SR2)
SR4 <= SR3;
always @(posedge SR3)
SR5 <= SR4;*/
always @(posedge CLKIN1)
Q <= Q0;
endmodule
SDC_MCP01
Description None.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity Error
SDC_MCP02
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Severity Error
Example
This example causes Leda to flag an error because multi cycle path is applied to hierarchical
ports.
// SDC File
create_clock -name CLK1 -period 5.0 -waveform {0.0 2.5} CLKIN
create_clock -name CLK2 -period 5.0 -waveform {0.0 2.5} {INST1/INST/D}
# SDC_MCP02 violation
set_multicycle_path 3 -from {INST/D} -to {Q}
set_multicycle_path 3 -from {INST1/INST/D} -to {Q}
set_multicycle_path 3 -from [get_clocks CLK2] -to {Q}
set_multicycle_path 3 -from {INST1/Q1} -to {Q}
// Design File
module mymodule (D, Q, CLK);
input D, CLK;
output Q;
reg Q;
initial
begin
Q <= D;
end
endmodule
SDC_MCP05
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If setup value is set for a multi cycle path using "set_multicycle_path" -setup,
Description
then hold value should also be specified using "set_multicycle_path" -hold.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to flag an error because -setup option was not used with -hold for
CLK2.
// SDC File
create_clock -name CLK1 -period 5.0 -waveform {0.0 2.5} CLKIN
create_clock -name CLK2 -period 5.0 -waveform {0.0 2.5} Q0
set_multicycle_path 5 -setup -from [get_ports D0] -to [get_ports Q]
set_multicycle_path 5 -hold -from [get_ports D0] -to [get_ports Q]
set_multicycle_path 5 -hold -from [get_ports D1] -to [get_ports Q]
set_multicycle_path 5 -setup -from [get_ports D1] -to [get_ports Q]
set_multicycle_path 5 -setup -from [get_ports D1] -through tmp -to
[get_ports Q]
set_multicycle_path 5 -hold -from [get_ports D1] -through [get_ports
tmp] -to [get_ports Q]
set_multicycle_path 5 -setup -from [get_ports CLKIN] -to [get_ports Q]
set_multicycle_path 5 -hold -from [get_ports CLKIN] -through [get_ports
tmp] -to [get_ports Q]
set_multicycle_path 5 -setup -to [get_ports tmp]
set_multicycle_path 5 -hold -through [get_ports Q0]
set_multicycle_path 5 -setup -from {D1 CLKIN} -to {tmp Q}
set_multicycle_path 5 -hold -from {CLKIN D1} -to {Q tmp}
set_multicycle_path 5 -setup -from [get_clocks CLK1] -to [get_ports Q]
set_multicycle_path 5 -hold -from [get_clocks CLK1] -to [get_ports Q]
# SDC_MCP05 violation
set_multicycle_path 5 -hold -from [get_clocks CLK2] -to [get_ports Q]
// Design File
module mSDC_MCP05 (D4, D0, D1, D2, sel, CLKIN, Q);
input D0, D1, D2, CLKIN, sel, D4;
output Q;
wire Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
assign Q = muxwirebar;
endmodule
Inputs Ruleset
The following rules are from the Inputs ruleset:
SDC_IDL01
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All input ports must be specified with input delay values using set_input_delay
commands. Without this information, you can get incorrect hardware
Description
optimizations. When Leda finds a violation of this rule, the output points to the
signal inferred as a clock.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows an SDC file without a set_input_delay command to set the delay value for
the clock.
// SDC File
create_clock -name CLK -period 10 [get_ports clk]
# SDC_IDL01 violation--unconstrained input
// Design File
module IDL01(in1, clk, out);
input in1, clk;
output out;
reg out, clk1;
always @(posedge clk)
clk1 <= in1;
always @(posedge clk1)
out <= in1;
endmodule
SDC_IDL02
This rule will flag violation if more than one input delay command is used on an
Description
input with different clocks and without add delay options.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to flag an error because more than one input delay command is
used on an input with different clocks.
// SDC File
create_clock -name CLK -period 10 [get_ports CLKIN]
create_generated_clock -name GCLK -source [get_ports CLKIN] -divide_by 2
Q1
create_clock -name VCLK -period 20
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# SDC_IDL02 violation
set_input_delay 2.5 [get_ports D2] -clock [get_clocks CLK]
set_input_delay 2.5 [get_ports D2] -clock [get_clocks GCLK] -add_delay
set_input_delay 2.5 [get_ports D2] -clock [get_clocks VCLK]
// Design File
module mSDC_IDL02 (D1, D2, D3, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_IDL03
Description This rule flags if all the elements of a bus do not have same min-max delays.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Warning
SDC_IDL04
When options such as -rise, -fall, -min, and -max are used with set_input_delay
Description commands to constraint an object, the counterpart options must be also
present. Otherwise, Leda flags an error.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
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This example shows an SDC file with a set_input_delay -max command that does not specify a
corresponding -min option. Leda flags these as errors. The output points to the
set_input_delay -max command.
// SDC File
create_clock -name CLK -period 10 [get_ports clk]
set_input_delay 1.2 -max -clock [get_clocks CLK] [all_inputs]
// Design File
module IDL04(in1, clk, out);
input in1, clk;
output out;
reg out, clk1;
always @(posedge clk)
clk1 <= in1;
always @(posedge clk1)
out <= in1;
endmodule
SDC_IDL05
Setting inconsistent delay values compared to the clock period may cause the
synthesis tool to run for a long time and result in poor quality of results.
Description
Inconsistent settings include input_delay_value > virtual_clock_period and min
> max with set_input_delay commands.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Error
SDC_IDL06
Message: Input constrained versus wrong (real) clock: Port: %s1, clock
(wrong): %s2
Setting input delay values with respect to a clock other than the clock that
drives the input signal in question can result in incorrect timing analysis and
synthesis results. Leda flags these as errors. The Path Viewer output shows the
path from the primary input to the flip-flop clocked by the signal that is not in
the constraint command.The secondary messages of this rule could be one of
Description the following:
Right clock is %s3
Right clock source is (this does not have a corresponding SDC clock
definition) %s4
This port drives only combinatorial paths %s5
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
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Severity Error
SDC_IDL07
Example
Using a virtual clock as reference clock may help in situations where you want to change the
reference clock from REAL_CLK1 to REAL_CLK2 (see example below). In this example, you
need to change the virtual clock definition (that is, modify its parameters similar to
REAL_CLK1). This changes the reference clock. Using the virtual clock helps avoid situations
where your real clock name is used in all set_input_delay and set_output_delay commands.
When you decide to change the reference clock, you have edit all the input and output delay
commands.
// SDC File
Create_clock -name REAL_CLK1 -period 10 -waveform{0,5} \
[get_ports clk_in1 ]
Create_clock -name REAL_CLK2 -period 15 -waveform{0,7.5} \
[get_ports clk_in2]
Create_clock -name Virtual_clk -period 10 -waveform {0,5}
#same parameters as REAL_CLK1
Set_input_delay 2.0 -source Virtual_clk [get_ports in1]
Set_input_delay 3.0 -source Virtual_clk [get_ports in2]
Set_input_delay 4.0 -source Virtual_clk [get_ports in3]
Set_input_delay 1.5 -source Virtual_clk [get_ports out1]
Set_input_delay 0.5 -source Virtual_clk [get_ports out2]
Set_input_delay 4.5 -source Virtual_clk [get_ports out3]
This next example shows an SDC file with a set_input_delay -clock command that does not
point to a virtual clock. Leda flags these as errors. The output points to the incorrect
set_input_delay -clock command.
// SDC File
create_clock -name CLK -period 10 clk
create_clock -name VCLK -period 10
set_input_delay 5 -max -clock VCLK {in1}
set_input_delay 5 -max -clock CLK {in1}
# SDC_IDL07 violation--input delay specified for real clock
// Design File
module IDL07(in1, clk, out);
input in1, clk;
output out;
reg out, clk1;
always @(posedge clk)
clk1 <= in1;
always @(posedge clk1)
out <= in1;
endmodule
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SDC_IDL08
This rule will flag violation if the input delay vs. clock period (respect to which
Description
clock it is specified) doesn't match with user-defined ratio.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to flag an error because the input delay vs. clock period doesn't
match with user-defined ratio.
// SDC File
create_clock -name CLK -period 10 [get_ports CLKIN]
create_generated_clock -name GCLK -source [get_ports CLKIN]
-divide_by 2 Q1
# SDC_IDL08 violation
set_input_delay 2.5 [get_ports D1]
set_input_delay 2.5 [get_ports D2] -clock [get_clocks CLK]
set_input_delay 2.5 [get_ports D3] -clock [get_clocks GCLK]
set_input_delay 2 [get_ports D4] -clock [get_clocks CLK]
// Design File
module mSDC_IDL08 (D1, D2, D3, D4, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3, D4;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2&D4;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_IDL09
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SDC_IDL10
SDC_IDL11
SDC_IDL12
Description This rule flags violation for non-negative min delay or negative max delay.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Warning
SDC_IDL20
This rule will flag violation if there is no -clock option in input delay constraint
Description
w.r.t an already defined clock.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
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Severity Error
Example
This example causes Leda to flag an error because input delay constraint is specified without -
clock option.
// SDC File
create_clock -name CLK -period 10 [get_ports CLKIN]
create_generated_clock -name GCLK -source [get_ports CLKIN]
-divide_by 2 Q1
# SDC_IDL20 violation
set_input_delay 2.5 [get_ports D1]
set_input_delay 2.5 [get_ports D2] -clock [get_clocks CLK]
set_input_delay 2.5 [get_ports D3] -clock [get_clocks CLK1]
// Design File
module mSDC_IDL20 (D1, D2, D3, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_IDL21
Description This rule will flag violation if input delay is specified on a hierarchical port.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
// SDC File
create_clock -name CLK1 -period 10 [get_ports CLKIN]
create_clock -name CLK2 -period 10 [get_ports CLKIN1]
# SDC_IDL21 violation
set_input_delay 2.5 [get_ports D1]
set_input_delay 2.5 [get_pins inst/D]
set_input_delay 2.5 [get_pins Q3_reg/D]
// Design File
module mSDC_IDL21 ( D0, D1, D2, CLKIN, CLKIN1, Q1, Q2, Q3 );
input D0;
input D1;
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input D2;
input CLKIN;
input CLKIN1;
output Q1;
output Q2;
output Q3;
wire Q0;
SDC_ITR01
All input ports must be specified with input transition values. Without these
input transition values, you may get poor quality of results from the timing
analysis and synthesis tools. You can constrain input ports with
Description
set_input_transition or set_driving_cell commands. If not, Leda flags these as
errors. The output points to a signal that Leda inferred as a clock. The Path
Viewer shows a path from this signal to a flip-flop.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This SDC file does not contain a set_input_transition command for the in1 input port. Leda
flags an error in this case.
// SDC File
create_clock -name CLK -period 10 clk
# SDC_ITR01 violation--no input transition specified for in1
// Design File
module ITR01(in1, clk, out);
input in1, clk;
output out;
reg out, clk1;
always @(posedge clk)
clk1 <= in1;
always @(posedge clk1)
out <= in1;
endmodule
SDC_ITR02
When some options such as -rise, -fall, -min, and -max are used with
set_input_transition commands to constrain an object, the counterpart options
Description
must also be present. Otherwise, Leda flags an error. The output points to the
incomplete command in the SDC file checked.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This SDC file does not contain a set_input_transition -min option that corresponds to the
specified -max option. Leda flags an error in this case.
// SDC File
create_clock -name CLK -period 10 clk
set_input_transition 2 -max [get_ports in1]
# SDC_ITR02 violation--max specified without corresponding min
// Design File
module ITR02(in1, clk, out);
input in1, clk;
output out;
reg out, clk1;
always @(posedge clk)
clk1 <= in1;
always @(posedge clk1)
out <= in1;
endmodule
SDC_ITR03
Setting the min greater than the max may cause the synthesis tool to run for a
long time and results in poor quality of results. Leda checks for such
Description
inconsistency on set_input_transition commands. The output points to the
inconsistent command in the SDC file checked.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This SDC file contains a set_input_transition -min option with a greater value than the
corresponding -max option. Leda flags an error in this case.
// SDC File
create_clock -name CLK -period 10 clk
set_input_transition 2 -max [get_ports in1]
set_input_transition 5 -min [get_ports in1]
# SDC_ITR03 violation--min greater than max
// Design File
module ITR02(in1, clk, out);
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input in1, clk;
output out;
reg out, clk1;
always @(posedge clk)
clk1 <= in1;
always @(posedge clk1)
out <= in1;
endmodule
SDC_ITR04
Example
module mSDC_ITR04
input D1, D2;
...
endmodule
.lib file
Library (test) {
...
default_max_transition : 5.0;
default_max_fanout : 20.0;
defaullt_fanout_load : 1.0;
...
}
Constraint file
...
set_input_transition -max 6.5 D1 -clock CLK1 //Flag violation
set_input_transition -min 1.5 D1 -clock CLK1 //OK
SDC_ITR05
This rule flags if the input transition is less than the transition value of the clock
Description
specified with -clock option for the set_input_transition command.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Warning
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SDC_ITR07
This rule fires when Leda detects clock and clock_fall options used with
set_input_transition or set_driving_cell commands. This rule also fires when
Leda detects max and min options used with set_driving_cell commands. These
Description
options are not supported by synthesis. They may apply for timing analysis
tools, but there could be discrepancies between the synthesis and timing
analysis tools.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This SDC file contains set_input_transition commands with -clock and -clock_fall options. Leda
flags these as errors and points to the unusual commands in the Checker output.
// SDC File
set_input_transition -clock clk 1.0 d1;
set_input_transition -clock_fall 1.0 d2;
set_driving_cell -clock clk d3;
set_driving_cell -clock_fall d4;
# SDC_ITR07 violations--clock and clock_fall options
// Design File
module ITR07 (clk, d, q);
parameter nb_bit = 8;
input clk;
input [1: nb_bit] d;
output [1: nb_bit] q;
reg [1: nb_bit] q;
This SDC file contains set_driving_cell commands with -max and -min options. Leda flags
these as errors and points to the unusual commands in the Checker output.
// SDC File
set_driving_cell -min d4;#FAIL SDC_ITR07_B x 1
set_driving_cell -max d5;#FAIL SDC_ITR07_B x 1
set_driving_cell -min -max d6;#FAIL SDC_ITR07_B x 1
# SDC_ITR07 violation--max and min options for set_driving_cell
// Design File
module ITR07 (clk, d, q);
parameter nb_bit = 8;
input clk;
input [1: nb_bit] d;
output [1: nb_bit] q;
reg [1: nb_bit] q;
SDC_ITR08
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SDC_ITR09
Negative transition values could increase runtimes for timing analysis and
Description
synthesis tools. Check for a typing error.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This SDC file contains a set_input_transition command that specifies a negative value. Leda
flags these as errors and points to the unusual commands in the Checker output.
// SDC File
set_input_transition -1.0 d1;#FAIL SDC_ITR09 x 1
# SDC_ITR09 violation--negative transition value specified
// Design File
module ITR07 (clk, d, q);
parameter nb_bit = 8;
input clk;
input [1: nb_bit] d;
output [1: nb_bit] q;
reg [1: nb_bit] q;
SDC_ITR10
This rule flags violation if set_driving_cell is set on an input port but set_load is
Description
not set on it.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Warning
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Naming Ruleset
The following rule is from the Naming ruleset:
SDC_NAM01
Using the same name for clocks as port or pin names confuses timing analysis
Description
and synthesis tools.
Policy Constraints
Ruleset Naming
Language VHDL/Verilog
Type SDC
Severity Error
Outputs Ruleset
The following rules are from the Outputs ruleset:
SDC_ODL01
This rule checks to make sure all outputs and inout ports of a block are
constrained by set_output_delay commands. If they aren't, Leda flags an error.
Description
The output points to the unconstrained output signal that Leda has inferred as a
clock, and the Path Viewer shows the path from this signal to a flip-flop.
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows an SDC file that is missing a set_output_delay command for an output
port in the design.
// SDC File
# SDC_ODL01 violation--no set_output_delay constraint for output port
// Design File
module simple_reg (clk, d, q);
parameter nb_bit = 8;
input clk;
input [1: nb_bit] d;
output [1: nb_bit] q;
reg [1: nb_bit] q;
always @(negedge clk) q = d;
endmodule
SDC_ODL02
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Description This rule will flag violation if more than one output delay constraint is used on
an output with different clocks and without add delay options.
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to flag an error because more than one output delay constraint is
used on an output with different clocks.
// SDC File
create_clock -name CLK -period 10 [get_ports CLKIN]
create_generated_clock -name GCLK -source [get_ports CLKIN]
-divide_by 2 Q1
create_clock -name VCLK -period 20
# SDC_ODL02 violation
set_output_delay 2.5 [get_ports Q1] -clock [get_clocks CLK]
set_output_delay 2.5 [get_ports Q1] -clock [get_clocks GCLK]
set_output_delay 2.5 [get_ports Q1] -clock [get_clocks VCLK]
// Design File
module mSDC_ODL02 (D1, D2, D3, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_ODL03
Description This rule flags if all the elements of a bus do not have same min-max delays.
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
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Type SDC
Severity Warning
SDC_ODL04
When some options such as -rise, -fall, -min, and -max are used with
set_output_delay commands, the counterpart options must also be present.
Description
Otherwise, Leda flags an error. The output points to the incomplete command in
the SDC file checked.
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows an SDC file with a min delay specified, but no max.
// SDC File
set_output_delay -min 1.09 clk
# SDC_ODL04 violation--min specified but no max
// Design File
module simple_reg (clk, d, q);
parameter nb_bit = 8;
input clk;
input [1: nb_bit] d;
output [1: nb_bit] q;
reg [1: nb_bit] q;
always @(negedge clk) q = d;
endmodule
SDC_ODL05
Setting inconsistent delay values compared to the clock period may cause the
Description
synthesis tool to run for a long time and result in poor quality of results.
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows an SDC file that contains conflicting delay values for the outputs relative
to the clock period.
// SDC File
create_clock -period 1.0 -name clk
set_output_delay -max -clock clk 1.1 q
set_output_delay -min -clock clk 1.1 q;
# SDC_ODL05 violation--output delay value inconsistent with clock period
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// Design File
module simple_reg (clk, d, q);
parameter nb_bit = 8;
input clk;
input [1: nb_bit] d;
output [1: nb_bit] q;
reg [1: nb_bit] q;
always @(negedge clk) q = d;
endmodule
SDC_ODL06
Setting inconsistent delay values compared to a wrong (real) clock period may
cause the synthesis tool to run for a long time and result in poor quality of
results. The secondary messages of this rule could be one of the following:
Description
Right clock is %s3
Right clock source is (this does not have a corresponding SDC clock
definition) %s4
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows an SDC file with output delays specified relative to the wrong clock.
// SDC File
create_clock -period 1.0 -name clk1 clk1
create_clock -period 1.0 -name clk2 clk2
set_output_delay -clock [get_clocks clk1] 0.5 q2
set_output_delay -clock [get_clocks clk2] 0.5 q1
// Design File
module top (clk1, clk2, d1, d2, q1, q2, q3);
input clk1, clk2;
input d1, d2;
output q1, q2;
reg q1, q2;
input d3;
output q3;
reg q3;
endmodule
SDC_ODL07
Description Setting output delay values compared to real clocks instead of virtual clocks
may cause the synthesis tool to run for a long time and result in poor quality of
results.
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Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
Using a virtual clock as reference clock may help in situations where you want to change the
reference clock from REAL_CLK1 to REAL_CLK2 (see example below). In this example, you
need to change the virtual clock definition (that is, modify its parameters similar to
REAL_CLK1). This changes the reference clock. Using the virtual clock helps avoid situations
where your real clock name is used in all set_input_delay and set_output_delay commands.
When you decide to change the reference clock, you have edit all the input and output delay
commands.
// SDC File
Create_clock -name REAL_CLK1 -period 10 -waveform{0,5} \
[get_ports clk_in1 ]
Create_clock -name REAL_CLK2 -period 15 -waveform{0,7.5} \
[get_ports clk_in2]
Create_clock -name Virtual_clk -period 10 -waveform {0,5}
#same parameters as REAL_CLK1
Set_input_delay 2.0 -source Virtual_clk [get_ports in1]
Set_input_delay 3.0 -source Virtual_clk [get_ports in2]
Set_input_delay 4.0 -source Virtual_clk [get_ports in3]
Set_input_delay 1.5 -source Virtual_clk [get_ports out1]
Set_input_delay 0.5 -source Virtual_clk [get_ports out2]
Set_input_delay 4.5 -source Virtual_clk [get_ports out3]
This next SDC file example shows an output delay value set to a real clock, which Leda flags
as an error.
// SDC File
create_clock -name clk1 -period 1.0 clk1
set_output_delay -clock clk1 1.0 q1
# SDC_ODL07 violation--output delay relative to real clock
// Design File
module simple_reg (clk1, clk2,d1,d2, q1,q2);
parameter nb_bit = 8;
input clk1,clk2;
input [1: nb_bit] d1,d2;
output [1: nb_bit] q1,q2;
reg [1: nb_bit] q1,q2;
always @(negedge clk1) q1 = d1;
always @(negedge clk2) q2 = d2;
endmodule
SDC_ODL08
This rule will flag violation if the output delay vs. clock period (respect to which
Description
clock it is specified) doesn't match with user-defined ratio.
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
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Severity Error
Example
This example causes Leda to flag an error because the output delay vs. clock period doesn't
match with user-defined ratio.
// SDC File
create_clock -name CLK -period 10 [get_ports CLKIN]
create_generated_clock -name GCLK -source [get_ports CLKIN]
-divide_by 2 Q1
# SDC_ODL08 violation
set_output_delay 2.5 [get_ports Q1]
set_output_delay 2.5 [get_ports Q2] -clock [get_clocks CLK]
set_output_delay 2.5 [get_ports Q3] -clock [get_clocks GCLK]
set_output_delay 2 [get_ports Q4] -clock [get_clocks CLK]
// Design File
module mSDC_ODL08 (D1, D2, D3, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_ODL09
SDC_ODL10
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Severity Note
SDC_ODL11
SDC_ODL12
Setting negative output delay values or positive/zero minimum delay values can
Description
cause problems for timing analysis and synthesis tools.
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example shows an SDC file with negative output delay values that Leda flags as errors.
// SDC File
set_output_delay -1.0 -max q2 -clock clk2
set_output_delay -1.0 -min q2 -clock clk2
set_output_delay -1.0 -min q1 -clock clk1
set_output_delay -1.0 -min q1 -clock clk1 -add_delay
set_output_delay 3.0 -min q1 -clock clk1 -add_delay
# SDC_ODL12 violation--negative output delays
// Design File
module simple_reg (clk1, clk2,d1,d2, q1,q2);
parameter nb_bit = 8;
input clk1,clk2;
input [1: nb_bit] d1,d2;
output [1: nb_bit] q1,q2;
reg [1: nb_bit] q1,q2;
always @(negedge clk1) q1 = d1;
always @(negedge clk2) q2 = d2;
endmodule
SDC_ODL20
This rule will flag violation if there is no -clock option in output delay constraint
Description
w.r.t an already defined clock.
Policy Constraints
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Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to flag an error because there is no clock option used in output
delay constraint w.r.t an already defined clock.
// SDC File
create_clock -name CLK -period 10 [get_ports CLKIN]
create_generated_clock -name GCLK -source [get_ports CLKIN]
-divide_by 2 Q1
# SDC_ODL20 violation
set_output_delay 2.5 [get_ports Q1]
set_output_delay 2.5 [get_ports Q2]
set_output_delay 2.5 [get_ports Q3] -clock [get_clocks CLK]
set_output_delay 2.5 [get_ports Q4] -clock [get_clocks CLK1]
// Design File
module mSDC_ODL20 (D1, D2, D3, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;\
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_ODL21
Description This rule will flag violation if output delay is specified for a hierarchical port.
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity Error
Example
This example causes Leda to flag an error because output delay is specified for a hierarchical
port.
// SDC File
create_clock -name CLK1 -period 10 [get_ports CLKIN]
create_clock -name CLK2 -period 10 [get_ports CLKIN1]
# SDC_ODL21 violation
set_output_delay 2.5 [get_ports Q1]
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set_output_delay 2.5 [get_pins inst/Q]
set_output_delay 2.5 [get_pins Q3_reg/Q]
// Design File
module mSDC_ODL21 ( D0, D1, D2, CLKIN, CLKIN1, Q1, Q2, Q3 );
input D0;
input D1;
input D2;
input CLKIN;
input CLKIN1;
output Q1;
output Q2;
output Q3;
wire Q0;
SDC_OLD01
For each output, a load value must be defined via a set_load command in your
Description constraint file. If a load value is not defined for an output (zero is the default
value), Leda flags an error for this rule.
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity Error
SDC_OLD02_A
This rule flags a violation if the load value (specified by set_load) is greater than
Description
the corresponding parameter value in the RTL.
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity Warning
Example
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module mSDC_OLD02
output Q;
...
endmodule
default_max_capacitance = 5
Constraint file
...
set_load 12.5 [get_ports Q] # Flag violation of SDC_OLD02_A
SDC_OLD02_B
This rule flags violation if the load value (specified by set_load) is greater than
Description
the default_max_capacitance value in library for NETLIST design.
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity Warning
Example
.lib file
Library (test) {
...
default_max_capacitance : 6.0;
default_max_fanout : 20.0;
defaullt_fanout_load : 1.0;
...
}
Constraint file
...
set_load 12.5 [get_ports Q] # Flag violation of SDC_OLD02_B
Power Ruleset
The following rules are from the Power ruleset:
SDC_POW01
Description None.
Policy Constraints
Ruleset Power
Language VHDL/Verilog
Type SDC
Severity Warning
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SDC_POW02
Description None.
Policy Constraints
Ruleset Power
Language VHDL/Verilog
Type SDC
Severity Warning
Structure Ruleset
The following rules are from the Structure ruleset:
SDC_STR21
Description This rule will flag violation if set_max_area is not set in constraint file.
Policy Constraints
Ruleset STR
Language VHDL/Verilog
Type SDC
Severity Warning
Example
Leda flags a warning for this example because set_max_area is not set in the constraint file.
// SDC File
# SDC_STR21 violation
set_max_dynamic_power 25
set_max_leakage_power 25
// Design File
module mSDC_STR21();
endmodule
SDC_STR23
This rule flags a violation if the specified operating condition is not found in the
Description
library.
Policy Constraints
Ruleset STR
Language VHDL/Verilog
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Type SDC
Severity Warning
SDC_STR24
This rule will flag violation if same operating condition is defined in constraint
Description
file more than once.
Policy Constraints
Ruleset STR
Language VHDL/Verilog
Type SDC
Severity Warning
Example
Leda flags a warning for this example because operating condition is defined more than once.
// SDC File
set_operating_conditions WCCOM
set_max_area 90
set_max_dynamic_power 25
# SDC_STR24 violation
set_operating_conditions WCIND
set_max_leakage_power 12.5
set_operating_conditions BCCOM
// Design File
module mSDC_STR24 ();
endmodule
Miscellaneous Ruleset
The following rules are from the miscellaneous ruleset:
SDC_MSC02
SDC_MSC04
This rule flags a violation if the specified wire_load model is not found in the
Description
library.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity Warning
SDC_MSC05
Description None.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity Error
SDC_MSC07
Description None.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity Error
SDC_MSC08
Description None.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity Error
SDC_MSC09
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Description None.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity Error
SDC_MSC11
Description None.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity Error
SDC_MSC13
Description None.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity Error
SDC_MSC14
Description None.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity Error
SDC_MSC16
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This rule flags violation when any of rise, fall or setup, hold option is used but
Description
the counterpart option is not present for inter-clocks.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity Error
SDC_MSC25
Example
module mSDC_MSC25
input D1, D2;
...
endmodule
Constraint file
...
set_driving_cell D1 -lib_cell IV //Flag violation
set_driving_cell D2 -lib_cell OR2 //OK
SDC_MSC26
This rule verifies that only library cells are specified as don't use (no design
Description cells); that is, if the cell used in the set_dont_use command is not found in
library, then Leda flags a violation.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity Warning
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Example
Constraint file
...
set_dont_use mylib/OR2 //OK
set_dont_use mylib/AND //Flag violation
module mSDC_MSC25
input D1, D2;
SDC_MSC27
Objects Ruleset
The following rules are from the objects ruleset:
SDC_OBJ01
Message: Do not set create_clock to input pin of black box macro cells
This rule checks if the create_clock command is set to the input pin of a black
Description
box macro cell. If it is, Leda issues a warning message.
Policy Constraints
Ruleset Objects
Language VHDL/Verilog
Type SDC
Severity Warning
The below test case can be used to validate all the rules of objects ruleset.
module test(clk,d,o,en);
input clk, d, en;
output o;
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endmodule
endmodule
SDC File:
#Objects
set PriInput [get_port "clk"] ;#1
set InPinMacro [get_pins "apll1/RCLK"] ;#2
set OutPinMacro [get_pins "apll1/CLKOA"] ;#3
set OutPinDntTouchCell [get_pin "RCTS1/Z"] ;#4
set HierPin [get_pins "CellA/dataout"] ;#5 CellA/en CellA/datain
set nets [get_nets "CellA/n2"] ;#6
set OutPinReg [get_pins "CellA/REG2/Q"] ;#7
set OutPinCombCell [get_pins "CellA/AND1/Z"] ;#8
set PriOutput [get_port "o"] ;#9
set ClkPinReg [get_pins "CellA/REG1/CP"] ;#10
set DataPinReg [get_pins "CellA/REG2/D"] ;#11
set InPinCombCell [get_pins "CellA/AND1/A"] ;#12
set Clock [get_clocks "clk"] ;#13
set LogicPinOnData [get_pins "CellA/DBUF5/Z"] ;#14
### Constraints
# create_clock
create_clock -p 5 $PriInput ;# OK
create_clock -p 5 $InPinMacro ;# NG, SDC_OBJ01
create_clock -p 5 $OutPinMacro ;# OK
create_clock -p 5 $OutPinDntTouchCell ;# OK
create_clock -p 5 $HierPin ;# NG,SDC_OBJ02
create_clock -p 5 $nets ;# NG,SDC_OBJ03
create_clock -p 5 $OutPinReg ;# OK,SDC_OBJ04
create_clock -p 5 $OutPinCombCell ;# NG,SDC_OBJ05
create_clock -p 5 $PriOutput ; #NG,SDC_OBJ06
create_clock -p 5 $ClkPinReg ;# NG,SDC_OBJ07
create_clock -p 5 $DataPinReg ;# NG,SDC_OBJ08
create_clock -p 5 $InPinCombCell ;# NG,SDC_OBJ09
create_clock -p 5 $Clock ;#NG, SDC_OBJ10
create_clock -p 5 $LogicPinOnData ;#NG,SDC_OBJ11
# create_generated_clock
create_generated_clock -source clk -div 1 -name gclk $PriInput ;#
NG,SDC_OBJ12
create_generated_clock -source clk -div 1 -name gclk $InPinMacro ;#
NG,SDC_OBJ13
create_generated_clock -source clk -div 1 -name gclk $OutPinMacro ;# OK
create_generated_clock -source clk -div 1 -name gclk
$OutPinDntTouchCell ;# OK
create_generated_clock -source clk -div 1 -name gclk $HierPin ;#
NG,SDC_OBJ14
create_generated_clock -source clk -div 1 -name gclk $nets ;#
NG,SDC_OBJ15
create_generated_clock -source clk -div 1 -name gclk $OutPinReg ;# OK
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create_generated_clock -source clk -div 1 -name gclk $OutPinCombCell ;#
NG,SDC_OBJ16
create_generated_clock -source clk -div 1 -name gclk $PriOutput ; # OK
create_generated_clock -source clk -div 1 -name gclk $ClkPinReg ;# OK
create_generated_clock -source clk -div 1 -name gclk $DataPinReg ;#
NG,SDC_OBJ17
create_generated_clock -source clk -div 1 -name gclk $InPinCombCell ;#
NG,SDC_OBJ18
create_generated_clock -source clk -div 1 -name gclk $Clock ;# NG,
SDC_OBJ19
create_generated_clock -source clk -div 1 -name gclk $LogicPinOnData
;#NG,SDC_OBJ20
SDC_OBJ02
This rule checks if the create_clock command is set to the hierarchical pin. If it
Description
is, Leda issues an error message.
Policy Constraints
Ruleset Objects
Language VHDL/Verilog
Type SDC
Severity Error
SDC_OBJ03
This rule checks if the create_clock command is set to a net. If it is, Leda issues
Description
an error message.
Policy Constraints
Ruleset Objects
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Language VHDL/Verilog
Type SDC
Severity Error
SDC_OBJ04
This rule checks if the create_clock command is set to the output pin of a
Description
register. If it is, Leda issues a warning message.
Policy Constraints
Ruleset Objects
Language VHDL/Verilog
Type SDC
Severity Warning
SDC_OBJ05
This rule checks if the create_clock command is set to the output pin of a
Description
combinational cell in clock line. If it is, Leda issues a warning message.
Policy Constraints
Ruleset Objects
Language VHDL/Verilog
Type SDC
Severity Warning
SDC_OBJ06
This rule checks if the create_clock command is set to a primary output. If it is,
Description
Leda issues a warning message.
Policy Constraints
Ruleset Objects
Language VHDL/Verilog
Type SDC
Severity Warning
SDC_OBJ07
Description This rule checks if the create_clock command is set to the clock pin of a
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SDC_OBJ08
This rule checks if the create_clock command is set to the data pin of a register.
Description
If it is, Leda issues a warning message.
Policy Constraints
Ruleset Objects
Language VHDL/Verilog
Type SDC
Severity Warning
SDC_OBJ09
This rule checks if the create_clock command is set to the input pin of a
Description
combinational cell in clock line. If it is, Leda issues a warning message.
Policy Constraints
Ruleset Objects
Language VHDL/Verilog
Type SDC
Severity Warning
SDC_OBJ12
SDC_OBJ13
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This rule checks if the create_generated_clock command is set to the input pin
Description
of a black box macro cell. If it is, Leda issues a warning message.
Policy Constraints
Ruleset Objects
Language VHDL/Verilog
Type SDC
Severity Warning
SDC_OBJ14
SDC_OBJ15
SDC_OBJ16
This rule checks if the create_generated_clock command is set to the output pin
Description
of a combinational cell in clock line. If it is, Leda issues a warning message.
Policy Constraints
Ruleset Objects
Language VHDL/Verilog
Type SDC
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Severity Warning
SDC_OBJ17
This rule checks if the create_generated_clock command is set to the data pin
Description
of a register. If it is, Leda issues a warning message.
Policy Constraints
Ruleset Objects
Language VHDL/Verilog
Type SDC
Severity Warning
SDC_OBJ18
This rule checks if the create_generated_clock command is set to the input pin
Description
of a combinational cell in clock line. If it is, Leda issues a warning message.
Policy Constraints
Ruleset Objects
Language VHDL/Verilog
Type SDC
Severity Warning
Changes in constraints data are usually made manually at different stages of the design flow.
With the design size growing exponentially, the size of the constraints file has also grown
significantly. Changing constraints data at different stages for a huge design and managing
them manually to make sure that a potential problem is not introduced is a herculean task.
SDC equivalency check is an approach to make sure that such faults are exposed at the right
stage of the design cycle.
SDC equivalency check compares two SDC files belonging to two different design phases and
reports any discrepancies in the intent of design constraints in the two files. The block diagram
of the SDC equivalency checker is as follows:
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Two SDC files are said to be equivalent, if the following information are same in both SDC
files:
SDC Equivalency checks can be used only through the Tcl mode. You can use the
-compare_file option with the read_constraints command to access the SDC Equivalency
checks. A simple example with two SDC files namely SDC1.tcl and SDC2.tcl is as follows:
To read the first constraints file, you need to use the read_constraints command in the same
way as you do when a SDC file for inconsistency. This SDC file is referred to as the reference
SDC file in the rule messages.
To read the second constraints file, you need to use -compare_file option with the
read_constraints command. This SDC file is referred to as the compare SDC file in the rule
messages.
The options -for_equivalency and -compare_file are functionally equivalent. Although, Leda
recommends you to replace the -for_equivalency option with -compare_file.
Leda Equivalency checks can be used to verify the equivalency between a pre-synthesis SDC
file and a post-synthesis SDC file. The post-synthesis (netlist) SDC file generated by the
implementation tools is most likely to be different from that of the pre-synthesis SDC file
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because of the various transformations done by the tool. The implementation tools generate
the automated setup file (.svf) that has the transformation information. You need to provide
this .svf file to check the equivalency between a pre-synthesis SDC file and a post-synthesis
SDC file. The usage model is as follows:
1. In Tcl shell mode, read in the post-synthesis netlist file that you want to check:
leda> read_verilog netlist_file.v
2. Elaborate the design by specifying the top-level module or entity:
leda> elaborate -top my_top_module -nohierdump
3. Read the reference SDC file of the design. Read in an SDC file using the read_constraints
command:
leda> read_constraints netlist_SDC_file.tcl
4. Provide the .svf file generated by DC during synthesis process to create the above netlist
using the following command:
leda> set_svf my_DC_run.svf
5. Read the pre-synthesis SDC file as compare SDC file.
leda> read_constraints -compare_file compare_SDC_file.tcl
6. Run the Checker using the check command with the -sdc switch and pointing to the
configuration file using the -config option:
leda> check -sdc -config config_file
You can use the command remove_constraint to remove the previously read constraints
information.
Syntax
remove_constraint [ -all ] [ -blocks ] [ -block block_name ] [ -compare ] [ -reference
]
Arguments
-all Removes all the constraints information from the memory.
-blocks Removes all the block level constraints information.
-blocks block_name Removes only the constraints information of specified block.
-compare Removes the constraints information of compare file.
-reference Removes the constraints information of reference file.
You can use the command set_svf to specify the .svf to be read by Leda to understand the
transformation information required for checking the equivalence between a pre-synthesis
SDC file and a post-synthesis SDC file.
Syntax
set_svf <file_name>
Arguments
file_name Specify the file to be read.
There are restrictions on the nature of SDC files that are given as inputs for checking SDC
equivalency for a reference design.
SDC is specified with respect to design nodes that do not change through
implementation. For example:
- Input/output ports
- Flip-flop/memory pins
- Hierarchical module ports/pins
You need to regenerate the golden SDC file, if re timing, and hierarchy manipulation
are done after golden SDC file is created.
If one of the SDC file belongs to RTL, then the design object reference in this file
should be in the way Synopsys Design Compiler supports.
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module test(D, Clk, rst, Q);
input D, Clk, rst;
output Q;
reg temp;
The inferred flip-flop pins (temp) in RTL code should be referred in RTL-SDC file as follows:
[ get_pins temp_reg/D ]
[ get_pins temp_reg/Q ]
[ get_pins temp_reg/CD ]
Equivalency Ruleset
The following rules are from the Equivalency ruleset:
SDC_EQCLK01
This rule checks for inconsistency between the reference file clock constraint
and the compare file clock constraint. For each primary clock definition in the
reference file, it checks if there exists a corresponding clock specification in the
compare file with same specifications.Leda issues this error message for the
Description following:
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk, a, b, c, dout );
input clk, a, b, c;
output dout;
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//reg temp1, temp2, temp3;
endmodule
endmodule
assign w1 = ~d;
always @(posedge clk)
q <= w1;
endmodule
// Output
cmp.sdc : 2 : NOTE : SDC command ignored for design object f2/clk
cmp.sdc : 3 : NOTE : SDC command ignored for design object b1/clk
1: create_clock -name CLK1 -period 10 [get_ports clk]
^
cmp.sdc:1: EQV> [ERROR] SDC_EQCLK01: Clock constraints are inconsistent
: Waveform not matching
/new_file.sdc:8: : : Reference SDC file clock parameters:
(ClockType)REAL CLOCK (Period) 10.000000 (Waveform) 0.000000 4.000000
cmp.sdc:1: : : Compare SDC file clock parameters: (ClockType)REAL CLOCK
(Period) 10.000000 (Waveform) 0.000000 5.000000
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQCLK01
#HTM1: "pol_constraints.html#SDC_EQCLK01"
SDC_EQCLK02
Description This rule checks for missing clock constraints between the reference constraint
file and the compare constraint file. Leda issues this error message for the
following:
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Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk, a, b, c, dout );
input clk, a, b, c;
output dout;
//reg temp1, temp2, temp3;
endmodule
endmodule
assign w1 = ~d;
always @(posedge clk)
q <= w1;
endmodule
// Output
9: create_clock [get_pins f2_q_reg/CP] -name CLK2 -period 20 -
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waveform {0 15}
^
new_file.sdc:9: EQV> [ERROR] SDC_EQCLK02: Clock constraint is missing in
compare SDC file
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO new_file.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQCLK02
#HTM1: "pol_constraints.html#SDC_EQCLK02"
SDC_EQCLK03
This rule checks for inconsistency between the clock transition values in
reference sdc file and compare sdc file. Leda flags this violation if the clock
transition values are inconsistent. Leda also issues this error message for the
following:
Description
clock transition constraint present in reference constraints file but
missing in compare constraints file.
clock transition constraint present in compare constraints file but
missing in reference constraints file.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk, a, b, c, dout );
input clk, a, b, c;
output dout;
//reg temp1, temp2, temp3;
endmodule
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endmodule
assign w1 = ~d;
always @(posedge clk)
q <= w1;
endmodule
// Output
1: create_clock -name CLK1 -period 10 [get_ports clk]
^
cmp.sdc:1: EQV> [ERROR] SDC_EQCLK03: Clock transition constraints are
inconsistent : Clock Transition missing in reference file
cmp.sdc:6: : : Compare SDC file clock transition parameters:(Max Rise)
0.000000 (Max Fall) 2.500000 (Min Rise) 0.000000 (Min Fall) 2.500000
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQCLK03
#HTM1: "pol_constraints.html#SDC_EQCLK03"
SDC_EQCLK04
This rule checks for inconsistency between the clock uncertainty values in
reference sdc file and compare sdc file. Leda flags this violation if the clock
uncertainty values are inconsistent. Leda also issues this error message for the
following:
Description
clock uncertainty constraint present in reference constraints file but
missing in compare constraints file.
clock uncertainty constraint present in compare constraints file but
missing in reference constraints file.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
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Severity Error
Example
// Design File
module test ( clk, a, b, c, dout );
input clk, a, b, c;
output dout;
//reg temp1, temp2, temp3;
endmodule
endmodule
assign w1 = ~d;
always @(posedge clk)
q <= w1;
endmodule
// Output
1: create_clock -name CLK1 -period 10 [get_ports clk]
^
cmp.sdc:1: EQV> [ERROR] SDC_EQCLK04: Clock uncertainty constraints are
inconsistent : Clock Uncertainty missing in reference file
cmp.sdc:5: : : Compare SDC file clock uncertainty parameters:(Setup)
0.100000 (Hold) 0.000000
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#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQCLK04
#HTM1: "pol_constraints.html#SDC_EQCLK04"
SDC_EQIDL01
This rule checks for inconsistency between the reference file input delay
constraint and the compare file input delay constraint. For each primary input,
the effective input delay constraint of the reference file is compared with the
effective input delay constraint of the compare file.Leda issues this error
Description message for the following:
Mismatch in max_rise, max_fall, min_rise, min_fall
max_rise, max_fall, min_rise, min_fall are present in one file but
missing in the other file with respect to same clock or time 0.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk, a, b, c, dout );
input clk, a, b, c;
output dout;
//reg temp1, temp2, temp3;
endmodule
endmodule
assign w1 = ~d;
always @(posedge clk)
q <= w1;
endmodule
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// Output
SDC_EQIDL02
This rule checks for missing input delay constraints between the reference
constraint file and the compare constraint file. Leda issues this error message
for the following:Leda issues this error message for the following:
Description No input delay present in reference file with reference to the same
clock or time 0, but specified in compare file.
No input delay present in compare file with reference to the same
clock or time 0, but specified in reference file.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk, a, b, c, dout );
input clk, a, b, c;
output dout;
//reg temp1, temp2, temp3;
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flop f2 (.clk(temp1), .d(b), .q(temp2) );
block b1 (.clk(temp2), .d(c), .q(dout) );
endmodule
endmodule
assign w1 = ~d;
always @(posedge clk)
q <= w1;
endmodule
// Output
11: set_input_delay -clock CLK1 5 [get_ports a]
^
new_file.sdc:11: EQV> [ERROR] SDC_EQIDL02: Input delay constraint is
missing in compare SDC wrt clock CLK1 for input port test.a
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO new_file.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQIDL02
#HTM1: "pol_constraints.html#SDC_EQIDL02"
SDC_EQODL01
Description This rule checks for inconsistency between the reference file output delay
constraint and the compare file output delay constraint. For each primary
output, the effective output delay constraint of the reference file is compared
with the effective output delay constraint of the compare file.Leda issues this
error message for the following:
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk, a, b, c, dout );
input clk, a, b, c;
output dout;
//reg temp1, temp2, temp3;
endmodule
endmodule
assign w1 = ~d;
always @(posedge clk)
q <= w1;
endmodule
// Output
4: set_output_delay 10 [get_ports zout] -clock [get_clocks CLK1]
^
cmp.sdc:4: EQV> [ERROR] SDC_EQODL01: Output delay constraints are
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inconsistent : MaxRise MaxFall MinRise MinFall delays not matching
new_file.sdc:9: : : Reference SDC output delays: (Max Rise) 11.000000
(Max Fall) 11.000000 (Min Rise) 11.000000 (Min Fall) 11.000000
cmp.sdc:4: : : Compare SDC output delays: (Max Rise) 10.000000 (Max
Fall) 10.000000 (Min Rise) 10.000000 (Min Fall) 10.000000
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQODL01
#HTM1: "pol_constraints.html#SDC_EQODL01"
SDC_EQODL02
This rule checks for missing output delay constraints between the reference
constraint file and the compare constraint file. Leda issues this error message
for the following:Leda issues this error message for the following:
Description No output delay present in reference file with reference to the same
clock or time 0, but specified in compare file.
No output delay present in compare file with reference to the same
clock or time 0, but specified in reference file.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk, a, b, c, dout );
input clk, a, b, c;
output dout;
//reg temp1, temp2, temp3;
endmodule
endmodule
assign w1 = ~d;
always @(posedge clk)
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q <= w1;
endmodule
SDC_EQFLP01
This rule checks for inconsistency between the compare file false path constraint
and the reference file false path constraint. Leda issues this error message if the
Description
setup_rise, setup_fall, hold_rise or hold_fall options are not matching for the
paths.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk1, clk2, d0, d1, d2, qout );
endmodule
endmodule
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input a, b;
output z;
assign z = a & b;
endmodule
// Output
10: set_false_path -fall -from [get_clocks CLK1] -to [get_clocks CLK2]
^
new_file.sdc:10: EQV> [ERROR] SDC_EQFLP01: False path constraints are
inconsistent : SetupFall HoldFall option not matching
new_file.sdc:10: : : Clock domain start point CLK1
new_file.sdc:10: : : Clock domain end point CLK2
NO_FILE_INFO:0: : : Compare SDC file false path command
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO new_file.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQFLP01
#HTM1: "pol_constraints.html#SDC_EQFLP01"
SDC_EQFLP02
This rule checks for missing false path constraints between the reference
constraint file and the compare constraint file. Leda issues this error message
for the following: For each false path specified in the reference file, this rule
checks if there exists a false path specification in the compare file which
Description
contains that path.Leda issues this error message if the reference file false path
is not covered by any false path constraint in equivalency file. Leda also
considers setup_rise, setup_fall, hold_rise and hold_fall conditions if they are
specified.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk1, clk2, d0, d1, d2, qout );
endmodule
endmodule
// Output
4: set_false_path -from [get_clocks CLK1] -to [get_clocks CLK2]
^
cmp.sdc:4: EQV> [ERROR] SDC_EQFLP02: False path constraint is missing in
reference SDC file
cmp.sdc:4: : : Clock domain start point CLK1
cmp.sdc:4: : : Clock domain end point CLK2
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQFLP02
#HTM1: "pol_constraints.html#SDC_EQFLP02"
SDC_EQMCP01
This rule checks for inconsistency between the reference file multicycle path
constraint and the compare file multicycle path constraint. Leda issues this error
Description
message if the setup_rise, setup_fall, hold_rise, hold_fall options are not
matching for the paths.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk1, clk2, d0, d1, d2, qout );
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input clk1, clk2, d0, d1, d2;
output qout;
wire and_z, combo_d, mux_z, temp;
endmodule
endmodule
// Output
10: set_multicycle_path 2 -from [get_clocks CLK1] -to [get_clocks CLK2]
^
new_file.sdc:10: EQV> [ERROR] SDC_EQMCP01: Multicycle path constraints
are inconsistent : SetupFall HoldRise HoldFall option not matching
NO_FILE_INFO:0: : : Clock domain start point: CLK1
NO_FILE_INFO:0: : : Clock domain end point: CLK2
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO new_file.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQMCP01
#HTM1: "pol_constraints.html#SDC_EQMCP01"
SDC_EQMCP02
This rule checks for missing multi-cycle path constraints between the reference
constraint file and the compare constraint file.For each multicycle path specified
in reference file, this rule checks if there exists a multicycle path specification in
equivalency file which contains that path.Leda issues this error message in the
Description following cases:
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Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk1, clk2, d0, d1, d2, qout );
endmodule
endmodule
// Violation
10: set_multicycle_path 2 -from [get_clocks CLK1] -to [get_clocks CLK2]
^
new_file.sdc:10: EQV> [ERROR] SDC_EQMCP01: Multicycle path constraints
are inconsistent : SetupFall HoldRise HoldFall option not matching
NO_FILE_INFO:0: : : Clock domain start point: CLK1
NO_FILE_INFO:0: : : Clock domain end point: CLK2
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO new_file.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQMCP01
#HTM1: "pol_constraints.html#SDC_EQMCP01"
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SDC_EQMCP03
This rule checks for inconsistency in the multipath multiplier values between the
reference constraint file and the compare constraints file.Leda issues this error
message in the following cases:
Description
Path multipliers do not match between the two files.
Leda also considers the setup_rise, setup_fall, hold_rise and hold_fall conditions
if they are specified.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk1, clk2, d0, d1, d2, qout );
endmodule
endmodule
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// Violation
4: set_multicycle_path 2 -from [get_clocks CLK1] -to [get_clocks CLK2]
^
cmp.sdc:4: EQV> [ERROR] SDC_EQMCP03: Multicycle path multiplier values
are inconsistent : SetupRise SetupFall HoldRise HoldFall path multiplier
not matching
cmp.sdc:4: : : Path Multiplier in Compare SDC: (SetupRise) 2
(SetupFall) 2 (HoldRise) 2 (HoldFall) 2
new_file.sdc:10: : : Path Multiplier in Reference SDC: (SetupRise) 6
(SetupFall) 6 (HoldRise) 6 (HoldFall) 6
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQMCP03
#HTM1: "pol_constraints.html#SDC_EQMCP03"
SDC_EQCMB01
This rule checks for inconsistency between the reference file max-delay path
Description constraint and the compare file max-delay path constraint. Leda flags this rule if
the rise, fall options are not matching for the paths.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk, d0, d1, d2, d3, sel, qout );
endmodule
endmodule
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module mux (z, sel, x, y);
input sel, x, y;
output z;
reg z;
always @(sel or x or y)
if (sel == 1'b0)
z = x;
else
z = y;
endmodule
// Output
5: set_max_delay 3 -from [get_ports d0] -rise
^
cmp.sdc:5: EQV> [ERROR] SDC_EQCMB01: Max delay path constraints are
inconsistent : SetupRise HoldRise option not matching
new_file.v:3: :test: Path start point: test.d0
/remote/in01home1/sathishm/SDC_EQV_testing/sdc_eqv/eqcmb_1/new_file.v:7:
:GTECH_FD3S: Path end point: test.f1_q_reg.~iw0
new_file.sdc:10: : : Reference SDC file Max delay path command
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQCMB01
#HTM1: "pol_constraints.html#SDC_EQCMB01"
SDC_EQCMB02
Description This rule checks for missing max delay path constraint between the reference
constraint file and the compare constraints file. Leda issues this error message
for the following conditions:
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7/28/2020 1 Constraints Coding Rules
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk, d0, d1, d2, d3, sel, qout );
endmodule
endmodule
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7/28/2020 1 Constraints Coding Rules
} {clk2}
set_min_delay 3 -from [get_ports i1]
SDC_EQCMB03
This rule checks for inconsistency between the max-delay path value present in
reference constraint file and the compare constraints file. Leda issues this error
message for the following conditions:
Description
The max delay values do not match between the two files.
Leda also considers the rise and fall conditions if they are specified.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk, d0, d1, d2, d3, sel, qout );
endmodule
endmodule
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7/28/2020 1 Constraints Coding Rules
input sel, x, y;
output z;
reg z;
always @(sel or x or y)
if (sel == 1'b0)
z = x;
else
z = y;
endmodule
SDC_EQCMB04
This rule checks for inconsistency between the reference file min-delay path
Description constraint and the compare file min-delay path constraint. Leda flags this rule if
the rise, fall options are not matching for the paths.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk, d0, d1, d2, d3, sel, qout );
endmodule
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7/28/2020 1 Constraints Coding Rules
input clk, d;
output q;
reg q;
endmodule
// Violation
3: set_min_delay 3 -from [get_ports d0] -rise
^
cmp.sdc:3: EQV> [ERROR] SDC_EQCMB04: Min delay path constraints are
inconsistent : SetupRise HoldRise option not matching
new_file.v:3: :test: Path start point: test.d0
new_file.v:7: :GTECH_FD3S: Path end point: test.f1_q_reg.~iw0
new_file.sdc:9: : : Reference SDC file Min delay path command
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQCMB04
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9: set_min_delay -fall 3 -from [get_ports d0]
^
new_file.sdc:9: EQV> [ERROR] SDC_EQCMB04: Min delay path constraints are
inconsistent : SetupFall HoldFall option not matching
new_file.v:3: :test: Path start point: test.d0
new_file.v:7: :GTECH_FD3S: Path end point: test.f1_q_reg.~iw0
cmp.sdc:3: : : Reference SDC file Min delay path command
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO new_file.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQCMB04
SDC_EQCMB05
This rule checks for missing min delay path constraint between the reference
constraint file and the compare constraints file. Leda issues this error message
for the following conditions:
Description
The compare file min-delay path is not covered by any min-delay path
constraint in the reference file.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
// Design File
module test ( clk, d0, d1, d2, d3, sel, qout );
endmodule
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q <= d;
endmodule
SDC_EQCMB06
This rule checks for inconsistency between the min-delay path value present in
reference constraint file and the compare constraints file. Leda issues this error
message for the following conditions:
Description
The min delay values do not match between the two files.
Leda also considers the rise and fall conditions if they are specified.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity Error
Example
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// Design File
module test ( clk, d0, d1, d2, d3, sel, qout );
endmodule
endmodule
// Violation
3: set_min_delay 13 -from [get_ports d0] -rise
^
cmp.sdc:3: EQV> [ERROR] SDC_EQCMB06: Min delay constraint values are
inconsistent : SetupRise HoldRise delay value not matching
cmp.sdc:3: : : Min delay values in Compare SDC: (SetupRise) 13.000000
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(HoldRise) 13.000000
new_file.sdc:9: : : Min delay values in Reference SDC: (SetupRise)
3.000000 (HoldRise) 3.000000
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQCMB06
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