Assign-1

module sevensegment( IN, A, B, C, D, E, F, G);

input [3:0] IN;

output A;
output B;
output C;
output D;
output E;
output F;
output G;

reg A;
reg B;
reg C;
reg D;
reg E;
reg F;
reg G;
always@(IN)
begin
case (IN)
4'b0000 : begin {A,B,C,D,E,F,G} = 7'b1111110; end
4'b0001 : begin {A,B,C,D,E,F,G} = 7'b0110000; end
4'b0010 : begin {A,B,C,D,E,F,G} = 7'b1101101; end
4'b0011 : begin {A,B,C,D,E,F,G} = 7'b1111001; end
4'b0100 : begin {A,B,C,D,E,F,G} = 7'b0110011; end
4'b0101 : begin {A,B,C,D,E,F,G} = 7'b1011011; end
4'b0110 : begin {A,B,C,D,E,F,G} = 7'b1011111; end
4'b0111 : begin {A,B,C,D,E,F,G} = 7'b1110000; end
4'b1000 : begin {A,B,C,D,E,F,G} = 7'b1111111; end
4'b1001 : begin {A,B,C,D,E,F,G} = 7'b1111011; end

4'b1010 : begin {A,B,C,D,E,F,G} = 7'b1110111; end

4'b1011 : begin {A,B,C,D,E,F,G} = 7'b0011111; end
4'b1100 : begin {A,B,C,D,E,F,G} = 7'b1001110; end
4'b1101 : begin {A,B,C,D,E,F,G} = 7'b0111101; end
4'b1110 : begin {A,B,C,D,E,F,G} = 7'b1001111; end
4'b1111 : begin {A,B,C,D,E,F,G} = 7'b1000111; end

endcase
end

endmodule

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Assign-2

module sevensegment( IN, A, B, C, D, E, F, G);

input [3:0] IN;

output A;
output B;
output C;
output D;
 output E;
output F;
output G;

reg A;
reg B;
reg C;
reg D;
reg E;
reg F;
reg G;
always@(IN)
begin
case (IN)
4'b0000 : begin {A,B,C,D,E,F,G} = 7'b1111110; end
4'b0001 : begin {A,B,C,D,E,F,G} = 7'b0110000; end
4'b0010 : begin {A,B,C,D,E,F,G} = 7'b1101101; end
4'b0011 : begin {A,B,C,D,E,F,G} = 7'b1111001; end
4'b0100 : begin {A,B,C,D,E,F,G} = 7'b0110011; end
4'b0101 : begin {A,B,C,D,E,F,G} = 7'b1011011; end
4'b0110 : begin {A,B,C,D,E,F,G} = 7'b1011111; end
4'b0111 : begin {A,B,C,D,E,F,G} = 7'b1110000; end
4'b1000 : begin {A,B,C,D,E,F,G} = 7'b1111111; end
4'b1001 : begin {A,B,C,D,E,F,G} = 7'b1111011; end
default : begin {A,B,C,D,E,F,G} = 7'b1001111; end

endcase
end

endmodule

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Assign-3

module adder(A, B, out);

input [3:0] A;
input [3:0] B;
output reg [6:0] out;
reg [4:0] temp;

always @(A or B)
begin
temp = A+B;
end

always @(temp)
begin
case (temp)
5'b00000 : begin out = 7'b1111110; end
5'b00001 : begin out = 7'b0110000; end
5'b00010 : begin out = 7'b1101101; end
5'b00011 : begin out = 7'b1111001; end
5'b00100 : begin out = 7'b0110011; end
5'b00101 : begin out = 7'b1011011; end
5'b00110 : begin out = 7'b1011111; end
5'b00111 : begin out = 7'b1110000; end
 5'b01000 : begin out = 7'b1111111; end
5'b1001 : begin out = 7'b1111011; end

5'b01010 : begin out = 7'b1110111; end

5'b01011 : begin out = 7'b0011111; end
5'b01100 : begin out = 7'b1001110; end
5'b01101 : begin out = 7'b0111101; end
5'b01110 : begin out = 7'b1001111; end
5'b01111 : begin out = 7'b1000111; end
default : begin out = 7'b0011101; end
endcase
end

endmodule

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Assign-4

module priprity(d, out);

input [7:0] d;
output [2:0] out;
reg [2:0] out;

always @(d)
begin
if(d[0]==1) out = 3'b000;
else if(d[1]==1) out = 3'b001;
else if(d[2]==1) out = 3'b010;
else if(d[3]==1) out = 3'b011;
else if(d[4]==1) out = 3'b100;
else if(d[5]==1) out = 3'b101;
else if(d[6]==1) out = 3'b110;
else if(d[7]==1) out = 3'b111;
end
endmodule