This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2675381, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS
A Square T-Type (ST-Type) Module for
Asymmetrical Multilevel Inverters
Emad Samadaei, A. Sheikholeslami, S.Asghar Gholamian, J. Adabi

Abstract—This paper introduces a new module for
asymmetrical multilevel inverters with the low number of
components. The module is a square combination of two back-to-
back T-type inverters and some other switches. Square T-Type
(ST-Type) Module produces 17 levels by 12 switches and four
unequal DC sources (two 3VDC and two 1VDC). Also it can be
extended as cascade connection in two strategies to achieve more
levels. The module and its cascade connection are suitable for the
applications with several DC sources systems such as photovoltaic
farms which lead to a modular topology with more voltage levels
at higher voltages. Inherent creation of the negative voltage levels
without any additional circuit (such as H-bridge circuit) is one of
the main features of proposed module. The low total harmonic
distortion (THD) of the output voltage/current and low number of
semiconductors are among other advantages of the proposed
module. Nearest level control (NLC) method as a switching
technique is used to produce high quality output voltage with
lower harmonic contents. Simulations are carried out in
MATLAB/Simulink and a prototype is implemented in the power
electronics laboratory which the simulation and experimental
results show a good performance.
Index Terms— asymmetric, ST-Type, multilevel inverter,
power electronics, Self- Balancing, Nearest Level Control
I. INTRODUCTION
M ultilevel inverters (MLIs) have been developed as a
significant power electronics device in recent years to
operate in renewable energy resources. MLIs are different
arrangements of semiconductor switches to synthesize several
small voltage steps to form a staircase output waveform using
several DC links. MLIs with salient features become attractive
converters for medium/high power applications in comparison
with two levels inverters at the applications of PV farms [1],
wind turbine [2], active power filer [3], drives systems [4] and
electrical vehicle [5]. Some of their superior advantages are
high number of output levels, low harmonic components, low
stress on switches, high efficiency, modularity, scalability and
etc. In general, multilevel converters are classified as:
• Neutral Point Clamped (NPC) [6].
• Flying Capacitor (FC) [7].
• Cascade H-bridge (CHB) [8].
Manuscript received April 25, 2016; revised September 1, 2016 and January
4, 2017; accepted February 22, 2017.
Emad Samadaei, Abdolreza Sheikholeslami, S.Asghar Gholamian and Jafar
Adabi are with the Babol Noshirvani University of Technology, Department of
Computer and Electrical Engineering, Babol, Iran (email:
e.samadaei@stu.nit.ac.ir, asheikh@nit.ac.ir, gholamian@nit.ac.ir,
j.adabi@nit.ac.ir).
0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1
Researchers have a tendency on CHB type due to some
drawbacks of NPC and FC including huge capacitors,
unbalanced DC links and high stress on switches. Moreover,
reduced numbers of components are targeted in design of CHB
topologies. [9-10] investigated conventional and vanguard
topologies for last decade as a reviewing study. Two switches
are considered for a DC link in [11] to generate each positive
level. The modules are connected in series and then H-bridge is
used to create negative levels at the end of modules. This was
followed by [12] with adding of two capacitors in DC sources
to achieve more levels for each module. H-bridges are split into
each module of [12] with the penalty of using more
components.
Asymmetric multilevel inverters with unequal DC links present
new type of topologies which reduced number of components
along with increasing of output waveform quality. Modules are
designed based on optimal using of unequal DC links by
reduced semiconductors. [13-14] designed crossing switches
generate more levels and dividing of stress on switches. [15-16]
presented a type of extended H-bridge with different amount of
DC links. Despite generation of higher levels than other ones,
stress on higher levels switches are obvious that needs higher
rate semiconductor devices. Some other MLIs like hybrid type
topologies are proposed in [17-19] to produce higher levels
although switch stress is reminded. Utilizing H-bridge circuits
to create negative voltage levels is the main disadvantage of
conventional topologies. These circuits increase switching
stress and total standing voltages (TSV) of the semiconductors.
Another constrain of multilevel inverter is voltage balancing.
There are some method to balance on asymmetrical multilevel
inverters [20-23] and there are also some self-balancing module
of multilevel inverters [24-26]. The proposed module are
designed on symmetrical paths of polar level (positive and
negative) without DC component like a self-balancing Module.
This feature make it easier to control the module.
A smart arrangement of semiconductor devices is proposed in
this paper to achieve maximum voltage levels from DC links
which improves economic implementation cost and power
quality. This module uses two DC links with amount of 1VDC
and two DC links with 3VDC. On the other hand, an asymmetric
CHB multilevel module is introduced which named as Square
T-Type (ST-Type). ST-Type module produces 8 positive levels,
8 negative levels and zero level (totally 17 levels) without any
additional circuit to create negative voltage levels. It just
implements 12 switches. The module can be connected together
as cascade connection easily to generate more and higher output
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2675381, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS 2

voltage levels. Section II illustrates proposed multilevel
inverters including module description, switching patterns,
cascade connection and comparison table with similar modules.
Nearest level control (NLC) is introduced for switching
modulation in section III. Power losses are calculated in
sections IV. Simulation and experimental results are shown, V
and VI, respectively. Conclusions are presented in section VII.
II. PROPOSED MOUDLE
Fig.1 shows a general schematic diagram of a T-connection
of switches (two unidirectional and one bidirectional switches)
where the mid-point switch needs to block in both polarities to
prevent the short circuit of DC links [27]. 0, ±𝑉𝐷𝐶 and ±2𝑉𝐷𝐶
can be formed in the output voltage.
Table 1 indicates switch pairs (S1, S2), (S3, S4) and (S5, S6)
which cannot be turned on at the same time. Fig.4 shows output
voltage of the proposed inverter with the associated pulse
pattern in one cycle of fundamental voltage. As shown in Fig.4,
switches S3, S4, S5, S6 and S8 are turned on in low frequency
which reduces switching losses to a great extent. Other switches
also operate in a reasonable switching frequency. Number of
switches turning on per one cycle for each switch is shown in
last row of Table 1.
A
S1 S2
S7

1VDC 1VDC

S3 S8 S4
3VDC 3VDC

Fig.1 The T- connection of switches

S9
It would be interesting to join two T-connections together by S5 S6
some switches to create a new structure to get more output
levels.
A. Module Configuration B
Fig. 2 Proposed ST-Type module of multilevel inverter
A ST-Type module can be achieved by back to back
connections of two T-connections from points A, B and C. This A A A A

S1 S2 S1 S2 S1 S2 S1 S2
means that two unidirectional switches are added from points A S7 S7 S7 S7

and C and one bidirectional switch is added from points B 1V 1V 1V 1V 1V 1V 1V 1V

(Fig.2). DC links are considered as 1VDC and 3VDC for the first S3
3V
S8

3V
S4 S3 S8

3V 3V
S4 S3 S8

3V 3V
S4 S3 S8

3V 3V
S4

and the second T-connections, respectively. Using this idea for S9 S9 S9 S9

S6 S6 S6 S6
multilevel inverters (a different ratio of DC links) generates S5 S5 S5 S5

different number of output voltage levels by fewer 1VDC

B B

2VDC
B

3VDC
B

4VDC
semiconductors. A reduction of harmonic components with low A A A A

switching frequency is expected by increasing the number of S1

S7
S2 S1
S7
S2 S1
S7
S2 S1
S7
S2

output voltage levels. 1V 1V 1V 1V 1V 1V 1V 1V

Fig.2 introduces ST-Type module with a new component S3 S8 S4 S3 S8 S4 S3 S8 S4 S3 S8 S4

3V 3V 3V 3V 3V 3V 3V 3V

arrangement including 12 switches, 12 diodes and 2 unequal S9 S9 S9 S9

DC source pairs. This arrangement sources produces 17 levels S5 S6 S5 S6 S5 S6 S5 S6

(8 positive levels, 8 negative levels and zero level). The main B B B B

-1VDC -2VDC -3VDC -4VDC

concept of this circuit is to create different paths from different A A A A

sides of a DC source to be connected to other sources to achieve S1

S7
S2 S1
S7
S2 S1
S7
S2 S1
S7
S2

negative levels in order to remove H-bridge. Different 1V 1V 1V 1V 1V 1V 1V 1V

switching conditions of ST-Type structure to generate the S3 S8 S4 S3 S8 S4 S3 S8 S4 S3 S8 S4

3V 3V 3V 3V
output levels are shown in Fig.3 and Table 1. 3V 3V 3V 3V

S9 S9 S9 S9
Surrounding switches (S1-S6) are unidirectional switches and S5 S6 S5 S6 S5 S6 S5 S6

middle switches (S7-S9) are bidirectional switches. The B B B B

designing of ST-Type module and their switching paths are 5VDC 6VDC 7VDC 8VDC
A A A A

smartly selected in such a way that There are no positive pole S1

S7
S2 S1
S7
S2 S1
S7
S2 S1
S7
S2

of DC links on the anode side of diode to conduct. Also Fig.3 1V 1V 1V 1V

1V 1V 1V 1V
illustrates the switching paths dose not form any close loop for S3 S8 S4 S3 S8 S4 S3 S8 S4 S3 S8 S4

DC links. Thus, diodes and bidirectional switches guarantees 3V 3V 3V 3V 3V 3V 3V 3V

that short circuiting will be not flowed in ST-Type module. S5

S9
S6 S5
S9
S6 S5
S9
S6 S5
S9
S6

Fig.3 draws the symmetric path of all levels in which the B B B B

balancing of output wave is stable. On other hand, the -5VDC -6VDC -7VDC -8VDC
Fig. 3 Different switching states of proposed ST-Type module of multilevel
number/type of components for each polar level are same. The inverter
module has self-balancing, inherently.

0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2675381, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS 3

TABLE 1 TSV (Total Standing Voltages) of circuit is presented in Table

SWITCHING TABLE
2 as a parameter. The maximum magnitude of the blocking
S1 S2 S3 S4 S5 S6 S7 S8 S9
8VDC 1 0 0 1 1 0 0 0 0
voltage of the power switches are calculated for each switches,
7VDC 0 0 0 1 1 0 1 0 0 according to Fig.3. Then sum of all blocking voltages for the
Positive Level

6VDC 0 1 0 1 1 0 0 0 0 power switches are defined as TSV.

5VDC 1 0 0 1 0 0 0 0 1 S1 is considered to descript the TSV calculation. The
4VDC 1 0 0 0 1 0 0 1 0 maximum blocking voltage of S1 (off-state) is calculated, from
3VDC 0 0 0 0 1 0 1 1 0
Fig.3.(-5VDC or -8VDC) in which two upper DC sources make
2VDC 0 1 0 0 1 0 0 1 0
1VDC 1 0 0 0 0 0 0 1 1 standing voltage on S1 as follows:
-1VDC 0 1 0 0 0 0 0 1 1 VS1=1VDC+1VDC=2VDC; from Fig.3.(-5VDC)
-2VDC 1 0 0 0 0 1 0 1 0 In this way,
Negative level

-3VDC 0 0 0 0 0 1 1 1 0 VS2=1VDC+1VDC=2VDC; from Fig.3.(5VDC)

-4VDC 0 1 0 0 0 1 0 1 0 VS3=1VDC+1VDC+3VDC+3VDC=8VDC; from Fig.3.(4VDC)
-5VDC 0 1 1 0 0 0 0 0 1
-6VDC 1 0 1 0 0 1 0 0 0
VS4=1VDC+1VDC+3VDC+3VDC=8VDC; from Fig.3.(-4VDC)
-7VDC 0 0 1 0 0 1 1 0 0 VS5=3VDC=3VDC; from Fig.3.(-6VDC)
-8VDC 0 1 1 0 0 1 0 0 0 VS6=3VDC=3VDC; from Fig.3.(6VDC)
Num. of turning on
9 9 1 1 3 3 9 2 6 VS7=1VDC =1VDC; from Fig.3.(1VDC)
per 1-cycle VS8=1VDC+3VDC=4VDC; from Fig.3.(5VDC)
VS9=3VDC=3VDC; from Fig.3.(2VDC)
8VDC
7VDC TSV=VS1+VS2+VS3+VS4+ VS5+VS6+VS7+VS8+VS9=40VDC
6VDC
5VDC Figures 5 and 6 are presented the voltage constraints
4VDC on the switches and circuit. Fig.5 illustrates total standing
3VDC
2VDC
1VDC
voltages of each level (-8L,-7L, …, 0, 7L, 8L). It also separates
-1VDC
the voltage standing on each switch for levels by different
-2VDC colors. It is notable that total standing voltage of some group
-3VDC
-4VDC switches are same value for all levels. V(S1+S2)=2VDC,
-5VDC
-6VDC V(S3+S4)=8VDC, V(S5+S6)=6VDC. Fig.6 also depicts the voltage of
-7VDC
-8VDC switches on circle graph in which S1, S2, S7, S8 and S9 have low
S1 voltage standing against total standing voltages for each level.
S2
S3
S4
S5
S6
S7
S8
S9
1VDC, Left
1VDC, Right
3VDC, Left
3VDC, Right
Fig.4 switching pattern/used DC sources of proposed inverter in one cycle

Fig.4 also shows used DC sources for each level with the
direction of polarities. is the symbol of direct polarity and Fig.5 The voltage constraints on the switches
is the symbol of invers polarity. The current of sources is
proportional with levels in which higher levels have higher
𝑉
current ( 𝑜𝑢𝑡). According to above preamble and Fig.4, the
𝑅
ration of power consumption are calculated for each sources as
follows: 1VDC, Left= 23.02%, 1VDC, Right= 13.81%, 3VDC,
Left= 31.57%, 3VDC, Right= 31.57%.
Table 2 shows equations of ST-Type module for number of
voltage levels, semiconductor components, DC sources and
drivers based on the number of module units (n) in middle
column and the number of output levels (NL) in last column. Fig.6 The voltage constraints on the switches
TABLE 2
EQUATIONS OF ST-TYPE MODULE B. Module Extension
Based on number of Based on number Modularity is other Property of ST-Type module to generate
module units of desired levels* more output levels. Cascade connections are useful in
Levels 16n+1 NL
12n 3(NL-1)/4
cumulative DC links applications such as solar PV farm. Fig.7
Number of Switches
Number of Diodes 12n 3(NL -1)/4 shows the cascade connection for two units in series. The first
Driver 9n (NL +1)/2 unit (u1) produces 0, ±1VDC, ±2VDC, ±3VDC, ±4VDC, ±5VDC,
Number of DC sources 4n (NL -1)/4 ±6VDC, ±7VDC and ±8VDC. For the second unit (u2), it can be
𝑁 −1
TSV 40n 5( 𝐿 ) considered two modes. Table 3 shows output levels of units for
2
*
Number of levels are in the form of 16n+1 (n=1, 2, 3…) cascade connections States:

0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2675381, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS 4

TABLE 3
OUTPUT LEVELS OF UNITS FOR CASCADE CONNECTIONS STATES
Unit 1 (u1) Unit 2 (u2)
Mode.I Mode.II
Vu2, VL2= the amount of DC links same as Vu2=total number of levels in pervious units,
Vu1=1VDC
pervious unit, VL2=3xVu,
Vu2=1VDC Vu2=17VDC
VL1=3VDC
VL2=3VDC VL2=51VDC
Output levels: Output levels: Output levels:
0 0 0
1VDC, ±2VDC ±3VDC, ±4VDC ±1VDC, ±2VDC ±3VDC, ±4VDC ±17VDC, ±34VDC ±51VDC, ±68VDC
±5VDC, ±6VDC ±7VDC, ±8VDC ±5VDC, ±6VDC ±7VDC, ±8VDC ±85VDC, ±102VDC ±119VDC, ±136VDC

The combination of unit 1 and unit 2 in mode.I, creates 33 TABLE 5

OUTPUT LEVELS OF UNITS FOR TWO MODULES TO CREATE 289 LEVELS
levels (16 positive levels, 16 negative levels and zero level) as
* u1=
Table 4 and also The combination of unit 1 and unit 2 in u2=
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8

mode.II, creates 289 levels (144 positive levels, 144 negative -136 -144 -143 -142 -141 -140 -139 -138 -137 -136 -135 -134 -133 -132 -131 -130 -129 -128
𝑉 -119 -127 -126 -125 -124 -123 -122 -121 -120 -119 -118 -117 -116 -115 -114 -113 -112 -111
levels and zero level) as Table 5. In Table 4 and 5, u1= 𝐴1𝐵1, -102 -110 -109 -108 -107 -106 -105 -104 -103 -102 -101 -100 -99 -98 -97 -96 -95 -94
𝑉𝐷𝐶
𝑉𝐴2𝐵2 -85 -93 -92 -91 -90 -89 -88 -87 -86 -85 -84 -83 -82 -81 -80 -79 -78 -77
u2= . It can be extended for several units. -68 -76 -75 -74 -73 -72 -71 -70 -69 -68 -67 -66 -65 -64 -63 -62 -61 -60
𝑉𝐷𝐶
-51 -59 -58 -57 -56 -55 -54 -53 -52 -51 -50 -49 -48 -47 -46 -45 -44 -43
A1
-34 -42 -41 -40 -39 -38 -37 -36 -35 -34 -33 -32 -31 -30 -29 -28 -27 -26
-17 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10 -9
S1 S2
0 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
S7
17 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
34 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
51 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
Vu1 Vu1
68 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
85 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93
S3 S8 S4
102 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110
VL1 VL1 119 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
136 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144

S9
S6
C. Comparative Study
S5
Table 6 presents both symmetrical and asymmetrical
B1 topologies in comparison with ST-Type module in mode.I and
A2 mode.II, since the proposed module (ST-Type) is introduced in
two modes. The comparative study between the proposed
S1 S2
S7
topology (in mode.I and mode.II) and other topologies are
investigated based on the number of switches/diodes, DC links,
TSV, the variety in DC sources (N variety) and ability to generate
Vu2 Vu2
negative voltage levels. These topologies are categorized two
S3 S8 S4 groups. Group 1: conventional CHB, Multilevel DC Links
VL2 VL2 (MLDCL) [11], two capacitor links H-bridge (2CLHB) [12]
and crossing switch MLI (CSMLI) [14] for mode.I comparison
S9 in which ST-Type in mode.I uses two variety in DC sources
S5 S6
(Nvariety) similar to [12]. Group 2: Novel H-Bridge [16] CHB
B2 with trinary algorithm (VDC, 3VDC, 9VDC … 3n VDC; n=0, 1, 2...)
Fig.7 The cascade arrangement of modular proposed multilevel [28] for mode.II comparison. In the first group, the number of
semiconductors (switches and diodes) and number of DC links
TABLE 4 3(𝑁 −1) (N −1)
OUTPUT LEVELS FOR TWO MODULES TO CREATE 33 LEVELS are reduced down to 𝐿 and L , respectively for ST-
4 4
* u1=
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 Type mode.I which are significantly lower than other
u2=
𝐿 5(𝑁 −1)
-8 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 topologies. Also TSV is VDC that is placed in
-7 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2
-6 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 reasonable range similar to other ones. Fig.8 shows the line
-5 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 diagram of the number of switches, DC links and TSV in terms
-4 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4
-3 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5
of number of levels for fifty levels for comparative studies for
-2 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 group 1 which declares predominance of proposed module in
-1 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
0 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
comparisons of reduced components. Also comparative studies
1 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 of group 2 are shown by Fig.9 There are not considerable
2 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 different in components between proposed module and CHB
3 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11
4 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12
(Trinary) and novel H-bridge and comparative index are in
5 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 similar ranges. Some issues are considerable in extended H-
6 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
-1 0
bridge module. All sources have different amplitude which
7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 increase cost of DC links. Therefore variety of sources

0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2675381, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS 5

investigated to comparison table in which proposed module voltage levels which does not need any additional circuit. This
(ST-Type) shows lower and better results (Fig.9.c). It is ability along with low components and reasonable TSV
noteworthy that ST-Type topology can generate negative confirms that the proposed inverter can perform well.
TABLE 6
COMPARISON OF SOME MODULAR MULTILEVEL INVERTER TOPOLOGY
Group 1 Group 2
CHB ST-Type CHB Novel H- ST-Type
MLDCL[11] 2CLHB[12] CSMLI[14]
(conventional) Mode.I (trinary) [28] Bridge [16] Mode.II
Number of 𝑁 𝑁 +1 𝑁
2(NL -1) NL+3 NL +1 NL +1 3(NL-1)/4 4𝐿𝑜𝑔3 𝐿 2𝐿𝑜𝑔2 𝐿 12𝐿𝑜𝑔17𝐿
Switches
Number of 𝑁 𝑁 +1 𝑁
2(NL -1) NL+3 NL +1 NL +1 3(NL -1)/4 4𝐿𝑜𝑔3 𝐿 2𝐿𝑜𝑔2 𝐿 12𝐿𝑜𝑔17𝐿
Diodes
Number of 𝑁 𝑁𝐿 +1 𝑁
(NL-1)/2 (NL-1)/2 (NL-1)/2 (NL-1)/2 (NL -1)/4 𝐿𝑜𝑔3 𝐿 𝐿𝑜𝑔2 2 4𝐿𝑜𝑔17𝐿
DC links
𝑁𝐿 −1 𝑁𝐿 −1
TSV* (xVDC) 2(NL -1) 3(NL -1) 2(NL -1) 2(NL -1) 5( ) 2(NL -1) 2(NL -1) 5( )
2 2
𝑁𝐿 +1
𝑁 𝑁
Nvariety 1 1 2 1 2 𝐿𝑜𝑔3 𝐿 𝐿𝑜𝑔2 2 2𝐿𝑜𝑔17𝐿
Negative With With With With With With
inherent inherent
level H-Bridge H-Bridge H-Bridge H-Bridge H-Bridge H-Bridge
* Total Standing Voltages

(a) (a)

(b)
(b)

(c)
Fig.8 comparative studies for group 1: The number of switches (a), DC links
(b) and TSV (c) in terms of number of levels
Symmetrical MLI is most useable in industrial because of
Photovoltaic farm (wind farm, HVDC …) have a same rate
output. Although PV panels can be a factor of each other in
output voltage by groups connection. This is usual method in
(c)
Fig.9 comparative studies for group 2: The number of switches (a), DC links
(b) and Nvariety (c) in terms of number of levels
PV farm to use asymmetric MLI for reducing of components.
In the meanwhile, the variety in DC sources (N variety) is
observed in CHB with trinary algorithm (VDC, 3VDC, 9VDC,
27VDC, 81VDC, 243VDC, 729VDC …), Novel H-bridge [16] and

0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2675381, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS 6

ST-Type in mode.II. There are some consideration as follow: IV. CALCULATION OF LOSSES
1. Although TSV is reasonable range in CHB with trinary Working of power electronics switching devices make two
algorithm, but stress on switches in higher level H-ridges important types of power losses: Conduction losses and
module (27VDC, 81VDC, 243VDC, 729VDC …) is very high. For switching losses. The calculation and behavior of losses in ST-
example: the stress of four switches on the first step are 1VDC Type are presented as follow:
and on fifth step are 81VDC.Thus the module should be provided
different and higher rate of switches that could increases the A. Conduction losses
cost of inverter. Conduction losses (Pc) is defined in on-state of
2. Accessibility to These different sources (27V DC, 81VDC, semiconductor devices. For this purpose, a typical power switch
243VDC, 729VDC …) is impractical. Nvariety is considered in and diode are aimed. It is extendable for a multilevel inverter.
comparison that proposed MLI (ST-Type) shows lower variety The instantaneous conduction losses for a transistor (pc,T(t))
for DC links in which can be reduced the costs (Table 6 and and diode (pc,D(t)) is as follows:
Fig.9.c). pc,T(t) = [VT + RT iβ (t)] i(t) (1)
3. Providing of practical high amplitude sources (27VDC, pc,D(t) = [VD + RD i(t)] i(t) (2)
81VDC, 243VDC, 729VDC …) are needed the series connection Where VT and VD are the on-state voltage of the transistor
of several solar panel (for solar farm application). On the other and diode, respectively. RT and RD are the equivalent resistance
hand, it requires a big area with absorbing for irradiation of of the transistor and diode, respectively, and β is a constant
solar. Atmosphere obstacles (such as cloud) make partial related to the specification of the transistor. Losses of each
shading in high amplitude sources. It causes a deep drop voltage device is calculated based on (1) and (2) and add together to
due to lack of high amplitude sources with low reliability. calculate conduction losses of ST-Type.
This paper presented ST-Type module in two modes
extension that mode.I is more practical for industrial. Although B. Switching Losses
ST-Type with mode.II extension, CHB with trinary algorithm The switching loss (Psw) is the power that is consuming
and extend H-bridge [16] are satisfied mathematically and during the switching turn-on and the turn-off. This loss is
complexity in practical applications. calculated for switch and the antiparallel diode. Turn-on and
turn-off energy loss (Eon, Eoff) can be calculated as follows:
III. NEAREST LEVEL CONTROL (NLC) MODULATION METHOD 𝑡 𝑡 𝑣𝑠𝑤,𝑘 𝐼
𝐸𝑜𝑓𝑓,𝑘 = ∫0 𝑜𝑓𝑓 𝑣(𝑡)𝑖(𝑡)𝑑𝑡 = ∫0 𝑜𝑓𝑓 [( 𝑡) (− (𝑡 −
𝑡𝑜𝑓𝑓 𝑡𝑜𝑓𝑓
The simplified nearest level control method (NLC) controls
switching technique in ST-Type modular multilevel [29]. The 1
𝑡𝑜𝑓𝑓 ))] 𝑑𝑡 = 𝑣𝑠𝑤,𝑘 𝐼 𝑡𝑜𝑓𝑓 (3)
aim is to use NLC method in inverter with a high number of 6
levels which can reduce and simplify the calculation of the 𝑡 𝑡 𝑣𝑠𝑤,𝑘 𝐼′
processor. Fig.10 depicts the NLC method to describe 𝐸𝑜𝑛,𝑘 = ∫0 𝑜𝑛 𝑣(𝑡)𝑖(𝑡)𝑑𝑡 = ∫0 𝑜𝑛 [( 𝑡) (− (𝑡 −
𝑡𝑜𝑛 𝑡𝑜𝑛
mechanism. As shown in Fig.10.a, the controller samples a
point from reference voltage (Vref) and then round it to the 1
𝑡𝑜𝑛 ))] 𝑑𝑡 = 𝑣𝑠𝑤,𝑘 𝐼 ′ 𝑡𝑜𝑛 (4)
6
nearest of voltage level (VaN). Each voltage level has a
switching logic according to the switching lookup table to Where Eoff,k is the turn-off loss of the switch k, toff is the turn
change switches status (Fig.10.b). The sampling is repeated for off time of the switch, I (I’) is the current through the switch
each sample time (Ts). before (after) turning off (on), and V sw,k is the off-state voltage
on the switch. Eon,k is the turn-on loss of the switch k, ton is the
turn-on time of the switch. Thus:
𝑁𝑠𝑤𝑖𝑡𝑐ℎ 𝑁𝑜𝑛,𝑘 𝑁𝑜𝑓𝑓,𝑘
𝑃𝑠𝑤 = 𝑓 [∑𝑘=1 (∑𝑖=1 𝐸𝑜𝑛,𝑘𝑖 + ∑𝑖=1 𝐸𝑜𝑓𝑓,𝑘𝑖 )] (5)
Where f is the fundamental frequency, Non,k and Noff,k are the
number of turning on and off the switch k during a period. Also,
Eon,ki is the energy loss of the switch k during the ith turning on
and Eoff,ki is the energy loss of the switch k during the ith turning
off. The total losses of ST-Type will be:
𝑃𝐿𝑜𝑠𝑠 = 𝑃𝐶 + 𝑃𝑠𝑤 (6)
In this paper, following parameters are considered to calculate
power loss of proposed module:
RT =0.15Ω, VT =2.5 V, RD =0.1Ω, VD =1.5 V, β =1, ton=toff=1
(a)
μs, f =50 Hz. Each dc voltage source has the value of 50 V. The
resistance of the load is 15 Ω.
The calculation is curried out for each switch for one period
by Eqs. (1) to (6) and total losses (Psw) for 1 second are
evaluated 51.395 mW. Also load consumes 5400 W (𝑃𝐿𝑜𝑎𝑑 =
𝑉𝑜𝑢𝑡,𝑅𝑀𝑆 2
for 1 second=1.5 W/sec) and. Therefore the efficiency
𝑅×3600
(b)
Fig.10 Nearest level control (a) Waveform synthesis (b) Control diagram
of ST-Type is 96.53% due to low switching frequency for each
switch (see Fig.4).

0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2675381, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS 7

V. SIMULATIONS RESULTS
The simulations of ST-Type module with NLC modulation
switching method are evaluated by MATLAB/Simulink. Three
cases are considered to investigate the proposed module and its
cascade connection as described in Table 7. Each level is set 10
volts to create 50 Hz sinusoidal waveform. It is expected that
case 3 has most and highest voltage levels and case 2 has more
(b)
and higher voltage levels than alone module in case 1. Fig.12 The output voltage of two ST-Type Modules in case 2 (33-levels) (a)
Waveform (b) Harmonics spectrums
TABLE 7
CASE STUDIES FOR SIMULATION AND EXPERIMENTAL TEST
Description Num. of Vmax (V) Vmax (V)
levels (Simulation) (Experimental)
Section.II.A
Case 1 17 80 192
(Fig.2)
Section.II.B-
Case 2 33 160 384
Mode.I (Fig.7)
Section.II.B-
Case 3 289 1440 --
Mode.II (Fig.7) (a)

Fig.11 shows the output voltage of 17 levels for the proposed

multilevel with THD%=2.77%. Also Fig.12 and Fig.13 depict
the results of cascade connection in case 2 and case 3. They
confirm the performance and modular abilities of proposed
topologies as 33 levels with THD=1.39% for case 2 and 289
levels with THD=0.04% for case 3. Fig.11.b, Fig.12.b and
Fig.13.b also illustrate harmonics spectrums which validate
each harmonic order is in low range and under 5% (based on
IEEE519). Cascade connections have good performance to
create waveform as well as the sinusoidal waveform. All results
satisfied IEEE 519 (i.e. max. of THD% ≤ 8%) in which the
output do not need any LC-filter.
(a)
(b)
Fig.13 The output voltage of two ST-Type Modules in case 3 (289-levels) (a)
Waveform (b) Harmonics spectrums
VI. EXPERIMENTAL RESULTS
The experimental tests are implemented to validate the results
of simulation and analysis in order to achieve 50 Hz sinusoidal
waveform. IGBT12N60A4, Diode RHRP15120 are used in the
laboratory prototype.
Microcontroller ATMEGA16 generates pulses for different
switches Based on Table 1 and Table 4 and the configuration of
Fig.14. The Microcontroller provides on/off pulses for all
switches. These pulses are needed to be amplified in order to
drive switches. Isolation from control and power sections of the
circuit is also required. These duties are done by an
optocoupler-driver (HCPL3120). Output pulses of HCPL driver
are applied between gate and emitter legs of switches. Fig.15
shows Experimental setup picture in the laboratory.
HCPL3120
V in1 Vout1

Vout1
ATM16 BUFFER
Vout2
(b)
V in2 Vout2
Fig.11 The output voltage of ST-Type Module in case 1 (17-levels) (a) IGBT/DIODE
Waveform (b) Harmonics spectrums Fig.14 Schematic of configuration in laboratory

(a)

Fig.15 Experimental setup picture in laboratory

0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2675381, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS
The testes are just considered for case 1 and case 2 due to the
limitations in laboratory facilities for case 3.The experimental
test on setup system is designed and ST-Type module is tested
with VDC=24 (V) to verify the accurate of topology under more
realistic value since one PV module voltage is 12 (V) or 24 (V).
DC suppliers are tuned on 24 (V) for 1VDC and 72 (V) for 3VDC.
96 VAC peak (8*VDC) and 192 Vac peak (16*VDC) are achieved
for single module and two module (mode.I), respectively. The
prototype is studied and tested under different resistive -
inductive load to show the performance of the proposed
module. 17 levels and 33 levels MLI supplies the load with
R=70Ω and L=150mH in parallel. Fig.16 demonstrates voltage
and current 50 Hz sinusoidal waveforms of the proposed
module for 17 levels under resistive load with PF=1 (Fig.16.a)
and under resistive - inductive loads with PF=0.8 (Fig.16.b).
THD is 3.06% for 17 levels in experimental test. Also Fig.17
shows the results for 33 levels which THD is 1.76%. THDi
(current THD) are calculated and the amount of these are
2.76%, 2.04%, 1.05% and 0.37% for Fig.16.a, Fig.16.b,
Fig.17.a and Fig.17.b, respectively.
(a)
(b)
Fig.16 Experimental results for 17 levels (case 1) on R-L loads (a) PF=1 (b)
PF=0.8
(a)
0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
8
(b)
Fig.17 Experimental results for 33 levels (case 2) on R-L loads (a) PF=1 (b)
PF=0.8
There are a column in the figures of experimental test
(Figs.16 and .17). Vavg is remarked amounts of DC order
which in milliVolts/milliAmpers scale. The experimental
results also confirm the balancing of module.
VII. CONCLUSION
This paper presented a new multilevel inverter topology
named Square T-Type (ST-Type) module which can generate
17 levels with reduced components. It can be used in high
voltage/power applications with unequal DC sources. As ST-
Type module can be easily modularized, it can be used in
cascade arrangements to form high voltage outputs with low
stress on semiconductors and lowering the number of devices.
Modular connection of these modules leads to achieve more
voltage levels with different possible paths. It causes an
improvement in the reliability of the modular inverter which
enables it to use redundant paths in case of malfunction for a
switch or a driver. The main advantage of proposed module is
its ability to generate both positive and negative output voltage
without any H-bridge circuit at the output of the inverter.
THDv% for one module is obtained 2.77% and 3.06% in
simulation and experimental results, respectively that satisfy
harmonics standard (IEEE519). THDv% for cascade
connection (two module) is calculated 1.39% in simulation and
1.76% in experimental results. Also module is tested under
different resistive – inductive loads which results shows good
performance.
REFERENCES
[1] Essakiappan, S.; Krishnamoorthy, H.S.; Enjeti, P.; Balog, R.S.; Ahmed,
S., "Multilevel Medium-Frequency Link Inverter for Utility Scale
Photovoltaic Integration," in Power Electronics, IEEE Transactions on ,
vol.30, no.7, pp.3674-3684, July 2015
[2] Xibo Yuan, "A Set of Multilevel Modular Medium-Voltage High Power
Converters for 10-MW Wind Turbines," in Sustainable Energy, IEEE
Transactions on , vol.5, no.2, pp.524-534, April 2014
[3] Ahmadi, D.; Jin Wang, "Online Selective Harmonic Compensation and
Power Generation With Distributed Energy Resources," in Power
Electronics, IEEE Transactions on , vol.29, no.7, pp.3738-3747, July
2014
[4] Mathew, J.; Rajeevan, P.P.; Mathew, K.; Azeez, N.A.; Gopakumar, K.,
"A Multilevel Inverter Scheme With Dodecagonal Voltage Space Vectors
Based on Flying Capacitor Topology for Induction Motor Drives," in
Power Electronics, IEEE Transactions on , vol.28, no.1, pp.516-525, Jan.
2013
[5] Zedong Zheng; Kui Wang; Lie Xu; Yongdong Li, "A Hybrid Cascaded
Multilevel Converter for Battery Energy Management Applied in Electric
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2675381, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS
Vehicles," in Power Electronics, IEEE Transactions on , vol.29, no.7,
pp.3537-3546, July 2014
[6] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped
PWM inverter,” IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518–523,
Sep./Oct. 1981.
[7] T. A. Meynard and H. Foch, “Multi-level choppers for high voltage appli-
cations, in Proc. Eur. Conf. Power Electron. Appl” 1992, vol.2, pp.45–50.
[8] F.Z.Peng,J.-S.Lai, J.W.McKeever, and J.Van Coevering,“Amultilevel
voltage source inverter with separate DC sources for static var
generation,” IEEE Trans. Ind. Appl., vol. 32, no. 5, pp. 1130–1138,
Sep./Oct. 1996.
[9] Zare, Firuz Power electronics education electronic-book. School of
Engineering Systems, Queensland University of Technology, [Brisbane,
Qld.], 2008.
[10] Gupta, K.K.; Ranjan, A.; Bhatnagar, P.; Sahu, L.K.; Jain, S., "Multilevel
Inverter Topologies With Reduced Device Count: A Review," in Power
Electronics, IEEE Transactions on , vol.31, no.1, pp.135-151, Jan. 2016
[11] E. Babaei and S. H. Hosseini, “New cascaded multilevel inverter topology
with minimum number of switches,” Elsevier J. Energy Convers. Manage,
vol. 50, no. 11, pp. 2761–2767, Nov. 2009.
[12] Babaei, E. Kangarlu, M.F. ; Sabahi, M. “Extended multilevel converters:
an attempt to reduce the number of independent DC voltage sources in
cascaded multilevel converters“ IET Power Electronics, Volume 7, Issue
1, January 2014, p. 157 – 166
[13] K.K. Gupta and S. Jain, “Topology for multilevel inverters to attain
maximum number of levels from given DC sources” IET Power
Electronics, Volume 5, Issue 4, April 2012, p. 435 – 446
[14] Farhadi Kangarlu, M.; Babaei, E., “Cross-switched multilevel inverter: an
innovative topology,”IET Power Electron., 2013. Vol. 6, no. 4, pp. 642–
651.
[15] E. Babaei, S. Laali, and S. Alilu, “Cascaded multilevel inverter with series
connection of novel H-bridge basic units,” IEEE Trans. Ind. Electron.,
vol. 61, no. 12, pp. 6664-6671, Dec. 2014.
[16] E. Babaei, S. Alilu, and S. Laali, “A new general topology for cascaded
multilevel inverters with reduced number of components based on
developed H-bridge,” IEEE Trans. Ind. Electron., vol. 61, no. 8, pp. 3932-
3939, Aug. 2014.
[17] Y. Ounejjar, K. Al-Haddad, L.-A. Grégoire, “Packed U Cells Multilevel
Converter Topology: Theoretical Study and Experimental
Validation“IEEE TRANSACTIONS ON INDUSTRIAL
ELECTRONICS, VOL. 58, NO.4, April 2011, P.1294 – 1306
[18] Rasoul Shalchi Alishah ; Daryoosh Nazarpour ; Seyyed Hossein
Hosseini ; Mehran Sabahi. “New hybrid structure for multilevel inverter
with fewer number of components for high-voltage levels” IET Power
Electronics, Volume 7, Issue 1, January 2014, p. 96 – 104
[19] M Farhadi Kangarlu, E Babaei, “A Generalized Cascaded Multilevel
Inverter Using Series Connection of Submultilevel Inverters” Power
Electronics, IEEE Transactions on 28 (2), Feb. 2013, 625-636
[20] R. Zeng, L. Xu, L. Yao and S. J. Finney, "Analysis and Control of
Modular Multilevel Converters under Asymmetric Arm Impedance
Conditions," in IEEE Transactions on Industrial Electronics, vol. 63, no.
1, pp. 71-81, Jan. 2016.
[21] P. Sochor and H. Akagi, "Theoretical Comparison in Energy-Balancing
Capability Between Star- and Delta-Configured Modular Multilevel
Cascade Inverters for Utility-Scale Photovoltaic Systems," in IEEE
Transactions on Power Electronics, vol. 31, no. 3, pp. 1980-1992, March
2016.
[22] X. She, A. Q. Huang and X. Ni, "Current Sensorless Power Balance
Strategy for DC/DC Converters in a Cascaded Multilevel Converter
Based Solid State Transformer," in IEEE Transactions on Power
Electronics, vol. 29, no. 1, pp. 17-22, Jan. 2014.
[23] J. Shi, W. Gou, H. Yuan, T. Zhao and A. Q. Huang, "Research on voltage
and power balance control for cascaded modular solid-state transformer,"
in IEEE Transactions on Power Electronics, vol. 26, no. 4, pp. 1154-1166,
April 2011.
[24] S. K. Chattopadhyay and C. Chakraborty, "A New Multilevel Inverter
Topology With Self-Balancing Level Doubling Network," in IEEE
Transactions on Industrial Electronics, vol. 61, no. 9, pp. 4622-4631, Sept.
2014.
[25] E. Samadaei, S. A. Gholamian, A. Sheikholeslami and J. Adabi, "An
Envelope Type (E-Type) Module: Asymmetric Multilevel Inverters With
Reduced Components," in IEEE Transactions on Industrial Electronics,
vol. 63, no. 11, pp. 7148-7156, Nov. 2016.
[26] H. Vahedi, P. A. Labbé and K. Al-Haddad, "Sensor-Less Five-Level
Packed U-Cell (PUC5) Inverter Operating in Stand-Alone and Grid-
0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
9
Connected Modes," in IEEE Transactions on Industrial Informatics, vol.
12, no. 1, pp. 361-370, Feb. 2016.
[27] Thiago B. Soeiro and Johann W. Kolar, “Novel 3-level Hybrid Neutral-
Point-Clamped Converter “, in Proc. IECON 2011 - 37th Annual
Conference on IEEE Industrial Electronics Society, Melbourne, 2011.
[28] Y. S. Lai and F. S. Shyu, "Topology for hybrid multilevel inverter," in
IEE Proceedings - Electric Power Applications, vol. 149, no. 6, pp. 449-
458, Nov 2002.
[29] Meshram, P. M., & Borghate, V. B.: 'A simplified nearest level control
(NLC) voltage balancing method for modular multilevel converter
(MMC)', Power Electronics, IEEE Transactions on, 2015, 30(1), 450-462
Emad Samadaei was born in Q'aemshahr, Iran. He
received his B.Sc. degree in electrical engineering
from the College of Engineering, Mazandaran
University, Babol, Iran in 2008. He received the M.Sc.
degree in electrical engineering from the faculty of
Electrical and Computer Engineering, Babol
University of technology, Babol, Iran in 2010. He is
currently a Ph.D. Student at Power Electronics,
Renewable Energy in power electronics laboratory at
the Electrical and Computer Engineering Department,
Babol University of technology.
Abdolreza Sheikholeslami was born in Iran. He
received the B.Sc. (Hons.) degree in electrical
engineering from Mazandaran University, Iran, and the
M.Sc. and Ph.D. degrees from the University of
Strathclyde, Glasgow, U.K., in 1978 and 1989,
respectively. He has been an Associate Professor with
the Department of Electrical and Computer
Engineering, Noshirvani University, Babol, Iran, since
2009. His current research interests include power
electronic, power quality, harmonics, smart grids, and
renewable energy.
Sayyed Asghar Gholamian was born in Babolsar,
Iran, in 1976. He received a B.Sc. degree in electrical
engineering from K.N.Toosi University of
Technology, Tehran, Iran in 1999 and a M.Sc. degree
in electric power engineering (electrical machines)
from university of Mazandaran, Babol, Iran in 2001.
He also received the Ph.D degree in electrical
engineering from K.N.Toosi University of
Technology, Tehran, Iran in 2008. He is currently an
assistant professor in the department of Electrical
Engineering at the Babol University of Technology, Iran. His research interests
include power electronic and design, simulation, modeling and control of
electrical machines.
Jafar Adabi was born in 1981. He received his BEng
and MEng degrees in electrical engineering from
Mazandaran University, Babol, Iran, in 2004 and 2006,
respectively. He finished his PhD degree in the School
of Engineering Systems at the Queensland University of
Technology, Brisbane, Queensland, Australia at 2010.
Currently, he is an assistant professor at Noshirvani
University of Technology, Babol, Iran. His research
interests are the optimal design and high frequency
modelling of power electronics and motor drive systems
for EMI analysis.