Tessent TestKompress & Adv.

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Student Workbook

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 Table of Contents
Module 1: TestKompress Basics .......................................................................... 13
Objectives ........................................................................................................................................... 14

Course Prerequisites ........................................................................................................................... 15

What Is Tessent TestKompress? ........................................................................................................ 16

What Is EDT? ..................................................................................................................................... 17

Why Tessent TestKompress? ............................................................................................................. 18

How Does Tessent TestKompress Impact the Design? ..................................................................... 19

Compression Logic Terminology....................................................................................................... 20

Standard Test Application Process ..................................................................................................... 21

Tessent TestKompress Test Application ............................................................................................ 22

Uncompressed ATPG versus EDT ..................................................................................................... 23

Uncompressed ATPG versus EDT (Cont.) ........................................................................................ 24

Uncompressed ATPG versus EDT (Cont.) ........................................................................................ 25

ATPG — Test Pattern Generation Process ........................................................................................ 26

TestKompress Pattern Generation Process ........................................................................................ 27

Calculating Data Compression ........................................................................................................... 28

Create Patterns .................................................................................................................................... 29

Report Statistics.................................................................................................................................. 30

Tessent TestKompress Logic Placement ............................................................................................ 31

External Logic Placement .................................................................................................................. 32

Internal Logic Placement ................................................................................................................... 33

Tessent TestKompress Output Files ................................................................................................... 34

Tessent TestKompress Output Files (Cont.) ...................................................................................... 35

Sharing Tessent TestKompress Pins .................................................................................................. 36

Tessent TestKompress Control Signals.............................................................................................. 37

Tessent TestKompress & Adv. Topics I

 Table of Contents
Basic Tessent TestKompress Logic Architecture (Cont.) .................................................................. 38

The Decompressor.............................................................................................................................. 39

Decompressor — Representative Block Diagram.............................................................................. 40

Tessent TestKompress Control Fill Rate ........................................................................................... 41

Test Pattern Decompression ............................................................................................................... 42

The Compactor ................................................................................................................................... 43

The Compactor (Cont.) ...................................................................................................................... 44

The Compactor (Cont.) ...................................................................................................................... 45

Scan Chain Masking........................................................................................................................... 46

Scan Chain Masking — Solution ....................................................................................................... 47

Fault Aliasing ..................................................................................................................................... 48

Fault Aliasing — Solution.................................................................................................................. 49

Additional Shift Cycles ...................................................................................................................... 50

Additional Shift Cycles (Cont.) .......................................................................................................... 51

Bypass Logic ...................................................................................................................................... 52

Bypass Logic (Cont.).......................................................................................................................... 53

Lockup Cells ...................................................................................................................................... 54

Example: Location of Lockup Cells ................................................................................................... 55

Pipeline Stages in the Compactor....................................................................................................... 56

Pipeline Stages in the Compactor (Cont.) .......................................................................................... 57

Pipeline Stages in Channel I/O ........................................................................................................... 58

Pipeline Stages in Channel I/O (Cont.) .............................................................................................. 59

Pipeline Stages in Channel I/O (Cont.) .............................................................................................. 60

Getting Help With Tessent Tools ....................................................................................................... 61

Getting Help With Tessent Tools (Cont.) .......................................................................................... 62

Tessent TestKompress & Adv. Topics II

 Table of Contents
Getting Help With Tessent Tools (Cont.) .......................................................................................... 63

Accessing UNIX Commands From the Tool Command Line ........................................................... 64

Getting Help: Useful Tool and System Commands ........................................................................... 65

Customer Support ............................................................................................................................... 66

Summary ............................................................................................................................................ 67

Lab 1: Exploring the Help System ..................................................................................................... 68

Module 2: TestKompress Insertion Flows .......................................................... 69

Objectives ........................................................................................................................................... 70

Tessent TestKompress Operation ....................................................................................................... 71

Additional Tessent TestKompress Commands .................................................................................. 72

Additional Tessent TestKompress Commands (Cont.) ...................................................................... 73

Additional Tessent TestKompress Commands (Cont.) ...................................................................... 74

Logic Creation Flows — External and Internal ................................................................................. 75

Logic Creation Flows — Post-Synthesis Flows ................................................................................. 76

Logic Creation Flows — Pre-Synthesis Flow .................................................................................... 77

Logic Creation Flows — Pre-Synthesis Flow (Cont.) ....................................................................... 78

Post-Synthesis External Logic Creation ............................................................................................. 79

Post-Synthesis External Logic Creation (Cont.) ................................................................................ 80

Post-Synthesis External Logic Creation Flow ................................................................................... 81

Insert Scan .......................................................................................................................................... 82

Scan Chain Insertion Dofile ............................................................................................................... 83

Create EDT Logic .............................................................................................................................. 84

Create EDT Logic (Cont.) .................................................................................................................. 85

Synthesize........................................................................................................................................... 86

Synthesize (Cont.) .............................................................................................................................. 87

Tessent TestKompress & Adv. Topics III

 Table of Contents
Test Pattern Generation ...................................................................................................................... 88

Test Pattern Generation (Cont.) ......................................................................................................... 89

Generate Patterns in Bypass Mode (Optional) ................................................................................... 90

Generate Patterns in Bypass Mode (Optional) (Cont.) ...................................................................... 91

Lab 2: Exercise 1 — Post-Synth. External Logic Creation............................................................... 92

Post-Synthesis Internal Logic Creation Flow ..................................................................................... 93

Post-Synthesis Internal Logic Creation Flow (Cont.) ........................................................................ 94

Post-Synthesis Internal Logic Insertion ............................................................................................. 95

TestKompress-Based EDT Logic Insertion ....................................................................................... 96

TestKompress-Based EDT Logic Insertion (Cont.) ........................................................................... 97

Synopsys DC-Based EDT Logic Insertion ......................................................................................... 98

Synopsys DC-Based EDT Logic Insertion (Cont.) ............................................................................ 99

Scan Chain Insertion ........................................................................................................................ 100

Scan Chain Insertion (Cont.) ............................................................................................................ 101

Tessent TestKompress Logic Creation Insertion ............................................................................. 102

Tessent TestKompress Logic Creation and Insertion (Cont.) .......................................................... 103

Synthesize Tessent TestKompress Logic ......................................................................................... 104

DC Synthesis Script: created_dc_script.scr ..................................................................................... 105

DC Synthesis Script: created_dc_script.scr (Cont.) ......................................................................... 106

Synthesis Script: created_dc_script.scr (Cont.)................................................................................ 107

Create Test Patterns .......................................................................................................................... 108

Create Test Patterns (Cont.) ............................................................................................................. 109

Lab 2: Exercise 2 — Post-Synth. Internal Logic Creation ............................................................... 110

Pre-Synthesis External Logic Creation ............................................................................................ 111

Pre-Synthesis External Logic Creation Flow ................................................................................... 112

Tessent TestKompress & Adv. Topics IV

 Table of Contents
create_skeleton_design Input File .................................................................................................... 113

Create a Design Interface File (External Flow Only)....................................................................... 114

create_skeleton_design Inputs and Outputs ..................................................................................... 115

Run the create_skeleton_design Utility............................................................................................ 116

Create Tessent TestKompress Logic ................................................................................................ 117

Create Tessent TestKompress Logic (Cont.) ................................................................................... 118

Design, Integrate, and Synthesize Design ........................................................................................ 119

Tessent TestKompress Pattern Generation ...................................................................................... 120

Tessent TestKompress Pattern Generation (Cont.) .......................................................................... 121

Created_edt.dofile ............................................................................................................................ 122

Created_bypass.dofile ...................................................................................................................... 123

Flattened Net Names in Dofiles ....................................................................................................... 124

Created_edt.testproc File .................................................................................................................. 125

Created_bypass.testproc ................................................................................................................... 126

Compressed Test Pattern Generation ............................................................................................... 127

Uncompressed Test Pattern Generation (Bypass) ............................................................................ 128

Saving Test Patterns ......................................................................................................................... 129

Saving Test Patterns (Cont.)............................................................................................................. 130

Saving Test Patterns for Verilog Simulation .................................................................................... 131

Pattern Reordering............................................................................................................................ 132

Why no Reordering After Saving Patterns ....................................................................................... 133

Why no Reordering After Saving Patterns (Cont.) .......................................................................... 134

Why no Reordering After Saving Patterns (Cont.) .......................................................................... 135

Summary .......................................................................................................................................... 136

Lab 2: Exercise 3 — Pre-Synth. Internal Logic Creation ................................................................ 137

Tessent TestKompress & Adv. Topics V

 Table of Contents
Lab 2: Exercise 4: Logic Options (Optional) .................................................................................. 138

Module 3: DRC and Simulation Mismatch Debug .......................................... 139

Objectives ......................................................................................................................................... 140

Tessent TestKompress K Design Rule Checks ................................................................................ 141

K19 Design Rule Check ................................................................................................................... 142

K19 Design Rule Check (Cont.) ...................................................................................................... 143

Using Gate Reporting ....................................................................................................................... 144

Using Gate Reporting (Cont.) .......................................................................................................... 145

Using Gate Reporting (Cont.) .......................................................................................................... 146

Using Gate Reporting (Cont.) .......................................................................................................... 147

Using Gate Reporting (Cont.) .......................................................................................................... 148

Inverted Signals (Cont.) ................................................................................................................... 149

K20 Design Rule Check ................................................................................................................... 150

K20 Design Rule Check (Cont.) ...................................................................................................... 151

K21 Design Rule Check ................................................................................................................... 152

K22 Design Rule Check ................................................................................................................... 153

K22 Design Rule Check (Cont.) ...................................................................................................... 154

Possible DRC Error Causes.............................................................................................................. 155

Possible DRC Error Causes (Cont.) ................................................................................................. 156

Summary: Troubleshooting K19 and K22 Violations...................................................................... 157

EDT Finder ....................................................................................................................................... 158

EDT Finder Usage ............................................................................................................................ 159

Common EDT Finder Design Rule Checks ..................................................................................... 160

EDT Finder F Rules in DFTVisualizer ............................................................................................ 161

EDT Logic Visualization ................................................................................................................. 162

Tessent TestKompress & Adv. Topics VI

 Table of Contents
F DRC Rule Debugging ................................................................................................................... 163

Report EDT Finder ........................................................................................................................... 164

Report EDT Finder (Cont.) .............................................................................................................. 165

Design Rule Checking: More Information ....................................................................................... 166

Lab 3 Exercise 1: Tessent TestKompress (DRC) ............................................................................. 167

Pattern Simulation and Mismatch Debug......................................................................................... 168

Analyze Simulation Mismatches ...................................................................................................... 169

Automatic Simulation Mismatch Analysis Flow ............................................................................. 170

Simulation Mismatch Debugging..................................................................................................... 171

Saving Pattern Files for Simulation Mismatch Debugging .............................................................. 172

Summary .......................................................................................................................................... 173

Lab 3 Exercise 2: Auto. Pattern Sim. Mismatch Analysis ............................................................... 174

Module 4: Maximizing Performance ................................................................. 175

Objectives ......................................................................................................................................... 176

Maximizing Performance ................................................................................................................. 177

Evaluating Performance ................................................................................................................... 178

Evaluating Performance (Cont.) ....................................................................................................... 179

Improving Performance Through Analysis ...................................................................................... 180

Chain to Channel Ratio: Analyze Compression ............................................................................... 181

Analyze Compression ...................................................................................................................... 182

Analyze Compression: Examples..................................................................................................... 183

Modular EDT Analyze Compression: Example............................................................................... 184

Analyze Compression Procedure ..................................................................................................... 185

Analyzing Results ............................................................................................................................ 186

Analyzing Results (Cont.) ................................................................................................................ 187

Tessent TestKompress & Adv. Topics VII

 Table of Contents
Automating Compression Analysis .................................................................................................. 188

Compression Advisor ....................................................................................................................... 189

Compression Advisor (Cont.) .......................................................................................................... 190

Resolving Compression Issues ......................................................................................................... 191

EDT Test Points ............................................................................................................................... 192

Test Point Types ............................................................................................................................... 193

Insertion Flows ................................................................................................................................. 194

Command Overview ........................................................................................................................ 195

Command Overview (Cont.) ............................................................................................................ 196

Example Flow – Post Scan Insertion ................................................................................................ 197

Example Flow – Post Scan Insertion: TP Stitching ......................................................................... 198

Report Test Points ............................................................................................................................ 199

Test Point Advisor ............................................................................................................................ 200

Summary .......................................................................................................................................... 201

Lab 4: Compression and Performance ............................................................................................. 202

Module 5: Modular TestKompress .................................................................... 203

Objectives ......................................................................................................................................... 204

Top Level TestKompress Implementation Options ......................................................................... 205

Top Level Modular Tessent TestKompress Implementation ........................................................... 206

Benefits of Modular Tessent TestKompress .................................................................................... 207

Modular TestKompress Implementation .......................................................................................... 208

Core Mapping ................................................................................................................................... 209

Module Level Core Mapping Flow .................................................................................................. 210

Module Level Core Mapping Flow (Cont.) ..................................................................................... 211

Tessent Core Description (.tcd) File................................................................................................. 212

Tessent TestKompress & Adv. Topics VIII

 Table of Contents
Top Level Core Mapping Flow ........................................................................................................ 213

Core Mapping at the Top Level ....................................................................................................... 214

Top Level Pattern Generation .......................................................................................................... 215

Modular Tessent TestKompress Rules ............................................................................................. 216

Broadcasting to Identical Blocks ...................................................................................................... 217

Broadcasting to Identical Blocks Implementation ........................................................................... 218

Modular TestKompress With Channel Sharing ............................................................................... 219

Modular TestKompress with Channel Sharing (Cont.) .................................................................... 220

Block-Level EDT Setup ................................................................................................................... 221

Example: No Channel-Sharing......................................................................................................... 222

Example: Channel-Sharing Case 1 ................................................................................................... 223

Example: Channel-Sharing Case 2 ................................................................................................... 224

Channel Sharing Implementation ..................................................................................................... 225

Channel Sharing Implementation (Cont.) ........................................................................................ 226

Top-Level Netlist ............................................................................................................................. 227

Asymmetrical Channel Configuration ............................................................................................. 228

Summary .......................................................................................................................................... 229

Lab 7: Modular Tessent TestKompress Flow .................................................................................. 230

Module 6: Additional Topics .............................................................................. 231

Objectives ......................................................................................................................................... 232

Set_Edt_Options On -Force_1hot_Masking .................................................................................... 233

Chain Masking ................................................................................................................................. 234

Dual Tessent TestKompress Configurations .................................................................................... 235

Dual Configuration Tessent TestKompress Logic ........................................................................... 236

Hybrid TestKompress / LogicBIST ................................................................................................. 237

Tessent TestKompress & Adv. Topics IX

 Table of Contents
Multi-Threaded ATPG (Distributed Processing) ............................................................................. 238

User Defined Fault Model (UDFM) ................................................................................................. 239

ATPG Model - Review .................................................................................................................... 240

User Defined Fault Model: Test Alternatives .................................................................................. 241

User Defined Fault Model: Gate Exhaustive ................................................................................... 242

User Defined Fault Model: Gate Exhaustive (Cont.) ....................................................................... 243

User Defined Fault Model: Cell-Aware ........................................................................................... 244

Cell-Aware Model Creation: Layout Extraction .............................................................................. 245

Cell-Aware Model Creation: Layout Extraction (Cont.) ................................................................. 246

Cell-Aware Model Creation: Fault Simulation ................................................................................ 247

Cell-Aware Model Creation: Model Generation .............................................................................. 248

Cell-Aware Model Creation: Usage ................................................................................................. 249

More Information ............................................................................................................................. 250

Low Power / Power Aware ATPG ................................................................................................... 251

Control and Observe Test Cube ....................................................................................................... 252

Reducing Switching Activity: Shift (Non-EDT) ............................................................................. 253

Reducing Switching Activity: Shift (EDT) ..................................................................................... 254

Limiting Switching During Capture (EDT and Non-EDT) ............................................................. 255

Basic Usage Flow for Low Power ATPG (EDT) ............................................................................. 256

EDT Power Control Block Diagram ................................................................................................ 257

Load/Response Shift Switching Activity ......................................................................................... 258

Low Power ATPG Flow ................................................................................................................... 259

Example 1: Power Metrics Reporting .............................................................................................. 260

Example 2: Power Metrics Reporting .............................................................................................. 261

Example 3: Power Metrics Reporting .............................................................................................. 262

Tessent TestKompress & Adv. Topics X

 Table of Contents
Example 4: Pattern Filtering ............................................................................................................ 263

Low-Power / Power-Aware Test Flow ............................................................................................. 264

IEEE1801 (UPF 2.0) and CPF 1.1 ................................................................................................... 265

Usage Overview ............................................................................................................................... 266

Usage Overview (Cont.) ................................................................................................................... 267

Test Sequencing ............................................................................................................................... 268

Power State During Scan Test .......................................................................................................... 269

Testing Low Power Components ..................................................................................................... 270

More Information ............................................................................................................................. 271

Motivations for Low Pin Count Test................................................................................................ 272

Top Level Routing Congestion ........................................................................................................ 273

Low Channel TestKompress ............................................................................................................ 274

Impact of Scan Channel Reduction .................................................................................................. 275

Tessent TestKompress Standard Pin Test Access ............................................................................ 276

Overlapping Use of Scan Clock With EDT Clock ........................................................................... 277

Low Pin Count Test Access ............................................................................................................. 278

Low Pin Count Controller Type 1 .................................................................................................... 279

Internally Generated EDT Signals: Overview ................................................................................. 280

Low Pin Count Controller Type 2 .................................................................................................... 281

Low Pin Count Controller Type 3 .................................................................................................... 282

Tessent TestKompress Three Pin Controller: Overview .................................................................. 283

Three Pin Controller ......................................................................................................................... 284

Overview: Where to Get Help .......................................................................................................... 285

Accessing SupportNet Material ....................................................................................................... 286

Customer Support ............................................................................................................................. 287

Tessent TestKompress & Adv. Topics XI

 Table of Contents
Customer Support (Cont.) ................................................................................................................ 288

Related Courses ................................................................................................................................ 289

Summary .......................................................................................................................................... 290

No Lab .............................................................................................................................................. 291

Tessent TestKompress & Adv. Topics XII