Pipelining

Overview
Pipelining is widely used in modern processors.

Pipelining improves system performance in terms of throughput.[No of

work done at a given time]
Pipelined organization requires sophisticated compilation techniques.
Making the Execution of Programs Faster

Use faster circuit technology to build the processor and the main memory.

Arrange the hardware so that more than one operation can be performed at the
same time.
In the latter way, the number of operations performed per second is increased
even though the elapsed time needed to perform any one operation is not
changed.
Pipeline
It is technique of decomposing a sequential process into suboperation,
with each suboperation completed in dedicated segment.

Pipeline is commonly known as an assembly line operation.

It is similar like assembly line of car manufacturing.

First station in an assembly line set up a chasis, next station is

installing the engine, another group of workers fitting the body.
• A Pipelining is a series of stages, where some work is done at
each stage in parallel.
• The stages are connected one to the next to form a pipe -
instructions enter at one end, progress through the stages, and exit
at the other end.
 Pipelining Case: Laundry

• 4 loads of laundry that need to washed, dried,

and folded.
– 30 minutes to wash, 40 min. to dry, and 20 min. to fold.
– We have 1 washer, 1 dryer, and 1 folding station.

• What’s the most efficient way to get the 4 loads

of laundry done?
Non Pipelined Laundry

6 PM 7 8 9 10 11 Midnight

Time

30 40 20 30 40 20 30 40 20 30 40 20
Sequential laundry takes 6
A
hours for 4 loads
If they learned pipelining,
B how long wouldlaundry
take?
C

D
Pipelined Laundry

6 PM 7 8 9 10 11 Midnight

Time
T
a 30 40 40 40 40 20
s
k A
Pipelined laundry takes
3.5 hours for 4 loads
O B
r
d C
e
D
r
 Traditional Pipeline Concept
Pipelining doesn’t help
6 PM latency of single task, it
7 8 9
helps throughput of entire
Time
workload
T
a 30 40 40 40 40 20 Pipeline rate limited by
slowest pipeline stage
s
A Multiple tasks operating
k
simultaneously using
different resources
O B Potential speedup = Number
r pipe stages
d Unbalanced lengths of pipe
C
e stages reduces speedup
r Time to “fill” pipeline and
D
time to “drain” it reduces
speedup
Stall for Dependences
Idea of pipelining in computer
The processor execute the program by fetching and executing instructions.
One after the other.

Let Fi and Ei refer to the fetch and execute steps for instruction Ii
Use the Idea of Pipelining in a Computer
Fetch + Execution

I1 I2 I3 T ime
Time
Clock cycle 1 2 3 4
F1 E1 F2 E 2 F3 E3
Instruction

(a) Sequential execution I1 F1 E1

I2 F2 E2
Interstage buffer
B1
I3 F3 E3

Instruction
fetch Execution (c) Pipelined execution
unit unit

Figure 8.1. Basic idea of instruction pipelining.

(b) Hardware organization
Contd.,
Computer that has two separate hardware units, one for fetching and
another for executing them.
the instruction fetched by the fetch unit is deposited in an
intermediate buffer B1.

This buffer needed to enable the execution unit while fetch unit
fetching the next instruction.
The computer is controlled by a clock.
Any instruction fetch and execute steps completed in one clock cycle.
Definition:
Pipelining is an speed up technique where multiple
instructions are overlapped in execution on a
processor.
Pipelining: Processors

• Computers, like laundry, typically perform the exact

same
steps for every instruction:
– Fetch an instruction from memory
– Decode the instruction
– Execute the instruction
– Read memory to get input
– Write the result back to memory
 Instruction Pipeline
• Instruction execution process lends itself naturally to
pipelining
– overlap the subtasks of instruction fetch, decode and execute

• Instruction pipeline has six operations,

Fetch instruction (FI)
Decode instruction (DI)
Calculate operands (CO)
Fetch operands (FO)
Execute instructions (EI)
Write result (WR)

Overlap these operations

CS211 8
Instructions Fetch
• The IF stage is responsible for obtaining the requested instruction from
memory. The instruction and the program counter are stored in the register
as temporary storage.

CS211 9
 Decode Instruction

• The DI stage is responsible for decoding the instruction and sending out the
various control lines to the other parts of the processor.

CS211 10
Calculate Operands

• The CO stage is where any calculations are performed. The main

component in this stage is the ALU. The ALU is made up of arithmetic,
logic and capabilities.

CS211 11
Fetch Operands and Execute Instruction
• The FO and EI stages are responsible for storing and loading values to and
from memory. They also responsible for input and output from the processor
respectively.

CS211 12
Write Operands
• The WO stage is responsible for writing the result of a calculation, memory
access or input into the register file.

CS211 13
Six Stage
Instruction
Pipeline
Use the Idea of Pipelining in a Computer
Time
Clock cycle 1 2 3 4 5 6 7

Instruction

Fetch + Decode I1 F1 D1 E1 W1

+ Execution + Write I2 F2 D2 E2 W2

I3 F3 D3 E3 W3

I4 F4 D4 E4 W4

(a) Instruction execution divided into four steps

Interstage buffers

D : Decode
F : Fetch E: Execute W : Write
instruction instruction and fetch operation results
operands
B1 B2 B3

(b) Hardware organization

Figure 8.2. A 4-stage pipeline.

Timing Diagram for Instruction Pipeline
Operation
 6

Pipeline Performance: Clock & Timing

Si S
i+1

τ τm d

Clock cycle of the pipeline : τ

Latch delay : d
τ = max {τm } + d

Pipeline frequency : f

f=1/τ CS211 16
 7

Pipeline Performance: Speedup & Efficiency

k-stage pipeline processes n tasks in k + (n-1) clock cycles:

k cycles for the first task and n-1 cycles for the remaining n-1 tasks

Total time to process n tasks

Tk = [ k + (n-1)] τ

For the non-pipelined processor

T1 = n k τ
T1 nkτ nk
Speedup factor Sk = [ k + (n-1)] τ = k + (n-1)
= Tk
CS211 17
Advantages

• Pipelining makes efficient use of resources.

• Quicker time of execution of large number of instructions

• The parallelism is invisible to the programmer.

 Can Pipelining Get Us Into Trouble?
❑ Yes:Pipeline Hazards
● structural hazards: attempt to use the same resource by
two different instructions at the same time
● data hazards: attempt to use data before it is ready
- An instruction’s source operand(s) are produced by a prior
instruction still in the pipeline
● control hazards: attempt to make a decision about program
control flow before the condition has been evaluated and the
new PC target address calculated
- branch instructions

❑ Can always resolve hazards by waiting

● pipeline control must detect the hazard
● and take action to resolve hazards

CSE431 L06 Basic MIPS Pipelining.19 Irwin, PSU, 2005

Thank
You!!!