Birla Institute of Technology and Science Pilani, Pilani Campus (Raj.

)
Department of Electrical and Electronics Engineering
EEE/INSTR F313 Analog & Digital VLSI Design
First Semester 2020-21
Max. Marks: 40 marks Test-1 Date: 14/09/2020
2020

1. A 500nm thick Silicon wafer is subjected to thermal oxidation in a class-10 clean room. If the
desired thickness of the oxide layer is 90nm, then the thickness of the silicon layer after the
oxidation in nm would be ____________________
For every 100nm of silicon consumed 45nm of oxide layer is formed.
So to form 90nm of oxide layer, 200nm of silicon would be consumed.
So the thickness of the silicon layer after oxidation is 500nm-200nm = 300nm

2. The voltage transfer characteristics (VTC) of an inverter are shown. Identify the correct statement
regarding the VTC of the inverter. NML: Noise Margin Low , NMH: Noise Margin High
(A) NML = NMH
(B) NML > NMH
(C) NML < NMH
(D) Data Insufficient to arrive at a conclusion.

3. A semiconductor manufacturing company has decided to upgrade its current fabrication facility
which is at 350nm to a new technology node at 130nm. They are to choose between constant field
scaling (full scaling) and constant voltage scaling. Identify the correct statement
S1: If the performance metric is chosen as power density, then constant field scaling is to be chosen.
S2: If the performance metric is gate delay then constant voltage scaling is to be chosen.
(A) Both S1 and S2 are correct
(B) Only S1 is correct
(C) Only S2 is correct
(D) Both S1 and S2 are wrong.

4. The following statements are the observation after scaling a CMOS circuit.
Statement-A: doping densities get doubled.
Statement-B: power dissipation reduces by a factor of four.
Then Identify the nature of scaling and the scaling factor S(>1) correctly.
(A) It is constant voltage scaling with S=2.
(B) It is constant voltage scaling with S=1.4.
(C) It is constant field scaling with S=1.4.
(D) It is constant field scaling with S=2.
5. For the Stick Diagram shown in the figure Identify the Boolean expression for the output variable
Y in terms of the input variables A, B, C, D
(A) AC+DB
(B) AB+CD
(C) AD+BC
(D) None of These

6. In a n-well CMOS process of fabricating a CMOS inverter, arrange the following process steps in
the correct sequence.
P1: Source/Drain Contacts
P2: Passivation
P3: Metallization
P4: Gate deposition
(A) P1, P3, P4, P2
(B) P4, P1, P3, P2
(C) P4, P1, P2, P3
(D) P1, P4, P3, P2

7. If the sheet resistance of a poly-silicon layer is 150Ω/square. Find the number of squares (between
the points P and Q). What is The total resistance of the resistor shown in the figure below? The
minimum width of a poly layer is 2λ, and the minimum spacing between two poly layers is 2λ. For
reducing the area, the minimum width and spacing rules are used in the layout of this resistor.

8. A silicon foundry which fabricates memory chips operating with 3V power supply at 500nm. has
observed that there is a detrition of the circuit performance if the power supply is reduced below
1.8V. Therefore, when they upgraded the technology to 250nm they maintained the supply voltage
as 1.8V. In the circuits fabricated under the new technology node identify the correct statement.
(A) Drain current approximately becomes half.
(B) Power dissipation approximately becomes half.
(C) Doping densities approximately doubles.
(D) None of these statements is correct.

*** End of Quiz ***

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 Test-1
Analog and Digital VLSI Design
CMOS Fabrication Process
14- Birds beak problem in field oxide growth process arises due to
(a) Isotropic nature of oxidation
(b) Anisotropic nature of oxidation
(c) High rate of oxidation
(d) Slow rate of oxidation
Answer:- (a) Birds beak problem arises during the growth of field oxide is subjected to the
isotropic nature of oxidation process.
15- In a typical optical lithography process following processing steps are carried out; P1-
Photoresist coating, P2-Etching, P3-RCA cleaning, P4-Pre-baking, P5-Exposure to
UV light, P6-Masking. Which of the following options represent the correct sequence of
the optical lithography process?
(a) P1-P3-P6-P4-P5-P2 (b) P3-P1-P6-P4-P5-P2 (c) P3-P1-P4-P6-P5-P2 (d) P1-P3-P4-
P6-P5-P2
Answer:- (c) Correct sequence for a typical optical lithography process is; RCA cleaning-
>Photoresist coating->Pre baking->Masking->Exposure to UV radiation->Etching
16- Channel stop implant is being created in which processing step?
(a) P-well process (b) Device isolation process (c) N-well process (d) Twin-tub process
Answer:- (b) Usually channel stop implants are created during the device isolation process
only.

17- Which of the following step can be skipped if electron-beam lithography is employed to
transfer a pattern on silicon substrate in 22 nm technology?
(a) Wafer cleaning (b) Pre-baking (c) Etching (d) Masking
Answer:- (d) In electron-beam lithography, instead of UV light high energy electron beam is
used which could transfer the desired pattern on the wafer without masking.
18- If a lightly doped silicon substrate is provided to fabricate a CMOS inverter for 14 nm
technology node, you may carry out the following processing steps to accomplish your
target; P1-Active area definition, P2-P-well process, P3-N-well process, P4-Twin tub
process, P5-Poly deposition, P6-Gate oxide growth, P7-Wafer cleaning, P8-
 Source/Drain implantation, P9-Metallization. Choose the option appended below which
represents the correct sequence of your fabrication process.
(a) P7-P1-P4-P6-P5-P8-P9 (b) P7-P1-P2-P6-P5-P8-P9 (c) P1-P7-P4-P6-P5-P8-P9
(d) P7-P1-P3-P6-P5-P8-P9
Answer:- (a) In case of a lightly doped semiconductor substrate we have to follow twin tub
process to fabricate a CMOS device. The correct sequence would be Wafer cleaning->Active
area definition->Twin tub process->Gate oxide growth->Poly gate deposition-
>Source/drain implantation->Metallization.