CXP82316/82320/82324

CMOS 8-bit Single Chip Microcomputer

For the availability of this product, please contact the sales office.
Description
The CXP82316/82320/82324 microcomputer is 80 pin QFP (Plastic)
composed of a CPU, ROM and RAM, and I/O ports.
These chips feature many other high-performance
circuits in a single-chip CMOS design, including an
A/D converter, serial interface, timer/counter, time-
base timer, capture timer/counter, fluorescent display
controller/driver, remote control receiver.
This device also includes a power-on reset function
and sleep/stop functions which can be used to
achieve low power consumption.

Features
• Instruction set which supports a wide array of data types
— 213 types of instructions which include 16-bit calculations, multiplication and division arithmetic, and
boolean bit operations.
• Minimum instruction cycle 400ns for 10MHz operation
• On-chip ROM 16K bytes (CXP82316)
20K bytes (CXP82320)
24K bytes (CXP82324)
• On-chip RAM 704 bytes (Including fluorescent display data area)
• Peripheral functions:
— A/D converter 8-bit, 8-channel, successive approximation system
(conversion rate 32µs/10MHz)
— Serial interface On-chip 8-bit, 8-stage FIFO (1 to 8 bytes auto transfer) 1 channel
8-bit clock synchronized 1 channel
— Timers 8-bit timer
8-bit timer/counter
19-bit time-base timer
16-bit capture timer/counter
— Fluorescent display controller/driver
Maximum of 336 segment display available
1 to 16 digits dynamic display
Dimmer function
High voltage tolerant output (40V)
On-chip pull-down resistor (Mask option)
— Remote control receiver circuit
On-chip noise elimination circuit
On-chip 6 stage FIFO 8-bit pulse measurement counter
• Interrupts 14 factors, 15 vectors multi-interruption possible
• Standby mode Sleep/stop
• Package 80-pin plastic QFP
• Piggyback/evaluator CXP82300 80-pin ceramic QFP

Structure
Silicon gate CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

–1–
E91722B78-PS
 Block Diagram

VSS

XTAL
VDD

EXTAL

INT1
RST

INT0
INT3
INT2
AN0 to AN7 8 A/D CONVERTER 8 PA0 to PA7
SPC700 CLOCK GEN./
PORT A

CPU CORE SYSTEM CONTROL

T0 to T7 8
T8/S28 FDP 7 PB0 to PB6
8 RAM
T15/S21 CONTROLLER/ PB7
PORT B

80 BYTES
S0 to S20 21 DRIVER

VFDP
8 PC0 to PC7
RMC
PORT C

REMOCON FIFO
ROM RAM
16K/20K/24K BYTES 704 BYTES
CS0 SERIAL 8 PD0 to PD7

INTERRUPT CONTROLLER
SI0
PORT D

–2–
INTERFACE FIFO
SO0
SCK0 UNIT 0
6 PE0 to PE5
SI1
SO1 SERIAL INTERFACE UNIT 1 2 PE6 to PE7
PORT E

SCK1
EC0 2
8 BIT TIMER/COUNTER 0 8 PF0 to PF7
PORT F

8 BIT TIMER 1
PRESCALER/
TIME BASE TIMER 4 PG0 to PG3
TO
PORT G

16 BIT CAPTURE 2
CINT
TIMER/COUNTER 2
EC1
CXP82316/82320/82324
 CXP82316/82320/82324

Pin Assignment (Top View)

PE1/EC1/INT1
PE0/EC0/INT0
PE2/IN2

VFDP
PG0
PG1
PG2
PG3

VDD
NC

T2
T1
T0

T5
T4
T3
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

PE3/INT3 1 64 T6
PE4/RMC 2 63 T7
PE5 3 62 T8/S28
PE6 4 61 T9/S27
PE7/TO 5 60 T10/S26
PB0/CINT 6 59 T11/S25
PB1/CS0 7 58 T12/S24
PB2/SCK0 8 57 T13/S23
PB3/SI0 9 56 T14/S22
PB4/SO0 10 55 T15/S21
PB5/SCK1 11 54 S20
PB6/SI1 12 53 S19
PB7/SO1 13 52 S18
PC0/KR0 14 51 S17
PC1/KR1 15 50 S16
PC2/KR2 16 49 PF7/S15
PC3/KR3 17 48 PF6/S14
PC4/KR4 18 47 PF5/S13
PC5/KR5 19 46 PF4/S12
PC6/KR6 20 45 PF3/S11
PC7/KR7 21 44 PF2/S10
PA0/AN0 22 43 PF1/S9
PA1/AN1 23 42 PF0/S8
PA2/AN2 24 41 PD7/S7

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PD4/S4
XTAL
PA4/AN4

PD3/S3
EXTAL
PA3/AN3

PD2/S2
RST

PD1/S1
PA7/AN7

PD6/S6
PD0/S0
PA6/AN6

PD5/S5
VSS
PA5/AN5

Note) NC (Pin 73) is always connected to VDD.

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 CXP82316/82320/82324

Pin Description

Symbol I/O Description

(Port A)
PA0/AN0
8-bit port; single bit Analog inputs to A/D converter.
to I/O/Analog input
addressable. (8 pins)
PA7/AN7
(8 pins)
PB0/CINT I/O/Input External capture input to 16-bit timer/counter.
PB1/CS0 I/O/Input Chip select input for serial interface (CH0).
PB2/SCK0 I/O/I/O (Port B) Serial clock (CH0) input/output.
Single bit addressable from
PB3/SI0 I/O/Input amongst lower 7 bits; Serial data (CH0) input.
PB4/SO0 I/O/Output highest bit (PB7) Serial data (CH0) output.
dedicated to output.
PB5/SCK1 I/O/I/O (8 pins) Serial clock (CH1) input/output.
PB6/SI1 I/O/Input Serial data (CH1) input.
PB7/SO1 Output/Output Serial data (CH1) output.
(Port C)
PC0/KR0 8-bit port; single bit
Key return input for FDP segment signal.
to I/O/Input addressable. Can provide
which performs key scanning.
PC7/KR7 12mA sink current.
(8 pins)
PE0/INT0/EC0 Input/Input/Input External event input
to timer/counter.
PE1/INT1/EC1 Input/Input/Input Input for external (2 pins)
interrupt requests.
PE2/INT2 Input/Input
(Port E) (4 pins)
PE3/INT3 Input/Input 8-bit port with lower 6 bits
dedicated to input and
PE4/RMC Input/Input Input for remote control receiver circuit.
upper 2 bits dedicated to
PE5 Input output.
(8 pins)
PE6 Output
Output pin for 16-bit timer/counter
PE7/TO Output/Output
rectangular waveform.
(Port G)
PG0 to PG3 I/O 4-bit input/output port; single bit addressable.
(4 pins)
PF0/S8 (Port F)
Segment signal
to Output/Output 8-bit dedicated output port.
output for FDP.
PF7/S15 (8 pins)
S16 to S20 Output Segment signal output for FDP.
T8/S28
to Output/Output Dual purpose output for FDP timing and segment signals.
T15/S21
T0 to T7 Output Timing signal output for FDP.
PD0/S0 (Port D)
to Output/Output 8-bit dedicated output port. Segment signal output for FDP.
PD7/S7 (8 pins)

–4–
 CXP82316/82320/82324

Symbol I/O Description

Provides voltage for FDP when on-chip resistor is selected under mask
VFDP
option.
EXTAL Input Connection for system clock oscillation crystal. When using an external
clock, input normal signal to EXTAL and reverse phase signal to the
XTAL Output XTAL pin.
System reset, active "L". The RST pin is an input/output pin which
RST I/O outputs a "L" level from the on-chip power on reset circuit when the
power is turned on. (Mask option)
NC NC pin is always connected to VDD.
VDD Positive power supply pin.
VSS GND

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 CXP82316/82320/82324

Input/Output Circuit Formats for Pins

Pin Circuit format When reset

Port A
Port A data

Port A detection Input

PA0/AN0 IP
protection
to "0" when reset circuit
PA7/AN7 Data bus Hi-Z

RD (Port A)

Port A input select

"0" when reset Input multiplexer

A/D converter
8 pins

Port B
Port B data

PB0/CINT
PB1/CS0 Port B direction IP
PB3/SI0 "0" when reset
Hi-Z
PB6/SI1 Data bus Schmitt input

RD (Port B)
CINT
CS0
4 pins SI0
SI1

Port B
SCK OUT
Output enable
Port B output select
"0" when reset

Port B data IP
PB2/SCK0
PB5/SCK1 Port B direction Hi-Z
"0" when reset

Data bus Schmitt input

RD (Port B)

SCK in
2 pins

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 CXP82316/82320/82324

Pin Circuit format When reset

Port B
SO
Output enable
Port B output select
"0" when reset

Port B data
PB4/SO0 IP

Hi-Z
Port B direction
"0" when reset

Data bus

1 pin RD (Port B)

Port B
Internal reset signal
SO
Output enable
Port B output select
∗
PB7/SO1 "0" when reset

Port B data High level

"1" when reset
Data bus
∗Pull-up transistor

RD (Port B)
1 pin

Port C

Port C data

PC0/KR0
∗
to Port C direction IP
PC7/KR7 "0" when reset
Hi-Z
Data bus

RD (Port C)

Key input signal

8 pins ∗Capable of driving 12mA large current

Port E EC0/INT0
PE0/EC0/INT0 EC1/INT1
PE1/EC1/INT1 Schmitt input INT2
INT3
PE2/INT2
IP RMC
PE3/INT3 Hi-Z
PE4/RMC Data bus

5 pins RD (Port E)

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 CXP82316/82320/82324

Pin Circuit format When reset

Port E

PE5
IP Data bus Hi-Z

RD (Port E)
1 pin

Port E

PE6
Port E data High level
"1" when reset

1 pin

Port E
TO
Output enable (T2OE)

Port E output select

PE7/TO "0" when reset
High level
Port E data
"1" when reset
Data bus

1 pin RD (Port E)

Port G

Port G data

PG0
to
Port G direction IP Hi-Z
PG3 "0" when reset

Data bus

RD (Port G)
4 pins

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 CXP82316/82320/82324

Pin Circuit format When reset

Port D
Port F ∗High voltage tolerant transistor
PD0/S0
Segment output data
to Hi-Z or
Output selection control signal ∗
PD7/S7
("0" when reset) Low level
PF0/S8 Port D data or (when PD
Port F data OP Mask option
to resistor is
"0" when reset Pull-down
PF7/S15 connected)
Data bus resistor
VFDP
16 pins
RD (Port D or Port F)

∗High voltage tolerance transistor

S16 to S20 Segment output data

∗ Hi-Z or
T15/S21 Output selection control signal
("0" when reset)
Low level
to
T8/S28 (when PD
T0 to T7 OP Mask option resistor is
Pull-down connected)
resistor
VFDP

21 pins

∗Diagram shows
circuit construction
EXTAL for oscillation.
EXTAL IP IP
XTAL ∗During stop Oscillation
feedback resistor is
disconnected.
XTAL

2 pins

Pull-up resistor

RST
OP Mask option
Low level
IP Schmitt input

From power on reset circuit

1 pin (Mask option)

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 CXP82316/82320/82324

Absolute Maximum Ratings (Vss = 0V)

Item Symbol Rating Unit Remarks

Supply voltage VDD –0.3 to +7.0 V
Input voltage VIN –0.3 to +7.0∗1 V
Output voltage VOUT –0.3 to +7.0∗1 V
VDD – 40 to As P channel transistor is open drain,
Display output voltage VOD V
VDD + 0.3 VDD voltage is determined as standerd.
IOH –5 mA Other than display output pins∗2 : per pin
IODH1 –15 mA Display outputs S0 to S20: per pin
High level output current
Display outputs T0 to T7,
IODH2 –35 mA
T8/S28 to T15/S21: per pin
∑IOH –40 mA Total of other than display output pins
High level total output current
∑IODH –100 mA Total of display output pins
IOL 15 mA Port 1 pin
Low level output current
IOLC 20 mA Large current port pin ∗3
Low level total output current ∑IOL 100 mA Entire pin total
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +150 °C
Allowable power dissipation PD 600 mW
∗1 VIN and VOUT cannot exceed VDD + 0.3V.
∗2 Rating for output current of general input/output port.
∗3 The large current drive transistor is an N-channel transistor of Port C.
Note) If the absolute maximum ratings are exceeded, the LSI could reach permanent breakdown. Also,
observing recommended operating conditions is desirable; otherwise, the LSI's reliability could be
affected.

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 CXP82316/82320/82324

Recommended Operating Conditions (Vss = 0V)

Item Symbol Min. Max. Unit Remarks

High-speed mode (1/2, 1/4 clock) guaranteed
4.5 5.5
range during operation
Supply voltage VDD V Low-speed mode (1/16 clock) guaranteed range
3.5 5.5
during operation
2.5 5.5 Guaranteed data hold operation range during stop
VIH 0.7VDD VDD V ∗1

Hysteresis input∗2
High level input
VIHS 0.8VDD VDD V
voltage
VIHEX VDD – 0.4 VDD + 0.3 V EXTAL pin∗3
VIL 0 0.3VDD V ∗1
Low level input
VILS 0 0.2VDD V Hysteresis input
voltage
VILEX –0.3 0.4 V EXTAL pin∗3
Operating temperature Topr –20 +75 °C
∗1 All regular input ports (PA, PB3, PB4, PB6, PC, PE5, PG).
∗2 For pins RST, CINT, CS0, SCK0, SCK1, EC0/INT0, EC1/INT1 , INT2, INT3, RMC.
∗3 Rating only for external clock input.

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 CXP82316/82320/82324

Electrical Characteristics
DC Characteristics (Ta = –20 to +75°C, Vss = 0V)

Item Symbol Pins Conditions Min. Typ. Max. Unit

High level VDD = 4.5V, IOH = –0.5mA 4.0 V

output voltage VOH
PA, PB, PC, PE6, VDD = 4.5V, IOH = –1.2mA 3.5 V
PE7, PG, RST∗1
(for VOL only) VDD = 4.5V, IOL = 1.8mA 0.4 V
Low level 0.6
VOL VDD = 4.5V, IOL = 3.6mA V
output voltage
PC VDD = 4.5V, IOL = 12.0mA 1.5 V
IIHE VDD = 5.5V, VIH = 5.5V 0.5 40 µA
EXTAL
Input current IILE VDD = 5.5V, VIL = 0.4V –0.5 –40 µA
IILR RST∗2 VDD = 5.5V, VIL = 0.4V –1.5 –400 µA
S0 to S20 –8 mA
Display output VDD = 4.5V
IOH S21/T15 to S28/T8
current VOH = VDD – 2.5V –20 mA
T0 to T7
Open drain output S0 to S20 VDD = 5.5V
leakage current ILOL S21/T15 to S28/T8 VOL = VDD – 35V –20 µA
(P-CH Tr off state) T0 to T7 VFDP = VDD – 35V
S0 to S20
Pull-down VDD = 5V
RL 100 270 kΩ
resistor∗3
S21/T15 to S28/T8 60
VOD – VFDP = 30V
T0 to T7
Input/output leak PA to PC, PE, PG, VDD = 5.5V
±10 µA
RST∗2
IIZ
current VI = 0, 5.5V
VDD = 5.5V
High-speed mode
(1/2 clock) operation
IDD1 25 40 mA
10MHz crystal
Supply current∗4 VDD oscillator
(C1 = C2 = 15pF)
IDDSL Sleep mode 3 8 mA
IDDST Stop mode 10 µA
For pins other
than S0 to S28,
1MHz clock
Input capacitance CIN T0 to T7, PB7, 10 20 pF
0V other than measured
PE6, PE7, VDD,
VSS, VFDP

∗1 RST pin is rated only when the power-on reset circuit is selected under the mask option.
∗2 RST pin is rated for input current when the pull-up resistor is selected; otherwise it is rated for leak current.
∗3 Applies when the on-chip pull-down resistor is selected under the mask option.
∗4 All output pins are left open.

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 CXP82316/82320/82324

AC Characteristics
(1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item Symbol Pins Conditions Min. Max. Unit
XTAL Fig. 1, Fig. 2
System clock frequency fC 1 10 MHz
EXTAL
tXL, Fig. 1, Fig. 2
45 ns
System clock input pulse width EXTAL External clock driver
tXH
System clock input rising and tCR, Fig. 1, Fig. 2
EXTAL External clock driver 200 ns
falling times tCF
Event count input clock pulse tEH, EC0,
Fig. 3 tsys +50* ns
width tEL EC1
Event count input clock rising tER, EC0,
Fig. 3 20 ms
and falling times tEF EC1
∗ tsys is determind by the upper two bits of the clock control resister (Address: 00FEH; CPU clock selected)
resulting in one of the 3 following values:
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Fig. 1. Clock timing

1/fc

VDD – 0.4V
EXTAL
0.4V

tXH tCF tXL tCR

Fig. 2. Clock applying condition

AAAA AAAA
Crystal oscillation

AAAA AAAA
Ceramic oscillation External clock

AAAA AAAA
EXTAL XTAL EXTAL XTAL

C1 C2 74HC04

Fig. 3. Event count clock timing

0.8VDD
EC0
EC1
0.2VDD

tEH tEF tEL tER

tTH tTF tTL tTR

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 CXP82316/82320/82324

(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item Symbol Pin Condition Min. Max. Unit

CS0 ↓ → SCK0 Chip select transfer mode
tDCSK SCK0 tsys + 200 ns
delay time (SCK0 = output mode)
CS0 ↑ → SCK0 Chip select transfer mode
tDCSKF SCK0 tsys + 200 ns
float delay time (SCK0 = output mode)
CS0 ↓ → SO0
tDCSO SO0 Chip select transfer mode tsys + 200 ns
delay time
CS0 ↑ → SO0
tDCSOF SO0 Chip select transfer mode tsys + 200 ns
float delay time
CS0 high level width tWHCS CS0 Chip select transfer mode tsys + 200 ns
Input mode 2tsys + 200 ns
SCK0 cycle time tKCY SCK0
Output mode 16000/fc ns

SCK0 tKH Input mode tsys + 100 ns

SCK0
high and low level width tKL Output mode 8000/fc – 50 ns

SI0 input setup time SCK0 input mode 100 ns

tSIK SI0
(against SCK0 ↑) SCK0 output mode 200 ns

SI0 input hold time SCK0 input mode tsys + 200 ns

tKSI SI0
(against SCK0 ↑) SCK0 output mode 100 ns

SCK0 ↓ → SO0 SCK0 input mode tsys + 200 ns

tKSO SO0
delay time SCK0 output mode 100 ns

Note 1) tsys is determind by the upper two bits of the clock control resister (Address: 00FEH; CPU clock
selected) resulting in one of the 3 following values:
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.

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 CXP82316/82320/82324

Fig. 4. Serial transfer CH0 timing

tWHCS

CS0
0.8VDD

0.2VDD

tKCY

tDCSK tDCSKF
tKL tKH

0.8VDD 0.8VDD

SCK0

0.2VDD

tSIK tKSI

0.8VDD

SI0 Input
data
0.2VDD

tDCSO tKSO tDCSOF

0.8VDD
SO0 Output data

0.2VDD

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 CXP82316/82320/82324

Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item Symbol Pin Condition Min. Max. Unit

Input mode 1000 ns
SCK1 cycle time tKCY SCK1
Output mode 16000/fc ns

tKH Input mode 400 ns

SCK1 high and low SCK1
level width tKL Output mode 8000/fc – 50 ns

SI1 input setup time SCK1 input mode 100 ns

tSIK SI1
(against SCK1 ↑) SCK1 output mode 200 ns

SI1 input hold time SCK1 input mode 200 ns

tKSI SI1
(against SCK1 ↑) SCK1 output mode 100 ns
SCK1 input mode 200 ns
SCK1 ↓ → SO1 delay time tKSO SO1
SCK1 output mode 100 ns

Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.

Fig. 5. Serial transfer CH1 timing

tKCY

tKL tKH

SCK1
0.8VDD

0.2VDD

tSIK tKSI

0.8VDD

SI1 Input data

0.2VDD

tKSO

0.8VDD

SO1 Output data

0.2VDD

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 CXP82316/82320/82324

(3) A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item Symbol Pin Condition Min. Typ. Max. Unit

Resolution 8 Bits
Linearity error A/D converter operation ±3 LSB
VZT∗1
only mV
Zero transition voltage –10 70 150
Ta = 25°C
VFT∗2
Full-scale transition VDD = 5.0V
4930 5050 5120 mV
voltage VSS = 0V
Conversion time tCONV 160/fADC ∗3 µs
Sampling time tSAMP 12/fADC ∗3 µs
Analog input voltage VIAN AN0 to AN7 0 VDD V

Fig. 6. Definition of A/D converter terms

FFH
FEH
∗1 VZT : Digital Value converted between 00H to 01H.
Digital conversion value

∗2 VFT : Digital Value converted between FEH to FFH.

∗3 fADC : ADC operation clock selection (MSC: Bit 0 of
address 01FFH) and assumes following values:
fADC = fc/2 when PS2 is selected.
Linearity error fADC = fc when PS1 is selected.

01H
00H
VZT VFT
Analog input

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 CXP82316/82320/82324

(4) Interrupts, reset inputs (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item Symbol Pin Condition Min. Max. Unit

INT0
External interrupt high and tIH INT1
1 µs
low level widths tIL INT2
INT3
Reset input low level width tRSL RST 8/fc µs

Fig. 7. Interrupt input timing

tIH tIL

0.8VDD

INT0 0.2VDD
INT1
tIL tIH
INT2
INT3 0.8VDD

0.2VDD

Fig. 8. RST input timing

tRSL

RST
0.2VDD

(5) Power-on reset

Power-on reset∗ (Ta = –20 to +75°C, VDD = 4.5 to 5.0V, VSS = 0V)

Item Symbol Pin Condition Min. Max. Unit

Power supply rising time tR Power-on reset 0.05 50 ms
VDD
Power supply cut-off time tOFF Repetitive power-on reset 1 ms
∗ Specifies only when power-on reset function is selected.

Fig. 9. Power-on reset

4.5V
VDD
0.2V 0.2V

tR tOFF
The power supply should be rise smoothly

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 CXP82316/82320/82324

Supplement

Fig. 10. Recommended Oscillation Circuit

AAAAA AAAAA
(i) (ii)

AAAAA AAAAA
AAAAA AAAAA
EXTAL XTAL EXTAL XTAL

C1 C2

C1 C2

Circuit
Manufacturer Model fc (MHz) C1 (pF) C2 (pF)
Example
CSA4.19MG 4.19
CSA8.00MG 8.00 (i)

MURATA MFG CSA10.0MT 10.00

CST4.19MGW∗
CO., LTD 30 30
4.19
CST8.00MTW∗ 8.00 (ii)
CST10.00MTW∗ 10.00
4.19
FUJI SANGYO
CO., LTD HC-49/U03 8.00 15 15
10.00
(i)
4.19
KINSEKI LTD. HC-49/U (-S) 8.00 27 27
10.00
∗ Indicates types with on-chip grounding capacitors (C1 and C2).

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 CXP82316/82320/82324

Package Outline Unit: mm

80PIN QFP (PLASTIC)

23.9 ± 0.4
+ 0.1
+ 0.4 0.15 – 0.05
20.0 – 0.1
0.15
64 41

65 40

17.9 ± 0.4
+ 0.4
14.0 – 0.1

16.3
A

80 25 + 0.2
0.1 – 0.05

1 24

0.8 ± 0.2
+ 0.15 + 0.35
0.8 0.35 – 0.1 2.75 – 0.15
0.12 M

0° to 10°

DETAIL A PACKAGE STRUCTURE

PACKAGE MATERIAL EPOXY RESIN

SONY CODE QFP-80P-L01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE QFP080-P-1420 LEAD MATERIAL 42/COPPER ALLOY

JEDEC CODE PACKAGE MASS 1.6g

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