Digital Circuits and Systems Lab

Laboratory report submitted for the partial fulfillment

of the requirements for the degree of

Bachelor of Technology
in
Electronics and Communication Engineering

by

Urvi Bhatia - 19UEC158.

Course Coordinator
Dr. Kusum Lata

Department of Electronics and Communication Engineering

The LNM Institute of Information Technology, Jaipur

August 2020
Copyright Ⓧ
c The LNMIIT 2017
All Rights Reserved
 Contents

Chapter Page

1 Experiment - 1 .................................................................................................................................. 1
1.1 Name of the Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Coding Techniques used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4.1 Half Adder using Dataflow Modeling . . . . . . . . . . . . . . . . . . . . . . 2
1.4.2 Half Adder using Behavioral modeling . . . . . . . . . . . . . . . . . . . . . 2
1.4.3 Full Adder using Dataflow modeling . . . . . . . . . . . . . . . . . . . . . . . 2
1.4.4 Full Adder using Behavioral modeling . . . . . . . . . . . . . . . . . . . . . . 2
1.4.5 Full Adder using Structural modeling . . . . . . . . . . . . . . . . . . . . . . 2
1.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

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 Chapter 1

Experiment - 1

1.1 Name of the Experiment

To design, simulate and implement Half adder, Full adder using dataflow, behavioral and structural
modeling in VHDL.

1.2 Theory

Half Adder - Half adder is a combinational circuit which uses two inputs( ’a’ and ’b’ ) and gives sum
and carry as output where, sum is ’a’ xor ’b’ and carry is ’a’ and ’b’. AND and XOR gate are employed
in its design implementation.
Full adder - Full adder is a combinational circuit which uses three inputs( ’a’ and ’b’ and ’cin’ ) and
gives sum and carry as output where, sum is ’a’ xor ’b’ xor ’cin’ and carry is ’a.b’ or ’b.cin’ or ’cin.a’.
Full adder can also be implemented using half adder.

1.3 Coding Techniques used

1. Data Flow Modeling

Data flow modeling is concurrent style of modeling in VHDL. It describes the architecture of the
entity under design without describing its components in terms of flow of data from input towards
output. This style of modeling is closet to RTL schematic of the circuit. In this experiment we have
implemented half adder and full adder using data flow modeling.
2. Behavioral Modeling
The beharioral style of modeling specifies the behavior of an entity as a set of statements that are
executed sequentially in the specified order. This set of sequential statements , that are specified inside
a process statement and specifies functionality of entity. In this experiment we have implemented half
adder and full adder using behavior modeling.

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 3. Structural Modeling
Structural modeling is used to describe circuit in terms of component which are already defined
earlier. We are using structural modeling to implement full adder using half adder as a component
and the half adder is defined earlier.

1.4 Simulation and Results

1.4.1 Half Adder using Dataflow Modeling

Figure 1.1 Schematic of the Half adder using Dataflow modeling

1.4.2 Half Adder using Behavioral modeling

1.4.3 Full Adder using Dataflow modeling

1.4.4 Full Adder using Behavioral modeling

1.4.5 Full Adder using Structural modeling

1.5 Summary
Make a tabular comparison of all the codes in terms of area and power usage.

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Figure 1.2 Project Summary of the Half adder using Dataflow modeling

Figure 1.3 Simulation of the Half adder using Dataflow modeling

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 Figure 1.4 Schematic of the Half adder using Behavioral modeling

Figure 1.5 Project Summary of the Half adder using Behavioral modeling

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Figure 1.6 Simulation of the Half adder using Behavioral modeling

Figure 1.7 Schematic of the Full adder using Dataflow modeling

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Figure 1.8 Project Summary of the Full adder using Dataflow modeling

Figure 1.9 Simulation of the Full adder using Dataflow modeling

Figure 1.10 Schematic of the Full adder using Behavioral modeling

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Figure 1.11 Project Summary of the Full adder using Behavioral modeling

Figure 1.12 Simulation of the Full adder using Behavioral modeling

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 Figure 1.13 Schematic of the Full adder using Structural modeling

Figure 1.14 Project Summary of the Full adder using Structural modeling

Figure 1.15 Simulation of the Full adder using Structural modeling

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 Name of the Entity
Half Adder using Dataflow
Half Adder using Behavioral
Full Adder using Dataflow
Full Adder using Behavioral
Full Adder using Structural
No. of LUT used Total On chip Power
1 0.721W
1 0.721W
1 0.958W
1 0.956W
1 0.958W

Table 1.1 Comparison of Area and power requirements for different kinds of adders.