CURRICULUM VITAE

Muni Reddy. M
S/o M.Ponneppa Reddy,
1-211 , Opp to Water Tank,
Sri Kalahasti,
Chittoor –A.P. 517644

Mobile: 09397974464
Email: munireddyjntu @gmail.com

OBJECTIVE

Seeking a professionally challenging position in the area of teaching that provides a highly motivated,
progressive, friendly environment which allows the pursuit of career advancement.

EXPERIENCE & CERTIFICATIONS

 Having Two Years of Experience at B.I.T.Institute of Technology, Hindupur, Affiliated to JNTU –

Anantapur, A.P.

 A Ratified Assistant Professor from JNT University, Anantapur (2010).

 Advanced certified training program in VLSI, MSRSAS, Bangalore.

EDUCATIONAL QUALIFICATIONS

Post Graduation

Masters Degree : M.Tech. In Digital System & Computer Electronics (DSCE)

Institution : JNTU College of engineering
University : JNTU University, Anantapur
Year of Completion : June 2009
Percentage of Marks : 67%
Class : First class

Graduation

Bachelor Degree : B.E. in Electronics and Communication Engineering

Institution : Sri Jayaram College of Engineering
University : Anna University, Chennai
Year of Completion : April 2006
Percentage of Marks : 73%
Class : First class

H.S.C.

Year of Completion : April 2002

Percentage of Marks : 70%
Class : First class

1
Skills:

Field/Area Specialization

Operating Systems Windows 98/2000/ XP and Cisco IOS. Unix/Linux

Office Packages MS Office Package.

Software C, Embedded C, VHDL, Verilog, MAT Lab

Assembly Languages INTEL 8085, 8086.

Project Undertaken in final year B Tech and M.Tech:

TITLE
Degree Period College

B.E 3 Months SJEC, ANNA UNIVERSITY Home Automation

M.Tech 1 YEAR JNTU CEA Design of LDPC (Digital Communication)

Title : Home Automation & Design of LDPC (Digital Communication)

Team Size : one

Organization : Own Project under the external guidance of SJEC Lecturer

Description : The project work deals with study and implementation of LDPC coding
system. The following work has been carried out (1) Construction of parity check matrix for block
lengths 100,500 and 1000, (2) Implementation of the Generator matrix (G) for block lengths100, 500
and 1000, (3)Implementation of Additive White Gaussian Noise(AWGN) and Rayleigh fading
channel models (4)Implementation of Decoder using following algorithms,(a)Bit flip algorithm,
(b)Belief Propagation Algorithm,(c) Sum Product Algorithm in Log domain, (d)Min-Sum
Algorithm, (e)Min-Sum Algorithm with correction factor. (5) Comparative performance evaluation
(Bit Error Rate Vs Eb/N0) of different decoding algorithms for different block lengths. (6)
Comparative computation time evaluation (Time Vs Eb/N0) for different decoding algorithms.
Tool Used : Mat lab 7.1
Student projects guided:

Level Degree/Program University/College Title Period

Embedded systems
UG BE Microcontroller, From 2008 onwards
JNTU University BIT. IT Robotics, DIP

Subjects Taught/Teaching:

2
S. No. Subjects Degree/Program

1 Cellular Mobile Communications B.Tech

2 Satellite Communication B.Tech

3 Digital Communication B.Tech

4 Logic Design & Digital Circuits B.Tech

5 Digital Image Processing B.Tech

6 Microprocessors and Interfacing B.Tech

Conferences/Seminars attended:

1. Attended a National Level Work Shop on “FPGA based system design” on Sep 2007 at Sir C.R.Reddy
College of Engineering, Eluru.

2. Attended a National Work shop ON DIPT (Digital Image Processing Trends), RTES (Recent Trends in
Embedded Systems) At JNTU CEA, Anantapur, 2009

Administration:

1. Experience in Examination organization.

2. Experience in National Board of Accreditation Process.

3. Faculty coordinator

Personal Particulars:

Sex : Male
Date of Birth : 10/06/1985
Father’s Name : M Ponnepa Reddy
Languages Known : English, Telugu, Tamil, Kannada

Declaration:

I here by declare that all the information stated above is true to the best of my knowledge.

Place:
Date: - - (M.Muni Reddy)