Modeling of Latches and Flip Flops

Prof. A. K. Swain
Asst. Prof., ECE Dept., NIT Rourkela

EC6203: Reconfigurable System Design

 Modeling Latches and Flip Flop
Learning Objectives:
o How to model a latch and flip flop.
o Difference between latch and flip flop.
o Difference between asynchronous and synchronous reset.
o Modelling JK and T flip flop

Modeling of Latches and Flip Flops EC6203 Reconfigurable System Design

 Latch
• Latch is a logic circuit used to store 1 bit data, It looses data, once the device is powered off.
• It acts as a memory device; level sensitive; bi-stable multivibrator.
• When enable is asserted the latch changes the stored value if the input data is changed.
• If enable is on, it keeps on sampling the input to the output.

Modeling of Latches and Flip Flops EC6203 Reconfigurable System Design

 D-Flip Flop
• D-Flip flops is used to store binary data.
• Flip fop is edge triggered : It changes state when clock is positive or negative edge triggered.
• Flip flop designs are more suitable for timing analysis than latch.

Latch Flip Flop

Latch is level sensitive.
Latch continuously transfer data from
input to output
Less area, Less power
Requires more effort to meet timing
Chances of glitches and race around
condition
Latch circuits are noisy.
Latches are faster
Flip flop is edge triggered.
Flip Flop depends on the rising and falling
edge of the controlling signal
More area and more powers
Suitable for timing analysis
Glitch free. Race around can be avoided
Flip flop designs are noise free.
Flip flop based designs are slower

Modeling of Latches and Flip Flops EC6203 Reconfigurable System Design

 D-Flip Flop
Reset:
Reset is used to initialize the hardware to a known state.
There are two types of Reset
Synchronous Reset Asynchronous Reset

Modeling of Latches and Flip Flops EC6203 Reconfigurable System Design

 D-Flip Flop
Reset:
Reset is used to initialize the hardware to a known state.
There are two types of Reset
Synchronous Reset Asynchronous Reset

Modeling of Latches and Flip Flops EC6203 Reconfigurable System Design

 Asynchronous Vs Synchronous Reset
Asynchronous Reset
Asynchronous reset is Fast
Reset gets highest priority
Does not require presence of clock to
reset circuit
Metasabilty may occur
Circuit may have glitches.
Less number of gates are required to
implement circuits.
Synchronous Reset
Synchronous reset is slow
Clock gets highest priority
Requires presence of clock to reset circuit
No metastability issue
Circuit may not be affected by glitches
Requires more gates to implement circuit

Modeling of Latches and Flip Flops EC6203 Reconfigurable System Design

 JK-Flip Flop
• If j=k=1, q=~q; If j=k=0, q=q; If j=1,k=0, q=1; If j=0,k=1, q=0

Modeling of Latches and Flip Flops EC6203 Reconfigurable System Design

 T-Flip Flop
• If t=1, q=~q; If t=0, q latches.

Modeling of Latches and Flip Flops EC6203 Reconfigurable System Design

References
Books:
A Verilog HDL Primer: by J Bhasker.
Design Through Verilog HDL: T.R. Padmanavan, B. Bala Tripura Sundari
Verilog Digital Design Synthesis: Samir Palnitkar.

website:
asic-world.com
www.xilinx.com