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 www.fairchildsemi.com

AN-8027
FAN480X PFC+PWM Combination Controller Application
FAN4800AU / FAN4800AS / FAN4800C / FAN4800CS / FAN4801S / FAN4802S

Introduction The synchronization of the PWM with the PFC simplifies

This application note describes step-by-step design the PWM compensation due to the controlled ripple on the
considerations for a power supply using the FAN480X PFC output capacitor (the PWM input capacitor). In
controller. The FAN480X combines a PFC controller and addition to power factor correction, a number of protection
a PWM controller. The PFC controller employs average features have been built in to the FAN480X. These
current mode control for Continuous Conduction Mode include programmable soft-start, PFC over-voltage
(CCM) boost converter in the front end. The PWM protection, pulse-by-pulse current limiting, brownout
controller can be used in either current mode or voltage protection, and under-voltage lockout.
mode for the downstream converter. In voltage mode, FAN480X feature programmable two-level PFC output to
feed-forward from the PFC output bus can be used to improve efficiency at light-load and low-line conditions.
improve the line transient response of PWM stage. In
either mode, the PWM stage uses conventional trailing- FAN480X is pin-to-pin compatible with FAN4800 and
edge duty cycle modulation, while the PFC uses leading- ML4800, only requiring adjustment of some peripheral
edge modulation. This proprietary leading/trailing-edge components. The FAN480X series comparison is
modulation technique can significantly reduce the ripple summarized in the Appendix A.
current of the PFC output capacitor.

F1 L BOOST DBOOST VBOUT

AC L 11 L1
2
Input CBOOST R FB1 Vo1
CIF1 DR1
Q1 Q2 DR1
Drv Drv
DF1 CO11 CO12
RCS1
R RAMP

D1 D2 L22
Vo2
DR2 L 2
1
DF2 CO21 CO22
Q3
Drv DR2

RLF2
CIC2 RCS2

R IAC
RLF1
RRMS1 RIC CIC1
RD Vo
RT
1
IEA VEA
CRMS1 IAC FBPFC
RRMS2 RB RBIAS
ISENSE VREF
VD VD
VRMS D CF RF ROS1
D RVC
CLF1 CSS SS OPFC
CRMS2 R FBPWM
RMS3 OPWM
CVC2 Vo2
RT/CT GND
CT ROS2
RAMP ILIMIT CVC1
FAN480X ROS3
CRAMP RFB2

CB CFB

CLF2 CDD CREF

Figure 1. Typical Application Circuit of FAN480X

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 6/21/13
AN-8027

Functional Description
Gain Modulator However, once PFC stops switching operation, the
junction capacitance of bridge diode is not discharged and
The gain modulator is the key block for PFC stage because VIN of Figure 2 is clamped at the peak of the line voltage.
it provides the reference to the current control error Then, the voltage of VRMS pin is given by:
amplifier for the input current shaping, as shown in Figure
2. The output current of gain modulator is a function of 2 RRMS 3
VEA, IAC, and VRMS. The gain of the gain modulator is VRMS NS  VLINE (2)
RRMS1  RRMS 2  RRMS 3
given in the datasheet as a ratio between IMO and IAC with a
given VRMS when VEA is saturated to HIGH. The gain is
inversely proportional to VRMS2, as shown in Figure 3, to Therefore, the voltage divider for VRMS should be
implement line feed-forward. This automatically adjusts designed considering the brownout protection trip point
the reference of current control error amplifier according and minimum operation line voltage.
to the line voltage such that the input power of PFC
converter is not changed with line voltage.
VIN PFC runs PFC stops
IL
VIN

IEA
R
M
ISENS
E
R IMO  G  I AC VRMS
RRMS1 M K  (VEA  0.7)
RIAC  I AC 
IA VRMS 2 (VEAMAX  0.7)
C
CRMS1 IAC
RRMS2 VRMS k
x
CRMS2 2

RRMS3
VEA Gain Figure 4. VRMS According to the PFC Operation
Modulator

The rectified sinusoidal signal is obtained by the current

Figure 2. Gain Modulator Block flowing into the IAC pin. The resistor RIAC should be large
enough to prevent saturation of the gain modulator as:
1
G
VRMS 2 2VLINE .BO MAX
G  159 A (3)
RIAC
where VLINE.BO is the line voltage that trips brownout
protection, GMAX is the maximum modulator gain when
VRMS is 1.08 V (which can be found in the datasheet), and
159 µA is the maximum output current of the gain
modulator.
Current and Voltage Control of Boost Stage
As shown in Figure 5, the FAN480X employs two control
VRMS loops for power factor correction: a current control loop
and a voltage control loop. The current control loop shapes
VRMS-UVP inductor current, as shown in Figure 6, based on the
reference signal obtained at the IAC pin as:
Figure 3. Modulation Gain Characteristics
I L  RCS1  I MO  RM  I AC  G  RM (4)
To sense the RMS value of the line voltage, an averaging
circuit with two poles is typically employed, as shown in
Figure 2. The voltage of VRMS pin in normal PFC
operation is given as:

2 RRMS 3 2
VRMS  VLINE  (1)
RRMS1  RRMS 2  RRMS 3 

where VLINE is RMS value of line voltage.

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 6/21/13 2
AN-8027

V IN VO It is typical to set the second boost output voltage as

340 V~300 V.
IL
VRMS
-
VBOUT
+

VDD 1.95/2.45
RCS1
RF1 +
RM RFB1
IEA 1.95/2.45
ISENSE RM FBPFC 20uA -

RIC
VEA
RRMS1 CF1
RIAC IMO
CIC2 2.5V
IAC CIC1
RFB2
CRMS1 IAC VREF
RRMS2 Drive logic
VRMS + For FAN4801S, VEA threshold is 2.8/3.35V
CRMS2
RRMS3 VEA - OPFC
RFB1 Figure 7. Block of Two-Level PFC Output
RVC
FBPFC
RVC2
RVC1 Oscillator
2.5V RFB2
The internal oscillator frequency of FAN480X is
determined by the timing resistor and capacitor on the
Figure 5. Gain Modulation Block
RT/CT pin. The frequency of the internal oscillator is
IAC given by:
1
fOSC  (6)
RM
0.56  RT  CT  360CT
I MO
RCS1

Because the PWM stage of FAN480X generally uses a

forward converter, it is required to limit the maximum duty
IL
cycle at 50%. To have a small tolerance of the maximum
duty cycle, a frequency divider with toggle flip-flops is
used, as illustrated in Figure 8. The operation frequency of
Figure 6. Inductor Current Shaping PFC and PWM stage is one quarter (1/4) of the oscillator
frequency. (For FAN4800CU, FAN4800CS, and
The voltage control loop regulates PFC output voltage
FAN4802S, the operation frequencies for PFC and PWM
using internal error amplifier such that the FBPFC voltage
stages are one quarter (1/4) and one half (1/2) of the
is same as internal reference of 2.5 V.
oscillator frequency, respectively).
Brownout Protection
The dead time for the PFC gate drive signal is determined
FAN480X has a built-in internal brownout protection by the equation:
comparator monitoring the voltage of the VRMS pin. Once
the VRMS pin voltage is lower than 1.05 V (0.9 V for
FAN4802S), the PFC stage is shutdown to protect the tDEAD  360CT (7)
system from over current. The FAN480X starts up the The dead time should be smaller than 2% of switching
boost stage once the VRMS voltage increases above 1.9 V period to minimize line current distortion around line
(1.65 V for FAN4802S). zero crossing.
Two-Level PFC Output T-FF T-FF
To improve system efficiency at low AC line voltage and VREF
T Q T Q
light load condition, FAN480X provides two-level PFC
output voltage. As shown in Figure 7, FAN480X monitors RT/
VEA and VRMS voltages to adjust the PFC output voltage. CT OSC OPFC, OPWM
When VEA and VRMS are lower than the thresholds, an
internal current source of 20 µA is enabled that flows OPWM (FAN4800CX, FAN4802S)
through RFB2, increasing the voltage of the FBPFC pin.
This causes the PFC output voltage to reduce when 20 µA
is enabled, calculated as: Figure 8. Oscillator Configuration

RFB1  RFB 2
VOPFC 2   (2.5 - 20 μA  RFB 2 ) (5)
RFB 2

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 6/21/13 3
AN-8027

RT/CT VBOUT

REF
PFC dead time RRAMP
1.5V PWM
-

OPFC CRAMP RAMP +

OPWM
FBPWM

OPWM (FAN4800CX, FAN4802S)

Figure 9. FAN480X Timing Diagram

Figure 10. PWM Ramp Generation Circuit
PWM Stage
The PWM stage is capable of current-mode or voltage-
mode operation. In current-mode applications, the PWM PWM Current Limit
ramp (RAMP) is usually derived directly from a current
The ILIMIT pin is a direct input to the cycle-by-cycle
sensing resistor or current transformer in the primary of the
current limiter for the PWM section. If the input voltage at
output stage and is thereby representative of the current
this pin exceeds 1 V, the output of the PWM is disabled
flowing in the converter’s output stage. ILIMIT, which
until the start of the next PWM clock cycle.
provides cycle-by-cycle current limiting, is typically
connected to RAMP in such applications. VIN OK Comparator
For voltage-mode operation, RAMP can be connected to a The VIN OK comparator monitors the output of the PFC
separate RC timing network to generate a voltage ramp stage and inhibits the PWM stage if this voltage is less
against which FBPWM voltage is compared. Under these than 2.4 V (96% of its nominal value). Once this voltage
conditions, the use of voltage feed-forward from the PFC goes above 2.4 V, the PWM stage begins to soft-start.
bus can be used for better line transient response.
PWM Soft-Start (SS)
No voltage error amplifier is included in the PWM stage, PWM startup is controlled by the soft-start capacitor. A
as this function is generally performed by a programmable 10 µA current source supplies the charging current for the
shunt regulator, such as KA431, in the secondary-side. To soft-start capacitor. Startup of the PWM is prohibited until
facilitate the design of opto-coupler feedback circuitry, an the soft-start capacitor voltage reaches 1.5 V.
offset voltage is built into the inverting input of PWM
comparator that allows FBPWM to command a zero
percent duty cycle when its pin voltage is below 1.5 V.

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 6/21/13 4
AN-8027

Design Considerations
In this section, a design procedure is presented using the a design example. The design specifications are
schematic in Figure 11 as reference. A 300 W PC power summarized in the table below. The two-switch forward
supply application with universal input range is selected as converter is used for DC-DC converter stage.

Design Specifications

Rated Voltage of Output 1 VOUT1 = 5 V PWM Stage Efficiency ηPWM = 0.86

Rated Current of Output 1 IOUT1 = 9 A Hold-up Time tHLD = 20 ms
Rated Voltage of Output 2 Vout2 = 12 V Minimum PFC Output Voltage 310 V
Rated Current of Output 2 IOUT2 = 16.5 A Nominal PFC output voltage VO_PFC = 387 V
Rated Voltage of Output 3 VOUT3 = -12 V PFC Output Voltage Ripple 12 VPP
Rated Current of Output 3 IOUT3 = 0.8 A PFC Inductor Ripple Current dI = 40%
Rated Voltage of Output 4 VOUT4 = 3.3 V AC Input Voltage Frequency fline = 50 ~ 60 Hz
Rated Current of Output 4 IOUT4 = 13.5 A Switching Frequency fS = 65 kHz
Rated Output Power PO = 300 W Total Harmonic Distortion α = 4%
Line Voltage Range 85~264 VAC Magnetic Flux Density ΔB = 0.27 T
Line Frequency 50 Hz Current Density Dcma = 400 C-m/A
Brownout Protection Line Voltage 72 VAC PWM Maximum Duty Cycle Dmax = 0.35
Overall Stage Efficiency η = 0.82 5-V Output Current Ripple ILo1 = 44%
12-V Output Current Ripple ILo2 = 10%

F1 L BOOST DBOOST VBOUT

AC L 11 L1
2
Input CBOOST R FB1 Vo1
CIF1 DR1
Q1 Q2 DR1
Drv Drv
DF1 CO11 CO12
RCS1
R RAMP

D1 D2 L22
Vo2
DR2 L2
1
DF2 CO21 CO22
Q3
Drv DR2

RLF2 Vo3
CIC2 RCS2 Vo4

R IAC
RLF1
RRMS1 RIC CIC1
RD
RT Vo1
IEA VEA
CRMS1 IAC FBPFC
RRMS2 RB RBIAS
ISENSE VREF
VD VD
VRMS D CF RF ROS1
D RVC
CLF1 CSS SS OPFC
CRMS2 R FBPWM
RMS3 OPWM
CVC2 Vo2
RT/CT GND
CT ROS2
RAMP ILIMIT CVC1
FAN480X ROS3
CRAMP RFB2

CB CFB

CLF2 CDD CREF

Figure 11. Reference Circuit for Design Example

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 6/21/13 5
AN-8027

[STEP-1] Define System Specifications

(Design Example) Since the switching frequency is
Since the overall system is comprised of two stages (PFC 65 kHz, CT is selected as 1 nF. Then the maximum duty
and DC-DC), as shown in Figure 12, the input power and cycle of PFC gate drive signal is obtained as:
output power of the boost stage are given as:
DMAX .PFC  1  360  CT  f SW  0.98
POUT
PIN  (8) The timing resistor is determined as:
 1 1
RT    6.9k 
POUT 4 0.56 f SW CT
PBOUT  (9)
 PWM
where  is the overall efficiency and PWM is the forward
converter efficiency. [STEP-3] Line Sensing Circuit Design
The nominal output current of boost PFC stage is given as: FAN480X senses the RMS value and instantaneous value of
line voltage using the VRMS and IAC pins, respectively, as
POUT shown in Figure 13. The RMS value of the line voltage is
I BOUT  (10) obtained by an averaging circuit using low pass filter with
 PWM VBOUT two poles. Meanwhile, the instantaneous line voltage
PBOUT information is obtained by sensing the current flowing into
PIN IBOUT POUT the IAC pin through RIAC.

Boost VBOUT Forward VOUT

VIN

PFC DC/DC
IL

Figure 12. Two-Stage Configuration

(Design Example)

POUT 300
PIN    366W
 0.82 RIAC
IAC
IA
C
POUT VRMS
300 RRMS1 120/100Hz
PBOUT    349W VIN
 PWM 0.86
CRMS1 RRMS2

POUT 300 VRMS

I BOUT    0.9 A CRMS2

 PWM VBOUT 0.86  387 fp1 fp2

RRMS3

[STEP-2] Frequency Setting Figure 13. Line Sensing Circuits

The switching frequency is determined by the timing RMS sensing circuit should be designed considering the
resistor and capacitor (RT and CT) as: nominal operation range of line voltage and brownout
1 1 protection trip point as:
f SW   (11)
4 0.56  RT  CT 2 RRMS 3 2
VRMS UVL  VLINE .BO  (13)
It is typical to use a 470 pF~1 nF capacitor for 50~75 kHz RRMS1  RRMS 2  RRMS 3 
switching frequency operation since the timing capacitor 2 RRMS 3
value determines the maximum duty cycle of PFC gate VRMS UVH  VLINE .MIN (14)
drive signal as: RRMS1  RRMS 2  RRMS 3

TOFF .MIN where VRMS-UVL and VRMS-UVH are the brown OUT/IN
DMAX .PFC  1   1  360  CT  f SW (12) thresholds of VRMS.
TSW
It is typical to set RRMS2 as 10% of RRMS1. The poles of the
low pass filter are given as:
1
f P1  (15)
2  CRMS1  RRMS 2
1
fP2  (16)
2  CRMS 2  RRMS 3

To properly attenuate the twice line frequency ripple in

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.2 • 6/21/13 6
AN-8027

VRMS, it is typical to set the poles around 10~20 Hz. The average of boost inductor current over one switching
cycle at the peak of the line voltage for low line is given as:
The resistor RIAC should be large enough to prevent
saturation of the gain modulator as: 2 POUT
I L. AVG  (20)
VLINE .MIN 
2VLINE .BO MAX
G  159 A (17) Therefore, with a given current ripple factor
RIAC
(KRB=IL/ILAVG), the boost inductor value is obtained as:
where VLINE.BO is the brownout protection line voltage,
GMAX is the maximum modulator gain when VRMS is 1.08 V VLINE .MIN 2  VBOUT  2VLINE 1
LBOOST    (21)
(which can be found in the datasheet), and 159 µA is the K RB  POUT VBOUT f SW
maximum output current of the gain modulator. The maximum current of boost inductor is given as:

(Design Example) The brownout protection threshold is K RB 2 POUT K

I L PK  I L. AVG  (1  )  (1  RB ) (22)
1.05 V (VRMS-UVL) and 1.9 V (VRMS-UVH), respectively. 2 VLINE .MIN  2
Then, the scaling down factor of the voltage divider is:
RRMS 3 V 
 RMS UVL  (Design Example) With the ripple current specification
RRMS 1  RRMS 2  RRMS 3 VLINE .BO 2 2 (40%), the boost inductor is obtained as:
1.05 
   0.0162 VLINE .MIN 2  VBOUT  2VLINE 1
72 2 2 LBOOST   
K RB  POUT VBOUT f SW
Then the startup of the PFC stage at the minimum line 852  0.82 387  2  85 103
voltage is checked as:     524 H
0.4  300 387 65
VLINE .MIN  2 RRMS 3 The average of boost inductor current over one switching
 85  2  0.0162  1.95  1.9V cycle at the peak of the line voltage for low line is
RRMS1  RRMS 2  RRMS 3 obtained as:
The resistors of the voltage divider network are selected 2 POUT 2  300
as RRMS1=2 M, RRMS1=200 k, and RRMS1=36 k. I L. AVG    6.09 A
VLINE .MIN  85  0.82
To place the poles of the low pass filter at 15 Hz and
22 Hz, the capacitors are obtained as: The maximum current of the boost inductor is given as:
1 1
CRMS1    53nF I L PK 
2 POUT K
 (1  RB )
2  f P1  RRMS 2 2 15  200 103 VLINE .MIN  2
1 1 2  300 0.4
CRMS 2    200nF   (1  )  7.31A
2  f P 2  RRMS 3 2  22  36 103 85  0.82 2

The condition for Resistor RIAC is:

2VLINE .BO MAX 2  72  9 [STEP-5] PFC Output Capacitor Selection
RIAC  G   5.8M 
159 106 159 106 The output voltage ripple should be considered when
selecting the PFC output capacitor. Figure 14 shows the
Therefore, 6 M resistor is selected for RIAC. twice line frequency ripple on the output voltage. With a
given specification of output ripple, the condition for the
output capacitor is obtained as:

[STEP-4] PFC Inductor Design I BOUT

CBOUT  (23)
2  f LINE  VBOUT , RIPPLE
The duty cycle of boost switch at the peak of line voltage is
given as: where IBOUT is nominal output current of boost PFC stage
and VBOUT,RIPPLE is the peak-to-peak output voltage ripple
VBOUT  2VLINE specification.
DLP  (18)
VBOUT
The hold-up time also should be considered when
Then, the maximum current ripple of the boost inductor at determining the output capacitor as:
the peak of line voltage for low line is given as:
PBOUT  tHOLD
CBOUT  (24)
2VLINE .MIN VBOUT  2VLINE 1 VBOUT 2  VBOUT , MIN 2
I L    (19)
LBOOST VBOUT f SW where PBOUT is nominal output power of boost PFC stage,
tHOLD is the required holdup time, and VBOUT,MIN is the
allowable minimum PFC output voltage during hold-up time.

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 6/21/13 7
AN-8027

VRMS
ID -
VBOUT
+

VDD 1.95/2.45
+
I D , AVG RFB1
1.95/2.45
FBPFC 20uA -
VEA
I D , AVG  I BOUT (1  cos(4  f LINE  t ))
2.5V
RFB2
I BOUT
For FAN4801S, VEA threshold is 2.8/3.35V.

I BOUT
VBOUT , RIPPLE  Figure 15. Two-Level PFC Output Block
2 f LINE CBOUT
The voltage divider network for the PFC output voltage
sensing should be designed such that FBPFC voltage is
VBOUT 2.5V at nominal PFC output voltage:
RFB 2
VBOUT   2.5V (26)
Figure 14. PFC Output Voltage Ripple RFB1  RFB 2

(Design Example) Assuming the second level of

(Design Example) With the ripple specification of PFC output voltage is 347 V:
12 VPP, the capacitor should be: VBOUT 2 2.5
RFB 2  (1  )
I BOUT 0.9 VBOUT 20 106
CBOUT    239 F
2  f LINE  VBOUT , RIPPLE 2  50 12 347 2.5
 (1  )  12.9k 
Since minimum allowable output voltage during one 387 20 106
cycle line (20 ms) drop-outs is 310 V, the capacitor 13 k is selected for RFB2.
should be:
PBOUT  tHOLD 2  349  20 103 VBOUT
CBOUT    260 F RFB1  (  1)  RFB 2
VOUT  VOUT , MIN
2 2
387  310
2 2 2.5
387
(  1) 13  103  1999k 
Thus, 270 F capacitor is selected for the PFC output 2.5
capacitor.
2 M is selected for RFB1.

[STEP-6] PFC Output Sensing Circuit

[STEP-7] PFC Current-Sensing Circuit Design
To improve system efficiency at low line and light load
condition, FAN480X provides two-level PFC output Figure 16 shows the PFC compensation circuits. The first
voltage. As shown in Figure 15, FAN480X monitors VEA step in compensation network design is to select the current-
and VRMS voltages to adjust the PFC output voltage. sensing resistor of PFC converter considering the control
window of voltage loop. Since line feed-forward is used in
The PFC output voltage when 20 µA is enabled is given as: FAN480X, the output power is proportional to the voltage
control error amplifier voltage as:
20 μA  RFB 2
VBOUT 2  VBOUT  (1 - ) (25)
2.5 VEA  0.6
PBOUT (VEA )  PBOUT MAX  (27)
VEASAT  0.6
It is typical second boost output voltage as 340 V~300 V.
where VEASAT is 5.6 V and the maximum power limit of
PFC is:
VLINE .BO 2  G MAX  RM
PBOUT MAX  (28)
RIAC RCS1

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 6/21/13 8
AN-8027

It is typical to set the maximum power limit of PFC stage The transfer function of the compensation circuit is given as:
around 1.2~1.5 of its nominal power such that the VEA is
s
around 4~4.5 V at nominal output power. By adjusting the 1
current-sensing resistor for PFC stage, the maximum vIEA 2 f II 2 f IC
  (31)
power limit of PFC stage can be programmed. vCS1 s s
1
To filter out the current ripple of switching frequency, an 2 f IP
RC filter is typically used for ISENSE pin. RLF1 should not where:
be larger than 100 Ω and the cut-off frequency of filter
GMI 1
should be 1/2~1/6 of the switching frequency. f II  , f IZ  and
2  CIC1 2  RIC  CIC1
Diodes D1 and D2 are required to prevent over-voltage on (32)
1
the ISENSE pin due to the inrush current that might f IP 
2  RIC  CIC 2
damage the IC. A fast recovery diode or ultra fast recovery
diode is recommended. The procedure to design the feedback loop is as follows:
VIN VO
(a) Determine the crossover frequency (fIC) around
IL 1/10~1/6 of the switching frequency. Then calculate
the gain of the transfer function of Equation (30) at
crossover frequency as:

vCS1 RCS1 VBOUT

 (33)
RCS1 vIEA @ f  f IC
VRAMP  2 f IC  LBOOST
RF1
RM
IEA
ISENS R
E M
RI (b) Calculate RIC that makes the closed loop gain unity at
RRMS1 CF1 C
IM crossover frequency:
RIAC O CIC2
IA
CIC1
C
1
CRMS1
RRMS2
IAC
VRMS
Drive
logic
VREF
RIC 
+
vCS1 (34)
GMI 
CRMS2
RRMS3 VEA - OPFC
vIEA @ f  f IC
RV RFB1
C
FBPFC
RVC2
RVC1
2.5V RFB2 (c) Since the control-to-output transfer function of power
stage has -20 dB/dec slope and -90o phase at the
crossover frequency is 0 dB, as shown in Figure 17; it
Figure 16. Gain Modulation Block
is necessary to place the zero of the compensation
network (fIZ) around 1/3 of the crossover frequency so
(Design Example) Setting the maximum power limit
that more than 45 phase margin is obtained. Then the
of PFC stage as 450W, the current sensing resistor is
capacitor CIC1 is determined as:
obtained as:
1
VLINE .BO 2  G MAX  RM 722  9  5.7 103 CIC1  (35)
RCS1    0.098 RIC  2 fC / 3
RIAC PBOUT MAX 6 106  450

Thus, 0.1- resistor is selected.

(d) Place compensator high-frequency pole (fCP) at least a
decade higher than fIC to ensure that it does not
[STEP-8] PFC Current Loop Design interfere with the phase margin of the current loop at
its crossover frequency.
The transfer function from duty cycle to the inductor
current of boost power stage is given as: 1
CIC 2  (36)
2  f IP  RIC
iL V
 BOUT (29)
d sLBOOST

The transfer function from the output of the current control

error amplifier to the inductor current-sensing voltage is
obtained as:
vCS1 R V
 CS1 BOUT (30)
vIEA VRAMP  sLBOOST

where VRAMP is the peak to peak voltage of ramp signal for

current control PWM comparator, which is 2.55 V.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.2 • 6/21/13 9
AN-8027

60dB 60dB
Closed Loop Gain
Control-to-output Closed-Loop Gain
40dB 40dB
Control-to-Output
Compensation
20dB
20dB
fIP
0dB fIZ
fIC fc
0dB

-20dB

-20dB
-40dB
10Hz 100Hz 1kHz 10kHz 100kHz 1MHz Compensation
-40dB
1Hz 10Hz 100Hz 1kHz 10kHz

Figure 17. Current Loop Compensation Figure 18. Voltage Loop Compensation

The transfer function of the compensation network is

(Design Example) Setting the crossover frequency
obtained as:
as 7 kHz:
s
vCS1 RCS1  VBOUT 1
 vˆCOMP 2 fVI 2 fVZ
vIEA @ f  f IC
VRAMP  2 f IC  LBOOST   (39)
vˆOUT s 1
s
0.1 387 2 fVP
  0.66
2.55  2  7  103  524 106 where:
1 1 2.5 GMV 1
RIC    17k  fVI   , fVZ  and
v 88 106  0.66 VBOUT 2  CVC1 2  RVC  CVC1
GMI  CS1 1
(40)
vIEA @ f  f IC fVP 
2  RVC  CVC 2
1 1
CIC1    4nF The procedure to design the feedback loop is as follows:
RIC  2 fC / 3 17 103  2  7 103 / 3
(a) Determine the crossover frequency (fVC) around
Setting the pole of the compensator at 70kHz, 1/10~1/5 of the line frequency. Since the control-to-
1 1 output transfer function of power stage has -20 dB/dec
CIC 2    0.13nF slope and -90o phase at the crossover frequency, as
2  f IP  RIC 2  70 103 17 103 shown in Figure 18 as 0dB; it is necessary to place the
zero of the compensation network (fVZ) around the
crossover frequency so that 45 phase margin is
[STEP-9] PFC Voltage Loop Design obtained. Then, the capacitor CVC1 is determined as:
Since FAN480X employs line feed-forward, the power GMV  I BOUT  K MAX 2.5
CVC1   (41)
stage transfer function becomes independent of the line 5  CBOUT  (2 fVC ) 2
VBOUT
voltage. Then, the low-frequency, small-signal, control-to-
To place the compensation zero at the crossover
output transfer function is obtained as:
frequency, the compensation resistor is obtained as:
vˆBOUT I BOUT  K MAX 1
  (37) 1
vˆEA 5 sCBOUT RVC  (42)
2  fVC  CVC1
where:
vˆBOUT I BOUT  K MAX 1
  (38) (b) Place compensator high-frequency pole (fVP) at least
vˆEA 5 sCBOUT
a decade higher than fC to ensure that it does not
interfere with the phase margin of the voltage
Proportional and integration (PI) control with high- regulation loop at its crossover frequency. It should
frequency pole is typically used for compensation. The also be sufficiently lower than the switching
compensation zero (fVZ) introduces phase boost, while the frequency of the converter so noise can be effectively
high-frequency compensation pole (fVP) attenuates the attenuated. Then, the capacitor CVC2 is determined as:
switching ripple, as shown in Figure 18.
1
CVC 2  (43)
2  fVP  RVC

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 6/21/13 10
AN-8027

(Design Example) Setting the crossover frequency Once the core for the transformer is determined, the
as 22 Hz: minimum number of turns for the transformer primary-side
to avoid saturation is given by:
GMV  I BOUT  K MAX 2.5
CVC1  
5  CBOUT  (2 fVC ) VBOUT
2 VBOUT MIN DMAX
N P MIN  (44)
Ae f SW B
70 106  0.9 1.27 2.5
 6
  20nF where Ae is the cross sectional area of the core in m2, fSW is
5  270 10  (2  22) 387
2
the switching frequency, and B is the maximum flux
1 1 density swing in Tesla for normal operation. B is
RVC    362k  typically 0.2-0.3 T for most power ferrite cores in the case
2  fVC  CVC1 2  22  20 109
of a forward converter.
Setting the pole of the compensator at 120 Hz: The turn ratio between the primary-side and secondary-
1 1 side winding for the first output is determined by:
CVC 2    3.7nF N V MIN
DMAX
2  fVP  RVC 2 120  362 103 n  P  BOUT (45)
N S1 (VO1  VF 1 )
where VF is the diode forward-voltage drop.
[STEP-10] Transformer Design for PWM
Stage Next, determine the proper integer for NS1 resulting in Np
larger than Npmin. Once the number of turns of the first
Figure 19 shows the typical secondary-side circuit of
output is determined, the number of turns of other output
forward converter for multi-output of PC power
(n-th output) can be determined by:
application.
VO ( n )  VF ( n )
A common technique for winding multiple outputs with N S (n)   N S1 (46)
the same polarity sharing a common ground is to stack the VO1  VF 1
secondary windings instead of winding each output
winding separately. This approach improves the load
regulation of the stacked outputs. The winding NS1 in The golden ratio between the secondary-side windings for
Figure 19 must be sized to accommodate its output current, the best regulation of 3.3 V, 5 V, and 12 V is known as
plus the current of the output (+12 V) stacked on top of it. 2:3:7.
To get tight regulation of 3.3 V output, magnetic amplifier (Design Example) The minimum PFC output voltage
(MAG-AMP) is used. The saturable core of MAG-AMP is 310 V and the maximum duty cycle of PWM
prevents the diode DREC from fully conducting by controller is 50%. By adding 5% margin to the
introducing high impedance until it is saturated. This maximum duty cycle, DMAX=0.45 is used for
allows the effective duty cycle of VREC to be controlled to transformer design. Assuming ERL35 (Ae=107 mm2)
be regulated the output voltage. core is used and B=0.28, the minimum turns for the
Additiona transformer primary side is obtained as:
l LC filter
VBOUT MIN DMAX 310  0.45
N P MIN    72
+12V
Ae f SW B 107 106  65 103  0.28
NS
2
The turns ratio for 5 V output is obtained as:
N P VBOUT MIN DMAX 310  0.45
Additiona n    25.6
Np NS l LC filter
+5V
NS (VO  VF ) (5  0.45)
1

The number of turns for the primary-side winding is

determined as:
MAG MAG AMP
AMP Control N p  n  NS1  2  25.6  51.2  N P MIN
+3.3
V
N p  n  N S1  3  25.6  76.8  N P MIN  N S1  3
DREC
+ Additiona
VREC l LC filter Then, the turns ratio for 12-V output is obtained as:
-
VO 2  VF 2 12  0.7
NS 2   N S1   3  6.99  7
VO1  VF 1 5  0.45

-12V
Therefore, the number of turns for each winding is
Additiona
NS
l LC filter
obtained as:
3
Np=78, NS1=3, NS2=7 (3+4 stack) and NS3=7.

Figure 19. Typical Secondary-Side Circuit

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 6/21/13 11
AN-8027

[STEP-11] Coupled Inductor Design for the
PWM Stage
When the forward converter has more than one output, as
shown in Figure 20, coupled inductors are usually employed
to improve the cross regulation and to reduce the ripple.
They are implemented by winding their separate coils on a
single, common core. The turns ratio should be the same as
the transformer turns ratio of the two outputs as:
One way to understand the operation of coupled inductor is
to normalize the outputs to one output. Figure 21 shows
how to normalize the second output (VO2) to the first
output (VO1). The transformer and inductor turns are
divided by NS2/NS1, the voltage and current are adjusted by
NS2/NS1. It is assumed that the leakage inductances of the
coupled inductor are much smaller than the magnetizing
inductance and evenly distributed for each winding.

NS 2 NL2 The inductor value of the first output can be obtained by:
 (47) VO1 (VO1  VF 1 )
N S1 N L1 L1   (1  DMIN )
I (48)
f SW ( PO1  PO 2 ) SUM
I SUM
L2
where:
MIN
NL2 V
N DMIN  DMAX BOUT
p N S2 VO2 VBOUT
(49)
PO1  PO 2
I SUM 
VO1

NL1 Then, the ripple current for each output is given as:
I O1 I SUM 1
L1   (50)
I O1 2 I O1
N S1
I O 2 I SUM N S1 1
VO1    (51)
IO 2 2 N S 2 IO 2

Figure 20. Coupled Inductor (Design Example) The minimum duty cycle of
PWM stage at nominal input (PFC output) voltage is:
D1 L1 VO1
VBOUT MIN 310
DMIN  DMAX  0.45  0.36
IO1 VBOUT 389
VPOUT  N S 1
NP
The sum of two normalize output current is:
0
PO1  PO 2 243
D2 VO2 I SUM    48.6 A
VO1 5
L2 IO2
VPOUT  N S 2
Assuming 16% p-p ripple current in LSUM, the inductor
NP
for the first output is obtained as:
0
VO1 (VO1  VF 1 )
L1   (1  DMIN )
I
VO 2 N 
N S1
VO 2  VO1 f SW ( PO1  PO 2 ) SUM
NS 2 I SUM
Normalized
IO 2 N 
NS 2 5(5  0.45)
IO 2   (1  0.36)  6.9uH
N S1 65  103 (5  9  12 16.5)  0.16
ISUM LM LLK D1 VO1

IO2
Then, the ripple current for each output is given as:
VPOUT  N S 1 I O1 I SUM 1 48.6  0.16 1
NP      43%
I O1 2 IO1 2 9
0

D2N VO2N
I O 2 I SUM N S1 1 48.6  0.16 3 1
       10%
LLK IO2N IO 2 2 N S 2 IO 2 2 7 16.5

Figure 21. Normalized Coupled Inductor Circuit

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 6/21/13 12
AN-8027

[STEP-12] PWM Ramp Circuit Design [STEP-13] Feedback Compensation Design

For voltage-mode operation, the RAMP pin can be for PWM Stage
connected to a DC voltage through a resistor. When it is Figure 21 shows the typical cross-regulation compensation
connected to the input of forward converter, ramp signal circuit configuration for multi-output converters. The
slope is automatically adjusted according to the input small-signal characteristics of the compensation network is
voltage providing line feed-forward operation. However, it given as:
can cause more power dissipation in the resistor. For better vFBPWM
efficiency and lower standby power consumption, it is
RB 1  s / CZ 1 1  s / CZ 2 (53)
recommended to connect the RAMP pin to the VREF pin.  ( vO1  vO 2 )
1  s / CP ROS1 RD CF s ROS 2 RD CF s

VREF
where:
1
RRAMP 1.5V PWM
CP 
- ( RB1 // RB 2 )CB
CRAMP RAMP + 1
CZ 1  (54)
RF CF
1
CZ 2 
( RF  ROS 2 )CF
FBPWM

VO2 VO1
VREF
ROS1
RB1 RD ROS2
Figure 22. Ramp Generation Circuit for PWM
FBPWM

It is typical to use 470 pF~1 nF capacitor on the RAMP RF CF

pin and to have the peak of the ramp signal around 2~3 V.
RB
The peak of the ram voltage is given as:
1 VREF 1 KA431
VRAMP PK    (52) CB ROS3
CRAMP RRAMP 2 f SW

(Design Example) Selecting CRAMP and RRAMP as 1 nF

and 22 kΩ, the PWM ramp voltage is obtained as: Figure 23. Feedback Compensation Circuit for
1 V 1 PWM Stage
VRAMP PK   REF 
CRAMP RRAMP 2 f SW The small signal equivalent circuit for control-to-output
1 7.5 1 transfer function of the PWM power stage can be simplified
 9
   2.6V as shown in Figure 24. The transfer function is fourth-order
110 22 10 2  65 103
3
system because additional LC filters are used to meet the
output voltage ripple specification. Therefore, it is
recommended to use engineering software, such as PSPICE
or Mathlab®, to design the feedback loop.
N S1
VBOUT  LM LLK LL12 VO1
NS 2

CO11 CO12 RL1

1
VRAMP VO2N VO2

LLK L22N
VFBPWM
CO21N CO22N
RL2N

NS1:NS2

Figure 24. Simplified Small Signal Equivalent Circuit for

Control-to-Output Transfer Function

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 6/21/13 13
AN-8027

Design Summary
Application Output Power Input Voltage Output Voltage / Output Current
ATX Power 300 W 85~264 VAC 12 V / 16.5 A; 5 V / 9 A; -12 V / 0.8 A; 3.3 V / 13.5 A

Features
 Meets 80+ specification
 FAN480X is fully pin-to-pin compatible with ML4800 and FAN4800 (needs a few parts modified)
 Switch-charge technique of gain modulator can provide better PF and lower THD
 Leading and trailing modulation technique for reduce output ripple
 Protections: OVP (Over-Voltage Protection), UVP (Under-Voltage Protection), OLP (Open-Loop Protection), and
maximum current limit

1.8uH
F1 L BOOST DBOOST VBOUT FYPF2006DN L 11 L1
2
Vo1 12V
AC BYC10600 DR1 CO11
FDA18N50 FCP11N60 CO12
Input CBOOST R FB1
CIF1 DR1 DF1 2200uF 1000uF
Q1 2M
Q2
5 270uF FR157
RCS1 DR2 L22 2uH
10 k Vo2 5V
0.1 L2 CO21 CO22
1
D1 100 nF FCP11N60 DF2 1000uF
D2 2200uF

STPS60L45CW
FR157
10 k Q3
R RAMP DR2 SF34DG
Vo3 -12V
22k L3
1
220uF
CO31
RLF2
0.13nF CIC2 RCS2 L43 3.3V
Vo4
R IAC 17k 4nF L4
2M L4 CO21
RLF1 1 2
RRMS1 6M RIC CIC1 DF2 CO22
RT
53nF IEA VEA
6.9 k
CRMS1 200 K FBPFC FR157
IAC 10
RRMS2 RB 7.5k
ISENSE VREF 362k
V D 1k
VD
VRMS D
200n D RVC FR157
36 k CLF1 C 3.7nF 300
F SS SS OPFC 3.4 k
CRMS2 R FBPWM
RMS3 OPWM
10 CVC2 1.2 k
RT/CT GND 20nF Vo1 1uF 10 k
CT
RAMP ILIMIT CVC1 RD 12V
1nF 5.45 k
FAN480X 32.4 k
1nF 12.9k
CRAMP RFB2 CF RF ROS1
0.47nF
100 11 k 5V
CB CFB
nF
Vo2
CLF2 CDD CREF ROS2
4.64 k
ROS3

Figure 25. Final Schematic of Design Example

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 6/21/13 14
AN-8027

Margin Tape Margin Tape

3 13
3mm 3mm
N1 N3
2 8,9 Mylar Tape 3T
N5
N5 Mylar Tape 1T
N2 N4
Mylar Tape 1T
6,7 10,11,12 N3
Mylar Tape 1T
N2
N4 Mylar Tape 3T
14 N1
Pin 1 BOBBIN-ERL35
Figure 26. Forward Converter Transformer Structure

Winding Specification
No Pin (s-f) Wire Turns Winding Method
N1 3-2 0.6Ф 37 Ts Solenoid Winding
Insulation: Mylar Tape t = 0.03 mm, 3 Layers
Copper-Foil Width
N2 8,9-10,11,12 Copper-Foil 10 mil 3 Ts
18 mm
Insulation: Mylar Tape t = 0.03 mm, 1 Layers
N3 13-8,9 1.0Ф*4 4 Ts Solenoid Winding
Insulation: Mylar Tape t = 0.03 mm, 1 Layers
N4 10,11,12-14 0.4Ф 6 Ts Solenoid Winding
Insulation: Mylar Tape t = 0.03 mm, 1 Layers
N5 2-6,7 0.6Ф 37 Ts Solenoid Winding
Insulation: Mylar Tape t = 0.03 mm, 3 Layers
Core-ERL35
Insulation: Mylar Tape t = 0.03 mm, 3 Layers
Insulation: Copper-Foil Tape t = 0.05 mm-pin1 Open Loop
Insulation: Mylar Tape t = 0.03 mm, 3 Layers

Core: ERL35 (Ae=107 mm2)

Bobbin: ERL35
Inductance: 13 mH

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 6/21/13 15
AN-8027

Appendix A
FAN480X Series Comparison Table of Relevant Parameters

FAN4800 New Generation New Generation New Generation New Generation

FAN4800AX FAN4800CX FAN4801S FAN4802S
VDD Maximum Rating 20 V 30 V
VDD OVP 17.9 V / Clamp 28 / Auto-Recover
VCC UVLO 10 V / 13 V 9.3 / 11 V
Two-Level PFC
NO NO YES
Output
PFC Soft-Start NO YES
Brownout NO YES
PFC：PWM
1：1 1：1 1：2 1：1 1：2
Frequency
Frequency Range 68 kHz~81 kHz 50 kHz~75 kHz
Gate Clamp NO 16 V
PFC Multiplier Traditional Switching Charge
VINOK 2.25 V / 1.1 V 2.40 V / 1.15 V
PWM Maximum Duty 42%~49% 49.5%~50%
Startup Current 100 μA 30 μA
Soft-Start Current 20 μA 10 μA
PWM Comparator
1.0 V 1.5 V
Level Shift
RAC 1~2 MΩ 5~8 MΩ

MOSFET and Diode Reference Specification

PFC MOSFETs
Voltage Rating Part Number
500 V FQP13N50C, FQPF13N50C, FDP18N50, FDPF18N50, FDA18N50, FDP20N50(T), FDPF20N50(T)
FCP11N60, FCPF11N60, FCP16N60, FCPF16N60, FCP20N60S, FCPF20N60S, FCA20N60S,
600 V
FCP20N60, FCPF20N60
Boost Diodes
600 V FFP08H60S, FFPF10H60S, FFP08S60S, FPF08S60SN, BYC10600
PWM MOSFETs
FQP/PF9N50C, FQPF9N50C, FQP13N50C, FQPF13N50C, FQA13N50C, FDP18N50, FDPF18N50,
500 V
FDP20N50(T), FDPF20N50(T)
FCP11N60, FCPF11N60, FCP16N60, FCPF16N60, FCA16N60, FCP20N60S, FCPF20N60S,
600 V
FCA20N60S, FCP20N60, FCPF20N60, FCA20N60

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 6/21/13 16
AN-8027

References
FAN480X — PFC/Forward PWM Controller Combo (FAN4800, FAN4801, FAN4802)
AN-6004 — 500 W Power Factor Corrected (PFC) Design with FAN4810
AN-6032 — FAN4800 Combo Controller Applications
AN-42030 — Theory and Application of the ML4821 Average Current Mode PFC Controller
AN-42009 — ML4824 Combo Controller Applications
ATX 300W 80+ Evaluation Board of FAN4800A+SG6520+FSQ0170

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF
THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE
UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in significant injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 6/21/13 17
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