Republic of Iraq

Ministry of Higher Education

And Scientific Research
Foundation of Technical Education
Technical College / Mosul

FPGA Based Three-Phase Sinusoidal PWM Control for Voltage

Source Inverter Fed IM

A Thesis Submitted to the Council of Technical College / Mosul as a Partial

Fulfillment of the Requirements for the Technical Master Degree in Electrical
Power Technology Engineering

By

Ahmed M. T. Ibraheem

Supervisor Supervisor
Dr. Abdul Kareem Z. Mansoor Dr. Nasseer M. Basheer
Assistant Professor Lecturer

2010 A.D. 1431 A.H.

 ‫ﺟﻤﻬﻮﺭﻳﺔ ﺍﻟﻌﺮﺍﻕ‬
‫ﻭﺯﺍﺭﺓ ﺍﻟﺘﻌﻠﻴﻢ ﺍﻟﻌﺎﻟﻲ ﻭﺍﻟﺒﺤﺚ ﺍﻟﻌﻠﻤﻲ‬
‫ﻫﻴﺌﺔ ﺍﻟﺘﻌﻠﻴﻢ ﺍﻟﺘﻘﻨﻲ‬
‫ﺍﻟﻜﻠﻴﺔ ﺍﻟﺘﻘﻨﻴﺔ ‪ /‬ﺍﻟﻤﻮﺻﻞ‬

‫ﺍﺳﺘﺨﺪﺍﻡ ﻣﺼﻔﻮﻓﺔ ﺍﻟﺒﻮﺍﺑﺎﺕ ﺍﻟﻤﺒﺮﻣﺠﺔ ﺣﻘﻠﻴﺎ ﻟﻠﺴﻴﻄﺮﺓ ﻋﻠﻰ ﻋﺎﻛﺲ ﻓﻮﻟﺘﻴﺔ‬

‫ﺛﻼﺛﻲ ﺍﻟﻄﻮﺭ ﻋﻦ ﻃﺮﻳﻖ ﺗﻀﻤﻴﻦ ﻋﺮﺽ ﺍﻟﻨﺒﻀﺔ ﺍﻟﺠﻴﺒﻲ ﻟﺘﻐﺬﻳﺔ ﻣﺤﺮﻙ ﺣﺜﻲ‬

‫ﺭﺳﺎﻟﺔ ﻣﻘﺪﻣﺔ ﺇﻟﻰ ﻣﺠﻠﺲ ﺍﻟﻜﻠﻴﺔ ﺍﻟﺘﻘﻨﻴﺔ ‪ /‬ﺍﻟﻤﻮﺻﻞ‬

‫ﻭﻫﻲ ﺟﺰء ﻣﻦ ﻣﺘﻄﻠﺒﺎﺕ ﻧﻴﻞ ﺩﺭﺟﺔ ﺍﻟﻤﺎﺟﺴﺘﻴﺮ ﺍﻟﺘﻘﻨﻲ ﻓﻲ ﺍﺧﺘﺼﺎﺹ‬
‫ﺗﻘﻨﻴﺎﺕ ﻫﻨﺪﺳﺔ ﺍﻟﻘﺪﺭﺓ ﺍﻟﻜﻬﺮﺑﺎﺋﻴﺔ‬

‫ﻣﻦ ﻗﺒﻞ ﺍﻟﻄﺎﻟﺐ‬

‫ﺃﺣﻤﺪ ﻣﺤﻤﺪ ﺗﻮﻓﻴﻖ ﺇﺑﺮﺍﻫﻴﻢ‬

‫ﺑﺈﺷﺮﺍﻑ‬

‫ﺩ‪ .‬ﻧﺼﻴﺮ ﻣﻴﺴﺮ ﺑﺸﻴﺮ‬ ‫ﺩ‪ .‬ﻋﺒﺪ ﺍﻟﻜﺮﻳﻢ ﺯﻭﺑﻊ ﻣﻨﺼﻮﺭ‬

‫ﻣﺪﺭﺱ‬ ‫ﺃﺳﺘﺎﺫ ﻣﺴﺎﻋﺪ‬

‫ﻣﻴﻼﺩﻱ‬ ‫ﻫﺠﺮﻱ‬
 ABSTRACT

This thesis presents a design and practical implementation of a

Field Programmable Gate Array (FPGA) based Sinusoidal Pulse Width
Modulation (SPWM) for a three-phase inverter to control the speed of a
three-phase Induction Motor (IM). The control is achieved via varying the
stator voltage, and varying the stator voltage and frequency with V/F
control method. The inverter is employed as a Voltage Source Inverter
(VSI). The FPGA is used to generate the appropriate PWM signals for the
inverter switches. The proposed control schemes have been realized and
implemented on the Spartan-3E Starter kit. The FPGA programme was
carried out using hardware description language VHDL and Xilinx-ISE
9.2i design software.
As compared with conventional digital PWM techniques, the
proposed methods offer several advantages: easy digital design, minimal
scaling of digital circuits, reconfigurability, flexibility in adaptation, and
direct hardware implementation. In addition to FPGA,
MATLAB/SIMULINK software was used for simulation and verification
of the proposed circuit performance. The simulation results have been
compared with the experimental results obtained from hardware circuit.
Simulation and experimental results show that both are in a close
agreement.
 ‫ﺍﻟﺨﻼﺻﺔ‬

‫ﻓﻲ ﻫﺬﻩ ﺍﻟﺮﺳﺎﻟﺔ ﺗﻢ ﺗﺼﻤﻴﻢ ﻭﺑﻨﺎء ﺩﺍﺋﺮﺓ ﻋﻤﻠﻴﺔ ﻟﻌﺎﻛﺲ ﻓﻮﻟﺘﻴﺔ ﺛﻼﺛﻲ ﺍﻟﻄﻮﺭ ﻭﺗﻤﺖ ﺍﻟﺴﻴﻄﺮﺓ‬

‫ﻋﻠﻴﻪ ﻣﻦ ﺧﻼﻝ ﻣﺼﻔﻮﻓﺔ ﺍﻟﺒﻮﺍﺑﺎﺕ ﺍﻟﻤﺒﺮﻣﺠﺔ ﺣﻘﻠﻴﺎ‪ .‬ﺗﻢ ﺍﺳﺘﺨﺪﺍﻡ ﺗﻘﻨﻴﺔ ﺗﻀﻤﻴﻦ ﻋﺮﺽ ﺍﻟﻨﺒﻀﺔ ﺃﻟﺠﻴﺒﻲ‬

‫)‪ (SPWM‬ﻟﻠﺴﻴﻄﺮﺓ ﻋﻠﻰ ﻣﺤﺮﻙ ﺣﺜﻲ ﺛﻼﺛﻲ ﺍﻟﻄﻮﺭ‪ .‬ﻫﺬﻩ ﺍﻟﺴﻴﻄﺮﺓ ﺗﻌﺘﻤﺪ ﻋﻠﻰ ﺗﻐﻴﻴﺮ ﺍﻟﺠﻬﺪ ﺍﻟﺪﺍﺧﻞ‬

‫ﻟﻠﻌﻀﻮ ﺍﻟﺜﺎﺑﺖ ﺍﻟﺨﺎﺹ ﺑﺎﻟﻤﺤﺮﻙ‪ ،‬ﻭﻋﻦ ﻃﺮﻳﻖ ﺗﻐﻴﻴﺮ ﺍﻟﺠﻬﺪ ﻭ ﺍﻟﺘﺮﺩﺩ ﺍﻟﺪﺍﺧﻞ ﻟﻠﻌﻀﻮ ﺍﻟﺜﺎﺑﺖ ﺍﻟﺨﺎﺹ‬

‫ﻹﺷﺎﺭﺍﺕ ﺗﻀﻤﻴﻦ ﻋﺮﺽ ﺍﻟﻨﺒﻀﺔ‬ ‫ﺑﺎﻟﻤﺤﺮﻙ‪ .‬ﺍﺳﺘﺨﺪﻣﺖ ﻣﺼﻔﻮﻓﺔ ﺍﻟﺒﻮﺍﺑﺎﺕ ﺍﻟﻤﺒﺮﻣﺠﺔ ﺣﻘﻠﻴﺎ ﻛﻤﻮﻟﺪ‬

‫ﻓﻲ ﻫﺬﺍ ﺍﻟﺒﺤﺚ‬ ‫ﺍﻟﻼﺯﻣﺔ ﻟﺘﺸﻐﻴﻞ ﻣﻔﺎﺗﻴﺢ ﻋﺎﻛﺲ ﺍﻟﻔﻮﻟﺘﻴﺔ‪ .‬ﺗﻢ ﺗﻤﺜﻴﻞ ﻭﺗﺤﻘﻴﻖ ﻃﺮﻕ ﺍﻟﺴﻴﻄﺮﺓ ﺍﻟﻤﻘﺘﺮﺣﺔ‬

‫‪ Xilinx‬ﻣﻦ ﻧﻮﻉ ‪Spartan-3E Starter‬‬ ‫ﺑﺎﺳﺘﺨﺪﺍﻡ ﻣﺼﻔﻮﻓﺔ ﺍﻟﺒﻮﺍﺑﺎﺕ ﺍﻟﻤﺒﺮﻣﺠﺔ ﺣﻘﻠﻴﺎ ﻣﻦ ﻋﺎﺋﻠﺔ‬

‫‪ .kit‬ﺗﻢ ﺍﺳﺘﺨﺪﺍﻡ ﻟﻐﺔ ﻭﺻﻒ ﺍﻟﻜﻴﺎﻧﺎﺕ ﺍﻟﻤﺎﺩﻳﺔ ) ‪ (VHDL‬ﻟﺒﺮﻣﺠﺔ ﻣﺼﻔﻮﻓﺔ ﺍﻟﺒﻮﺍﺑﺎﺕ ﺍﻟﻤﺒﺮﻣﺠﺔ ﺣﻘﻠﻴﺎ‬

‫ﻣﻊ ﺑﺮﻧﺎﻣﺞ ﺍﻟﻤﺤﺎﻛﺎﺓ ‪ ISE 9.2i‬ﺍﻟﻤﺰﻭﺩﺓ ﻣﻦ ﺷﺮﻛﺔ ‪.Xilinx‬‬

‫ﻣﻘﺎﺭﻧﺔ ﺑﺘﻘﻨﻴﺎﺕ ﺗﻀﻤﻴﻦ ﻋﺮﺽ ﺍﻟﻨﺒﻀﺔ ﺍﻟﺮﻗﻤﻴﺔ ﺍﻷﺧﺮﻯ‪ ،‬ﺗﻘﺪﻡ ﺍﻟﻄﺮﻳﻘﺔ ﺍﻟﻤﻘﺘﺮﺣﺔ ﻋﺪﺓ ﻓﻮﺍﺋﺪ‬

‫ﻣﻨﻬﺎ‪ :‬ﺍﻟﺘﺼﻤﻴﻢ ﺍﻟﺮﻗﻤﻲ ﺍﻟﺴﻬﻞ‪ ،‬ﺍﺳﺘﺨﺪﺍﻡ ﺃﻗﻞ ﻣﺎ ﻳﻤﻜﻦ ﻣﻦ ﺍﻟﺪﻭﺍﺋﺮ ﺍﻟﺮﻗﻤﻴﺔ‪ ،‬ﻗﺎﺑﻠﻴﺔ ﺇﻋﺎﺩﺓ ﺍﻟﺘﻬﻴﺌﺔ‪ ،‬ﻣﺮﻭﻧﺔ‬

‫ﻓﻲ ﺍﻟﺘﻜﻴﻒ‪ ،‬ﻭﺍﻟﺘﻄﺒﻴﻖ ﺍﻟﻌﻤﻠﻲ ﺍﻟﻤﺒﺎﺷﺮ‪ .‬ﺑﺎﻹﺿﺎﻓﺔ ﺇﻟﻰ ﻣﺼﻔﻮﻓﺔ ﺍﻟﺒﻮﺍﺑﺎﺕ ﺍﻟﻤﺒﺮﻣﺠﺔ ﺣﻘﻠﻴﺎ‪ ،‬ﺗﻢ ﺍﺳﺘﺨﺪﺍﻡ‬

‫ﺑﺮﻧﺎﻣﺞ ‪ MATLAB/SIMULINK‬ﻟﻠﻤﺤﺎﻛﺎﺓ ﻭﺍﻟﺘﺤﻘﻖ ﻣﻦ ﺍﻟﺪﺍﺋﺮﺓ ﺍﻟﻤﻘﺘﺮﺣﺔ‪ .‬ﺗﻢ ﻣﻘﺎﺭﻧﺔ ﺍﻟﻨﺘﺎﺋﺞ‬

‫ﺍﻟﺘﻲ ﺗﻢ ﺍﻟﺤﺼﻮﻝ ﻋﻠﻴﻬﺎ ﻣﻦ ﺍﻟﻤﺤﺎﻛﺎﺓ ﻣﻊ ﺍﻟﺘﻲ ﺗﻢ ﺍﻟﺤﺼﻮﻝ ﻋﻠﻴﻬﺎ ﻣﻦ ﺍﻟﻨﻤﻮﺫﺝ ﺍﻟﻌﻤﻠﻲ‪ .‬ﺃﻭﺿﺤﺖ‬

‫ﺍﻟﻤﻘﺎﺭﻧﺔ ﺑﺎﻥ ﺍﻟﻨﺘﺎﺋﺞ ﻣﺘﻘﺎﺭﺑﺔ ﺟﺪﺍ‪.‬‬

 I
CONTENTS

Title Page

Contents
0B I
List of Figures IV
0T

List of Tables VII

0T

List of Abbreviations VIII

0T

List of Symbols Х
CHAPTER ONE: INTRODUCTION
1B 1
1-1: Preface 1
1-2: Literature Survey 2
1-3: Aim of the Work 5
1-4: The Scope of the Thesis 6
CHAPTER TWO:THEORETICAL BACKGROUND 7
2-1: Three-Phase Voltage Source Inverter (VSI) 7
2-2: PWM Techniques 8
2-2-1: Sinusoidal Pulse Width Modulation 9
2-2-2: Third-Harmonic Injection PWM (THIPWM) 11
2-2-3: 60-Degree PWM 12
2-2-4: Space Vector Modulation 13
2-3: Three-Phase SPWM Harmonic Analysis 13
2-4: Induction Motor (IM) 15
2-5: Induction Motor Drive 15
2-5-1: Stator Voltage Control 16
2-5-2: Frequency Control 17
2-5-3: Voltage and Frequency Control 18
2-6: Field Programmable Gate Array 21
2-7: Spartan-3E FPGA Family 22
2-8: Spartan-3E XC3S500E Architecture 22
2-9: FPGA Design Advantage 26
II

Title Page

2-10: FPGA Design Flow 27

2-11: Hardware Description Language 30
CHAPTER THREE: PROPOSED ARCHITECTURES TO
31
GENERATE PWM VIA FPGA
3-1: Preface 31
3-2: FPGA based SPWM Control Architectures 31
3-2-1: FPGA Based SPWM Control Scheme for Variable
32
Voltage Control
3-2-1-1: Three-Phase Sine Wave Generator Module 33
3-2-1-2: Triangular Wave Generator Module 37
3-2-1-3: Modulation Index Control Module Digital 39
3-2-1-4: Three-Digital Comparators Module 41
3-2-1-5: Dead Time Module 43
3-2-2: FPGA Based SPWM Control Scheme for VVVF
45
using V/F control Strategy
3-2-2-1: Three-Phase Sine Wave Generator Module 46
3-2-2-2: V/F Control Module 47
CHAPTER FOUR: HARDWARE CONSTRUCTION OF
49
THE AC DRIVE SYSTEM AND THE RESULTS
4-1: Hardware Configuration 49
4-1-1: FPGA As PWM Generator 49
4-1-2: Gate Drive Circuit 51
4-1-2-1: Buffer Circuit 52
4-1-2-2: Optocoupler Circuit 52
4-1-2-3: Matching Circuit 52
4-1-3: Three-Phase Bridge Inverter 53
4-1-4: Three-Phase Transformer 55
4-1-5: Three-Phase Induction Motor 55
 III

Title Page

4-2: Simulation via MATLAB/SIMULINK 56

4-3: Waveforms of the SPWM Signals 57
4-4: Dead Time Results 60
4-5: Results of the FPGA based SPWM Control Scheme for
61
Variable Voltage Control
4-6: FFT Analysis 68
4-7: Results of the FPGA based SPWM Control Scheme for
71
VVVF Using V/F Control Strategy
CHAPTER FIVE: CONCLUSIONS AND FUTURE WORK 76
5-1: Conclusions 76
5-2: Future Work 78
References 79
IV
LIST OF FIGURES

Figure Page
Figure Title
No. No.

2.1 Three-phase bridge inverter circuit 7

2.2 Sinusoidal PWM for three-phase inverter 10
2.3 Third-harmonic injection PWM 12
2.4 60-Degree PWM 12
2.5 Equivalent circuit of IM 16
Torque/speed characteristics with variable stator
2.6 17
voltage
2.7 Torque/speed characteristics with frequency control 18
2.8 Voltage frequency relationship 19
2.9 Torque/speed characteristics with constant V/F ratio 20
2.10 Voltage source induction motor drive 20
2.11 Spartan-3E family architecture 22
2.12 CLB locations 23
2.13 Arrangement of Slices within the CLB 23
2.14 Block diagram of the FPGA design flow 27
2.15 iMPACT programming succeeded 29
3.1 Illustration of sampling process 32
FPGA based SPWM control scheme for variable
3.2 33
voltage control
3.3 Sine/Cosine schematic symbol 34
3.4 Sine schematic symbol 35
3.5 Three-phase sine wave generator module 36
3.6 Modulation index adjustment 39
3.7 Modulation index control module 40
3.8 Circuit diagram of the two external switches 40
 V
Waveform of the Multiplication process of the ISE
3.9 41
simulator
3.10 Three-digital comparators module 42
3.11 Generation of PWM pulses 42
Waveform of the comparison process of the ISE
3.12 43
simulator
3.13 Block diagram of dead time module 44
3.14 FPGA based SPWM control scheme for VVVF control 46
Block diagram for the proposed practical AC drive
4.1 49
system
4.2 Expansion headers 50
4.3 FPGA connections to the J2 accessory header 50

4.4 FPGA connections to the J4 accessory header 51

4.5 Gate drive circuit 51

4.6 Practical gate drive circuit 53

4.7 Three-phase bridge inverter circuit 54

4.8 Practical circuit of three-phase bridge inverter 54

4.9 Experimental setup 55

4.10 Simulation of the SPWM three-phase VSI fed IM 56

Results of the gate switching signals for modulation
index (m i = 0.875) and carrier frequency (f carrier =
R R R R

4.11 58
1050Hz): (a) ISE simulator, (b) Simulation, and (c)
Experimental
Results of the gate switching signals for modulation
index (m i = 0.875) and carrier frequency (f carrier =
R R R R

4.12 59
1950Hz) : (a) ISE simulator, (b) Simulation, and (c)
Experimental
VI

Results of dead-time control circuit:(a) ISE simulator,

4.13 60
and (b) Experimental
Results of the line-to-line output voltage waveforms at
4.14 modulation index (m i = 0.1875) and carrier frequency
R R 62
(f carrier =1050Hz) :(a) Simulation, and (b) Experimental
R R

Results of the line-to-line output voltage waveforms at

4.15 modulation index (m i = 0.875) and carrier frequency
R R 63
(f carrier = 1050 Hz) :(a) Simulation, and (b) Experimental
R R

Results of the line-to-line output voltage waveforms at

4.16 modulation index (m i = 0.1875) and carrier frequency
R R 64
(f carrier =1950 Hz) :(a) Simulation, and (b) Experimental
R R

Results of the line-to-line output voltage waveforms at

4.17 modulation index (m i = 0.875) and carrier frequency
R R 65
(f carrier =1950 Hz) :(a) Simulation, and (b) Experimental
R R

Results of the stator current waveform at modulation

4.18 index (m i = 0.9375) and carrier frequency (f carrier
R R R R 66
=1050 Hz) :(a) Simulation, and (b) Experimental
Results of the stator current waveform at modulation
4.19 index (m i = 0.9375) and carrier frequency (f carrier
R R R R 67
=1950 Hz) :(a) Simulation, and (b) Experimental
FFT analysis for frequency order at (m i = 1) and at
R R

4.20 :(a) Carrier frequency (f carrier =1050 Hz), (b) (f carrier

R R R 68
R =1950 Hz)
4.21 Harmonic profile of SPWM 70
Experimental results of the line-to-line output voltage
4.22 73
waveform of the inverter for VVVF using V/F control
Experimental results of the stator current waveform of
4.23 75
the IM for VVVF using V/F control
 VII
LIST OF TABLES

No. of Table Name of Table Page

2.1 Valid switch states for a three-phase VSI 13

2.2 DFS signals 25
2.3 Status Logic Signals 26
Device utilization summary of the FPGA based
3.1
SPWM control for variable voltage control 45
Device utilization summary of the FPGA Based
3.2 SPWM Control Scheme for VVVF using V/F 48
control strategy
4.1
2B Results of the open loop V/F control of the IM 71
VIII
LIST OF ABBREVIATIONS

Abbreviation Description

AC Alternating Current
ASIC Application Specific Integrated Circuit
BJT Bipolar Junction Transistor
CLB Configurable Logic Block
DC Direct Current
DCM Digital Clock Manager

DFS Digital Frequency Synthesizer

DLL Delay Locked Loop

DSP Digital Signal Processor
FFT Fast Fourier transform
FPGA Field Programmable Gate Array
HDL Hardware Description Language
IC Integrated Circuit
IEEE Institute of Electrical and Electronic Engineers
IGBT Insulated Gate Bipolar Transistor
IM Induction Motor

IOB Input Output Block

IP Intellectual Property
ISE Integrated Software Environment
LED Light Emitting Diode
LUT Look Up Table
MATLAB MATrix LABoratory program
MOSFET Metal-Oxide Semiconductor Field-Effect Transistor
PS Phase Shifter
PV Photovoltaic
RAM Random Access Memory
 IX

RMS
20B Root Mean Square
ROM Read Only Memory

SVM
21B
Space Vector Modulation
THD
2B Total Harmonic Distortion
THIPWM
23B
Third-Harmonic Injection PWM

TTL
24B
Transistor Transistor Logic

UCF
25B User Constraints File
VHDL VHSIC Hardware Description Language

VHSIC
26B Very High Speed Integrated Circuit
VSI Voltage Source Inverter
VVVF
27B
Variable Voltage Variable Frequency
X
LIST OF SYMBOLS

Symbol Description

Ac
29B Peak value of the triangular carrier wave
30B

Ar
31B Peak value of the sinusoidal reference wave
32B

CLKFX
3B Clock frequency which obtained from DFS unit of the DCM
34B

f Supply frequency
fcarrier Carrier waveform frequency
fclock Main system frequency of the FPGA
fclk
35B Clock frequency
freference
36B Reference waveform frequency
h
37B Harmonic order
Ls Stator inductance
𝐿𝐿𝑟𝑟 ′ Rotor inductance referred to the stator
Lm Magnetizing inductance
m Theta width
mf Frequency modulation ratio
mi
38B Modulation index
n Bit size of the up/down counter
p Number of poles of IM
r Bit size of the sine wave
𝑅𝑅𝑠𝑠 Per phase resistance of the stator winding of the IM
𝑅𝑅 𝑟𝑟 ′ Rotor resistance referred to the stator
S Slip of the motor
𝑇𝑇𝑑𝑑 Torque developed
Vcr
39B carrier signal
VDC
40B DC input voltage
41B

Vs Stator supply voltage

 XI
Van , Vbn,
Phase-voltages
Vcn
Vra,Vrb,
Reference waveform phases
Vrc
Vab, Vbc,
Line-voltages
Vca
VGS(TH) Gate threshold voltage
w Angular velocity
𝑋𝑋𝑠𝑠 Per phase leakage reactance of the stator winding of the IM
𝑋𝑋𝑟𝑟 ′ Rotor reactance referred to the stator
∅ Stator flux
𝜔𝜔𝑠𝑠 Synchronous speed
 1

CHAPTER ONE
INTRODUCTION

1-1: Preface
U

Advance in power electronics has led to an increased interest in

three-phase Voltage Source Inverters (VSIs) with Pulse Width Modulation
(PWM) control[1]. There are various kinds of PWM techniques available
such as sinusoidal PWM, Third-Harmonic Injection PWM (THIPWM), 60-
Degree PWM, current tracking PWM, Space Vector Modulation(SVM),
and others[2]. All these techniques aim at generating a sinusoidal inverter
output voltage without low-order harmonics. The most widely used in
industrial applications are the sinusoidal PWM and space vector PWM [1].
Most PWM techniques are carried out using analog circuits or modern
digital control circuits, such as microprocessors, microcontrollers, Digital
Signal Processors (DSPs), or Application Specific Integrated Circuits
(ASICs), where reprogramming of the carrier frequency and reference
frequency are possible[1,2].
Microprocessor based control schemes have the advantage of
flexibility, higher reliability and lower cost, but the demanding control
requirements of modern power conditioning systems will overload most of
the general purpose microprocessors and the computing speed of
microprocessor limits the use of microprocessor in complex algorithms.
DSPs and Microcontrollers are used for digital control applications. But
DSPs and Microcontrollers can no longer keep pace with the new
generation of applications that requires higher performance and more
flexible without increasing cost and resources. Further microprocessors,
Microcontrollers, and DSPs are sequential machines that mean tasks are
executed sequentially which takes longer processing time to accomplish the
same task. The high speed hard wired logic can enhance the computation
capability. The ASIC based technology provides a rapid and low cost
2

solution for special applications with large market. Owing to the progress
of technology, the life cycle of most modern electronic products become
shorter than their design cycle. The emergence of FPGA has drawn much
attention due to its shorter design cycle, lower cost and higher density. The
simplicity and programmability of FPGA make it the most favorable choice
for prototyping digital systems[3]. For this reason, in the work the FPGA is
used as a sinusoidal PWM generator for the signals driving the three-phase
VSI. A three-phase VSI based on sinusoidal PWM make it possible to
control magnitude of the voltage applied to a motor, and to control both
the frequency and magnitude of the voltage applied to a motor with
constant V/F control method in open loop mode.
The work in this thesis is divided into three parts: FPGA as a
controller card, power electronics part (DC-to-AC converter), and
machines part (induction motor).

1-2: Literature Survey

U

Field programmable gate array based digital controller for power

electronic applications was a very popular choice in the last few years,
there are many published researches on this approach:
Saad Mekhilef and N. A. Rahim (2002) have proposed an analysis and
practical implementation of the regular (symmetric, asymmetric) sampled
three-phase PWM inverter waveform. Xilinx FPGA XC4008E was used
for the generation the three-phase PWM signals. Simulation and
experimental results confirmed that the harmonic distortion of the output
current waveform of the inverter fed to the grid was within the stipulated
limits laid down by the utility companies. This made the inverter
configuration highly suitable for grid connected Photovoltaic (PV)
application[4].
 3

Zhaoyong Zhou et al (2004) have proposed a design and implementation

of an FPGA based three-phase sinusoidal PWM (SPWM) Variable
Voltage Variable Frequency (VVVF) controller with constant V/F ratio.
The FPGA based SPWM was designed using Verilog HDL Programming
language and compiled and simulated in the environment of Altera
MAXplus II software. The proposed SPWM scheme was then implemented
on an ALRERA FLEX10K100E-208 FPGA, which used about 3000 logic
cells. The basis of the proposed scheme was a modified single-edge
sinusoidal PWM technology developed from synchronized asymmetric
regular sampled method and dual-edge modulation principle.
The controller can give a fundamental frequency output up to 2kHz or
more, and its switching frequency can be set to 30kHz[5].

Andrew Vareed and Avilesh Pranish (2004) have designed and

constructed an FPGA based sine wave push-pull inverter with Root Mean
Square (RMS) control to ensure that the voltage does not drop, and Total
Harmonic Distortion (THD) minimization to ensure the output waveform is
a clean signal, where the waveform distortion is at minimum. The
Flex10k70RC240-4 FPGA sub-system was used to generate a train of
PWM pulses that is supplied to the power stage module. In the power stage,
the pulses are amplified and used to drive two switches that control voltage
through a centre-tapped transformer. The transformer output is then filtered
using a power filter and the AC voltage is delivered to the load. The main
advantage of the push-pull inverter was that no more than one switch in
series conducts at any time[6].

N. Praveen Kumar et al (2006) have proposed a design and

implementation of an open loop V/F induction motor drive in a developed
platform. Complete experimental hardware was used for testing the
proposed control scheme, this consists of a squirrel cage induction motor
fed by a three-phase voltage source inverter. A sine-triangle based PWM
4

technique was employed for running the inverter, ALTERA

EP1C2Q240C8 FPGA based control platform was used for
implementation the control strategy[7].

M. N. Md Isa et al (2007) used an FPGA to generate sinusoidal pulse

width modulation (SPWM) signals. The switching pulses requirements
(number of pulses, switching time, duty cycle generation and dead time ) of
the single-phase inverter based unipolar PWM technique were
predetermined and then implemented using VHDL programming and then
realized using FPGA Altera Max Plus II simulation tools. The
predetermined and pre-calculated switching parameters; frequency,
amplitude and duty cycle before being tested on the FPGA board means
that the modulation index cannot be varied in real time[8].

Ali. M. Eltamaly (2007) has proposed a digital speed control strategy for
three-phase induction motor. This strategy depended on varying the stator
voltage to control the speed of an induction motor. The system consisted of
six bidirectional switches. The digital control strategy used a saw-tooth
waveform with twice the supply frequency as a control signal to be
compared with triangular waveform as a carrier signal. The voltage output
from AC voltage regulator was controlled by varying the voltage level of
the saw-tooth waveform. The simulation of the system was carried out by
Powersim (PSIM) computer program. The control strategy was
implemented by using FPGA. The simulation and experimental results
showed stable operation for wide range of speed control[9].

Kariyappa B. S. and M. Uttara Kumari (2008) have proposed a Xilinx

FPGA based speed control of AC servomotor using sinusoidal PWM
technique. FPGA was used to generate (50 Hz) sine wave, the triangular
wave and the sinusoidal PWM signals. The FPGA based SPWM was
designed using VHDL Programming language. The frequency, amplitude
 5

of sine wave and sinusoidal PWM were verified using Modelsim

simulation tool. The proposed control scheme was realized using Xilinx
FPGA SPARTAN XC3S400 and tested using Alternating Current (AC)
servomotor[3].

Nitish Patel and Udaya Madawala (2008) have proposed a novel bit-
stream based of a constant V/F scalar controller technique for induction
machines. The technique was ideally suited for FPGA or Application
Specific Integrated Circuits (ASIC) implementation. The digital circuits
have been simulated using VHDL within Modelsim and synthesized on a
Stratix FPGA using Altera’s Quartus tool chain. The inverter drive was a
standard power stage consisting of six N channel MOSFETs[10].

S. N. SINGH and A.K. SINGH (2009) have proposed a solar inverter,

where the input DC power stored in the battery bank obtained through
Photovoltaic (PV) and/or grid sources. A centre-tap inverter topology was
configured to generate AC output voltage. The semiconductor power
switches were used to produce a multilevel three output voltage state: day
time (under high and low insolation, night hour (under no insolation), and
under low battery condition (less than 50%) during day or night hour. The
FPGA technology was used to generate PWM pulses for the solar inverter
using VHDL programming language. The VHDL code was downloaded in
FPGA Spartan-3E starter kit to produce base drive signals for inverter
power device switches[11].

1-3: Aim of the Work

U

The main purpose of the present work is design and implement an

experimental setup of a three-phase bridge inverter based on Xilinx FPGA
as a controller kit to control the speed of a three-phase IM.
6

1-4: The Scope of the Thesis

U

The thesis consists of five chapters, and are organized as follows:

Chapter One covered the introduction and literature survey. Chapter Two
gives the theoretical background for the voltage source inverter (VSI),
types of PWM techniques, induction motor drive, FPGA and its advantage,
architecture of Spartan-3E family, and HDL. Chapter Three describes the
proposed architectures design of the SPWM in Xilinx FPGA, this chapter
also develops some of the ISE simulation results of the VHDL design of
PWM in Xilinx FPGA. Chapter Four describes the details of the major
parts that are utilized in the hardware circuit, simulation of sinusoidal
PWM three-phase inverter feeding IM via MATLAB/SIMULINK, and the
MATLAB/SIMULINK simulation and experimental results. The last
chapter concludes the work result and suggests future work possibilities.
 7

CHAPTER TWO
THEORETICAL BACKGROUND

2-1: Three-Phase Voltage Source Inverter

DC-to-AC converters are known as inverters. The function of an
inverter is to change a DC input voltage to a symmetrical AC output
voltage of desired magnitude and frequency. The output voltage could be
fixed or variable at fixed or variable frequency[12].
The inverters can be operated by controlled turn-on and turn-off
semiconductor devices such as Bipolar Junction Transistors (BJTs), power
Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs),
Insulated Gate Bipolar Transistors (IGBTs) and others. Inverters are widely
used in industrial applications (e.g. induction motor drive, induction
heating, standby power supply, and uninterruptible power supplies). The
VSI can be further divided into a single-phase inverter and a three-phase
inverter. The three-phase VSIs are normally used for high-power
applications and widely used for AC motor drives. A three-phase inverter is
considered as three single-phase inverters and the output of each single-
phase inverter is shifted by (120°), the diagram of the power circuit of a
three-phase VSI is shown in Fig.(2.1)[12,13].

D1 D3 D5
S1 S3 S5

VDC A
B
C
S4 D4 D6 D2
S6 S2

Fig.(2.1): Three-phase bridge inverter circuit

8

The circuit has a bridge topology with three leg branches (A, B, and
C), each consisting of two power switches. The input DC supply VDC is
usually obtained from a single-phase or three-phase utility power supply
through a diode bridge rectifier and LC or C filter. For an inductive load,
the load current in each phase remains positive after the voltage in that
phase became negative, i.e. after the top switch has been turned off. The
load current then flows through the antiparallel diode of the bottom switch,
returning power to the DC link. The same happens of course when the
bottom switch is turned off and the load current flows through the
antiparallel diode of the top switch[13].
A certain switching algorithm can be applied to each of the six
switch modules S1, S2, S3, S4, S5, and S6 in order to control the inverter to

generate the desired sinusoidal output with the desired frequency and
magnitude. Among the practical switching schemes, pulse width
modulation (PWM) is classical and most widely used. It will be discussed
in detail in the following sections[12].

2-2: PWM Techniques

U

Because an inverter contains power switches, it is possible to

control the output voltage as well as optimize the harmonics by performing
multiple switching within the inverter with the constant DC input voltage
VDC. The most common switching technique is called Pulse Width
Modulation (PWM) which involves applying voltages to the gates of the
power switches at different times for varying durations to produce the
desired output waveform[13].
There are various PWM techniques used for the three-phase VSI,
includes; following are some of them:
 9

2-2-1: Sinusoidal Pulse Width Modulation:

The sinusoidal PWM technique is very popular for industrial
converters. The generation of gating signals with sinusoidal PWM is shown
in Fig.(2.2). There are three reference sine waves (Vra, Vrb, and Vrc) each
shifted by 120° at the desired output frequency (freference).
A triangular carrier wave (Vcr) is compared with the reference
signal corresponding to a phase to generate the gating signals for that
phase. Comparing the carrier signal (Vcr) with the reference phases (Vra,
Vrb, and Vrc) produces (g1, g3, and g5) respectively. Where (g1, g3, and
g5) are the gating signals applied to switches (S1, S3, and S5) respectively

of the three-phase bridge inverter[12].

The principle of SPWM can be summarized as follows:

When Vra > Vcr ; S1 on & S4 off

When Vrb > Vcr ; S3 on & S6 off

When Vrc > Vcr ; S5 on & S2 off

Upper and lower switches of the same leg should not be switched
on at the same time. This will prevent the DC bus supply from being
shorted. A dead time is given between switching off the upper switch and
switching on the lower switch and vice versa, as will be explained in next
chapter[13].
The instantaneous line-to-line output voltages of the three-phase
bridge inverter can be expressed as follows:
Vab = VDC (g1 – g3) ………………… (2.1)
Vbc = VDC (g3 – g5) ………………… (2.2)
Vca = VDC (g5 – g1) ………………… (2.3)
10

Vcr Vra Vrb Vrc

Ac --
Ar --

2π
g1

2π
g4

2π
g3

2π
g6

2π
g5

2π
g2

Vab
VDC

-VDC
2π
Vbc
VDC

-VDC
2π
Vca
VDC

-VDC
2π

Fig.(2.2): Sinusoidal PWM for three-phase inverter

 11

Because the maximum amplitude of the fundamental phase voltage

in the linear region (mi ≤ 1) is VDC/2, the maximum amplitude of the
fundamental AC output line voltage is[12]:
Vab1 = √3 VDC /2 ………………… (2.4)
Therefore, one can write the peak amplitude as
V DC
Vab1 = 𝑚𝑚𝑖𝑖 √3 for 0 < mi ≤ 1 ………………… (2.5)
2

Where :
mi is the modulation index ratio, defined as the ratio of the
amplitude of the reference and carrier signals and is given by
𝐴𝐴𝑟𝑟
mi = ………………… (2.6)
Ac

Ar is the peak value of the three sine reference wave, and

Ac is the peak value of the triangular carrier wave.
Ideally, mi can be varied between 0 and 1 to give linear relation
between the modulating and output wave [13].
The frequency modulation ratio (mf) is defined as the ratio of the
frequencies of the triangular carrier wave and the reference signals which is
written as[12,13]:
𝑓𝑓carrier
𝑚𝑚𝑓𝑓 = ………………… (2.7)
𝑓𝑓 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟

Where; 𝑓𝑓carrier = carrier waveform frequency, and

𝑓𝑓𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 = reference waveform frequency.

2-2-2: Third-Harmonic Injection PWM :

The THIPWM is implemented in same manner as sinusoidal PWM.
The difference is that the reference AC waveform (modulating signal) is
non-sinusoidal but consists of both a fundamental component and a third
harmonic component as shown in Fig.(2.3)[14].
The modulating signal (Vr) is given by:
Vr = 1.15 sin (ωt) + 0.19 sin (3 ωt) 0 ≤ ωt ≤ 2π ..……… (2.8)
12

1.5
Fundamental waveform
1
Modulating waveform
0.5

-0.5
Injected waveform

-1

-1.5
π 2π

Fig.(2.3): Third-harmonic injection PWM

The result is flat-topped waveform and reduced amount of over
modulation. It provides a higher fundamental amplitude and low distortion
of the output voltage[14].

2-2-3: 60-Degree PWM:

The idea behind 60° PWM is the "flat top" the waveform from 60°
to 120° and 240° to 300° as shown in Fig.(2.4). The power devices are held
on for one-third of the cycle and have reduce the switching losses. All
triple harmonics (3rd, 9th, 15th, 21st, 27th, etc.) are absent in the three-phase
voltages[12].
1.5
Fundamental waveform
1

Modulating waveform
0.5

-0.5
Triple harmonics
-1

-1.5
0
π 2π
Fig.(2.4): 60-Degree PWM
 13

2-2-4: Space Vector Modulation:

The SVM is a digital modulating technique in which the objective
is to generate PWM load line voltages that are on average equal to given
load line voltages. This is done in each sampling period by properly
selecting the switch states from the valid ones of the VSI (Table 2.1) and
by proper calculation of the period of times they are used. The selection
and calculation times are based upon the SV transformation[15].

Table (2.1):Valid switch states for a three-phase VSI

State Space vector

State No. Vbc Vbc Vca
S1, S2, and S6 are on and
S4, S5, and S3 are off 1 VDC 0 -VDC V1 = 1 + j0.577
S2, S3, and S1 are on and
S5, S6, and S4 are off 2 0 VDC -VDC V2 = j1.155
S3, S4, and S2 are on and
S6, S1, and S5 are off 3 -VDC VDC 0 V3 = −1 + j0.577
S4, S5, and S3 are on and
S1, S2, and S6 are off 4 -VDC 0 VDC V4 = −1 − j0.577
S6, and S4 are on and
S2, S3, and S1 are off 5 0 -VDC VDC V5 = −j1.155
S6, S1, and S5 are on and
S3, S4, and S2 are off 6 VDC -VDC 0 V6 = 1 − j0.577
S1, S3, and S5 are on and
S4, S6, and S2 are off 7 0 0 0 V7 = 0
S4, S6, and S2 are on and
S1, S3, and S5 are off 8 0 0 0 V8 = 0

2-3: Three-Phase SPWM Harmonic Analysis

Inverter operation at high carrier frequency is better than at low
carrier frequency where the harmonic components could be shifted to high
order. However at high frequency more switching stress and power losses
occur in the devices especially in the three devices controlled bridge
topology[4].
14

In order to use a single carrier signal and preserve the features of

the PWM technique, the normalized carrier frequency (mf) should be odd
multiple of three. Thus, all phase-voltage (Van, Vbn, and Vcn) are identical,
but 120° out of phase without even harmonics; moreover, harmonics at
frequencies multiple of three are identical in amplitude and phase in all
phases[15].
For instance, if the ninth harmonic voltage in phase (a) is
𝑉𝑉𝑎𝑎𝑎𝑎 9 (𝑡𝑡) = 𝑉𝑉9 sin(9𝑤𝑤𝑤𝑤) ………………… (2.9)
The corresponding ninth harmonics in phase (b) will be,
𝑉𝑉𝑏𝑏𝑏𝑏 9 (𝑡𝑡) = 𝑉𝑉9 sin�9(𝑤𝑤𝑤𝑤 − 120°)� = 𝑉𝑉9 sin(9𝑤𝑤𝑤𝑤 − 1080°) = 𝑉𝑉9 sin(9𝑤𝑤𝑤𝑤)
……………… (2.10)
Thus, the AC output line voltage ( Vab = Van – Vbn ) doesn't contain
the ninth harmonic. Therefore, for odd multiples of three times the
normalized carrier frequency (mf), the harmonics in the AC output voltage
appear at normalized frequencies fh centred around mf and its multiples,
specifically, at[12,15]
ℎ = 𝑗𝑗𝑚𝑚𝑓𝑓 ± 𝑘𝑘 ………………… (2.11)
Where 𝑗𝑗= 1, 3, 5, . . . for 𝑘𝑘 = 2, 4, 6, . . . ; and 𝑗𝑗= 2, 4, . . . for 𝑘𝑘= 1,
5, 7, ..., such that ℎ is not a multiple of three. Therefore, the harmonics are
at 𝑚𝑚𝑓𝑓 ± 2, 𝑚𝑚𝑓𝑓 ± 4… , 2𝑚𝑚𝑓𝑓 ± 1, 2𝑚𝑚𝑓𝑓 ± 5 , … , 3𝑚𝑚𝑓𝑓 ± 2, 3𝑚𝑚𝑓𝑓 ± 4…,
4𝑚𝑚𝑓𝑓 ± 1, 4𝑚𝑚𝑓𝑓 ± 5, … For nearly sinusoidal AC load current, the
harmonics in the DC link current are at frequencies given by
ℎ = 𝑗𝑗𝑚𝑚𝑓𝑓 ± 𝑘𝑘 ± 1 ………………… (2.12)
where 𝑗𝑗 = 0, 2, 4, . . . for 𝑘𝑘 = 1, 5, 7, . . .; and 𝑗𝑗 = 1, 3, 5, . . . for 𝑘𝑘 = 2, 4, 6,
. . . , such that ℎ = 𝑗𝑗𝑚𝑚𝑓𝑓 ± 𝑘𝑘 is positive and not a multiple of three[15].
The values of carrier frequencies in our application is (1050Hz,
1950Hz) led to make value of the mf equal to odd multiple of three.
 15

2-4: Induction Motor

Three-phase IMs are the most common motors used in industrial
motion control systems. Low-cost, simple and rugged design, and low
maintenance are the main advantages of induction motors. Due to that,
these motors are often called the workhorse of the motion industry. IMs
are classified either as squirrel cage or wound-rotor motors, almost 90% of
the three-phase IMs is squirrel cage motor (widely type of induction motors
used in industry). This is because the squirrel cage rotor has a simple and
rugged construction[16].

2-5: Induction Motor Drive

AC motor drives are widely used to control the speed of conveyor
systems, blower speeds, pump speeds, machine tool speeds, and other
applications that require variable speed with variable torque[17].
The control and estimation of AC drives in general are
considerably more complex than those of DC drives, and this complexity
increases substantially if high performances are demanded. The main
reasons for this complexity are the need of variable-frequency harmonically
optimum converter power supplies, the complex dynamics of AC
machines, machine parameter variations, and the difficulties of processing
feedback signals in the presence of harmonics[13]. Power electronic
devices known as motor drives are used to operate AC induction motors at
frequencies other than that of the supply. Drives consist of two main
sections, a controller to set the gating signals and a three-phase inverter to
generate the required sinusoidal three-phase system from a DC bus voltage.
There are various methods used to control the induction motor
torque and speed; following are some of them:
16

2-5-1: Stator Voltage Control:

Equation (2.13) indicates that the torque developed (𝑇𝑇𝑑𝑑 ) by the
motor is proportional to the square of the stator supply voltage (Vs), the
reduction/augmentation in operating the speed of an IM can be achieved by
reducing/ augmenting the stator supply voltage[18].
3 𝑅𝑅 𝑟𝑟′ 𝑉𝑉𝑠𝑠 2
𝑇𝑇𝑑𝑑 = 𝑅𝑅 ′ 2 2
…………………………(2.13)
𝑠𝑠 𝜔𝜔 𝑠𝑠 [�𝑅𝑅𝑠𝑠 + 𝑟𝑟 � + � 𝑋𝑋𝑠𝑠 + 𝑋𝑋 𝑟𝑟 ′ � ]
𝑠𝑠

Where:
𝑅𝑅𝑠𝑠 , 𝑋𝑋𝑠𝑠 are the per phase resistance and leakage reactance of the
stator winding as shown in the equivalent circuit of induction
motor in Fig.(2.5).
𝑅𝑅 𝑟𝑟 ′ , 𝑋𝑋𝑟𝑟 ′ are the rotor resistance and reactance referred to the stator
s is the slip of the motor
𝜔𝜔 𝑠𝑠 −𝜔𝜔 𝑚𝑚
𝑠𝑠 = ………………………..(2.14)
𝜔𝜔 𝑠𝑠

𝜔𝜔𝑠𝑠 is the synchronous angular speed

2 𝑤𝑤
𝜔𝜔𝑠𝑠 = .……………………..(2.15)
𝑝𝑝

𝑤𝑤 is the angular speed

𝑤𝑤 = 2𝜋𝜋𝜋𝜋 .……………………..(2.16)
𝑝𝑝 is the number of poles of IM
𝑓𝑓 is the supply frequency
ω𝑚𝑚 is the angular rotor speed.

Fig.(2.5): Equivalent circuit of IM

 17

Fig.(2.6) shows the torque/speed characteristics for various values

of stator supply voltage (Vs)[18].

Vs1> Vs2> Vs3 Vs1

Vs2

Vs3

Fig.(2.6): Torque/speed characteristics with variable stator voltage

The stator voltage can be varied by one of the following methods:

(1) AC voltage controllers, (2) voltage-fed variable DC-link inverters, or
(3) Pulse Width Modulation (PWM) inverters[12]. Stator voltage control is
a simple control method (eliminates the complex circuitry of the adjustable
frequency schemes) but it is not suitable for a constant load torque and is
normally used for applications requiring low starting torque and narrow
range of speed (to achieve an appreciable change in speed a relatively large
change in the applied voltage is required) at relatively low slip[12,18].

2-5-2: Frequency Control:

The torque and speed of induction motor can be controlled by
changing the supply frequency.
𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣(𝑉𝑉𝑠𝑠 ) = [𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓(∅)] ∗ [𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣(𝑤𝑤)]
𝑉𝑉𝑠𝑠
∅ = ……………………..(2.17)
𝑤𝑤

At rated voltage and rated frequency, the flux has rated value.
18

If the voltage is maintained fixed at its rated value while the

frequency is reduced below its rated value, the flux increases, thus any
reduction in the supply frequency without a change in the terminal voltage
causes an increase in the air-gap flux. Induction motors are designed to
operate at the knee point of the magnetization characteristics to make full
use of the magnetic material. Therefore the increase in flux will saturate the
motor. This will increase the magnetizing current, distort the line current
and voltage, increase the core loss and the stator copper loss, and produce a
high pitch accoustic noise, this type of frequency control is not normally
used [12,17].
If the frequency is increased above its rated value, the flux and
torque would decrease. The torque/speed characteristics of an induction
motor operates at five different frequencies higher than the rated value are
given in Fig.(2.7)[19].

Fig.(2.7): Torque/speed characteristics with frequency control

2-5-3: Voltage and Frequency Control:

Variable frequency control below the rated frequency is generally
carried out by reducing the machine phase voltage, along with the
frequency in such a manner that the flux is maintained constant. Above the
rated frequency, the motor is operated at a constant voltage because of the
limitation imposed by stator insulation or by supply voltage limitations as
 19

shown in Fig.(2.8). This type of control is usually known as volts/hertz

(V/F) control[12,17].

Voltage
V rate

F rate Frequency

Fig.(2.8): Voltage frequency relationship

The torque developed by the motor is directly proportional to the

magnetic field produced by the stator. So, the voltage applied to the stator
is directly proportional to the product of stator flux and angular velocity.
𝑉𝑉𝑠𝑠 = ∅ ∗ 𝑤𝑤
𝑉𝑉𝑠𝑠 = ∅ ∗ 2𝜋𝜋𝜋𝜋
𝑉𝑉𝑠𝑠
∅∝ �𝑓𝑓 ……………………..(2.18)

This makes the flux produced by the stator proportional to the ratio
of applied voltage and frequency of supply. By varying the frequency, the
speed of the motor can be varied. Therefore, by varying the voltage and
frequency at the same ratio, flux and hence, the torque can be kept constant
throughout the speed range. This method enables us to obtain a wide range
variation in the operating speed of an IM. The Torque/speed characteristics
of an induction motor at four different values of V/F ratio are given in
Fig.(2.9)[19].
20

Fig.(2.9): Torque/speed characteristics with constant V/F ratio

Three possible circuit arrangements for obtaining variable voltage

and frequency are shown in Fig.(2.10). In Fig.(2.10.a), the DC voltage
remains constant and the PWM techniques are applied to vary both voltage
and frequency within the inverter. In Fig.(2.10.b), the DC-DC converter
varies the DC voltage to the inverter and the inverter controls the
frequency. In Fig.(2.10.c), the DC voltage is varied by the dual converter
and frequency is controlled within the inverter[12].

Fig.(2.10): Voltage source induction motor drive

 21

2-6: Field Programmable Gate Array

U

FPGA, which is an acronym for Field Programmable Gate Array, is

a digital integrated circuit that can be programmed to do any type of digital
logic functions. FPGAs are programmed using a supporting software and a
download cable connected to computer. Once they are programmed, they
can be disconnected from the computer and will retain their functionality
until the power is removed from the chip. The FPGAs can be programmed
while they run, because they can be reprogrammed in the order of
microseconds[20]. Many manufacturers deliver FPGAs such as Quicklogic,
Altera, Atmel, Xilinx, etc.
Applications of FPGAs include industrial motor drives, real time
systems, medical imaging, speech recognition, home networking,
display/projection, and digital television equipment, cryptography,
computer hardware emulation and a growing range of other areas[19,21].
There are four benefits of FPGA technology[22]:
1. Performance: Taking advantage of hardware parallelism, FPGAs
exceed the computing power of DSPs by breaking the paradigm of
sequential execution and accomplishing more per clock cycle.
2. Time to market: FPGA technology offers flexibility and rapid
prototyping capabilities in the face of increased time-to-market
concerns. You can test an idea or concept and verify it in hardware
without going through the long fabrication process.
3. Reliability: While software tools provide the programming
environment, FPGA circuitry is truly a “hard” implementation of
program execution.
4. Long-term maintenance: As mentioned earlier, FPGA chips are
field-upgradable. Digital communication protocols, for example,
have specifications that can change over time. Being reconfigurable,
FPGA chips are able to keep up with future modifications that might
be necessary.
22

2-7: Spartan-3E FPGA Family

U

The Spartan™-3E family of FPGAs is specifically designed to

meet the needs of high volume, cost-sensitive consumer electronic
applications. The Spartan-3E family builds on the success of the earlier
Spartan-3 family by increasing the amount of logic per I/O, significantly
reducing the cost per logic cell. The five-member family (XC3S100E,
XC3S250E, XC3S500E, XC3S1200E, and XC3S1600E) offers densities
ranging from 100,000 to 1.6 million system gates[21]. In the work the
Xilinx Spartan-3E XC3S500E FPGA is used. The key features of the
Spartan-3E Starter Kit are available at the APPENDIX(A1),

2-8: Spartan-3E XC3S500E Architecture

U

The Spartan-3E XC3S500E architecture consists of five

fundamental programmable functional elements as shown in Fig.(2.11)[21]:

Fig.(2.11): Spartan-3E family architecture

1. Configurable Logic Blocks (CLBs) and Slice Resources:

The Configurable Logic Blocks (CLBs) constitute the main
logic resource for implementing synchronous as well as combinatorial
circuits. Each CLB contains four slices, and each slice contains two
Look-Up Tables (LUTs) to implement logic and two dedicated storage
elements that can be used as flip-flops or latches.
 23

The CLBs are arranged in a regular array of rows and columns

as shown in Fig. (2.12).

Fig.(2.12): CLB locations

Each CLB comprises four interconnected slices, as shown in Fig.

(2.13).

Fig.(2.13): Arrangement of Slices within the CLB

2. Input/Output Blocks (IOBs):

The Input/Output Block (IOB) provides a programmable,
unidirectional or bidirectional interface between a package pin and
the FPGA’s internal logic.
3. Block RAM:
Spartan-3E XC3S500E device incorporate 20 dedicated block
RAMs, which are organized as dual-port configurable 18 Kbit
blocks.
24

4. Dedicated Multipliers:
The Spartan-3E XC3S500E device provide 20 dedicated
multiplier blocks per device. Multiplier blocks accept two 18-bit
binary numbers as inputs and calculate the product. The multiplier
blocks primarily perform two’s complement numerical
multiplication. Each multiplier performs the principle operation P =
A × B, where 'A' and 'B' are 18-bit words in two’s complement form,
and 'P' is the full-precision 36-bit product, also in two’s complement
form.
5. Digital Clock Manager (DCM) Blocks:
The Spartan-3E XC3S500E device provide 4 DCMs. DCMs
provide flexible, complete control over clock frequency, phase shift
and skew. To accomplish this, the DCM employs a Delay-Locked
Loop (DLL), a fully digital control system that uses feedback to
maintain clock signal characteristics with a high degree of precision
despite normal variations in operating temperature and voltage. The
DCM supports three major functions:
• Clock-skew Elimination (delay locked loop).
• Frequency Synthesis (multiplication, and division).
• High-resolution Phase Shifting.
The DCM consists of four interrelated functional units:
A. Delay-Locked Loop (DLL): The most basic function of the DLL
component is to eliminate clock skew. The main signal path of the
DLL consists of an input stage, followed by a series of discrete
delay elements or steps, which in turn leads to an output stage.
This path together with logic for phase detection and control
forms a system complete with feedback. The DLL component has
two clock inputs, CLKIN and CLKFB, as well as seven clock
outputs, CLK0, CLK90, CLK180, CLK270, CLK2X,
CLK2X180, and CLKDV.
 25

B. Digital Frequency Synthesizer(DFS): The DFS unit generates

clock signals where the output frequency is a product of the
CLKIN input clock frequency and a ratio of two user-specified
integers. The CLKFX and CLKFX180 outputs in conjunction
with the CLKFX_MULTIPLY and CLKFX_DIVIDE attributes
provide a frequency synthesizer that can be any multiple or
division of CLKIN. The two dedicated outputs from the DFS unit,
CLKFX and CLKFX180, are defined in Table (2.2). This unit is
used in the work.

Table (2.2): DFS signals

Signal Direction Description

CLKFX Output Multiplies the CLKIN frequency by the

attribute-value ratio
(CLKFX_MULTIPLY/CLKFX_DIVIDE)
to generate a clock signal with a new target
frequency.
CLKFX180 Output Generates a clock signal with the same
frequency as CLKFX, but shifted 180° out-
of-phase.

C. Phase Shifter (PS): The DCM provides two approaches to

control the phase of a DCM clock output signal relative to the
CLKIN signal: First, eight of the nine DCM clock outputs –
CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180,
CLKFX, and CLKFX180 – provide either quadrant or half-period
phase shifting of the input clock. Second, the PS unit provides
additional fine phase shift control of all nine DCM outputs.
26

D. Status Logic: The Status Logic indicates the present state of the
DCM and a means to reset the DCM to its initial known state.
The Status Logic signals are described in Table (2.3).

Table (2.3): Status Logic Signals

Signal Direction Description

RST Input A High resets the entire DCM to its

initial power-on state. Initializes the
DLL taps for a delay of zero. Sets the
LOCKED output Low.
STATUS[7:0] Output The bit values on the STATUS bus
provide information regarding the state
of DLL and PS operation.
LOCKED Output Indicates that the CLKIN and CLKFB
signals are in phase by going High. The
two signals are out-of-phase when Low.

2-9: FPGA Design Advantage

U U

Some advantages of FPGA based design are listed below:

1. Lower Development Costs: FPGAs offer very low development
costs. Because of its re-programmability, it's easily and very
inexpensively to change designs. This allows optimizing designs and
continuing to add new features to enhance products[19].
2. Reduced Board Area: FPGAs offer a high level of integration and
are available in very small form factor packages. This provides the
perfect solution for designers whose products must fit into small
enclosures or have a limited amount of circuit board space to
implement the logic design[19].
3. Fast design to product time: Both the time for circuit development
and programming the FPGA device are short [23].
 27

4. Easy simulation and debugging: Software simulators and

debuggers provide efficient methods for finding bugs and estimating
performance[23].

2-10: FPGA Design Flow

The Integrated Software Environment (ISE) is the Xilinx design
software suite that allows to take the proposed design from design entry
through Xilinx device programming. The ISE Project Navigator manages
and processes the proposed design through the following steps in the ISE
design flow. Block diagram of the FPGA design flow is shown in Fig.
(2.14)[24].

Fig.(2.14): Block diagram of the FPGA design flow

1. Design Entry: Design entry is the first step in the ISE design flow.
During this step, the source files based on the proposed design objectives
is created. The top-level design file can be created by using a Hardware
Description Language (HDL), such as VHDL, Verilog, or using the
schematic approach.
28

2. Synthesis: After design entry and optional simulation, the synthesis step
should be run. During this step, VHDL, Verilog, or mixed language
designs become netlist files that are accepted as input to the
implementation step.
3. Implementation: Design implementation converts the logical design
into a physical file format that can be downloaded to the selected target
device. From Project Navigator, the implementation process can be run
in one step.
Design Implementation includes the following steps[25]:
• Translate (merges multiple design files to a single netlist).
• Map (maps the generic gates in the netlist to FPGAs logic cells
and IOBs and the ISE tool gives a report about the usage
hardware resources (Design Summary).
• Place and Route (derives the physical layout inside the FPGA
chip) in this process, all the components, signals and connections
are placed and routed in the FPGA package which gives a report
about the consumer hardware resources and errors.
4. Verification: Design verification is testing the functionality and
performance of the design. Design verification includes following
ways[24]:
• Simulation (functional and timing).
• Static timing analysis.
• In-circuit verification (In-circuit verification tests the circuit under
typical operating conditions).
5. Device Configuration: The last step is to generate the configuration file
and download this file from a host computer to the FPGA device to
configure the logic cells and switches[25]. The Spartan-3E Starter Kit
board supports a variety of FPGA configuration options[26]:
• Download FPGA designs directly to the Spartan-3E FPGA via

JTAG, using the onboard USB interface.

 29

• Program the on-board 4 Mbit Xilinx XCF04S serial Platform Flash

PROM, then configure the FPGA from the image stored in the
Platform Flash PROM using Master Serial mode.
• Program the on-board 16 Mbit ST Microelectronics SPI serial Flash

PROM, then configure the FPGA from the image stored in the SPI
serial Flash PROM using SPI mode.
• Program the on-board 128 Mbit Intel Strata Flash parallel NOR

Flash PROM, then configure the FPGA from the image stored in the
Flash PROM using BPI Up or BPI Down configuration modes.
In this work the first configuration option is used to download
the configuration file.
There are two tasks in this configuration option[26]:
1. Connecting the USB Cable: The Spartan-3E Starter Kit includes
embedded USB-based programming logic and an USB connector.
When the board is powered on, the Windows operating system
should recognize and install the associated driver software. When
the USB cable driver is successfully installed and the board is
correctly connected to the PC, a green LED lights up, indicating a
good connection.
2. Programming via iMPACT: After successfully compiling an
FPGA design using the Xilinx development software, the design
can be downloaded using the iMPACT programming software.
When the FPGA successfully programs, the iMPACT software
indicates success, as shown in Fig.(2.15).

Fig.(2.15): iMPACT programming succeeded

30

The FPGA application is now executing on the board and the

DONE pin LED lights up.

2-11: Hardware Description Language

U

A digital design can be created using schematic digital design editor

that uses graphic symbols of the circuit or by using Hardware Description
Languages (HDLs) such as VHDL, and Verilog[24].
VHDL is a hardware description language. It describes the behaviour
of an electronic circuit or system, from which the physical circuit or system
can then be attained (implemented). VHDL stands for VHSIC Hardware
Description Language. VHSIC is itself an abbreviation for Very High
Speed Integrated Circuits[27]. The key advantage of VHDL when used for
systems design is that it allows the behaviour of the required system to be
described (modelled) and verified (simulated) before synthesis tools
translate the design into real hardware (gates and wires)[20]. Once the
VHDL code has been written, it can be used either to implement the circuit
in a programmable device (from Altera, Xilinx, Atmel, etc.) or can be
submitted to a foundry for fabrication of an ASIC chip[27].
Some of the advantages of VHDL is given below[28]:
1. Standard format for design exchange.
2. Support for large as well as small designs.
3. Support for wide range of abstraction in modelling.
4. Simulation oriented (including for writing test bench).
5. Timing constructs.
 31
CHAPTER THREE
PROPOSED ARCHITECTURES TO GENERATE PWM VIA FPGA

3-1: Preface
To design the PWM signals generation using field programmable
gate arrays, first the functional description of the design is modelled in
VHDL using the behavioural, and structural abstraction level. Then this
VHDL code is synthesized and simulated using Xilinx synthesis and
simulation tools. After successfully synthesizing and simulating then the
design can be downloaded to the targeting device (FPGA).
This chapter discusses how the functional description is generated
and modelled in VHDL to generate the Sinusoidal Pulse Width Modulation
(SPWM) signals suitable for three-phase voltage source inverter.

3-2: FPGA based SPWM Control Architectures

For variable speed drive applications (control the speed of a three-
phase Induction Motor (IM)) the stator voltage and frequency should be
varied. Therefore, sinusoidal PWM technique is used to give ability for
varying the output voltage and frequency of the three-phase inverter. The
FPGA kit is used to implement this technique.
The principle of sinusoidal PWM is based on the comparison of an
analogue sine reference wave at the desired frequency with an analogue
triangular carrier wave to produce gating signals. The same switching
function can be obtained in digital manner by using FPGA as shown in this
chapter. Sampled sine reference wave is compared with sampled triangular
carrier wave at high repetition rates to obtain the required time resolution,
as shown in Fig.(3.1)[29].
 32

triangular wave (analogue)

Sine wave (analogue)

Sampled sine
wave

Sampled
triangular wave

Fig.(3.1): Illustration of sampling SPWM process

There are two adopted architectures for an FPGA based SPWM

implementation: (1) FPGA based SPWM control scheme for variable
voltage control, and (2) FPGA based SPWM control scheme for Variable
Voltage Variable Frequency (VVVF) using V/F control strategy.
All parts of the architectures design have been designed by using
VHDL language with support from Xilinx Intellectual Property (IP) cores
such as: Digital Clock Manager (DCM) using Xilinx Architecture Wizard,
and the Sine/Cosine Look-Up Table v5.0 using Xilinx Core Generator.

3-2-1: FPGA Based SPWM Control Scheme for Variable Voltage

Control:
The purpose of this architecture is to feed the IM with variable
stator voltage via varying the modulation index (mi) of the inverter.
The block diagram of this architecture is shown in Fig.(3.2). This scheme
consists of five major parts: (1) three-phase sine wave generator module to
produce reference modulating signal, (2) triangular wave generator module
to produce carrier wave signal, (3) modulation index control module, (4)
three-digital comparators module, and (5) dead time module. Each of these
five modules will be discussed individually subsections.
 33

(2) Triangular wave FPGA

generator module Kit
DCM/ Up/down Vcr
DFS counter (4) (5) PWMAU

Three digital Dead time PWMAL

comparators module PWMBU

PWMBL
module
Vra PWMCU
rst Vrb rst PWMCL
Vrc
fclock
50MHz
internal Multipliers External data

(1) Three-phase sine (3) Modulation

wave generator module index control
module

Fig.(3.2): FPGA based SPWM control scheme for variable voltage control

3-2-1-1: Three-Phase Sine Wave Generator Module:

The key of the proposed three-phase sine wave generator module
architecture takes the advantage of the Xilinx CORE Generator feature that
is available in ISE9.2i.
The sine wave generation is implemented via Sine/Cosine Look-Up
Table which has the following features[30]:
• User specified option for table value storage in distributed/block
memory
• Supports THETA input widths of 3 to 10 bits for Distributed ROM
and 3 to 16 bits for Block ROM
• Supports output Sine/Cosine widths of 4 to 32 bits
• Supports negative Sine/Cosine outputs
• Symmetric Output option uses an extra integer bit in the output so
that the effective range is -1.0 to +1.0
• For use with v6.2i or later of the Xilinx CORE Generator™ system.
 34
The Sin/Cosine schematic symbol is shown in Fig.(3.3).

Fig.(3.3): Sine/Cosine schematic symbol

The Sine/Cosine module accepts an unsigned input value THETA

and produces two’s complement outputs of SINE (THETA) and/or
COSINE (THETA). The user controls the input THETA width and output
SINE and /or COSINE width values[30].
Equation (3.1) defines the relationship between the integer input
angle THETA supplied to the core (refer to Fig.(3.3)) and the actual radian
angle (θ)[30].
2𝜋𝜋
𝜃𝜃 = THETA 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 ………...... (3.1)
2𝑚𝑚

Where : m is THETA width.

The core computes sin(θ) and cos(θ) and presents the two’s
complement on the output ports SINE and COSINE respectively. The
values for the sine and cosine wave are stored in an internal ROM[30].
In the work only the options (THETA, CLK, SINE) has been used,
and the other options of the Sine/Cosine module is not used, then the Sine
schematic symbol is shown in Fig.(3.4).
 35

Fig.(3.4): Sine schematic symbol

To generate a sine reference wave, the input data (THETA) in Sine

module will be integer, coming from a programmable up counter,
which will contain the different values of the discretized sine wave input
THETA (0 to 2π). To generate a three-phase sine reference waves (sine
out-a, sine out-b, and sine out-c), three separate Sine modules are used
with (120°) phase shift between each other. In order to adjust the three sine
reference waves frequency conveniently, a clock divider is used to divide
the main system frequency (fclock) which equals to 50 MHz to clock
frequency (fclk) which is used here. The reference frequency (freference) has a
relationship with the clock frequency (fclk) and the THETA width (m),
could be expressed as:
𝑓𝑓 𝑐𝑐𝑐𝑐𝑐𝑐
𝑓𝑓reference = ………...... (3.2)
2𝑚𝑚

The reference frequency (freference) has been decided to operate at

(50.0288 Hz) which is the nearest value to the wanted frequency value of
(50 Hz), the clock frequency (fclk) is (409.836 KHz) ((50 MHz) divided by
(122), and the THETA width (m = 13-bits).
To make a phase-shift of (120°) between the three outputs, the
THETA input of the second Sine module is forced to initialize after a delay
of one third of the period (sin(-120°) = sin(240°) = sin( 4π /3 )) of the
modulating signal by making the programmable up counter of this phase to
initialize with "1010101010101" as shown in the following equation.
 36
2π
4π /3 = THETA radians
213

4π /3 × 8192
THETA = = 5461 = 1010101010101
2π (d ) (bin)
The THETA input of the third Sine module (third phase) is forced
to initialize after a delay of two thirds of the period (sin(-240°) = sin(120°)
= sin( 2π /3 )) by making the programmable up counter of this phase
initialize with "0101010101011" as shown in the following equation.
2π
2π /3 = THETA radians
213

2π /3 × 8192
THETA = = 2731 = 0101010101011
2π (d ) (bin)
Fig.(3.5) shows the three-phase sine wave generator module.

Initial value 13-bits Theta

"0000000000000" Up
counter Sine
fclk rst sine out-a
module

rst fclk

"1010101010101"
Up Theta
counter
fclk rst Sine
module sine out-b
fclock CLK fclk
divider fclk
50MHz

"0101010101011" Up Theta
counter
fclk rst Sine
module sine out-c

fclk

Fig.(3.5): Three-phase sine wave generator module

 37
3-2-1-2: Triangular Wave Generator Module:
The triangular carrier wave is generated by using a programmable
up/down counter of (n) bits, which is incremented and decremented until
the maximum value and the minimum value of the triangular carrier wave
is reached respectively. Determination of the frequency of the triangular
carrier wave (carrier frequency) is the important part of the design process,
where the clock frequency needs to be calculated precisely because the
carrier frequency has a relationship with the clock frequency.
Then to adjust the clock frequency as required by the programmable
up/down counter the DCM function is used based on Digital Frequency
Synthesizer (DFS) unit. The Xilinx Architecture Wizard is used to
implement the DCM function.
The clock frequency which has been used for the generation of the
carrier frequency (for the programmable up/down counter) can be obtained
as the following equation:
𝐶𝐶𝐶𝐶𝐶𝐶𝐹𝐹𝐹𝐹 _𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀
𝐶𝐶𝐶𝐶𝐶𝐶𝐹𝐹𝐹𝐹 = 𝐶𝐶𝐶𝐶𝐶𝐶𝐼𝐼𝐼𝐼 ∗ ………...... (3.4)
𝐶𝐶𝐶𝐶𝐶𝐶𝐹𝐹𝐹𝐹 _𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷

Where:
𝐶𝐶𝐶𝐶𝐶𝐶𝐹𝐹𝐹𝐹 is the clock frequency which is obtained from digital
frequency synthesizer (DFS) unit of the digital clock
manager (DCM), and used for the generation of the
carrier frequency,
𝐶𝐶𝐶𝐶𝐶𝐶𝐼𝐼𝐼𝐼 is the DFS clock frequency input which is equal to the
system frequency ( f clock = 50 MHz),
𝐶𝐶𝐶𝐶𝐶𝐶𝐹𝐹𝐹𝐹_𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 is an integer ranging from 2 to 32, and
𝐶𝐶𝐶𝐶𝐶𝐶𝐹𝐹𝐹𝐹_𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 is an integer ranging from 1 to 32.
The carrier frequency (𝑓𝑓𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 ) has a relationship with the clock
frequency and the up/down counter state which can be expressed as:
𝐶𝐶𝐶𝐶𝐶𝐶𝐹𝐹𝐹𝐹
𝑓𝑓𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 = ………...... (3.5)
2(𝑛𝑛 +1) +1
 38
The peak amplitude of the triangular carrier wave (Ac) depends on
the bit size of the up/down counter (n), as shown in the equation (3.6)
below;
𝐴𝐴𝑐𝑐 = 2(𝑛𝑛 −1) − 1 ……...... (3.6)
The value of the frequency modulation ratio (mf) should be odd
multiple of three as mentioned in Chapter Two. Therefore, the values of
carrier frequency (1050 Hz, and 1950 Hz) are used to operate the three-
phase inverter.
• In the first selected carrier frequency, the DCM is used to multiply the
11
main clock frequency (50 MHz) by the ratio of ( ) via DFS unit to
4

generate (𝐶𝐶𝐶𝐶𝐶𝐶𝐹𝐹𝐹𝐹 ) equal to (137.5 MHz), then the carrier frequency

(fcarrier) can be calculated from equation (3.5) to be (1049.0337 Hz)
which is the nearest value to the wanted frequency value of (1050 Hz),
and the bit size of the up/down counter is (n = 16-bits).
• The DCM is used to multiply the main clock frequency (50 MHz) by
23
the ratio of ( ) via the DFS unit to generate (𝐶𝐶𝐶𝐶𝐶𝐶𝐹𝐹𝐹𝐹 ) equalling to
9

(127.7777778 MHz), then the second carrier frequency (fcarrier) equals

now to (1949.704408 Hz) which is the nearest value to the wanted
frequency value of (1950 Hz), and the bit size of the up/down counter
is (n = 15-bits).
The reason of choosing two values of carrier frequency is to study
the performance characteristics (voltage linearity, and harmonic distortion)
of a SPWM voltage source inverter at different switching frequencies.
 39
3-2-1-3: Modulation Index Control Module:
The ratio of amplitude of the sine reference wave (Ar), to the
triangular carrier wave (Ac) is known as the modulation index (mi), as
shown in equation (3.7)[12].
𝐴𝐴𝑟𝑟
mi = ………………… (3.7)
Ac

The amplitude of the triangular carrier wave (Ac) is generally kept

constant, then controlling the amplitude of the sine reference wave (Ar)
gives a variation of the modulation index for controlling the output voltage
of the three-phase voltage source inverter which is an input supply to the
induction motor as shown in Fig.(3.6)[2,29].
Increasing modulation index(mi)

Fig.(3.6): Modulation index adjustment

Three multipliers are used to multiply the values of the three sine
reference waves (sine out-a, sine out-b, and sine out-c) which are stored in
an internal block ROM (r = 10-bits) with the external data (multiply)
(ex = 6-bits) to get a variation in the sine reference wave amplitude
resulting in a variation of the modulation index as shown in Fig.(3.7). To
avoid the negative sign in the multiply then its bit size (ex) is increased by
one bit as a most significant bit (sign bit) and kept constant at logic '0' in
the VHDL code as shown in equations (3.8).
multiplicand = '0' " multiply" (ex =7-bits) ………………… (3.8)
 40

multiplicand

sine out-a
× Vra

sine out-b
× Vrb

sine out-c
× Vrc

Fig.(3.7): Modulation index control module

The peak value of the sine reference wave (Ar) depends on the
width bit (r) of the output of a three-phase sine reference waves (sine out-
a, sine out-b, and sine out-c), and the multiplicand as shown in equation
(3.9).
2𝑟𝑟
𝐴𝐴𝑟𝑟 = ∗ 𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚 ……...... (3.9)
4

Hence the sine wave width bit (r) and the multiplicand will determine the
modulation index of the SPWM. The value of the external data (ex = 6-bits)
can be adjusted by using six slide switches (four of them are the switches
already existing on the FPGA kit, and two switches added externally with
circuit diagram shown in Fig.(3.8)).
Voltage regulator
L7805CV
+
Vin Vout
External gnd
9V
+
- Voltage To
supply + 5V + 3.3V FPGA
divider
-

Fig.(3.8): Circuit diagram of the two external switches

Fig.(3.9) shows the multiplication process waveform as shown of

the ISE simulator.
 41

Fig.(3.9): Multiplication process waveform

3-2-1-4: Three-Digital Comparators Module:

The triangular carrier wave (Vcr) is to be compared with the
multiplied sine reference waves (Vra, Vrb, and Vrc) (output data from the
multipliers) by using a three-digital comparators as shown in Fig.(3.10).
 42

Vcr PWMAU
Digital
PWMAL
comparator
Vra

PWMBU
Digital
comparator PWMBL
Vrb

PWMCU
Digital
Vrc comparator PWMCL

Fig.(3.10): Three-digital comparators module

The digital comparator output is logic '1' if the value of the sine
reference wave is greater than the value of the triangular carrier wave;
otherwise its output is logic '0' as shown in Fig.(3.11). Each the
comparators outputs (PWMAU, PWMBU, PWMCU) are negated to produce
the complement signals (PWMAL, PWMBL, PWMCL) of each value to
trigger the lower power switches of the three-phase inverter.

Sine wave Triangular

wave

Resulting PWM
waveform

'1'
'0'

Fig.(3.11): Generation of PWM pulses

Fig.(3.12) shows the comparison process waveform as shown in the

ISE simulator.
 43

Fig.(3.12): Comparison process waveform

3-2-1-5: Dead Time Module:

In the design of inverters, it is necessary to include a "dead time" or
"Blanking time" in switching signals in order to avoid simultaneous
conduction of the devices on the same electrical trajectory or leg. The
turn-off time of power devices is usually longer than its turn-on time,
and, therefore an appropriate dead time must be inserted between the upper
and lower gating signals. The incorporation of the dead time provides a
safety zone, but it causes distortion of the output voltage and reduces its
magnitude[13,31].
The dead time for each leg was set to (4 μsec) as usually used in
these applications. The block diagram of dead time module is shown in
Fig.(3.13). The control over dead time is achieved by controlling the
divider value which is used to divide the main system clock (50 MHz).
Dead time module outputs are used to trigger the inverter switches. To get
dead time equal to (4 μsec) the main system clock (50 MHz) should be
divided by (200) to get clock frequency equal to (250 KHz).
 44

rst
fclock
50MHz
internal

rst

rst

Fig.(3.13): Block diagram of dead time module

Final note regarding architecture control design is that the reset (rst)
signal is used to force the PWM signals to be logic '0' at anytime. The reset
(rst) signal can be applied by using push-button switch which is already
existing on the FPGA kit.
The FPGA utilization summary of this proposed architecture design
is shown below in Table (3.1).
 45
Table (3.1): Device utilization summary of the FPGA based SPWM
control for variable voltage control

Logic Utilization Used Available Utilization

Number of Slices 243 4656 5%

Number of Slice Flip Flops 233 9312 2%
Number of 4 input LUTs 416 9312 4%
Number of bonded IOBs 14 232 6%
Number of BRAMs 3 20 15%
Number of MULT18*18SIOs 3 20 15%
Number of GCLKs 3 24 12%
Number of DCMs 1 4 25%

The User Constraints File (UCF) of the FPGA based SPWM control
for variable voltage control architecture that downloaded in the Xilinx
XC3S500E Spartan-3E FPGA is given in APPENDIX (A2).

3-2-2: FPGA Based SPWM Control Scheme for VVVF using V/F
Control Strategy:
The purpose of this architecture is to adjust the speed of the IM by
controlling the frequency and amplitude of the stator voltage, the ratio of
stator voltage to frequency should be kept constant. As shown in Fig.(3.14),
the architecture of the control consists of five major parts: (1) three-phase
sine wave generator module, (2) triangular wave generator module, (3)
three-digital comparators module, (4) dead time module, and (5) V/F
control module.
 46

(2) Triangular wave FPGA

generator module Kit
DFS Up/down (3) (4) PWMAU
counter Three-digital Dead time PWMAL
comparators module PWMBU
module PWMBL

rst PWMCU
rst PWMCL
fclock
50MHz
internal

Three Sine
modules Multipliers

(5) V/F control

fclk
module
Variable
CLK Multiplexer
divider

External data
(1) Three-phase
sine wave generator
module

Fig.(3.14): FPGA based SPWM control scheme for VVVF control

The triangular wave generator module, three-digital comparators

module, and dead time module are similar to those modules in the previous
architecture control (FPGA based SPWM control scheme for variable
voltage control).

3-2-2-1: Three-Phase Sine Wave Generator Module:

This module is also similar to the sine wave module in the previous
architecture control, but there are some differences.
 47
If a variable frequency sine reference wave generator is required
then clock frequency ( fclk) should also be made variable. The reference
frequency (freference) has a relationship with the clock frequency (fclk) and
the THETA width (m), then a variable clock divider (clock divider gives
different values of clock frequency suitable for adjusting the reference
frequency) is used to adjust the reference frequency at different values with
range of (0 < freference ≤ 50 Hz) (instead of using a single clock divider that
adjusts the reference frequency at 50 Hz only) at fixed THETA width (m)
according equation (3.2).

3-2-2-2: V/F Control Module:

External data (4-bits) (as a multiplicand data) are used to multiply
with the values of the three sine reference waves (sine out-a, sine out-b, and
sine out-c) that are stored in the internal block ROM via using three
multipliers to get a variation in the amplitude of the sine reference waves
resulting in a variation of the modulation index with range of (0 < mi ≤ 1).
At the same time, these external data are used as a data selector for a
multiplexer which is used to supply the three Sine modules with the clock
frequency ( fclk ) from the variable clock divider (adjust the clock
frequency ( fclk ) for the three Sine modules).
The multiplexer works as follows:
For example
if (external data = "1111") then fclk = 409.836 KHz;
(mi =1) ( freference = 50 Hz)

elsif (external data = "1110") then fclk = 358.4 KHz;

(mi =0.875) ( freference = 43.75 Hz)

elsif (external data = "1101") then fclk = 332.8 KHz;

(mi =0.8125) ( freference = 40.625 Hz)

By this manner the inverter output voltage over the reference

frequency inverter will be constant. The value of the external data
 48
(ratio V/F ) can be adjusted by using the four slide switches which already
exist on the FPGA kit.
This module can also adjust the reference frequency value with
range of ( 0 < freference ≤ 50 Hz) according to the state of the data selector
and fixing the amplitude of the output voltage via fixing the amplitude of
the modulation index to specified value (mi = 1, for example).
The FPGA utilization summary of the second proposed design
(FPGA based SPWM control scheme for Variable Voltage Variable
Frequency (VVVF) using V/F control strategy) is shown below in Table
(3.2).
Table (3.2): Device utilization summary of the FPGA Based SPWM
Control Scheme for VVVF using V/F control strategy

Logic Utilization Used Available Utilization

Number of Slices 441 4656 9%

Number of Slice Flip Flops 386 9312 4%

Number of 4 input LUTs 818 9312 8%

Number of bonded IOBs 12 232 5%

Number of BRAMs 6 20 30%

Number of MULT18*18SIOs 3 20 15%

Number of GCLKs 3 24 12%

Number of DCMs 1 4 25%

The UCF constraints of the FPGA Based SPWM Control Scheme

for VVVF using V/F control strategy architecture that downloaded in the
Xilinx XC3S500E Spartan-3E FPGA is given in APPENDIX(A2).
 49

CHAPTER FOUR
HARDWARE CONSTRUCTION OF THE AC DRIVE SYSTEM
AND THE RESULTS

4-1: Hardware Configuration

U

The basic block diagram of the AC drive system with FPGA control
is shown in Fig.(4.1). This system is divided into five stages. The first stage
represents generating the PWM signals via FPGA. The second stage
represents gate drive circuit to isolate and buffer the FPGA from the three-
phase bridge inverter circuit. The third stage represents designing the three-
phase bridge inverter circuit. The forth stage represents the three-phase step
up transformer. Last stage represents the three-phase IM. Each of these five
stages will be discussed in the next subsections.

VDC Three-phase Three-phase

IM
Bridge Inverter Transformer

FPGA Gate
Drive
Kit
Circuit

Fig.(4.1): Block diagram for the proposed practical AC drive system

4-1-1: FPGA PWM Generator:

The output (PWM signals) from FPGA kit with switching sequence
are used to drive the gate drive circuits through header J2, and header J4
and each output is connected to switches gate pin in the three-phase bridge
inverter circuit. Fig.(4.2) shows the header J2, and header J4.
 50

Fig.(4.2): Expansion headers[26]

The FPGA connections to the J2 accessory header is shown in

Fig.(4.3). This header uses a female 6-pin 90° socket. Four FPGA pins
connect to the J2 header, FX2_IO<8:5>. The board supplies 3.3V to the
accessory board mounted in the J2 socket on the bottom pin[26].
This header provides gating signals (PWMAL, PWMBL, and
PWMCL) to the gate drive circuit through (A6, B6, and E7) respectively.

Fig.(4.3): FPGA connections to the J2 accessory header

The FPGA connections to the J4 accessory header is shown in

Fig.(4.4). This header uses a 6-pin header consisting of 0.1-inch centered
stake pins. Four FPGA pins connect to the J4 header, FX2_IO<12:9>. The
board supplies 3.3V to the accessory board mounted in the J4 socket on the
bottom pin[26].
This header provides gating signals PWMAU, PWMBU, and PWMCU
to the gate drive circuit through (D7, C7, and F8) respectively.
 51

Fig.(4.4): FPGA connections to the J4 accessory header

4-1-2: Gate Drive Circuit:

The FPGA output pins should be protected from being overloaded
by excessive currents and to be isolated from the high voltage appearing
on the power switches terminals. Also power switches require relatively
higher voltages than those which can be given by the FPGA output pins.
So, first a buffer circuit is used to protect the FPGA pins, then an
optocoupler stage is used for voltage level isolation, and the last part is
the matching circuit which gives the appropriate level of voltage
demanded for operating the power switches of the three-phase bridge
inverter circuit. Each of these three stages will be discussed individually in
the next sections. One of the six gate drive circuits for the three-phase
bridge inverter is shown in Fig.(4.5).

Fig.(4.5): Gate drive circuit

 52
4-1-2-1: Buffer Circuit:
In order to protect the FPGA output pins from excessive current
loading, a transistor buffer is used. The transistor used is the npn 2N2222
connected in a common emitter arrangement. This will furnish the required
power and in the same time let the FPGA work safely.

4-1-2-2: Optocoupler Circuit:

The optocoupler (also known as an opto-isolator) provides an
optical connection between two circuits, at the same time it provides an
electrical isolation. The optocoupler circuit has two purposes: First, it
protects the FPGA output pins from being damaged if the power stage
encountered a short circuit or other forms of electrical hazards.
The second purpose of the optocoupler circuit is to prevent ground
sharing between the FPGA chip and the three-phase bridge inverter circuit
(because the ground of the upper MOSFET gate pulses should be isolated
from each other and from that the of lower MOSFETs gate pulses also as
shown in Fig. (A3.1) in APPENDIX (A3)). The optocoupler used is the
(6N137); it consists of a LED optically coupled to a very high speed
integrated photo-detector logic gate, and its data sheet is given in
APPENDIX(A4).

4-1-2-3: Matching Circuit:

The PWM signal from the optocoupler circuit stage varies between
(0-5)V, this voltage level is not enough to drive the power switches of the
inverter. Thus the output of the optocoupler needs to be boosted before is
supplied to the gate pins of the power switches[32]. A matching circuit
using (2N2222) npn transistor is used to boost the voltage level of the
optocoupler from the range of (0-5)V to range of (0-9)V (greater than the
gate threshold voltage (VGSTH) of the power switch and within the allowed
range for gate voltage value).
 53

Complete gate drive circuit (six gate drive circuits) is shown in

APPENDIX (A3). Fig.(4.6) shows the practical gate drive circuit.

Buffer Optocoupler Matching

Circuits Circuits Circuits

Fig.(4.6): Practical gate drive circuit

4-1-3: Three-Phase Bridge Inverter:

The PWM signals from the matching circuits are connected to
switches gate pin in the three-phase bridge inverter circuit. The basic three-
phase bridge inverter circuit is shown in Fig.(4.7). The power switch type
chosen for the voltage source bridge inverter is the (IRFP450). The switch
is an N-Channel power MOSFET (Metal Oxide Semiconductor Field-
Effect Transistor). It is a rugged device, capable of withstanding voltages
up to 500V and currents up to 14A. Its data sheet can be seen in
APPENDIX (A4). In addition, it has a built-in fast recovery diode, useful
when inductive loads and stray inductances are present in the circuit (it
works as a freewheeling diode to provide an alternate path for the motor
current after the MOSFET is turned off ).
 54

Fig.(4.7): Three-phase bridge inverter circuit

In order to protect the power MOSFETs from temperature raising,

each one is mounted on an individual heat sink.
The three-phase voltage source inverter is utilized to drive a three-phase
IM. The practical circuit of the three-phase bridge inverter is shown in
Fig.(4.8).

Fig.(4.8): Practical circuit of the three-phase bridge inverter

 55

4-1-4: Three-Phase Transformer:

Three-phase step-up transformer is used for stepping up the output
voltage of the three-phase inverter to feed the three-phase IM. The
transformer used is ∆/∆ (connection), 50 Hz, 2kVA, transformation ratio of
63.5V/220V per phase.

4-1-5: Three-Phase Induction Motor:

A three-phase squirrel cage induction motor has been used, it is
manufactured by ASEA company. The motor is a four poles, 50Hz,
380 V line ∆ , 0.55 KW, and 1410 rpm. The equivalent circuit parameters
of the three-phase IM were determined by performing three tests, these
are : (a) the stator-resistance test (DC test), (b) the blocked-rotor test, and
(c) the no-load test[18]. Then the parameters of the IM is given in
APPENDIX (A5).
The complete experimental setup of the three-phase inverter fed IM
with the FPGA control is shown in Fig.(4.9).

Induction
Three-Phase
Bridge Inverter Motor

DC Power
Supply

FPGA
Gate Drive
Circuit

Three-Phase
Transformer

Fig.(4.9): Experimental setup

 56
4-2: Simulation via MATLAB/SIMULINK
To verify the experimental results, the simulation of sinusoidal
PWM three-phase inverter feeding IM was made using
MATLAB/SIMULINK and simpower system toolbox. The scheme of the
system is shown in Fig.(4.10). It consists of three major parts (three-phase
bridge inverter circuit, PWM generator, and three-phase induction motor).
The three-phase sine reference waves (sinwave(A), sinwave(B), and
sinwave(C)) are comparing with the triangular carrier wave by using three
relational operator and the intersection of these waves generates the gating
signals (g1, g3, and g5) that applied to the upper switches (S1, S3, and S5),

each of these gating signals are negated by using three logical operator
(NOT) to produce a gating signals (g4, g6, and g2) are applied to the lower
switches (S4, S6, and S2) of the three-phase bridge inverter to generate

three-phase AC output voltage waveform to feed the induction motor. The

induction motor parameters of the simulation circuit are according to the
parameter of the actual IM that’s given in APPENDIX (A5).

Three-phase
bridge inverter

PWM
generator

Fig.(4.10): MATLAB Simulation of the SPWM three-phase VSI fed IM

 57

4-3: Waveforms of the SPWM Signals

U

The ISE simulator, MATLAB simulation, and experimental results

of the gate switching signals at reference frequency ( freference = 50 Hz), and
at modulation index (mi = 0.875) are shown in Figures (4.11), and (4.12).
Fig.(4.11) shows the results at carrier frequency (fcarrier =1050 Hz).
Fig.(4.12) shows the results at carrier frequency (fcarrier =1950 Hz).
The ISE simulator results shows six gating signals (g1, g2, g3, g4,
g5, and g6), while the MATLAB simulation and experimental results show
two gating signals (g1 and g4) only.
 58

(a)
1.5

g1
g1

0 0.02

1.5

g4
g2

0 0.02

(b)

PWMAU
(g1)

PWMAL
(g4)

(c)
Fig.(4.11): Results of the gate switching signals at modulation index
(mi = 0.875) and carrier frequency (fcarrier =1050 Hz): (a) ISE simulator,
(b) Simulation, and (c) Experimental
 59

(a)
1.5

1
g1

g1
0

0 0.02

1.5

g40.5
g2

0 0.02

(b)

PWMAU
(g1)

PWMAL
(g4)
(c)
Fig.(4.12): Results of the gate switching signals at modulation index
(mi = 0.875) and carrier frequency (fcarrier =1950 Hz): (a) ISE simulator,
(b) Simulation, and (c) Experimental
 60
4-4: Dead Time Results
U

Fig.(4.13) shows ISE simulator and experimental results of the dead

time technique.

(a)

PWM

PWM

(b)

Fig.(4.13): Results of dead time technique: (a) ISE simulator, and

(b) Experimental

This figure shows that the dead time is equal to (4 μsec).

 61

4-5: Results of the FPGA based SPWM Control Scheme for Variable
U

U Voltage Control
The line-to-line output voltage waveforms of the inverter circuit
(stator voltage of IM) with variable voltage control at different modulation
indexes and carrier frequencies are shown in Fig.(4.14), Fig.(4.15),
Fig.(4.16), and Fig.(4.17). The input DC supply (VDC) equals to 100V (the
voltage probe was set to 10:1 scale), for the reference frequency ( freference =
50 Hz).
Figures (4.14), and (4.15) show the simulation and experimental
results of the line-to-line output voltages (Vab, and Vcb) at two values of the
modulation indexes: (mi = 0.1875), and (mi = 0.875) respectively, at the
carrier frequency (fcarrier =1050 Hz).
Figures (4.16), and (4.17) show the results of the line-to-line output
voltages (Vab, and Vcb) at two values of the modulation indexes: (mi =
0.1875), and (mi = 0.875) respectively, at the carrier frequency (fcarrier
=1950 Hz).
The capability of variation the modulation index can provide a soft
starting for the induction motor. The soft starting is implemented by
starting the motor with low value of modulation index and then increasing
it gradually during the starting period to avoid a high starting current.
The experimental results are similar to the simulation results, i.e.
there is no different in the general switching pattern in both results, these
uniform voltage waveform has a fundamental sinusoidal component
responsible for a sinusoidal stator current and flux.
 62

100
Vab

-100
0.02

100
Vcb

-100
0.02

(a)

Vab

Vcb

(b)
Fig.(4.14): Results of the line-to-line output voltages waveforms at
modulation index (mi = 0.1875) and carrier frequency (fcarrier =1050 Hz)
:(a) Simulation, and (b) Experimental
 63

100

Vab
0

-100
0.02

100
Vcb

-100
0.02

(a)

Vab

Vcb

(b)
Fig.(4.15): Results of the line-to-line output voltages waveforms at
modulation index (mi = 0.875) and carrier frequency (fcarrier = 1050 Hz)
:(a) Simulation, and (b) Experimental
 64

100

Vab

-100
0.02

100
Vcb

-100
0.02

(a)

Vab

Vcb

(b)

Fig.(4.16): Results of the line-to-line output voltages waveforms at

modulation index (mi = 0.1875) and carrier frequency (fcarrier =1950 Hz)
:(a) Simulation, and (b) Experimental
 65

100

Vab
0

-100
0.02

100
Vcb

-100
0.02

(a)

Vab

Vcb

(b)

Fig.(4.17): Results of the line-to-line output voltages waveforms at

modulation index (mi = 0.875) and carrier frequency (fcarrier =1950 Hz)
:(a) Simulation, and (b) Experimental

The simulation and experimental results of the stator current

(Phase (A) Ia) waveform of the three-phase IM at modulation index
 66
(mi = 0.9375) are shown in Fig.(4.18) at carrier frequency of the inverter
(fcarrier =1050 Hz), and Fig.(4.19) at carrier frequency (fcarrier =1950 Hz).
The stator current waveform of the IM is measured across a
resistance (1 Ω) because there is not available Hall effect current sensors.

(a)

Ia

(b)
Fig.(4.18): Results of the stator current waveform at modulation index
(mi = 0.9375) and carrier frequency (fcarrier =1050 Hz) :(a) Simulation,
and (b) Experimental
 67

(a)

Ia

(b)
Fig.(4.19): Results of the stator current waveform at modulation index
(mi = 0.9375) and carrier frequency (fcarrier =1950 Hz) :(a) Simulation,
and (b) Experimental
68

The stator current waveform of the induction motor is a sine wave

due to inductive nature of the load although the output voltage waveform of
the inverter is non sinusoidal.
The experimental and simulation results show that stator current
waveform of the IM in case of operation at carrier frequency of (1950 Hz)
is smoother (more closer to sine wave and lower ripple) than at carrier
frequency (1050 Hz).

4-6: FFT Analysis

Fig.(4.20) shows the Fast Fourier Transform (FFT) analysis of the
output voltage of the three-phase VSI for frequency order at modulation
index (mi = 1). Fig.(4.20.a) shows the FFT analysis at carrier frequency
(fcarrier =1050 Hz), while Fig.(4.20.b) shows the FFT analysis carrier
frequency (fcarrier =1950 Hz).

(a)

(b)
Fig.(4.20): FFT analysis for frequency order at (mi = 1) and at
:(a) Carrier frequency (fcarrier =1050 Hz), (b) (fcarrier =1950 Hz)
 69

The FFT analysis of the output voltage of the inverter shows that in
case carrier frequency (1950 Hz and 1050 Hz respectively) the harmonic
components are shifted to be centred about the modulation frequencies (mf)
order (39th and 21st respectively). This means that as the value of mf is
increased the harmonic components are shifted away from the fundamental
component which has the advantage of reduced filter size, although the
switching loss is slightly increased.
Fig.(4.21.a) shows the variation of the fundamental voltage
component V1/VDC versus modulation index (mi) at different carrier
frequencies (fcarrier = 1050 Hz, and fcarrier = 1950 Hz), Fig.(4.21.b) illustrates
the variation of the Total Harmonic Distortion (THD) of the output voltage
of the inverter versus mi, and Fig.(4.21.c) illustrates the variation of the
THD of the stator current versus mi.
 70

1
fcarrier=1050Hz
0.9 fcarrier=1950Hz

0.8

0.7

0.6
V1/Vdc

0.5

0.4

0.3

0.2

0.1

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Modulation index (m i)
(a)

350 fcarrier=1050Hz
fcarrier=1950Hz
300

250
%THD

200

150

100

50

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Modulation index (m i)
(b)
40 fcarrier=1050Hz
fcarrier=1950Hz
30
%THD

20

10

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Modulation index (m i)
(c)

Fig.(4.21): Harmonic profile of SPWM

The harmonic profile of the output voltage of the inverter shows a

linear variation of the fundamental voltage component (V1) (which reaches
0.866 VDC at (mi = 1)) with the modulation indexes (mi). On the other hand,
the THDV starts with large value of (350%) at (mi = 0.1). This high value is
 71

due to the low voltage (V1) and high value of the other harmonic
components, then the THD decays to less than (70%) at (mi = 1).

4-7: Results of the FPGA Based SPWM Control Scheme for VVVF
U

Using V/F Control Strategy

U

Table (4.1) shows the actual speed of the IM with variable voltage
variable frequency controller in open loop mode.

Table (4.1): Results of the open loop V/F control of the IM

Stator Synchronous Actual

Supply
Voltage speed (rpm) Speed (rpm)
Frequency
(V) 𝟏𝟏𝟏𝟏𝟏𝟏 ∗ 𝒇𝒇 (as measured)
(Hz) (𝑵𝑵𝒎𝒎 = )
𝒑𝒑

12.5 95 375 373

15.625 118.75 468.75 466
18.75 142.5 562.5 558.4
21.875 166.25 656.25 650
25 190 750 746.4
50 380 1500 1487

Fig.(4.22) shows the experimental results of the line-to-line output

voltages (Vab, and Vcb) waveforms of the inverter circuit for VVVF using
V/F control.
72

Vab

Vcb

(a): reference frequency ( freference=25 Hz)

Vab

Vcb

(b): freference=21.875 Hz

Vab

Vcb

(c): freference=18.75 Hz
 73

Vab

Vcb

(d): freference=15.625 Hz

Vab

Vcb

(e): freference=12.5 Hz
Fig.(4.22): Experimental results of the line-to-line output voltage
waveform of the inverter for VVVF using V/F control

Fig.(4.23) shows the experimental results of the stator current

(Ia) waveforms of the IM for VVVF using V/F control.
74

Ia

(a): reference frequency ( freference=25 Hz)

Ia

(b): freference=21.875 Hz

Ia

(c): freference=18.75 Hz
 75

Ia

(d): freference=15.625 Hz

Ia

(e): freference=12.5 Hz

Fig.(4.23): Experimental results of the stator current waveform

of the IM for VVVF using V/F control
 76

CHAPTER FIVE
CONCLUSIONS AND FUTURE WORK

5-1: Conclusions
In this thesis the generation of PWM gating signals for the three-
phase VSI switches based on FPGA was successfully realized. Using
FPGA to generate PWM provides flexibility to modify the designed circuit
without altering the hardware part, easy and fast circuit modification,
comparatively low cost for a complex circuitry and rapid prototyping. The
control algorithm of the three-phase VSI was constructed in the
FPGA chip, also the hardware equipments needed for this driver were
constructed. They contain: a three-phase bridge inverter, and a gate driving
circuit.
Here are some conclusion points that can be highlighted as:
• The experimental and simulation results had shown satisfactory
results in terms of the gating PWM pulses (shape and number),
output voltage waveforms of the three-phase voltage source inverter
which fed the three-phase IM, and the load current (stator current
waveforms of the IM).

• The FPGA can provide digital control for the induction motor via
soft starting technique by varying the modulation index.

• The FPGA can generate SPWM with a wide range variation of

modulation indexes (0 < mi < 1, with step size of 0.015625).

• The FPGA can implement the V/F speed control strategy for the
induction motor to give ability for varying the speed with
maintaining the torque is constant.
77

• The output fundamental frequency in the V/F speed control strategy

can be varied from 0 Hz to 50 kHz (with step size of 6.25Hz), at the
same time the modulation index can be varied from 0 to 1(with step
size of 0.125).

• With the FPGA’s filed-programmable capability, the flexible

adjustment of dead time, and switching frequency, make it suitable
to drive various switching devices in practical applications.

• An integer number representation has been used instead of the

floating point representation in generation the three-phase sine wave.
This choice minimizes efficiently the required hardware resources
with reasonable accuracy.

• Using the DCM attribute resulted in increasing the time resolution

(i.e. increasing the ability to adjust the carrier frequency to more
accurate values).

• The device utilization summary of the proposed architectures shows

that the generation of the PWM is achieved in small size of the
available area of the FPGA chip. The device utilization summary of
the proposed architectures shows that the generation of the PWM
with VVVF is achieved with larger size of the available area of the
FPGA chip compared with the generation of the PWM with variable
voltage only.

• The higher modulation index and switching frequencies give the best
Total Harmonic Distortion (THD) value.

• Although increasing the carrier frequency gives better operation

regarding the harmonic contents, it is accompanied by the drawback
of more power losses occur.
 78

6-2: Future Work

There are some ideas for future work and recommendations to
improve this research, the following points display these ideas:

1. Applying closed loop V/F control strategy for IM drive.

2. Using SVM technique based on FPGA to generate PWM instead of

SPWM, because the SVM offers many advantages compared to the
SPWM.

3. Applying vector control strategy where both the magnitude and

phase of the control variables are controlled.

4. Applying on-line dead-time compensation technique based on

FPGA.
 79
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80

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 81
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82

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U U

[31] Victor M. Cgrdenas G. et al, "Elimination of Dead Time Effects

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 A1-1
APPENDIXES

APPENDIX (A1)

Spartan-3E Starter Kit

The Spartan-3E Starter Kit board is shown in Fig.(A1-1).

Fig.(A1-1): Spartan-3E Starter Kit board

Key features of the Spartan-3E Starter Kit board:

• Xilinx XC3S500E Spartan-3E FPGA
Up to 232 user-I/O pins
320-pin FPGA package
Over 10,000 logic cells
• Xilinx 4 Mbit Platform Flash configuration PROM
• Xilinx 64-macrocell XC2C64A CoolRunner CPLD
• 64 MByte (512 Mbit) of DDR SDRAM.
A1-2

• 16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)

FPGA configuration storage
MicroBlaze code storage/shadowing
• 16 Mbits of SPI serial Flash (STMicro)
FPGA configuration storage
MicroBlaze code shadowing
• 2-line, 16-character LCD screen
• PS/2 mouse or keyboard port
• VGA display port
• 10/100 Ethernet PHY (requires Ethernet MAC in FPGA)
• Two 9-pin RS-232 ports (DTE- and DCE-style)
• On-board USB-based FPGA/CPLD download/debug interface
• 50 MHz clock oscillator
• SHA-1 1-wire serial EEPROM for bitstream copy protection
• Hirose FX2 expansion connector
• Three Digilent 6-pin expansion connectors
• Four-output, SPI-based Digital-to-Analog Converter (DAC)
• Two-input, SPI-based Analog-to-Digital Converter (ADC) with
programmable-gain pre-amplifier
• ChipScope™ SoftTouch debugging port
• Rotary-encoder with push-button shaft
• Eight discrete LEDs
• Four slide switches
• Four push-button switches
• SMA clock input
• 8-pin DIP socket for auxiliary clock oscillator
 A2-1

APPENDIX (A2)

UCF Location Constraints

Fig.(A2-1) provides the UCF location constraints of the FPGA
based SPWM control for variable voltage control that downloaded in the.
Xilinx XC3S500E Spartan-3E FPGA.

Fig.(A2-1): UCF Location Constraints of the FPGA based SPWM

control for variable voltage control

Fig.(A2-2) provides the UCF location constraints of Based SPWM

Control Scheme for VVVF using V/F control strategy that downloaded in
the Xilinx XC3S500E Spartan-3E FPGA.
A2-2

Fig.(A2-2): UCF Location Constraints of the FPGA Based SPWM

Control Scheme for VVVF using V/F control strategy
 APPENDIX (A3)
Fig.(A3.1): Complete gate drive circuit

PWMAU PWMAL

PWMBU PWMBL

PWMCU PWMCL
 A4-3

APPENDIX (A4)

Data sheets for the components which are used in the

hardware circuit:
1- Data sheet for the optocoupler (6N137):
A4-4
 A4-3

2- Data sheet for the MOSFET (IRFP450)

A4-4
 A5-1

APPENDIX (A5)
Parameters of the IM

The parameters of the IM are:

Number of pairs of poles: 2
Rated frequency: 50 Hz
Rated speed : 1410 rpm
Rated voltage : 380V ∆
Stator resistance (𝑅𝑅𝑠𝑠 ) : 50 Ω
Stator inductance ( Ls ) :104.34 mH
Rotor resistance referred to the stator (𝑅𝑅 𝑟𝑟 ′ ) : 22.34 Ω
Rotor inductance referred to the stator ( 𝐿𝐿𝑟𝑟 ′ ) : 104.34 mH
Magnetizing inductance : ( Lm ) 1.877 H